root / target-mips / cpu.h @ a5c95808
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#if !defined (__MIPS_CPU_H__)
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#define __MIPS_CPU_H__
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//#define DEBUG_OP
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#define TARGET_HAS_ICE 1 |
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#define ELF_MACHINE EM_MIPS
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#define CPUArchState struct CPUMIPSState |
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#include "config.h" |
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#include "qemu-common.h" |
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#include "mips-defs.h" |
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#include "exec/cpu-defs.h" |
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#include "fpu/softfloat.h" |
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struct CPUMIPSState;
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typedef struct r4k_tlb_t r4k_tlb_t; |
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struct r4k_tlb_t {
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target_ulong VPN; |
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uint32_t PageMask; |
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uint_fast8_t ASID; |
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uint_fast16_t G:1;
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uint_fast16_t C0:3;
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uint_fast16_t C1:3;
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uint_fast16_t V0:1;
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uint_fast16_t V1:1;
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uint_fast16_t D0:1;
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uint_fast16_t D1:1;
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target_ulong PFN[2];
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}; |
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#if !defined(CONFIG_USER_ONLY)
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typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
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struct CPUMIPSTLBContext {
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uint32_t nb_tlb; |
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uint32_t tlb_in_use; |
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int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
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void (*helper_tlbwi)(struct CPUMIPSState *env); |
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void (*helper_tlbwr)(struct CPUMIPSState *env); |
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void (*helper_tlbp)(struct CPUMIPSState *env); |
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void (*helper_tlbr)(struct CPUMIPSState *env); |
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX]; |
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} r4k; |
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} mmu; |
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}; |
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#endif
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typedef union fpr_t fpr_t; |
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union fpr_t {
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float64 fd; /* ieee double precision */
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float32 fs[2];/* ieee single precision */ |
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uint64_t d; /* binary double fixed-point */
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uint32_t w[2]; /* binary single fixed-point */ |
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}; |
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/* define FP_ENDIAN_IDX to access the same location
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* in the fpr_t union regardless of the host endianness
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*/
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#if defined(HOST_WORDS_BIGENDIAN)
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# define FP_ENDIAN_IDX 1 |
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#else
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# define FP_ENDIAN_IDX 0 |
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#endif
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typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
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struct CPUMIPSFPUContext {
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/* Floating point registers */
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fpr_t fpr[32];
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float_status fp_status; |
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0; |
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#define FCR0_F64 22 |
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#define FCR0_L 21 |
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#define FCR0_W 20 |
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#define FCR0_3D 19 |
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#define FCR0_PS 18 |
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#define FCR0_D 17 |
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#define FCR0_S 16 |
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#define FCR0_PRID 8 |
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#define FCR0_REV 0 |
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/* fcsr */
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uint32_t fcr31; |
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#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
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#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
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#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
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#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
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#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
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#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
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#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
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#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
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#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
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#define FP_INEXACT 1 |
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#define FP_UNDERFLOW 2 |
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#define FP_OVERFLOW 4 |
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#define FP_DIV0 8 |
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#define FP_INVALID 16 |
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#define FP_UNIMPLEMENTED 32 |
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}; |
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#define NB_MMU_MODES 3 |
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
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struct CPUMIPSMVPContext {
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int32_t CP0_MVPControl; |
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#define CP0MVPCo_CPA 3 |
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#define CP0MVPCo_STLB 2 |
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#define CP0MVPCo_VPC 1 |
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#define CP0MVPCo_EVP 0 |
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int32_t CP0_MVPConf0; |
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#define CP0MVPC0_M 31 |
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#define CP0MVPC0_TLBS 29 |
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#define CP0MVPC0_GS 28 |
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#define CP0MVPC0_PCP 27 |
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#define CP0MVPC0_PTLBE 16 |
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#define CP0MVPC0_TCA 15 |
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#define CP0MVPC0_PVPE 10 |
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#define CP0MVPC0_PTC 0 |
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int32_t CP0_MVPConf1; |
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#define CP0MVPC1_CIM 31 |
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#define CP0MVPC1_CIF 30 |
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#define CP0MVPC1_PCX 20 |
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#define CP0MVPC1_PCP2 10 |
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#define CP0MVPC1_PCP1 0 |
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}; |
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typedef struct mips_def_t mips_def_t; |
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#define MIPS_SHADOW_SET_MAX 16 |
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#define MIPS_TC_MAX 5 |
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#define MIPS_FPU_MAX 1 |
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#define MIPS_DSP_ACC 4 |
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typedef struct TCState TCState; |
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struct TCState {
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target_ulong gpr[32];
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target_ulong PC; |
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target_ulong HI[MIPS_DSP_ACC]; |
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target_ulong LO[MIPS_DSP_ACC]; |
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target_ulong ACX[MIPS_DSP_ACC]; |
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target_ulong DSPControl; |
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int32_t CP0_TCStatus; |
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#define CP0TCSt_TCU3 31 |
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#define CP0TCSt_TCU2 30 |
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#define CP0TCSt_TCU1 29 |
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#define CP0TCSt_TCU0 28 |
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#define CP0TCSt_TMX 27 |
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#define CP0TCSt_RNST 23 |
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#define CP0TCSt_TDS 21 |
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#define CP0TCSt_DT 20 |
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#define CP0TCSt_DA 15 |
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#define CP0TCSt_A 13 |
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#define CP0TCSt_TKSU 11 |
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#define CP0TCSt_IXMT 10 |
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#define CP0TCSt_TASID 0 |
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int32_t CP0_TCBind; |
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#define CP0TCBd_CurTC 21 |
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#define CP0TCBd_TBE 17 |
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#define CP0TCBd_CurVPE 0 |
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target_ulong CP0_TCHalt; |
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target_ulong CP0_TCContext; |
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target_ulong CP0_TCSchedule; |
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target_ulong CP0_TCScheFBack; |
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int32_t CP0_Debug_tcstatus; |
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}; |
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typedef struct CPUMIPSState CPUMIPSState; |
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struct CPUMIPSState {
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TCState active_tc; |
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CPUMIPSFPUContext active_fpu; |
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uint32_t current_tc; |
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uint32_t current_fpu; |
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uint32_t SEGBITS; |
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uint32_t PABITS; |
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target_ulong SEGMask; |
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target_ulong PAMask; |
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int32_t CP0_Index; |
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/* CP0_MVP* are per MVP registers. */
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int32_t CP0_Random; |
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int32_t CP0_VPEControl; |
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#define CP0VPECo_YSI 21 |
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#define CP0VPECo_GSI 20 |
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#define CP0VPECo_EXCPT 16 |
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#define CP0VPECo_TE 15 |
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#define CP0VPECo_TargTC 0 |
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int32_t CP0_VPEConf0; |
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#define CP0VPEC0_M 31 |
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#define CP0VPEC0_XTC 21 |
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#define CP0VPEC0_TCS 19 |
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#define CP0VPEC0_SCS 18 |
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#define CP0VPEC0_DSC 17 |
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#define CP0VPEC0_ICS 16 |
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#define CP0VPEC0_MVP 1 |
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#define CP0VPEC0_VPA 0 |
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int32_t CP0_VPEConf1; |
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#define CP0VPEC1_NCX 20 |
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#define CP0VPEC1_NCP2 10 |
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#define CP0VPEC1_NCP1 0 |
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target_ulong CP0_YQMask; |
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target_ulong CP0_VPESchedule; |
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target_ulong CP0_VPEScheFBack; |
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int32_t CP0_VPEOpt; |
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#define CP0VPEOpt_IWX7 15 |
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#define CP0VPEOpt_IWX6 14 |
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#define CP0VPEOpt_IWX5 13 |
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#define CP0VPEOpt_IWX4 12 |
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#define CP0VPEOpt_IWX3 11 |
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#define CP0VPEOpt_IWX2 10 |
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#define CP0VPEOpt_IWX1 9 |
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#define CP0VPEOpt_IWX0 8 |
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#define CP0VPEOpt_DWX7 7 |
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#define CP0VPEOpt_DWX6 6 |
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#define CP0VPEOpt_DWX5 5 |
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#define CP0VPEOpt_DWX4 4 |
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#define CP0VPEOpt_DWX3 3 |
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#define CP0VPEOpt_DWX2 2 |
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#define CP0VPEOpt_DWX1 1 |
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#define CP0VPEOpt_DWX0 0 |
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target_ulong CP0_EntryLo0; |
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target_ulong CP0_EntryLo1; |
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target_ulong CP0_Context; |
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int32_t CP0_PageMask; |
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int32_t CP0_PageGrain; |
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int32_t CP0_Wired; |
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int32_t CP0_SRSConf0_rw_bitmask; |
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int32_t CP0_SRSConf0; |
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#define CP0SRSC0_M 31 |
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#define CP0SRSC0_SRS3 20 |
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#define CP0SRSC0_SRS2 10 |
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#define CP0SRSC0_SRS1 0 |
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int32_t CP0_SRSConf1_rw_bitmask; |
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int32_t CP0_SRSConf1; |
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#define CP0SRSC1_M 31 |
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#define CP0SRSC1_SRS6 20 |
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#define CP0SRSC1_SRS5 10 |
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#define CP0SRSC1_SRS4 0 |
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int32_t CP0_SRSConf2_rw_bitmask; |
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int32_t CP0_SRSConf2; |
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#define CP0SRSC2_M 31 |
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#define CP0SRSC2_SRS9 20 |
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#define CP0SRSC2_SRS8 10 |
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#define CP0SRSC2_SRS7 0 |
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int32_t CP0_SRSConf3_rw_bitmask; |
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int32_t CP0_SRSConf3; |
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#define CP0SRSC3_M 31 |
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#define CP0SRSC3_SRS12 20 |
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#define CP0SRSC3_SRS11 10 |
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#define CP0SRSC3_SRS10 0 |
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int32_t CP0_SRSConf4_rw_bitmask; |
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int32_t CP0_SRSConf4; |
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#define CP0SRSC4_SRS15 20 |
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#define CP0SRSC4_SRS14 10 |
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#define CP0SRSC4_SRS13 0 |
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int32_t CP0_HWREna; |
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target_ulong CP0_BadVAddr; |
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int32_t CP0_Count; |
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target_ulong CP0_EntryHi; |
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int32_t CP0_Compare; |
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int32_t CP0_Status; |
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#define CP0St_CU3 31 |
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#define CP0St_CU2 30 |
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#define CP0St_CU1 29 |
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#define CP0St_CU0 28 |
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#define CP0St_RP 27 |
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#define CP0St_FR 26 |
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#define CP0St_RE 25 |
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#define CP0St_MX 24 |
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#define CP0St_PX 23 |
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#define CP0St_BEV 22 |
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#define CP0St_TS 21 |
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#define CP0St_SR 20 |
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#define CP0St_NMI 19 |
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#define CP0St_IM 8 |
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#define CP0St_KX 7 |
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#define CP0St_SX 6 |
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#define CP0St_UX 5 |
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#define CP0St_KSU 3 |
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#define CP0St_ERL 2 |
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#define CP0St_EXL 1 |
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#define CP0St_IE 0 |
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int32_t CP0_IntCtl; |
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#define CP0IntCtl_IPTI 29 |
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#define CP0IntCtl_IPPC1 26 |
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#define CP0IntCtl_VS 5 |
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int32_t CP0_SRSCtl; |
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#define CP0SRSCtl_HSS 26 |
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#define CP0SRSCtl_EICSS 18 |
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#define CP0SRSCtl_ESS 12 |
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#define CP0SRSCtl_PSS 6 |
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#define CP0SRSCtl_CSS 0 |
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int32_t CP0_SRSMap; |
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#define CP0SRSMap_SSV7 28 |
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#define CP0SRSMap_SSV6 24 |
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#define CP0SRSMap_SSV5 20 |
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#define CP0SRSMap_SSV4 16 |
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#define CP0SRSMap_SSV3 12 |
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#define CP0SRSMap_SSV2 8 |
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#define CP0SRSMap_SSV1 4 |
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#define CP0SRSMap_SSV0 0 |
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int32_t CP0_Cause; |
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#define CP0Ca_BD 31 |
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#define CP0Ca_TI 30 |
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#define CP0Ca_CE 28 |
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#define CP0Ca_DC 27 |
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#define CP0Ca_PCI 26 |
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#define CP0Ca_IV 23 |
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#define CP0Ca_WP 22 |
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#define CP0Ca_IP 8 |
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#define CP0Ca_IP_mask 0x0000FF00 |
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#define CP0Ca_EC 2 |
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target_ulong CP0_EPC; |
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int32_t CP0_PRid; |
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int32_t CP0_EBase; |
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int32_t CP0_Config0; |
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#define CP0C0_M 31 |
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#define CP0C0_K23 28 |
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#define CP0C0_KU 25 |
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#define CP0C0_MDU 20 |
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#define CP0C0_MM 17 |
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#define CP0C0_BM 16 |
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#define CP0C0_BE 15 |
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#define CP0C0_AT 13 |
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#define CP0C0_AR 10 |
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#define CP0C0_MT 7 |
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#define CP0C0_VI 3 |
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#define CP0C0_K0 0 |
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int32_t CP0_Config1; |
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#define CP0C1_M 31 |
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#define CP0C1_MMU 25 |
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#define CP0C1_IS 22 |
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#define CP0C1_IL 19 |
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#define CP0C1_IA 16 |
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#define CP0C1_DS 13 |
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#define CP0C1_DL 10 |
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#define CP0C1_DA 7 |
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#define CP0C1_C2 6 |
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#define CP0C1_MD 5 |
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#define CP0C1_PC 4 |
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#define CP0C1_WR 3 |
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#define CP0C1_CA 2 |
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#define CP0C1_EP 1 |
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#define CP0C1_FP 0 |
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int32_t CP0_Config2; |
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#define CP0C2_M 31 |
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#define CP0C2_TU 28 |
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#define CP0C2_TS 24 |
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#define CP0C2_TL 20 |
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#define CP0C2_TA 16 |
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#define CP0C2_SU 12 |
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#define CP0C2_SS 8 |
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#define CP0C2_SL 4 |
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#define CP0C2_SA 0 |
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int32_t CP0_Config3; |
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#define CP0C3_M 31 |
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#define CP0C3_ISA_ON_EXC 16 |
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#define CP0C3_DSPP 10 |
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#define CP0C3_LPA 7 |
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#define CP0C3_VEIC 6 |
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#define CP0C3_VInt 5 |
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#define CP0C3_SP 4 |
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#define CP0C3_MT 2 |
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#define CP0C3_SM 1 |
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#define CP0C3_TL 0 |
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int32_t CP0_Config6; |
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int32_t CP0_Config7; |
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/* XXX: Maybe make LLAddr per-TC? */
|
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target_ulong lladdr; |
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target_ulong llval; |
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target_ulong llnewval; |
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target_ulong llreg; |
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target_ulong CP0_LLAddr_rw_bitmask; |
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int CP0_LLAddr_shift;
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target_ulong CP0_WatchLo[8];
|
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int32_t CP0_WatchHi[8];
|
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target_ulong CP0_XContext; |
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int32_t CP0_Framemask; |
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int32_t CP0_Debug; |
385 |
#define CP0DB_DBD 31 |
386 |
#define CP0DB_DM 30 |
387 |
#define CP0DB_LSNM 28 |
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#define CP0DB_Doze 27 |
389 |
#define CP0DB_Halt 26 |
390 |
#define CP0DB_CNT 25 |
391 |
#define CP0DB_IBEP 24 |
392 |
#define CP0DB_DBEP 21 |
393 |
#define CP0DB_IEXI 20 |
394 |
#define CP0DB_VER 15 |
395 |
#define CP0DB_DEC 10 |
396 |
#define CP0DB_SSt 8 |
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#define CP0DB_DINT 5 |
398 |
#define CP0DB_DIB 4 |
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#define CP0DB_DDBS 3 |
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#define CP0DB_DDBL 2 |
401 |
#define CP0DB_DBp 1 |
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#define CP0DB_DSS 0 |
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target_ulong CP0_DEPC; |
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int32_t CP0_Performance0; |
405 |
int32_t CP0_TagLo; |
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int32_t CP0_DataLo; |
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int32_t CP0_TagHi; |
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int32_t CP0_DataHi; |
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target_ulong CP0_ErrorEPC; |
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int32_t CP0_DESAVE; |
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/* We waste some space so we can handle shadow registers like TCs. */
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TCState tcs[MIPS_SHADOW_SET_MAX]; |
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CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
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/* QEMU */
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int error_code;
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uint32_t hflags; /* CPU State */
|
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/* TMASK defines different execution modes */
|
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#define MIPS_HFLAG_TMASK 0xC07FF |
419 |
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
420 |
/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
|
422 |
the bits as the value of mmu_idx. */
|
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#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
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#define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
425 |
#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
426 |
#define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
427 |
#define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
428 |
#define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
429 |
#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
430 |
#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
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#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
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/* True if the MIPS IV COP1X instructions can be used. This also
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controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
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and RSQRT.D. */
|
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#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
436 |
#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
437 |
#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ |
438 |
#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
439 |
#define MIPS_HFLAG_M16_SHIFT 10 |
440 |
/* If translation is interrupted between the branch instruction and
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441 |
* the delay slot, record what type of branch it is so that we can
|
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* resume translation properly. It might be possible to reduce
|
443 |
* this from three bits to two. */
|
444 |
#define MIPS_HFLAG_BMASK_BASE 0x03800 |
445 |
#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
446 |
#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
447 |
#define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
448 |
#define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
449 |
/* Extra flags about the current pending branch. */
|
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#define MIPS_HFLAG_BMASK_EXT 0x3C000 |
451 |
#define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
452 |
#define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
453 |
#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
454 |
#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ |
455 |
#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
|
456 |
/* MIPS DSP resources access. */
|
457 |
#define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */ |
458 |
#define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ |
459 |
target_ulong btarget; /* Jump / branch target */
|
460 |
target_ulong bcond; /* Branch condition (if needed) */
|
461 |
|
462 |
int SYNCI_Step; /* Address step size for SYNCI */ |
463 |
int CCRes; /* Cycle count resolution/divisor */ |
464 |
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
|
465 |
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
|
466 |
int insn_flags; /* Supported instruction set */ |
467 |
|
468 |
target_ulong tls_value; /* For usermode emulation */
|
469 |
|
470 |
CPU_COMMON |
471 |
|
472 |
CPUMIPSMVPContext *mvp; |
473 |
#if !defined(CONFIG_USER_ONLY)
|
474 |
CPUMIPSTLBContext *tlb; |
475 |
#endif
|
476 |
|
477 |
const mips_def_t *cpu_model;
|
478 |
void *irq[8]; |
479 |
struct QEMUTimer *timer; /* Internal timer */ |
480 |
}; |
481 |
|
482 |
#include "cpu-qom.h" |
483 |
|
484 |
#if !defined(CONFIG_USER_ONLY)
|
485 |
int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
486 |
target_ulong address, int rw, int access_type); |
487 |
int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
488 |
target_ulong address, int rw, int access_type); |
489 |
int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
490 |
target_ulong address, int rw, int access_type); |
491 |
void r4k_helper_tlbwi(CPUMIPSState *env);
|
492 |
void r4k_helper_tlbwr(CPUMIPSState *env);
|
493 |
void r4k_helper_tlbp(CPUMIPSState *env);
|
494 |
void r4k_helper_tlbr(CPUMIPSState *env);
|
495 |
|
496 |
void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
|
497 |
int is_write, int is_exec, int unused, int size); |
498 |
#endif
|
499 |
|
500 |
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
|
501 |
|
502 |
#define cpu_exec cpu_mips_exec
|
503 |
#define cpu_gen_code cpu_mips_gen_code
|
504 |
#define cpu_signal_handler cpu_mips_signal_handler
|
505 |
#define cpu_list mips_cpu_list
|
506 |
|
507 |
#define CPU_SAVE_VERSION 3 |
508 |
|
509 |
/* MMU modes definitions. We carefully match the indices with our
|
510 |
hflags layout. */
|
511 |
#define MMU_MODE0_SUFFIX _kernel
|
512 |
#define MMU_MODE1_SUFFIX _super
|
513 |
#define MMU_MODE2_SUFFIX _user
|
514 |
#define MMU_USER_IDX 2 |
515 |
static inline int cpu_mmu_index (CPUMIPSState *env) |
516 |
{ |
517 |
return env->hflags & MIPS_HFLAG_KSU;
|
518 |
} |
519 |
|
520 |
static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) |
521 |
{ |
522 |
if (newsp)
|
523 |
env->active_tc.gpr[29] = newsp;
|
524 |
env->active_tc.gpr[7] = 0; |
525 |
env->active_tc.gpr[2] = 0; |
526 |
} |
527 |
|
528 |
static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
529 |
{ |
530 |
int32_t pending; |
531 |
int32_t status; |
532 |
int r;
|
533 |
|
534 |
if (!(env->CP0_Status & (1 << CP0St_IE)) || |
535 |
(env->CP0_Status & (1 << CP0St_EXL)) ||
|
536 |
(env->CP0_Status & (1 << CP0St_ERL)) ||
|
537 |
/* Note that the TCStatus IXMT field is initialized to zero,
|
538 |
and only MT capable cores can set it to one. So we don't
|
539 |
need to check for MT capabilities here. */
|
540 |
(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
|
541 |
(env->hflags & MIPS_HFLAG_DM)) { |
542 |
/* Interrupts are disabled */
|
543 |
return 0; |
544 |
} |
545 |
|
546 |
pending = env->CP0_Cause & CP0Ca_IP_mask; |
547 |
status = env->CP0_Status & CP0Ca_IP_mask; |
548 |
|
549 |
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
550 |
/* A MIPS configured with a vectorizing external interrupt controller
|
551 |
will feed a vector into the Cause pending lines. The core treats
|
552 |
the status lines as a vector level, not as indiviual masks. */
|
553 |
r = pending > status; |
554 |
} else {
|
555 |
/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
|
556 |
treats the pending lines as individual interrupt lines, the status
|
557 |
lines are individual masks. */
|
558 |
r = pending & status; |
559 |
} |
560 |
return r;
|
561 |
} |
562 |
|
563 |
#include "exec/cpu-all.h" |
564 |
|
565 |
/* Memory access type :
|
566 |
* may be needed for precise access rights control and precise exceptions.
|
567 |
*/
|
568 |
enum {
|
569 |
/* 1 bit to define user level / supervisor access */
|
570 |
ACCESS_USER = 0x00,
|
571 |
ACCESS_SUPER = 0x01,
|
572 |
/* 1 bit to indicate direction */
|
573 |
ACCESS_STORE = 0x02,
|
574 |
/* Type of instruction that generated the access */
|
575 |
ACCESS_CODE = 0x10, /* Code fetch access */ |
576 |
ACCESS_INT = 0x20, /* Integer load/store access */ |
577 |
ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
578 |
}; |
579 |
|
580 |
/* Exceptions */
|
581 |
enum {
|
582 |
EXCP_NONE = -1,
|
583 |
EXCP_RESET = 0,
|
584 |
EXCP_SRESET, |
585 |
EXCP_DSS, |
586 |
EXCP_DINT, |
587 |
EXCP_DDBL, |
588 |
EXCP_DDBS, |
589 |
EXCP_NMI, |
590 |
EXCP_MCHECK, |
591 |
EXCP_EXT_INTERRUPT, /* 8 */
|
592 |
EXCP_DFWATCH, |
593 |
EXCP_DIB, |
594 |
EXCP_IWATCH, |
595 |
EXCP_AdEL, |
596 |
EXCP_AdES, |
597 |
EXCP_TLBF, |
598 |
EXCP_IBE, |
599 |
EXCP_DBp, /* 16 */
|
600 |
EXCP_SYSCALL, |
601 |
EXCP_BREAK, |
602 |
EXCP_CpU, |
603 |
EXCP_RI, |
604 |
EXCP_OVERFLOW, |
605 |
EXCP_TRAP, |
606 |
EXCP_FPE, |
607 |
EXCP_DWATCH, /* 24 */
|
608 |
EXCP_LTLBL, |
609 |
EXCP_TLBL, |
610 |
EXCP_TLBS, |
611 |
EXCP_DBE, |
612 |
EXCP_THREAD, |
613 |
EXCP_MDMX, |
614 |
EXCP_C2E, |
615 |
EXCP_CACHE, /* 32 */
|
616 |
EXCP_DSPDIS, |
617 |
|
618 |
EXCP_LAST = EXCP_DSPDIS, |
619 |
}; |
620 |
/* Dummy exception for conditional stores. */
|
621 |
#define EXCP_SC 0x100 |
622 |
|
623 |
/*
|
624 |
* This is an interrnally generated WAKE request line.
|
625 |
* It is driven by the CPU itself. Raised when the MT
|
626 |
* block wants to wake a VPE from an inactive state and
|
627 |
* cleared when VPE goes from active to inactive.
|
628 |
*/
|
629 |
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
|
630 |
|
631 |
int cpu_mips_exec(CPUMIPSState *s);
|
632 |
MIPSCPU *cpu_mips_init(const char *cpu_model); |
633 |
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
634 |
|
635 |
static inline CPUMIPSState *cpu_init(const char *cpu_model) |
636 |
{ |
637 |
MIPSCPU *cpu = cpu_mips_init(cpu_model); |
638 |
if (cpu == NULL) { |
639 |
return NULL; |
640 |
} |
641 |
return &cpu->env;
|
642 |
} |
643 |
|
644 |
/* TODO QOM'ify CPU reset and remove */
|
645 |
void cpu_state_reset(CPUMIPSState *s);
|
646 |
|
647 |
/* mips_timer.c */
|
648 |
uint32_t cpu_mips_get_random (CPUMIPSState *env); |
649 |
uint32_t cpu_mips_get_count (CPUMIPSState *env); |
650 |
void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
|
651 |
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
|
652 |
void cpu_mips_start_count(CPUMIPSState *env);
|
653 |
void cpu_mips_stop_count(CPUMIPSState *env);
|
654 |
|
655 |
/* mips_int.c */
|
656 |
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
657 |
|
658 |
/* helper.c */
|
659 |
int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, |
660 |
int mmu_idx);
|
661 |
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
|
662 |
void do_interrupt (CPUMIPSState *env);
|
663 |
#if !defined(CONFIG_USER_ONLY)
|
664 |
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); |
665 |
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
666 |
int rw);
|
667 |
#endif
|
668 |
|
669 |
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
670 |
target_ulong *cs_base, int *flags)
|
671 |
{ |
672 |
*pc = env->active_tc.PC; |
673 |
*cs_base = 0;
|
674 |
*flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
675 |
} |
676 |
|
677 |
static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) |
678 |
{ |
679 |
env->tls_value = newtls; |
680 |
} |
681 |
|
682 |
static inline int mips_vpe_active(CPUMIPSState *env) |
683 |
{ |
684 |
int active = 1; |
685 |
|
686 |
/* Check that the VPE is enabled. */
|
687 |
if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { |
688 |
active = 0;
|
689 |
} |
690 |
/* Check that the VPE is activated. */
|
691 |
if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
692 |
active = 0;
|
693 |
} |
694 |
|
695 |
/* Now verify that there are active thread contexts in the VPE.
|
696 |
|
697 |
This assumes the CPU model will internally reschedule threads
|
698 |
if the active one goes to sleep. If there are no threads available
|
699 |
the active one will be in a sleeping state, and we can turn off
|
700 |
the entire VPE. */
|
701 |
if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
702 |
/* TC is not activated. */
|
703 |
active = 0;
|
704 |
} |
705 |
if (env->active_tc.CP0_TCHalt & 1) { |
706 |
/* TC is in halt state. */
|
707 |
active = 0;
|
708 |
} |
709 |
|
710 |
return active;
|
711 |
} |
712 |
|
713 |
static inline bool cpu_has_work(CPUState *cpu) |
714 |
{ |
715 |
CPUMIPSState *env = &MIPS_CPU(cpu)->env; |
716 |
bool has_work = false; |
717 |
|
718 |
/* It is implementation dependent if non-enabled interrupts
|
719 |
wake-up the CPU, however most of the implementations only
|
720 |
check for interrupts that can be taken. */
|
721 |
if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
722 |
cpu_mips_hw_interrupts_pending(env)) { |
723 |
has_work = true;
|
724 |
} |
725 |
|
726 |
/* MIPS-MT has the ability to halt the CPU. */
|
727 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
728 |
/* The QEMU model will issue an _WAKE request whenever the CPUs
|
729 |
should be woken up. */
|
730 |
if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
|
731 |
has_work = true;
|
732 |
} |
733 |
|
734 |
if (!mips_vpe_active(env)) {
|
735 |
has_work = false;
|
736 |
} |
737 |
} |
738 |
return has_work;
|
739 |
} |
740 |
|
741 |
#include "exec/exec-all.h" |
742 |
|
743 |
static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) |
744 |
{ |
745 |
env->active_tc.PC = tb->pc; |
746 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
747 |
env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
748 |
} |
749 |
|
750 |
static inline void compute_hflags(CPUMIPSState *env) |
751 |
{ |
752 |
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
753 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
754 |
MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); |
755 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
756 |
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
757 |
!(env->hflags & MIPS_HFLAG_DM)) { |
758 |
env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
759 |
} |
760 |
#if defined(TARGET_MIPS64)
|
761 |
if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
|
762 |
(env->CP0_Status & (1 << CP0St_PX)) ||
|
763 |
(env->CP0_Status & (1 << CP0St_UX))) {
|
764 |
env->hflags |= MIPS_HFLAG_64; |
765 |
} |
766 |
if (env->CP0_Status & (1 << CP0St_UX)) { |
767 |
env->hflags |= MIPS_HFLAG_UX; |
768 |
} |
769 |
#endif
|
770 |
if ((env->CP0_Status & (1 << CP0St_CU0)) || |
771 |
!(env->hflags & MIPS_HFLAG_KSU)) { |
772 |
env->hflags |= MIPS_HFLAG_CP0; |
773 |
} |
774 |
if (env->CP0_Status & (1 << CP0St_CU1)) { |
775 |
env->hflags |= MIPS_HFLAG_FPU; |
776 |
} |
777 |
if (env->CP0_Status & (1 << CP0St_FR)) { |
778 |
env->hflags |= MIPS_HFLAG_F64; |
779 |
} |
780 |
if (env->insn_flags & ASE_DSPR2) {
|
781 |
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
|
782 |
so enable to access DSPR2 resources. */
|
783 |
if (env->CP0_Status & (1 << CP0St_MX)) { |
784 |
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; |
785 |
} |
786 |
|
787 |
} else if (env->insn_flags & ASE_DSP) { |
788 |
/* Enables access MIPS DSP resources, now our cpu is DSP ASE,
|
789 |
so enable to access DSP resources. */
|
790 |
if (env->CP0_Status & (1 << CP0St_MX)) { |
791 |
env->hflags |= MIPS_HFLAG_DSP; |
792 |
} |
793 |
|
794 |
} |
795 |
if (env->insn_flags & ISA_MIPS32R2) {
|
796 |
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
797 |
env->hflags |= MIPS_HFLAG_COP1X; |
798 |
} |
799 |
} else if (env->insn_flags & ISA_MIPS32) { |
800 |
if (env->hflags & MIPS_HFLAG_64) {
|
801 |
env->hflags |= MIPS_HFLAG_COP1X; |
802 |
} |
803 |
} else if (env->insn_flags & ISA_MIPS4) { |
804 |
/* All supported MIPS IV CPUs use the XX (CU3) to enable
|
805 |
and disable the MIPS IV extensions to the MIPS III ISA.
|
806 |
Some other MIPS IV CPUs ignore the bit, so the check here
|
807 |
would be too restrictive for them. */
|
808 |
if (env->CP0_Status & (1 << CP0St_CU3)) { |
809 |
env->hflags |= MIPS_HFLAG_COP1X; |
810 |
} |
811 |
} |
812 |
} |
813 |
|
814 |
#endif /* !defined (__MIPS_CPU_H__) */ |