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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "block.h"
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#include "qemu-timer.h"
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#include "isa.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, args...) \
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do { printf("FLOPPY: " fmt , ##args); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, args...)
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#endif
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#define FLOPPY_ERROR(fmt, args...) \
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do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN 512
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#define FD_SECTOR_SC  2   /* Sector size code */
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} fdisk_type_t;
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typedef enum fdrive_type_t {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} fdrive_type_t;
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typedef enum fdisk_flags_t {
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    FDISK_DBL_SIDES  = 0x01,
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} fdisk_flags_t;
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typedef struct fdrive_t {
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    BlockDriverState *bs;
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    /* Drive status */
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    fdrive_type_t drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    fdisk_flags_t flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} fdrive_t;
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static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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{
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    /* Drive */
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    drv->bs = bs;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int _fd_sector (uint8_t head, uint8_t track,
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                       uint8_t sect, uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv)
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{
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    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
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                    int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = _fd_sector(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct fd_format_t {
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    fdrive_type_t drive;
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    fdisk_type_t  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} fd_format_t;
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static const fd_format_t fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv)
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{
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    const fd_format_t *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
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static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
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static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
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enum {
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    FD_DIR_WRITE   = 0,
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    FD_DIR_READ    = 1,
322 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
323 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
324 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
325 8977f3c1 bellard
};
326 8977f3c1 bellard
327 8977f3c1 bellard
enum {
328 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
329 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
330 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
331 8977f3c1 bellard
};
332 8977f3c1 bellard
333 9fea808a blueswir1
enum {
334 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
335 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
336 9fea808a blueswir1
    FD_REG_DOR = 0x02,
337 9fea808a blueswir1
    FD_REG_TDR = 0x03,
338 9fea808a blueswir1
    FD_REG_MSR = 0x04,
339 9fea808a blueswir1
    FD_REG_DSR = 0x04,
340 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
341 9fea808a blueswir1
    FD_REG_DIR = 0x07,
342 9fea808a blueswir1
};
343 9fea808a blueswir1
344 9fea808a blueswir1
enum {
345 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
346 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
347 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
348 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
349 65cef780 blueswir1
    FD_CMD_READ = 0x06,
350 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
351 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
352 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
353 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
354 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
355 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
356 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
357 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
358 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
359 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
360 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
361 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
362 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
363 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
364 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
365 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
366 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
367 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
368 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
369 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
370 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
371 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
372 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
373 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
374 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
375 9fea808a blueswir1
};
376 9fea808a blueswir1
377 9fea808a blueswir1
enum {
378 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
379 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
380 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
381 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
382 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
383 9fea808a blueswir1
};
384 9fea808a blueswir1
385 9fea808a blueswir1
enum {
386 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
387 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
388 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
389 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
390 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
391 9fea808a blueswir1
};
392 9fea808a blueswir1
393 9fea808a blueswir1
enum {
394 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
395 77370520 blueswir1
};
396 77370520 blueswir1
397 77370520 blueswir1
enum {
398 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
399 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
400 77370520 blueswir1
};
401 77370520 blueswir1
402 77370520 blueswir1
enum {
403 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
404 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
405 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
406 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
407 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
408 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
409 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
410 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
411 8c6a4d77 blueswir1
};
412 8c6a4d77 blueswir1
413 8c6a4d77 blueswir1
enum {
414 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
415 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
416 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
417 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
418 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
419 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
420 8c6a4d77 blueswir1
};
421 8c6a4d77 blueswir1
422 8c6a4d77 blueswir1
enum {
423 78ae820c blueswir1
#if MAX_FD == 4
424 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
425 78ae820c blueswir1
#else
426 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
427 78ae820c blueswir1
#endif
428 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
429 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
430 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
431 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
432 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
433 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
434 9fea808a blueswir1
};
435 9fea808a blueswir1
436 9fea808a blueswir1
enum {
437 78ae820c blueswir1
#if MAX_FD == 4
438 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
439 78ae820c blueswir1
#else
440 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
441 78ae820c blueswir1
#endif
442 9fea808a blueswir1
};
443 9fea808a blueswir1
444 9fea808a blueswir1
enum {
445 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
446 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
447 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
448 9fea808a blueswir1
};
449 9fea808a blueswir1
450 9fea808a blueswir1
enum {
451 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
452 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
453 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
454 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
455 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
456 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
457 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
458 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
459 9fea808a blueswir1
};
460 9fea808a blueswir1
461 9fea808a blueswir1
enum {
462 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
463 9fea808a blueswir1
};
464 9fea808a blueswir1
465 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
466 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
467 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
468 8977f3c1 bellard
469 baca51fa bellard
struct fdctrl_t {
470 4b19ec0c bellard
    /* Controller's identification */
471 8977f3c1 bellard
    uint8_t version;
472 8977f3c1 bellard
    /* HW */
473 d537cf6c pbrook
    qemu_irq irq;
474 8977f3c1 bellard
    int dma_chann;
475 5dcb6b91 blueswir1
    target_phys_addr_t io_base;
476 4b19ec0c bellard
    /* Controller state */
477 ed5fd2cc bellard
    QEMUTimer *result_timer;
478 8c6a4d77 blueswir1
    uint8_t sra;
479 8c6a4d77 blueswir1
    uint8_t srb;
480 368df94d blueswir1
    uint8_t dor;
481 46d3233b blueswir1
    uint8_t tdr;
482 b9b3d225 blueswir1
    uint8_t dsr;
483 368df94d blueswir1
    uint8_t msr;
484 8977f3c1 bellard
    uint8_t cur_drv;
485 77370520 blueswir1
    uint8_t status0;
486 77370520 blueswir1
    uint8_t status1;
487 77370520 blueswir1
    uint8_t status2;
488 8977f3c1 bellard
    /* Command FIFO */
489 33f00271 balrog
    uint8_t *fifo;
490 8977f3c1 bellard
    uint32_t data_pos;
491 8977f3c1 bellard
    uint32_t data_len;
492 8977f3c1 bellard
    uint8_t data_state;
493 8977f3c1 bellard
    uint8_t data_dir;
494 890fa6be bellard
    uint8_t eot; /* last wanted sector */
495 8977f3c1 bellard
    /* States kept only to be returned back */
496 8977f3c1 bellard
    /* Timers state */
497 8977f3c1 bellard
    uint8_t timer0;
498 8977f3c1 bellard
    uint8_t timer1;
499 8977f3c1 bellard
    /* precompensation */
500 8977f3c1 bellard
    uint8_t precomp_trk;
501 8977f3c1 bellard
    uint8_t config;
502 8977f3c1 bellard
    uint8_t lock;
503 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
504 8977f3c1 bellard
    uint8_t pwrd;
505 741402f9 blueswir1
    /* Sun4m quirks? */
506 a06e5a3c blueswir1
    int sun4m;
507 8977f3c1 bellard
    /* Floppy drives */
508 78ae820c blueswir1
    fdrive_t drives[MAX_FD];
509 baca51fa bellard
};
510 baca51fa bellard
511 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
512 baca51fa bellard
{
513 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
514 baca51fa bellard
    uint32_t retval;
515 baca51fa bellard
516 a541f297 bellard
    switch (reg & 0x07) {
517 8c6a4d77 blueswir1
    case FD_REG_SRA:
518 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
519 4f431960 j_mayer
        break;
520 8c6a4d77 blueswir1
    case FD_REG_SRB:
521 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
522 4f431960 j_mayer
        break;
523 9fea808a blueswir1
    case FD_REG_DOR:
524 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
525 4f431960 j_mayer
        break;
526 9fea808a blueswir1
    case FD_REG_TDR:
527 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
528 4f431960 j_mayer
        break;
529 9fea808a blueswir1
    case FD_REG_MSR:
530 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
531 4f431960 j_mayer
        break;
532 9fea808a blueswir1
    case FD_REG_FIFO:
533 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
534 4f431960 j_mayer
        break;
535 9fea808a blueswir1
    case FD_REG_DIR:
536 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
537 4f431960 j_mayer
        break;
538 a541f297 bellard
    default:
539 4f431960 j_mayer
        retval = (uint32_t)(-1);
540 4f431960 j_mayer
        break;
541 a541f297 bellard
    }
542 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
543 baca51fa bellard
544 baca51fa bellard
    return retval;
545 baca51fa bellard
}
546 baca51fa bellard
547 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
548 baca51fa bellard
{
549 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
550 baca51fa bellard
551 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
552 ed5fd2cc bellard
553 a541f297 bellard
    switch (reg & 0x07) {
554 9fea808a blueswir1
    case FD_REG_DOR:
555 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
556 4f431960 j_mayer
        break;
557 9fea808a blueswir1
    case FD_REG_TDR:
558 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
559 4f431960 j_mayer
        break;
560 9fea808a blueswir1
    case FD_REG_DSR:
561 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
562 4f431960 j_mayer
        break;
563 9fea808a blueswir1
    case FD_REG_FIFO:
564 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
565 4f431960 j_mayer
        break;
566 a541f297 bellard
    default:
567 4f431960 j_mayer
        break;
568 a541f297 bellard
    }
569 baca51fa bellard
}
570 baca51fa bellard
571 62a46c61 bellard
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
572 62a46c61 bellard
{
573 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
574 62a46c61 bellard
}
575 62a46c61 bellard
576 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
577 62a46c61 bellard
                              target_phys_addr_t reg, uint32_t value)
578 62a46c61 bellard
{
579 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
580 62a46c61 bellard
}
581 62a46c61 bellard
582 e80cfcfc bellard
static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
583 62a46c61 bellard
    fdctrl_read_mem,
584 62a46c61 bellard
    fdctrl_read_mem,
585 62a46c61 bellard
    fdctrl_read_mem,
586 e80cfcfc bellard
};
587 e80cfcfc bellard
588 e80cfcfc bellard
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
589 62a46c61 bellard
    fdctrl_write_mem,
590 62a46c61 bellard
    fdctrl_write_mem,
591 62a46c61 bellard
    fdctrl_write_mem,
592 e80cfcfc bellard
};
593 e80cfcfc bellard
594 7c560456 blueswir1
static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
595 7c560456 blueswir1
    fdctrl_read_mem,
596 7c560456 blueswir1
    NULL,
597 7c560456 blueswir1
    NULL,
598 7c560456 blueswir1
};
599 7c560456 blueswir1
600 7c560456 blueswir1
static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
601 7c560456 blueswir1
    fdctrl_write_mem,
602 7c560456 blueswir1
    NULL,
603 7c560456 blueswir1
    NULL,
604 7c560456 blueswir1
};
605 7c560456 blueswir1
606 3ccacc4a blueswir1
static void fd_save (QEMUFile *f, fdrive_t *fd)
607 3ccacc4a blueswir1
{
608 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->head);
609 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->track);
610 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->sect);
611 3ccacc4a blueswir1
}
612 3ccacc4a blueswir1
613 3ccacc4a blueswir1
static void fdc_save (QEMUFile *f, void *opaque)
614 3ccacc4a blueswir1
{
615 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
616 78ae820c blueswir1
    uint8_t tmp;
617 78ae820c blueswir1
    int i;
618 cefec4f5 blueswir1
    uint8_t dor = s->dor | GET_CUR_DRV(s);
619 3ccacc4a blueswir1
620 8c6a4d77 blueswir1
    /* Controller state */
621 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->sra);
622 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->srb);
623 cefec4f5 blueswir1
    qemu_put_8s(f, &dor);
624 46d3233b blueswir1
    qemu_put_8s(f, &s->tdr);
625 77370520 blueswir1
    qemu_put_8s(f, &s->dsr);
626 77370520 blueswir1
    qemu_put_8s(f, &s->msr);
627 77370520 blueswir1
    qemu_put_8s(f, &s->status0);
628 77370520 blueswir1
    qemu_put_8s(f, &s->status1);
629 77370520 blueswir1
    qemu_put_8s(f, &s->status2);
630 77370520 blueswir1
    /* Command FIFO */
631 3ccacc4a blueswir1
    qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
632 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_pos);
633 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_len);
634 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_state);
635 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_dir);
636 3ccacc4a blueswir1
    qemu_put_8s(f, &s->eot);
637 77370520 blueswir1
    /* States kept only to be returned back */
638 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer0);
639 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer1);
640 3ccacc4a blueswir1
    qemu_put_8s(f, &s->precomp_trk);
641 3ccacc4a blueswir1
    qemu_put_8s(f, &s->config);
642 3ccacc4a blueswir1
    qemu_put_8s(f, &s->lock);
643 3ccacc4a blueswir1
    qemu_put_8s(f, &s->pwrd);
644 78ae820c blueswir1
645 78ae820c blueswir1
    tmp = MAX_FD;
646 78ae820c blueswir1
    qemu_put_8s(f, &tmp);
647 78ae820c blueswir1
    for (i = 0; i < MAX_FD; i++)
648 78ae820c blueswir1
        fd_save(f, &s->drives[i]);
649 3ccacc4a blueswir1
}
650 3ccacc4a blueswir1
651 3ccacc4a blueswir1
static int fd_load (QEMUFile *f, fdrive_t *fd)
652 3ccacc4a blueswir1
{
653 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->head);
654 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->track);
655 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->sect);
656 3ccacc4a blueswir1
657 3ccacc4a blueswir1
    return 0;
658 3ccacc4a blueswir1
}
659 3ccacc4a blueswir1
660 3ccacc4a blueswir1
static int fdc_load (QEMUFile *f, void *opaque, int version_id)
661 3ccacc4a blueswir1
{
662 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
663 78ae820c blueswir1
    int i, ret = 0;
664 78ae820c blueswir1
    uint8_t n;
665 3ccacc4a blueswir1
666 77370520 blueswir1
    if (version_id != 2)
667 3ccacc4a blueswir1
        return -EINVAL;
668 3ccacc4a blueswir1
669 8c6a4d77 blueswir1
    /* Controller state */
670 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->sra);
671 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->srb);
672 cefec4f5 blueswir1
    qemu_get_8s(f, &s->dor);
673 cefec4f5 blueswir1
    SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
674 cefec4f5 blueswir1
    s->dor &= ~FD_DOR_SELMASK;
675 46d3233b blueswir1
    qemu_get_8s(f, &s->tdr);
676 77370520 blueswir1
    qemu_get_8s(f, &s->dsr);
677 77370520 blueswir1
    qemu_get_8s(f, &s->msr);
678 77370520 blueswir1
    qemu_get_8s(f, &s->status0);
679 77370520 blueswir1
    qemu_get_8s(f, &s->status1);
680 77370520 blueswir1
    qemu_get_8s(f, &s->status2);
681 77370520 blueswir1
    /* Command FIFO */
682 3ccacc4a blueswir1
    qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
683 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_pos);
684 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_len);
685 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_state);
686 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_dir);
687 3ccacc4a blueswir1
    qemu_get_8s(f, &s->eot);
688 77370520 blueswir1
    /* States kept only to be returned back */
689 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer0);
690 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer1);
691 3ccacc4a blueswir1
    qemu_get_8s(f, &s->precomp_trk);
692 3ccacc4a blueswir1
    qemu_get_8s(f, &s->config);
693 3ccacc4a blueswir1
    qemu_get_8s(f, &s->lock);
694 3ccacc4a blueswir1
    qemu_get_8s(f, &s->pwrd);
695 78ae820c blueswir1
    qemu_get_8s(f, &n);
696 3ccacc4a blueswir1
697 78ae820c blueswir1
    if (n > MAX_FD)
698 78ae820c blueswir1
        return -EINVAL;
699 78ae820c blueswir1
700 78ae820c blueswir1
    for (i = 0; i < n; i++) {
701 78ae820c blueswir1
        ret = fd_load(f, &s->drives[i]);
702 78ae820c blueswir1
        if (ret != 0)
703 78ae820c blueswir1
            break;
704 78ae820c blueswir1
    }
705 3ccacc4a blueswir1
706 3ccacc4a blueswir1
    return ret;
707 3ccacc4a blueswir1
}
708 3ccacc4a blueswir1
709 3ccacc4a blueswir1
static void fdctrl_external_reset(void *opaque)
710 3ccacc4a blueswir1
{
711 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
712 3ccacc4a blueswir1
713 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
714 3ccacc4a blueswir1
}
715 3ccacc4a blueswir1
716 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
717 2be17ebd blueswir1
{
718 2be17ebd blueswir1
    //fdctrl_t *s = opaque;
719 2be17ebd blueswir1
720 2be17ebd blueswir1
    if (level) {
721 2be17ebd blueswir1
        // XXX
722 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
723 2be17ebd blueswir1
    }
724 2be17ebd blueswir1
}
725 2be17ebd blueswir1
726 baca51fa bellard
/* XXX: may change if moved to bdrv */
727 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
728 caed8802 bellard
{
729 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
730 8977f3c1 bellard
}
731 8977f3c1 bellard
732 8977f3c1 bellard
/* Change IRQ state */
733 baca51fa bellard
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
734 8977f3c1 bellard
{
735 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
736 8c6a4d77 blueswir1
        return;
737 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
738 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
739 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
740 8977f3c1 bellard
}
741 8977f3c1 bellard
742 77370520 blueswir1
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
743 8977f3c1 bellard
{
744 b9b3d225 blueswir1
    /* Sparc mutation */
745 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
746 b9b3d225 blueswir1
        /* XXX: not sure */
747 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
748 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
749 77370520 blueswir1
        fdctrl->status0 = status0;
750 4f431960 j_mayer
        return;
751 6f7e9aec bellard
    }
752 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
753 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
754 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
755 8977f3c1 bellard
    }
756 77370520 blueswir1
    fdctrl->status0 = status0;
757 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
758 8977f3c1 bellard
}
759 8977f3c1 bellard
760 4b19ec0c bellard
/* Reset controller */
761 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
762 8977f3c1 bellard
{
763 8977f3c1 bellard
    int i;
764 8977f3c1 bellard
765 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
766 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
767 4b19ec0c bellard
    /* Initialise controller */
768 8c6a4d77 blueswir1
    fdctrl->sra = 0;
769 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
770 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
771 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
772 baca51fa bellard
    fdctrl->cur_drv = 0;
773 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
774 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
775 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
776 8977f3c1 bellard
    /* FIFO state */
777 baca51fa bellard
    fdctrl->data_pos = 0;
778 baca51fa bellard
    fdctrl->data_len = 0;
779 b9b3d225 blueswir1
    fdctrl->data_state = 0;
780 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
781 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
782 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
783 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
784 77370520 blueswir1
    if (do_irq) {
785 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
786 77370520 blueswir1
    }
787 baca51fa bellard
}
788 baca51fa bellard
789 baca51fa bellard
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
790 baca51fa bellard
{
791 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
792 baca51fa bellard
}
793 baca51fa bellard
794 baca51fa bellard
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
795 baca51fa bellard
{
796 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
797 46d3233b blueswir1
        return &fdctrl->drives[1];
798 46d3233b blueswir1
    else
799 46d3233b blueswir1
        return &fdctrl->drives[0];
800 baca51fa bellard
}
801 baca51fa bellard
802 78ae820c blueswir1
#if MAX_FD == 4
803 78ae820c blueswir1
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
804 78ae820c blueswir1
{
805 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
806 78ae820c blueswir1
        return &fdctrl->drives[2];
807 78ae820c blueswir1
    else
808 78ae820c blueswir1
        return &fdctrl->drives[1];
809 78ae820c blueswir1
}
810 78ae820c blueswir1
811 78ae820c blueswir1
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
812 78ae820c blueswir1
{
813 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
814 78ae820c blueswir1
        return &fdctrl->drives[3];
815 78ae820c blueswir1
    else
816 78ae820c blueswir1
        return &fdctrl->drives[2];
817 78ae820c blueswir1
}
818 78ae820c blueswir1
#endif
819 78ae820c blueswir1
820 baca51fa bellard
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
821 baca51fa bellard
{
822 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
823 78ae820c blueswir1
        case 0: return drv0(fdctrl);
824 78ae820c blueswir1
        case 1: return drv1(fdctrl);
825 78ae820c blueswir1
#if MAX_FD == 4
826 78ae820c blueswir1
        case 2: return drv2(fdctrl);
827 78ae820c blueswir1
        case 3: return drv3(fdctrl);
828 78ae820c blueswir1
#endif
829 78ae820c blueswir1
        default: return NULL;
830 78ae820c blueswir1
    }
831 8977f3c1 bellard
}
832 8977f3c1 bellard
833 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
834 8c6a4d77 blueswir1
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
835 8c6a4d77 blueswir1
{
836 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
837 8c6a4d77 blueswir1
838 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
839 8c6a4d77 blueswir1
840 8c6a4d77 blueswir1
    return retval;
841 8c6a4d77 blueswir1
}
842 8c6a4d77 blueswir1
843 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
844 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
845 8977f3c1 bellard
{
846 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
847 8c6a4d77 blueswir1
848 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
849 8c6a4d77 blueswir1
850 8c6a4d77 blueswir1
    return retval;
851 8977f3c1 bellard
}
852 8977f3c1 bellard
853 8977f3c1 bellard
/* Digital output register : 0x02 */
854 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
855 8977f3c1 bellard
{
856 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
857 8977f3c1 bellard
858 8977f3c1 bellard
    /* Selected drive */
859 baca51fa bellard
    retval |= fdctrl->cur_drv;
860 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
861 8977f3c1 bellard
862 8977f3c1 bellard
    return retval;
863 8977f3c1 bellard
}
864 8977f3c1 bellard
865 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
866 8977f3c1 bellard
{
867 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
868 8c6a4d77 blueswir1
869 8c6a4d77 blueswir1
    /* Motors */
870 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
871 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
872 8c6a4d77 blueswir1
    else
873 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
874 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
875 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
876 8c6a4d77 blueswir1
    else
877 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
878 8c6a4d77 blueswir1
879 8c6a4d77 blueswir1
    /* Drive */
880 8c6a4d77 blueswir1
    if (value & 1)
881 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
882 8c6a4d77 blueswir1
    else
883 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
884 8c6a4d77 blueswir1
885 8977f3c1 bellard
    /* Reset */
886 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
887 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
888 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
889 8977f3c1 bellard
        }
890 8977f3c1 bellard
    } else {
891 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
892 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
893 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
894 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
895 8977f3c1 bellard
        }
896 8977f3c1 bellard
    }
897 8977f3c1 bellard
    /* Selected drive */
898 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
899 368df94d blueswir1
900 368df94d blueswir1
    fdctrl->dor = value;
901 8977f3c1 bellard
}
902 8977f3c1 bellard
903 8977f3c1 bellard
/* Tape drive register : 0x03 */
904 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
905 8977f3c1 bellard
{
906 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
907 8977f3c1 bellard
908 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
909 8977f3c1 bellard
910 8977f3c1 bellard
    return retval;
911 8977f3c1 bellard
}
912 8977f3c1 bellard
913 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
914 8977f3c1 bellard
{
915 8977f3c1 bellard
    /* Reset mode */
916 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
917 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
918 8977f3c1 bellard
        return;
919 8977f3c1 bellard
    }
920 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
921 8977f3c1 bellard
    /* Disk boot selection indicator */
922 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
923 8977f3c1 bellard
    /* Tape indicators: never allow */
924 8977f3c1 bellard
}
925 8977f3c1 bellard
926 8977f3c1 bellard
/* Main status register : 0x04 (read) */
927 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
928 8977f3c1 bellard
{
929 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
930 8977f3c1 bellard
931 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
932 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
933 b9b3d225 blueswir1
934 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
935 8977f3c1 bellard
936 8977f3c1 bellard
    return retval;
937 8977f3c1 bellard
}
938 8977f3c1 bellard
939 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
940 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
941 8977f3c1 bellard
{
942 8977f3c1 bellard
    /* Reset mode */
943 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
944 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
945 4f431960 j_mayer
        return;
946 4f431960 j_mayer
    }
947 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
948 8977f3c1 bellard
    /* Reset: autoclear */
949 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
950 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
951 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
952 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
953 8977f3c1 bellard
    }
954 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
955 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
956 8977f3c1 bellard
    }
957 b9b3d225 blueswir1
    fdctrl->dsr = value;
958 8977f3c1 bellard
}
959 8977f3c1 bellard
960 ea185bbd bellard
static int fdctrl_media_changed(fdrive_t *drv)
961 ea185bbd bellard
{
962 ea185bbd bellard
    int ret;
963 4f431960 j_mayer
964 5fafdf24 ths
    if (!drv->bs)
965 ea185bbd bellard
        return 0;
966 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
967 ea185bbd bellard
    if (ret) {
968 ea185bbd bellard
        fd_revalidate(drv);
969 ea185bbd bellard
    }
970 ea185bbd bellard
    return ret;
971 ea185bbd bellard
}
972 ea185bbd bellard
973 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
974 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
975 8977f3c1 bellard
{
976 8977f3c1 bellard
    uint32_t retval = 0;
977 8977f3c1 bellard
978 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
979 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
980 78ae820c blueswir1
#if MAX_FD == 4
981 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
982 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
983 78ae820c blueswir1
#endif
984 78ae820c blueswir1
        )
985 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
986 8977f3c1 bellard
    if (retval != 0)
987 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
988 8977f3c1 bellard
989 8977f3c1 bellard
    return retval;
990 8977f3c1 bellard
}
991 8977f3c1 bellard
992 8977f3c1 bellard
/* FIFO state control */
993 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
994 8977f3c1 bellard
{
995 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
996 baca51fa bellard
    fdctrl->data_pos = 0;
997 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
998 8977f3c1 bellard
}
999 8977f3c1 bellard
1000 8977f3c1 bellard
/* Set FIFO status for the host to read */
1001 baca51fa bellard
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1002 8977f3c1 bellard
{
1003 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1004 baca51fa bellard
    fdctrl->data_len = fifo_len;
1005 baca51fa bellard
    fdctrl->data_pos = 0;
1006 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1007 8977f3c1 bellard
    if (do_irq)
1008 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1009 8977f3c1 bellard
}
1010 8977f3c1 bellard
1011 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1012 65cef780 blueswir1
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1013 8977f3c1 bellard
{
1014 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1015 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1016 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1017 8977f3c1 bellard
}
1018 8977f3c1 bellard
1019 746d6de7 blueswir1
/* Seek to next sector */
1020 746d6de7 blueswir1
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1021 746d6de7 blueswir1
{
1022 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1023 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1024 746d6de7 blueswir1
                   fd_sector(cur_drv));
1025 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1026 746d6de7 blueswir1
       error in fact */
1027 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1028 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1029 746d6de7 blueswir1
        cur_drv->sect = 1;
1030 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1031 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1032 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1033 746d6de7 blueswir1
                cur_drv->head = 1;
1034 746d6de7 blueswir1
            } else {
1035 746d6de7 blueswir1
                cur_drv->head = 0;
1036 746d6de7 blueswir1
                cur_drv->track++;
1037 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1038 746d6de7 blueswir1
                    return 0;
1039 746d6de7 blueswir1
            }
1040 746d6de7 blueswir1
        } else {
1041 746d6de7 blueswir1
            cur_drv->track++;
1042 746d6de7 blueswir1
            return 0;
1043 746d6de7 blueswir1
        }
1044 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1045 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1046 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1047 746d6de7 blueswir1
    } else {
1048 746d6de7 blueswir1
        cur_drv->sect++;
1049 746d6de7 blueswir1
    }
1050 746d6de7 blueswir1
    return 1;
1051 746d6de7 blueswir1
}
1052 746d6de7 blueswir1
1053 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1054 baca51fa bellard
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1055 4f431960 j_mayer
                                  uint8_t status1, uint8_t status2)
1056 8977f3c1 bellard
{
1057 baca51fa bellard
    fdrive_t *cur_drv;
1058 8977f3c1 bellard
1059 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1060 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1061 8977f3c1 bellard
                   status0, status1, status2,
1062 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1063 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1064 baca51fa bellard
    fdctrl->fifo[1] = status1;
1065 baca51fa bellard
    fdctrl->fifo[2] = status2;
1066 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1067 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1068 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1069 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1070 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1071 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1072 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1073 ed5fd2cc bellard
    }
1074 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1075 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1076 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1077 8977f3c1 bellard
}
1078 8977f3c1 bellard
1079 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1080 baca51fa bellard
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1081 8977f3c1 bellard
{
1082 baca51fa bellard
    fdrive_t *cur_drv;
1083 8977f3c1 bellard
    uint8_t kh, kt, ks;
1084 77370520 blueswir1
    int did_seek = 0;
1085 8977f3c1 bellard
1086 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1087 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1088 baca51fa bellard
    kt = fdctrl->fifo[2];
1089 baca51fa bellard
    kh = fdctrl->fifo[3];
1090 baca51fa bellard
    ks = fdctrl->fifo[4];
1091 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1092 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1093 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1094 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1095 8977f3c1 bellard
    case 2:
1096 8977f3c1 bellard
        /* sect too big */
1097 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1098 baca51fa bellard
        fdctrl->fifo[3] = kt;
1099 baca51fa bellard
        fdctrl->fifo[4] = kh;
1100 baca51fa bellard
        fdctrl->fifo[5] = ks;
1101 8977f3c1 bellard
        return;
1102 8977f3c1 bellard
    case 3:
1103 8977f3c1 bellard
        /* track too big */
1104 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1105 baca51fa bellard
        fdctrl->fifo[3] = kt;
1106 baca51fa bellard
        fdctrl->fifo[4] = kh;
1107 baca51fa bellard
        fdctrl->fifo[5] = ks;
1108 8977f3c1 bellard
        return;
1109 8977f3c1 bellard
    case 4:
1110 8977f3c1 bellard
        /* No seek enabled */
1111 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1112 baca51fa bellard
        fdctrl->fifo[3] = kt;
1113 baca51fa bellard
        fdctrl->fifo[4] = kh;
1114 baca51fa bellard
        fdctrl->fifo[5] = ks;
1115 8977f3c1 bellard
        return;
1116 8977f3c1 bellard
    case 1:
1117 8977f3c1 bellard
        did_seek = 1;
1118 8977f3c1 bellard
        break;
1119 8977f3c1 bellard
    default:
1120 8977f3c1 bellard
        break;
1121 8977f3c1 bellard
    }
1122 b9b3d225 blueswir1
1123 8977f3c1 bellard
    /* Set the FIFO state */
1124 baca51fa bellard
    fdctrl->data_dir = direction;
1125 baca51fa bellard
    fdctrl->data_pos = 0;
1126 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1127 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1128 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1129 baca51fa bellard
    else
1130 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1131 8977f3c1 bellard
    if (did_seek)
1132 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1133 baca51fa bellard
    else
1134 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1135 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1136 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1137 baca51fa bellard
    } else {
1138 4f431960 j_mayer
        int tmp;
1139 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1140 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1141 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1142 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1143 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1144 baca51fa bellard
    }
1145 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1146 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1147 8977f3c1 bellard
        int dma_mode;
1148 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1149 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1150 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1151 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1152 4f431960 j_mayer
                       dma_mode, direction,
1153 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1154 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1155 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1156 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1157 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1158 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1159 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1160 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1161 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1162 8977f3c1 bellard
             * recall us...
1163 8977f3c1 bellard
             */
1164 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1165 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1166 8977f3c1 bellard
            return;
1167 baca51fa bellard
        } else {
1168 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1169 8977f3c1 bellard
        }
1170 8977f3c1 bellard
    }
1171 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1172 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1173 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1174 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1175 8977f3c1 bellard
    /* IO based transfer: calculate len */
1176 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1177 8977f3c1 bellard
1178 8977f3c1 bellard
    return;
1179 8977f3c1 bellard
}
1180 8977f3c1 bellard
1181 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1182 baca51fa bellard
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1183 8977f3c1 bellard
{
1184 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1185 77370520 blueswir1
1186 8977f3c1 bellard
    /* We don't handle deleted data,
1187 8977f3c1 bellard
     * so we don't return *ANYTHING*
1188 8977f3c1 bellard
     */
1189 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1190 8977f3c1 bellard
}
1191 8977f3c1 bellard
1192 8977f3c1 bellard
/* handlers for DMA transfers */
1193 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1194 85571bc7 bellard
                                    int dma_pos, int dma_len)
1195 8977f3c1 bellard
{
1196 baca51fa bellard
    fdctrl_t *fdctrl;
1197 baca51fa bellard
    fdrive_t *cur_drv;
1198 baca51fa bellard
    int len, start_pos, rel_pos;
1199 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1200 8977f3c1 bellard
1201 baca51fa bellard
    fdctrl = opaque;
1202 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1203 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1204 8977f3c1 bellard
        return 0;
1205 8977f3c1 bellard
    }
1206 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1207 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1208 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1209 77370520 blueswir1
        status2 = FD_SR2_SNS;
1210 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1211 85571bc7 bellard
        dma_len = fdctrl->data_len;
1212 890fa6be bellard
    if (cur_drv->bs == NULL) {
1213 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1214 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1215 4f431960 j_mayer
        else
1216 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1217 4f431960 j_mayer
        len = 0;
1218 890fa6be bellard
        goto transfer_error;
1219 890fa6be bellard
    }
1220 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1221 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1222 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1223 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1224 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1225 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1226 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1227 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1228 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1229 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1230 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1231 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1232 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1233 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1234 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1235 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1236 8977f3c1 bellard
                               fd_sector(cur_drv));
1237 8977f3c1 bellard
                /* Sure, image size is too small... */
1238 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1239 8977f3c1 bellard
            }
1240 890fa6be bellard
        }
1241 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1242 4f431960 j_mayer
        case FD_DIR_READ:
1243 4f431960 j_mayer
            /* READ commands */
1244 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1245 85571bc7 bellard
                              fdctrl->data_pos, len);
1246 4f431960 j_mayer
            break;
1247 4f431960 j_mayer
        case FD_DIR_WRITE:
1248 baca51fa bellard
            /* WRITE commands */
1249 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1250 85571bc7 bellard
                             fdctrl->data_pos, len);
1251 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1252 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1253 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1254 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1255 baca51fa bellard
                goto transfer_error;
1256 890fa6be bellard
            }
1257 4f431960 j_mayer
            break;
1258 4f431960 j_mayer
        default:
1259 4f431960 j_mayer
            /* SCAN commands */
1260 baca51fa bellard
            {
1261 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1262 baca51fa bellard
                int ret;
1263 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1264 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1265 8977f3c1 bellard
                if (ret == 0) {
1266 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1267 8977f3c1 bellard
                    goto end_transfer;
1268 8977f3c1 bellard
                }
1269 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1270 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1271 8977f3c1 bellard
                    status2 = 0x00;
1272 8977f3c1 bellard
                    goto end_transfer;
1273 8977f3c1 bellard
                }
1274 8977f3c1 bellard
            }
1275 4f431960 j_mayer
            break;
1276 8977f3c1 bellard
        }
1277 4f431960 j_mayer
        fdctrl->data_pos += len;
1278 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1279 baca51fa bellard
        if (rel_pos == 0) {
1280 8977f3c1 bellard
            /* Seek to next sector */
1281 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1282 746d6de7 blueswir1
                break;
1283 8977f3c1 bellard
        }
1284 8977f3c1 bellard
    }
1285 4f431960 j_mayer
 end_transfer:
1286 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1287 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1288 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1289 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1290 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1291 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1292 77370520 blueswir1
        status2 = FD_SR2_SEH;
1293 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1294 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1295 baca51fa bellard
    fdctrl->data_len -= len;
1296 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1297 4f431960 j_mayer
 transfer_error:
1298 8977f3c1 bellard
1299 baca51fa bellard
    return len;
1300 8977f3c1 bellard
}
1301 8977f3c1 bellard
1302 8977f3c1 bellard
/* Data register : 0x05 */
1303 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1304 8977f3c1 bellard
{
1305 baca51fa bellard
    fdrive_t *cur_drv;
1306 8977f3c1 bellard
    uint32_t retval = 0;
1307 746d6de7 blueswir1
    int pos;
1308 8977f3c1 bellard
1309 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1310 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1311 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1312 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1313 8977f3c1 bellard
        return 0;
1314 8977f3c1 bellard
    }
1315 baca51fa bellard
    pos = fdctrl->data_pos;
1316 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1317 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1318 8977f3c1 bellard
        if (pos == 0) {
1319 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1320 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1321 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1322 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1323 746d6de7 blueswir1
                    return 0;
1324 746d6de7 blueswir1
                }
1325 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1326 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1327 77370520 blueswir1
                               fd_sector(cur_drv));
1328 77370520 blueswir1
                /* Sure, image size is too small... */
1329 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1330 77370520 blueswir1
            }
1331 8977f3c1 bellard
        }
1332 8977f3c1 bellard
    }
1333 baca51fa bellard
    retval = fdctrl->fifo[pos];
1334 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1335 baca51fa bellard
        fdctrl->data_pos = 0;
1336 890fa6be bellard
        /* Switch from transfer mode to status mode
1337 8977f3c1 bellard
         * then from status mode to command mode
1338 8977f3c1 bellard
         */
1339 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1340 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1341 ed5fd2cc bellard
        } else {
1342 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1343 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1344 ed5fd2cc bellard
        }
1345 8977f3c1 bellard
    }
1346 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1347 8977f3c1 bellard
1348 8977f3c1 bellard
    return retval;
1349 8977f3c1 bellard
}
1350 8977f3c1 bellard
1351 baca51fa bellard
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1352 8977f3c1 bellard
{
1353 baca51fa bellard
    fdrive_t *cur_drv;
1354 baca51fa bellard
    uint8_t kh, kt, ks;
1355 8977f3c1 bellard
1356 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1357 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1358 baca51fa bellard
    kt = fdctrl->fifo[6];
1359 baca51fa bellard
    kh = fdctrl->fifo[7];
1360 baca51fa bellard
    ks = fdctrl->fifo[8];
1361 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1362 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1363 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1364 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1365 baca51fa bellard
    case 2:
1366 baca51fa bellard
        /* sect too big */
1367 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1368 baca51fa bellard
        fdctrl->fifo[3] = kt;
1369 baca51fa bellard
        fdctrl->fifo[4] = kh;
1370 baca51fa bellard
        fdctrl->fifo[5] = ks;
1371 baca51fa bellard
        return;
1372 baca51fa bellard
    case 3:
1373 baca51fa bellard
        /* track too big */
1374 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1375 baca51fa bellard
        fdctrl->fifo[3] = kt;
1376 baca51fa bellard
        fdctrl->fifo[4] = kh;
1377 baca51fa bellard
        fdctrl->fifo[5] = ks;
1378 baca51fa bellard
        return;
1379 baca51fa bellard
    case 4:
1380 baca51fa bellard
        /* No seek enabled */
1381 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1382 baca51fa bellard
        fdctrl->fifo[3] = kt;
1383 baca51fa bellard
        fdctrl->fifo[4] = kh;
1384 baca51fa bellard
        fdctrl->fifo[5] = ks;
1385 baca51fa bellard
        return;
1386 baca51fa bellard
    case 1:
1387 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1388 baca51fa bellard
        break;
1389 baca51fa bellard
    default:
1390 baca51fa bellard
        break;
1391 baca51fa bellard
    }
1392 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1393 baca51fa bellard
    if (cur_drv->bs == NULL ||
1394 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1395 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1396 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1397 baca51fa bellard
    } else {
1398 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1399 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1400 4f431960 j_mayer
            /* Last sector done */
1401 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1402 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1403 4f431960 j_mayer
            else
1404 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1405 4f431960 j_mayer
        } else {
1406 4f431960 j_mayer
            /* More to do */
1407 4f431960 j_mayer
            fdctrl->data_pos = 0;
1408 4f431960 j_mayer
            fdctrl->data_len = 4;
1409 4f431960 j_mayer
        }
1410 baca51fa bellard
    }
1411 baca51fa bellard
}
1412 baca51fa bellard
1413 65cef780 blueswir1
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1414 65cef780 blueswir1
{
1415 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1416 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1417 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1418 65cef780 blueswir1
}
1419 65cef780 blueswir1
1420 65cef780 blueswir1
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1421 65cef780 blueswir1
{
1422 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1423 65cef780 blueswir1
1424 65cef780 blueswir1
    /* Drives position */
1425 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1426 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1427 78ae820c blueswir1
#if MAX_FD == 4
1428 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1429 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1430 78ae820c blueswir1
#else
1431 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1432 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1433 78ae820c blueswir1
#endif
1434 65cef780 blueswir1
    /* timers */
1435 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1436 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1437 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1438 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1439 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1440 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1441 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1442 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1443 65cef780 blueswir1
}
1444 65cef780 blueswir1
1445 65cef780 blueswir1
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1446 65cef780 blueswir1
{
1447 65cef780 blueswir1
    /* Controller's version */
1448 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1449 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1450 65cef780 blueswir1
}
1451 65cef780 blueswir1
1452 65cef780 blueswir1
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1453 65cef780 blueswir1
{
1454 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1455 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1456 65cef780 blueswir1
}
1457 65cef780 blueswir1
1458 65cef780 blueswir1
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1459 65cef780 blueswir1
{
1460 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1461 65cef780 blueswir1
1462 65cef780 blueswir1
    /* Drives position */
1463 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1464 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1465 78ae820c blueswir1
#if MAX_FD == 4
1466 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1467 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1468 78ae820c blueswir1
#endif
1469 65cef780 blueswir1
    /* timers */
1470 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1471 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1472 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1473 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1474 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1475 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1476 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1477 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1478 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1479 65cef780 blueswir1
}
1480 65cef780 blueswir1
1481 65cef780 blueswir1
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1482 65cef780 blueswir1
{
1483 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1484 65cef780 blueswir1
1485 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1486 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1487 65cef780 blueswir1
    /* Drives position */
1488 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1489 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1490 78ae820c blueswir1
#if MAX_FD == 4
1491 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1492 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1493 78ae820c blueswir1
#else
1494 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1495 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1496 78ae820c blueswir1
#endif
1497 65cef780 blueswir1
    /* timers */
1498 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1499 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1500 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1501 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1502 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1503 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1504 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1505 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1506 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1507 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1508 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1509 65cef780 blueswir1
}
1510 65cef780 blueswir1
1511 65cef780 blueswir1
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1512 65cef780 blueswir1
{
1513 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1514 65cef780 blueswir1
1515 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1516 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1517 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1518 65cef780 blueswir1
                   qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1519 65cef780 blueswir1
}
1520 65cef780 blueswir1
1521 65cef780 blueswir1
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1522 65cef780 blueswir1
{
1523 65cef780 blueswir1
    fdrive_t *cur_drv;
1524 65cef780 blueswir1
1525 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1526 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1527 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1528 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1529 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1530 65cef780 blueswir1
    else
1531 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1532 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1533 65cef780 blueswir1
    cur_drv->bps =
1534 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1535 65cef780 blueswir1
#if 0
1536 65cef780 blueswir1
    cur_drv->last_sect =
1537 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1538 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1539 65cef780 blueswir1
#else
1540 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1541 65cef780 blueswir1
#endif
1542 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1543 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1544 65cef780 blueswir1
     * the sector with the specified fill byte
1545 65cef780 blueswir1
     */
1546 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1547 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1548 65cef780 blueswir1
}
1549 65cef780 blueswir1
1550 65cef780 blueswir1
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1551 65cef780 blueswir1
{
1552 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1553 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1554 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1555 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1556 368df94d blueswir1
    else
1557 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1558 65cef780 blueswir1
    /* No result back */
1559 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1560 65cef780 blueswir1
}
1561 65cef780 blueswir1
1562 65cef780 blueswir1
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1563 65cef780 blueswir1
{
1564 65cef780 blueswir1
    fdrive_t *cur_drv;
1565 65cef780 blueswir1
1566 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1567 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1568 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1569 65cef780 blueswir1
    /* 1 Byte status back */
1570 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1571 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1572 65cef780 blueswir1
        (cur_drv->head << 2) |
1573 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1574 65cef780 blueswir1
        0x28;
1575 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1576 65cef780 blueswir1
}
1577 65cef780 blueswir1
1578 65cef780 blueswir1
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1579 65cef780 blueswir1
{
1580 65cef780 blueswir1
    fdrive_t *cur_drv;
1581 65cef780 blueswir1
1582 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1583 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1584 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1585 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1586 65cef780 blueswir1
    /* Raise Interrupt */
1587 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1588 65cef780 blueswir1
}
1589 65cef780 blueswir1
1590 65cef780 blueswir1
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1591 65cef780 blueswir1
{
1592 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1593 65cef780 blueswir1
1594 65cef780 blueswir1
#if 0
1595 65cef780 blueswir1
    fdctrl->fifo[0] =
1596 cefec4f5 blueswir1
        fdctrl->status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1597 65cef780 blueswir1
#else
1598 77370520 blueswir1
    /* XXX: status0 handling is broken for read/write
1599 65cef780 blueswir1
       commands, so we do this hack. It should be suppressed
1600 65cef780 blueswir1
       ASAP */
1601 65cef780 blueswir1
    fdctrl->fifo[0] =
1602 cefec4f5 blueswir1
        FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1603 65cef780 blueswir1
#endif
1604 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1605 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1606 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1607 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1608 65cef780 blueswir1
}
1609 65cef780 blueswir1
1610 65cef780 blueswir1
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1611 65cef780 blueswir1
{
1612 65cef780 blueswir1
    fdrive_t *cur_drv;
1613 65cef780 blueswir1
1614 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1615 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1616 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1617 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1618 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1619 65cef780 blueswir1
    } else {
1620 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1621 65cef780 blueswir1
        /* Raise Interrupt */
1622 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1623 65cef780 blueswir1
    }
1624 65cef780 blueswir1
}
1625 65cef780 blueswir1
1626 65cef780 blueswir1
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1627 65cef780 blueswir1
{
1628 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1629 65cef780 blueswir1
1630 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1631 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1632 65cef780 blueswir1
    /* No result back */
1633 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1634 65cef780 blueswir1
}
1635 65cef780 blueswir1
1636 65cef780 blueswir1
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1637 65cef780 blueswir1
{
1638 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1639 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1640 65cef780 blueswir1
    /* No result back */
1641 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1642 65cef780 blueswir1
}
1643 65cef780 blueswir1
1644 65cef780 blueswir1
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1645 65cef780 blueswir1
{
1646 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1647 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1648 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1649 65cef780 blueswir1
}
1650 65cef780 blueswir1
1651 65cef780 blueswir1
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1652 65cef780 blueswir1
{
1653 65cef780 blueswir1
    /* No result back */
1654 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1655 65cef780 blueswir1
}
1656 65cef780 blueswir1
1657 65cef780 blueswir1
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1658 65cef780 blueswir1
{
1659 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1660 65cef780 blueswir1
1661 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1662 65cef780 blueswir1
        /* Command parameters done */
1663 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1664 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1665 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1666 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1667 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1668 65cef780 blueswir1
        } else {
1669 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1670 65cef780 blueswir1
        }
1671 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1672 65cef780 blueswir1
        /* ERROR */
1673 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1674 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1675 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1676 65cef780 blueswir1
    }
1677 65cef780 blueswir1
}
1678 65cef780 blueswir1
1679 65cef780 blueswir1
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1680 65cef780 blueswir1
{
1681 77370520 blueswir1
    fdrive_t *cur_drv;
1682 65cef780 blueswir1
1683 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1684 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1685 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1686 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1687 65cef780 blueswir1
    } else {
1688 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1689 65cef780 blueswir1
    }
1690 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1691 77370520 blueswir1
    /* Raise Interrupt */
1692 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1693 65cef780 blueswir1
}
1694 65cef780 blueswir1
1695 65cef780 blueswir1
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1696 65cef780 blueswir1
{
1697 77370520 blueswir1
    fdrive_t *cur_drv;
1698 65cef780 blueswir1
1699 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1700 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1701 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1702 65cef780 blueswir1
        cur_drv->track = 0;
1703 65cef780 blueswir1
    } else {
1704 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1705 65cef780 blueswir1
    }
1706 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1707 65cef780 blueswir1
    /* Raise Interrupt */
1708 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 65cef780 blueswir1
}
1710 65cef780 blueswir1
1711 678803ab blueswir1
static const struct {
1712 678803ab blueswir1
    uint8_t value;
1713 678803ab blueswir1
    uint8_t mask;
1714 678803ab blueswir1
    const char* name;
1715 678803ab blueswir1
    int parameters;
1716 678803ab blueswir1
    void (*handler)(fdctrl_t *fdctrl, int direction);
1717 678803ab blueswir1
    int direction;
1718 678803ab blueswir1
} handlers[] = {
1719 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1720 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1721 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1722 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1723 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1724 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1725 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1726 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1727 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1728 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1729 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1730 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1731 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1732 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1733 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1734 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1735 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1736 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1737 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1738 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1739 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1740 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1741 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1742 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1743 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1744 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1745 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1746 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1747 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1748 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1749 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1750 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1751 678803ab blueswir1
};
1752 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1753 678803ab blueswir1
static uint8_t command_to_handler[256];
1754 678803ab blueswir1
1755 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1756 baca51fa bellard
{
1757 baca51fa bellard
    fdrive_t *cur_drv;
1758 65cef780 blueswir1
    int pos;
1759 baca51fa bellard
1760 8977f3c1 bellard
    /* Reset mode */
1761 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1762 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1763 8977f3c1 bellard
        return;
1764 8977f3c1 bellard
    }
1765 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1766 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1767 8977f3c1 bellard
        return;
1768 8977f3c1 bellard
    }
1769 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1770 8977f3c1 bellard
    /* Is it write command time ? */
1771 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1772 8977f3c1 bellard
        /* FIFO data write */
1773 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1774 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1775 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1776 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1777 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1778 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1779 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1780 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1781 77370520 blueswir1
                return;
1782 77370520 blueswir1
            }
1783 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1784 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1785 746d6de7 blueswir1
                               fd_sector(cur_drv));
1786 746d6de7 blueswir1
                return;
1787 746d6de7 blueswir1
            }
1788 8977f3c1 bellard
        }
1789 890fa6be bellard
        /* Switch from transfer mode to status mode
1790 8977f3c1 bellard
         * then from status mode to command mode
1791 8977f3c1 bellard
         */
1792 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1793 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1794 8977f3c1 bellard
        return;
1795 8977f3c1 bellard
    }
1796 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1797 8977f3c1 bellard
        /* Command */
1798 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1799 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1800 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1801 8977f3c1 bellard
    }
1802 678803ab blueswir1
1803 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1804 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1805 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1806 8977f3c1 bellard
        /* We now have all parameters
1807 8977f3c1 bellard
         * and will be able to treat the command
1808 8977f3c1 bellard
         */
1809 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1810 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1811 8977f3c1 bellard
            return;
1812 8977f3c1 bellard
        }
1813 65cef780 blueswir1
1814 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1815 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1816 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1817 8977f3c1 bellard
    }
1818 8977f3c1 bellard
}
1819 ed5fd2cc bellard
1820 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1821 ed5fd2cc bellard
{
1822 ed5fd2cc bellard
    fdctrl_t *fdctrl = opaque;
1823 b7ffa3b1 ths
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1824 4f431960 j_mayer
1825 b7ffa3b1 ths
    /* Pretend we are spinning.
1826 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1827 b7ffa3b1 ths
     * sector interleaving.
1828 b7ffa3b1 ths
     */
1829 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1830 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1831 b7ffa3b1 ths
    }
1832 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1833 ed5fd2cc bellard
}
1834 678803ab blueswir1
1835 678803ab blueswir1
/* Init functions */
1836 678803ab blueswir1
static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1837 678803ab blueswir1
                                     target_phys_addr_t io_base,
1838 678803ab blueswir1
                                     BlockDriverState **fds)
1839 678803ab blueswir1
{
1840 678803ab blueswir1
    fdctrl_t *fdctrl;
1841 678803ab blueswir1
    int i, j;
1842 678803ab blueswir1
1843 678803ab blueswir1
    /* Fill 'command_to_handler' lookup table */
1844 678803ab blueswir1
    for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
1845 678803ab blueswir1
        for (j = 0; j < sizeof(command_to_handler); j++) {
1846 678803ab blueswir1
            if ((j & handlers[i].mask) == handlers[i].value)
1847 678803ab blueswir1
                command_to_handler[j] = i;
1848 678803ab blueswir1
        }
1849 678803ab blueswir1
    }
1850 678803ab blueswir1
1851 678803ab blueswir1
    FLOPPY_DPRINTF("init controller\n");
1852 678803ab blueswir1
    fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1853 678803ab blueswir1
    if (!fdctrl)
1854 678803ab blueswir1
        return NULL;
1855 678803ab blueswir1
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1856 678803ab blueswir1
    if (fdctrl->fifo == NULL) {
1857 678803ab blueswir1
        qemu_free(fdctrl);
1858 678803ab blueswir1
        return NULL;
1859 678803ab blueswir1
    }
1860 678803ab blueswir1
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1861 678803ab blueswir1
                                          fdctrl_result_timer, fdctrl);
1862 678803ab blueswir1
1863 678803ab blueswir1
    fdctrl->version = 0x90; /* Intel 82078 controller */
1864 678803ab blueswir1
    fdctrl->irq = irq;
1865 678803ab blueswir1
    fdctrl->dma_chann = dma_chann;
1866 678803ab blueswir1
    fdctrl->io_base = io_base;
1867 678803ab blueswir1
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1868 678803ab blueswir1
    if (fdctrl->dma_chann != -1) {
1869 678803ab blueswir1
        DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1870 678803ab blueswir1
    }
1871 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1872 678803ab blueswir1
        fd_init(&fdctrl->drives[i], fds[i]);
1873 678803ab blueswir1
    }
1874 77370520 blueswir1
    fdctrl_external_reset(fdctrl);
1875 77370520 blueswir1
    register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1876 678803ab blueswir1
    qemu_register_reset(fdctrl_external_reset, fdctrl);
1877 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1878 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1879 678803ab blueswir1
    }
1880 678803ab blueswir1
1881 678803ab blueswir1
    return fdctrl;
1882 678803ab blueswir1
}
1883 678803ab blueswir1
1884 678803ab blueswir1
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1885 678803ab blueswir1
                       target_phys_addr_t io_base,
1886 678803ab blueswir1
                       BlockDriverState **fds)
1887 678803ab blueswir1
{
1888 678803ab blueswir1
    fdctrl_t *fdctrl;
1889 678803ab blueswir1
    int io_mem;
1890 678803ab blueswir1
1891 678803ab blueswir1
    fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1892 678803ab blueswir1
1893 678803ab blueswir1
    fdctrl->sun4m = 0;
1894 678803ab blueswir1
    if (mem_mapped) {
1895 678803ab blueswir1
        io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1896 678803ab blueswir1
                                        fdctrl);
1897 678803ab blueswir1
        cpu_register_physical_memory(io_base, 0x08, io_mem);
1898 678803ab blueswir1
    } else {
1899 678803ab blueswir1
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1900 678803ab blueswir1
                             fdctrl);
1901 678803ab blueswir1
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1902 678803ab blueswir1
                             fdctrl);
1903 678803ab blueswir1
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1904 678803ab blueswir1
                              fdctrl);
1905 678803ab blueswir1
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1906 678803ab blueswir1
                              fdctrl);
1907 678803ab blueswir1
    }
1908 678803ab blueswir1
1909 678803ab blueswir1
    return fdctrl;
1910 678803ab blueswir1
}
1911 678803ab blueswir1
1912 678803ab blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1913 678803ab blueswir1
                             BlockDriverState **fds, qemu_irq *fdc_tc)
1914 678803ab blueswir1
{
1915 678803ab blueswir1
    fdctrl_t *fdctrl;
1916 678803ab blueswir1
    int io_mem;
1917 678803ab blueswir1
1918 368df94d blueswir1
    fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
1919 678803ab blueswir1
    fdctrl->sun4m = 1;
1920 678803ab blueswir1
    io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1921 678803ab blueswir1
                                    fdctrl_mem_write_strict,
1922 678803ab blueswir1
                                    fdctrl);
1923 678803ab blueswir1
    cpu_register_physical_memory(io_base, 0x08, io_mem);
1924 678803ab blueswir1
    *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1925 678803ab blueswir1
1926 678803ab blueswir1
    return fdctrl;
1927 678803ab blueswir1
}