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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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int gen_new_label(void); |
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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} |
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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} |
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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} |
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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} |
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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} |
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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} |
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
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TCGv_i32 arg2, TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
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TCGv_i64 arg2, TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
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TCGv_ptr base, TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
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TCGv_ptr base, TCGArg offset) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_PTR(base); |
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*gen_opparam_ptr++ = offset; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
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TCGv_i32 addr, TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I32(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
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TCGv_i64 addr, TCGArg mem_index) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(val); |
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*gen_opparam_ptr++ = GET_TCGV_I64(addr); |
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*gen_opparam_ptr++ = mem_index; |
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} |
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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} |
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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} |
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGArg arg3, TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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} |
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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} |
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
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TCGv_i32 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
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} |
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
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TCGv_i64 arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
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} |
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
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TCGv_i32 arg3, TCGv_i32 arg4, |
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TCGv_i32 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
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TCGv_i64 arg3, TCGv_i64 arg4, |
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TCGv_i64 arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
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TCGv_i32 arg2, TCGv_i32 arg3, |
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TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
321 |
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static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
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TCGv_i64 arg2, TCGv_i64 arg3, |
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TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
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*gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
334 |
|
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static inline void gen_set_label(int n) |
336 |
{ |
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tcg_gen_op1i(INDEX_op_set_label, n); |
338 |
} |
339 |
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static inline void tcg_gen_br(int label) |
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{ |
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tcg_gen_op1i(INDEX_op_br, label); |
343 |
} |
344 |
|
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
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{ |
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if (!TCGV_EQUAL_I32(ret, arg))
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tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
349 |
} |
350 |
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
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{ |
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tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
354 |
} |
355 |
|
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/* A version of dh_sizemask from def-helper.h that doesn't rely on
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preprocessor magic. */
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static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) |
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{ |
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return (is_64bit << n*2) | (is_signed << (n*2 + 1)); |
361 |
} |
362 |
|
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/* helper calls */
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static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
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TCGArg ret, int nargs, TCGArg *args)
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{ |
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TCGv_ptr fn; |
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fn = tcg_const_ptr((tcg_target_long)func); |
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tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
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nargs, args); |
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tcg_temp_free_ptr(fn); |
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} |
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|
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/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
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reserved for helpers in tcg-runtime.c. These helpers are all const
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and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
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TCG_CALL_PURE. This may need to be adjusted if these functions
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start to be used with other helpers. */
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static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
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TCGv_i32 a, TCGv_i32 b) |
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{ |
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TCGv_ptr fn; |
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TCGArg args[2];
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fn = tcg_const_ptr((tcg_target_long)func); |
385 |
args[0] = GET_TCGV_I32(a);
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args[1] = GET_TCGV_I32(b);
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tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
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GET_TCGV_I32(ret), 2, args);
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tcg_temp_free_ptr(fn); |
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} |
391 |
|
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static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
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TCGv_i64 a, TCGv_i64 b) |
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{ |
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TCGv_ptr fn; |
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TCGArg args[2];
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fn = tcg_const_ptr((tcg_target_long)func); |
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args[0] = GET_TCGV_I64(a);
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args[1] = GET_TCGV_I64(b);
|
400 |
tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
401 |
GET_TCGV_I64(ret), 2, args);
|
402 |
tcg_temp_free_ptr(fn); |
403 |
} |
404 |
|
405 |
/* 32 bit ops */
|
406 |
|
407 |
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
408 |
{ |
409 |
tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
410 |
} |
411 |
|
412 |
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
413 |
{ |
414 |
tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
415 |
} |
416 |
|
417 |
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
418 |
{ |
419 |
tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
420 |
} |
421 |
|
422 |
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
423 |
{ |
424 |
tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
425 |
} |
426 |
|
427 |
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
428 |
{ |
429 |
tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
430 |
} |
431 |
|
432 |
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
433 |
{ |
434 |
tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
435 |
} |
436 |
|
437 |
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
438 |
{ |
439 |
tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
440 |
} |
441 |
|
442 |
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
443 |
{ |
444 |
tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
445 |
} |
446 |
|
447 |
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
448 |
{ |
449 |
tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
450 |
} |
451 |
|
452 |
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
453 |
{ |
454 |
/* some cases can be optimized here */
|
455 |
if (arg2 == 0) { |
456 |
tcg_gen_mov_i32(ret, arg1); |
457 |
} else {
|
458 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
459 |
tcg_gen_add_i32(ret, arg1, t0); |
460 |
tcg_temp_free_i32(t0); |
461 |
} |
462 |
} |
463 |
|
464 |
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
465 |
{ |
466 |
tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
467 |
} |
468 |
|
469 |
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
470 |
{ |
471 |
TCGv_i32 t0 = tcg_const_i32(arg1); |
472 |
tcg_gen_sub_i32(ret, t0, arg2); |
473 |
tcg_temp_free_i32(t0); |
474 |
} |
475 |
|
476 |
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
477 |
{ |
478 |
/* some cases can be optimized here */
|
479 |
if (arg2 == 0) { |
480 |
tcg_gen_mov_i32(ret, arg1); |
481 |
} else {
|
482 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
483 |
tcg_gen_sub_i32(ret, arg1, t0); |
484 |
tcg_temp_free_i32(t0); |
485 |
} |
486 |
} |
487 |
|
488 |
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
489 |
{ |
490 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
491 |
tcg_gen_mov_i32(ret, arg1); |
492 |
} else {
|
493 |
tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
494 |
} |
495 |
} |
496 |
|
497 |
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
498 |
{ |
499 |
/* some cases can be optimized here */
|
500 |
if (arg2 == 0) { |
501 |
tcg_gen_movi_i32(ret, 0);
|
502 |
} else if (arg2 == 0xffffffff) { |
503 |
tcg_gen_mov_i32(ret, arg1); |
504 |
} else {
|
505 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
506 |
tcg_gen_and_i32(ret, arg1, t0); |
507 |
tcg_temp_free_i32(t0); |
508 |
} |
509 |
} |
510 |
|
511 |
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
512 |
{ |
513 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
514 |
tcg_gen_mov_i32(ret, arg1); |
515 |
} else {
|
516 |
tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
517 |
} |
518 |
} |
519 |
|
520 |
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
521 |
{ |
522 |
/* some cases can be optimized here */
|
523 |
if (arg2 == 0xffffffff) { |
524 |
tcg_gen_movi_i32(ret, 0xffffffff);
|
525 |
} else if (arg2 == 0) { |
526 |
tcg_gen_mov_i32(ret, arg1); |
527 |
} else {
|
528 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
529 |
tcg_gen_or_i32(ret, arg1, t0); |
530 |
tcg_temp_free_i32(t0); |
531 |
} |
532 |
} |
533 |
|
534 |
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
535 |
{ |
536 |
if (TCGV_EQUAL_I32(arg1, arg2)) {
|
537 |
tcg_gen_movi_i32(ret, 0);
|
538 |
} else {
|
539 |
tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
540 |
} |
541 |
} |
542 |
|
543 |
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
544 |
{ |
545 |
/* some cases can be optimized here */
|
546 |
if (arg2 == 0) { |
547 |
tcg_gen_mov_i32(ret, arg1); |
548 |
} else {
|
549 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
550 |
tcg_gen_xor_i32(ret, arg1, t0); |
551 |
tcg_temp_free_i32(t0); |
552 |
} |
553 |
} |
554 |
|
555 |
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
556 |
{ |
557 |
tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
558 |
} |
559 |
|
560 |
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
561 |
{ |
562 |
if (arg2 == 0) { |
563 |
tcg_gen_mov_i32(ret, arg1); |
564 |
} else {
|
565 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
566 |
tcg_gen_shl_i32(ret, arg1, t0); |
567 |
tcg_temp_free_i32(t0); |
568 |
} |
569 |
} |
570 |
|
571 |
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
572 |
{ |
573 |
tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
574 |
} |
575 |
|
576 |
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
577 |
{ |
578 |
if (arg2 == 0) { |
579 |
tcg_gen_mov_i32(ret, arg1); |
580 |
} else {
|
581 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
582 |
tcg_gen_shr_i32(ret, arg1, t0); |
583 |
tcg_temp_free_i32(t0); |
584 |
} |
585 |
} |
586 |
|
587 |
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
588 |
{ |
589 |
tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
590 |
} |
591 |
|
592 |
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
593 |
{ |
594 |
if (arg2 == 0) { |
595 |
tcg_gen_mov_i32(ret, arg1); |
596 |
} else {
|
597 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
598 |
tcg_gen_sar_i32(ret, arg1, t0); |
599 |
tcg_temp_free_i32(t0); |
600 |
} |
601 |
} |
602 |
|
603 |
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
604 |
TCGv_i32 arg2, int label_index)
|
605 |
{ |
606 |
tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
607 |
} |
608 |
|
609 |
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
610 |
int32_t arg2, int label_index)
|
611 |
{ |
612 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
613 |
tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
614 |
tcg_temp_free_i32(t0); |
615 |
} |
616 |
|
617 |
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
618 |
TCGv_i32 arg1, TCGv_i32 arg2) |
619 |
{ |
620 |
tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
621 |
} |
622 |
|
623 |
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
624 |
TCGv_i32 arg1, int32_t arg2) |
625 |
{ |
626 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
627 |
tcg_gen_setcond_i32(cond, ret, arg1, t0); |
628 |
tcg_temp_free_i32(t0); |
629 |
} |
630 |
|
631 |
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
632 |
{ |
633 |
tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
634 |
} |
635 |
|
636 |
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
637 |
{ |
638 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
639 |
tcg_gen_mul_i32(ret, arg1, t0); |
640 |
tcg_temp_free_i32(t0); |
641 |
} |
642 |
|
643 |
#ifdef TCG_TARGET_HAS_div_i32
|
644 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
645 |
{ |
646 |
tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
647 |
} |
648 |
|
649 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
650 |
{ |
651 |
tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
652 |
} |
653 |
|
654 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
655 |
{ |
656 |
tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
657 |
} |
658 |
|
659 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
660 |
{ |
661 |
tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
662 |
} |
663 |
#elif defined(TCG_TARGET_HAS_div2_i32)
|
664 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
665 |
{ |
666 |
TCGv_i32 t0; |
667 |
t0 = tcg_temp_new_i32(); |
668 |
tcg_gen_sari_i32(t0, arg1, 31);
|
669 |
tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
670 |
tcg_temp_free_i32(t0); |
671 |
} |
672 |
|
673 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
674 |
{ |
675 |
TCGv_i32 t0; |
676 |
t0 = tcg_temp_new_i32(); |
677 |
tcg_gen_sari_i32(t0, arg1, 31);
|
678 |
tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
679 |
tcg_temp_free_i32(t0); |
680 |
} |
681 |
|
682 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
683 |
{ |
684 |
TCGv_i32 t0; |
685 |
t0 = tcg_temp_new_i32(); |
686 |
tcg_gen_movi_i32(t0, 0);
|
687 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
688 |
tcg_temp_free_i32(t0); |
689 |
} |
690 |
|
691 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
692 |
{ |
693 |
TCGv_i32 t0; |
694 |
t0 = tcg_temp_new_i32(); |
695 |
tcg_gen_movi_i32(t0, 0);
|
696 |
tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
697 |
tcg_temp_free_i32(t0); |
698 |
} |
699 |
#else
|
700 |
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
701 |
{ |
702 |
int sizemask = 0; |
703 |
/* Return value and both arguments are 32-bit and signed. */
|
704 |
sizemask |= tcg_gen_sizemask(0, 0, 1); |
705 |
sizemask |= tcg_gen_sizemask(1, 0, 1); |
706 |
sizemask |= tcg_gen_sizemask(2, 0, 1); |
707 |
|
708 |
tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); |
709 |
} |
710 |
|
711 |
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
712 |
{ |
713 |
int sizemask = 0; |
714 |
/* Return value and both arguments are 32-bit and signed. */
|
715 |
sizemask |= tcg_gen_sizemask(0, 0, 1); |
716 |
sizemask |= tcg_gen_sizemask(1, 0, 1); |
717 |
sizemask |= tcg_gen_sizemask(2, 0, 1); |
718 |
|
719 |
tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); |
720 |
} |
721 |
|
722 |
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
723 |
{ |
724 |
int sizemask = 0; |
725 |
/* Return value and both arguments are 32-bit and unsigned. */
|
726 |
sizemask |= tcg_gen_sizemask(0, 0, 0); |
727 |
sizemask |= tcg_gen_sizemask(1, 0, 0); |
728 |
sizemask |= tcg_gen_sizemask(2, 0, 0); |
729 |
|
730 |
tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2, 0);
|
731 |
} |
732 |
|
733 |
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
734 |
{ |
735 |
int sizemask = 0; |
736 |
/* Return value and both arguments are 32-bit and unsigned. */
|
737 |
sizemask |= tcg_gen_sizemask(0, 0, 0); |
738 |
sizemask |= tcg_gen_sizemask(1, 0, 0); |
739 |
sizemask |= tcg_gen_sizemask(2, 0, 0); |
740 |
|
741 |
tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2, 0);
|
742 |
} |
743 |
#endif
|
744 |
|
745 |
#if TCG_TARGET_REG_BITS == 32 |
746 |
|
747 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
748 |
{ |
749 |
if (!TCGV_EQUAL_I64(ret, arg)) {
|
750 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
751 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
752 |
} |
753 |
} |
754 |
|
755 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
756 |
{ |
757 |
tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
758 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
759 |
} |
760 |
|
761 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
762 |
tcg_target_long offset) |
763 |
{ |
764 |
tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
765 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
766 |
} |
767 |
|
768 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
769 |
tcg_target_long offset) |
770 |
{ |
771 |
tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
772 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
|
773 |
} |
774 |
|
775 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
776 |
tcg_target_long offset) |
777 |
{ |
778 |
tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
779 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
780 |
} |
781 |
|
782 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
783 |
tcg_target_long offset) |
784 |
{ |
785 |
tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
786 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
787 |
} |
788 |
|
789 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
790 |
tcg_target_long offset) |
791 |
{ |
792 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
793 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
794 |
} |
795 |
|
796 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
797 |
tcg_target_long offset) |
798 |
{ |
799 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
800 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
801 |
} |
802 |
|
803 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
804 |
tcg_target_long offset) |
805 |
{ |
806 |
/* since arg2 and ret have different types, they cannot be the
|
807 |
same temporary */
|
808 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
809 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
810 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
|
811 |
#else
|
812 |
tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
813 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
814 |
#endif
|
815 |
} |
816 |
|
817 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
818 |
tcg_target_long offset) |
819 |
{ |
820 |
tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
821 |
} |
822 |
|
823 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
824 |
tcg_target_long offset) |
825 |
{ |
826 |
tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
827 |
} |
828 |
|
829 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
830 |
tcg_target_long offset) |
831 |
{ |
832 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
833 |
} |
834 |
|
835 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
836 |
tcg_target_long offset) |
837 |
{ |
838 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
839 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
840 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
|
841 |
#else
|
842 |
tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
843 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
844 |
#endif
|
845 |
} |
846 |
|
847 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
848 |
{ |
849 |
tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
850 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
851 |
TCGV_HIGH(arg2)); |
852 |
} |
853 |
|
854 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
855 |
{ |
856 |
tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
857 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
858 |
TCGV_HIGH(arg2)); |
859 |
} |
860 |
|
861 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
862 |
{ |
863 |
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
864 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
865 |
} |
866 |
|
867 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
868 |
{ |
869 |
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
870 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
871 |
} |
872 |
|
873 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
874 |
{ |
875 |
tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
876 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
877 |
} |
878 |
|
879 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
880 |
{ |
881 |
tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
882 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
883 |
} |
884 |
|
885 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
886 |
{ |
887 |
tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
888 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
889 |
} |
890 |
|
891 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
892 |
{ |
893 |
tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
894 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
895 |
} |
896 |
|
897 |
/* XXX: use generic code when basic block handling is OK or CPU
|
898 |
specific code (x86) */
|
899 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
900 |
{ |
901 |
int sizemask = 0; |
902 |
/* Return value and both arguments are 64-bit and signed. */
|
903 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
904 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
905 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
906 |
|
907 |
tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); |
908 |
} |
909 |
|
910 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
911 |
{ |
912 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
913 |
} |
914 |
|
915 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
916 |
{ |
917 |
int sizemask = 0; |
918 |
/* Return value and both arguments are 64-bit and signed. */
|
919 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
920 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
921 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
922 |
|
923 |
tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); |
924 |
} |
925 |
|
926 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
927 |
{ |
928 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
929 |
} |
930 |
|
931 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
932 |
{ |
933 |
int sizemask = 0; |
934 |
/* Return value and both arguments are 64-bit and signed. */
|
935 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
936 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
937 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
938 |
|
939 |
tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); |
940 |
} |
941 |
|
942 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
943 |
{ |
944 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
945 |
} |
946 |
|
947 |
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
948 |
TCGv_i64 arg2, int label_index)
|
949 |
{ |
950 |
tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
951 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
952 |
TCGV_HIGH(arg2), cond, label_index); |
953 |
} |
954 |
|
955 |
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
956 |
TCGv_i64 arg1, TCGv_i64 arg2) |
957 |
{ |
958 |
tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
959 |
TCGV_LOW(arg1), TCGV_HIGH(arg1), |
960 |
TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
961 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
962 |
} |
963 |
|
964 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
965 |
{ |
966 |
TCGv_i64 t0; |
967 |
TCGv_i32 t1; |
968 |
|
969 |
t0 = tcg_temp_new_i64(); |
970 |
t1 = tcg_temp_new_i32(); |
971 |
|
972 |
tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
973 |
TCGV_LOW(arg1), TCGV_LOW(arg2)); |
974 |
|
975 |
tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
976 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
977 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
978 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
979 |
|
980 |
tcg_gen_mov_i64(ret, t0); |
981 |
tcg_temp_free_i64(t0); |
982 |
tcg_temp_free_i32(t1); |
983 |
} |
984 |
|
985 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
986 |
{ |
987 |
int sizemask = 0; |
988 |
/* Return value and both arguments are 64-bit and signed. */
|
989 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
990 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
991 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
992 |
|
993 |
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
994 |
} |
995 |
|
996 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
997 |
{ |
998 |
int sizemask = 0; |
999 |
/* Return value and both arguments are 64-bit and signed. */
|
1000 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
1001 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1002 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1003 |
|
1004 |
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
1005 |
} |
1006 |
|
1007 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1008 |
{ |
1009 |
int sizemask = 0; |
1010 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1011 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1012 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1013 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1014 |
|
1015 |
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
1016 |
} |
1017 |
|
1018 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1019 |
{ |
1020 |
int sizemask = 0; |
1021 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1022 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1023 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1024 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1025 |
|
1026 |
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
1027 |
} |
1028 |
|
1029 |
#else
|
1030 |
|
1031 |
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
1032 |
{ |
1033 |
if (!TCGV_EQUAL_I64(ret, arg))
|
1034 |
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
1035 |
} |
1036 |
|
1037 |
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
1038 |
{ |
1039 |
tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
1040 |
} |
1041 |
|
1042 |
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1043 |
tcg_target_long offset) |
1044 |
{ |
1045 |
tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
1046 |
} |
1047 |
|
1048 |
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1049 |
tcg_target_long offset) |
1050 |
{ |
1051 |
tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
1052 |
} |
1053 |
|
1054 |
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1055 |
tcg_target_long offset) |
1056 |
{ |
1057 |
tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
1058 |
} |
1059 |
|
1060 |
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1061 |
tcg_target_long offset) |
1062 |
{ |
1063 |
tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
1064 |
} |
1065 |
|
1066 |
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1067 |
tcg_target_long offset) |
1068 |
{ |
1069 |
tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
1070 |
} |
1071 |
|
1072 |
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2, |
1073 |
tcg_target_long offset) |
1074 |
{ |
1075 |
tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
1076 |
} |
1077 |
|
1078 |
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset) |
1079 |
{ |
1080 |
tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
1081 |
} |
1082 |
|
1083 |
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1084 |
tcg_target_long offset) |
1085 |
{ |
1086 |
tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
1087 |
} |
1088 |
|
1089 |
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1090 |
tcg_target_long offset) |
1091 |
{ |
1092 |
tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
1093 |
} |
1094 |
|
1095 |
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2, |
1096 |
tcg_target_long offset) |
1097 |
{ |
1098 |
tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
1099 |
} |
1100 |
|
1101 |
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset) |
1102 |
{ |
1103 |
tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
1104 |
} |
1105 |
|
1106 |
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1107 |
{ |
1108 |
tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
1109 |
} |
1110 |
|
1111 |
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1112 |
{ |
1113 |
tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
1114 |
} |
1115 |
|
1116 |
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1117 |
{ |
1118 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1119 |
tcg_gen_mov_i64(ret, arg1); |
1120 |
} else {
|
1121 |
tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
1122 |
} |
1123 |
} |
1124 |
|
1125 |
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1126 |
{ |
1127 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1128 |
tcg_gen_and_i64(ret, arg1, t0); |
1129 |
tcg_temp_free_i64(t0); |
1130 |
} |
1131 |
|
1132 |
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1133 |
{ |
1134 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1135 |
tcg_gen_mov_i64(ret, arg1); |
1136 |
} else {
|
1137 |
tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
1138 |
} |
1139 |
} |
1140 |
|
1141 |
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1142 |
{ |
1143 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1144 |
tcg_gen_or_i64(ret, arg1, t0); |
1145 |
tcg_temp_free_i64(t0); |
1146 |
} |
1147 |
|
1148 |
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1149 |
{ |
1150 |
if (TCGV_EQUAL_I64(arg1, arg2)) {
|
1151 |
tcg_gen_movi_i64(ret, 0);
|
1152 |
} else {
|
1153 |
tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
1154 |
} |
1155 |
} |
1156 |
|
1157 |
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1158 |
{ |
1159 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1160 |
tcg_gen_xor_i64(ret, arg1, t0); |
1161 |
tcg_temp_free_i64(t0); |
1162 |
} |
1163 |
|
1164 |
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1165 |
{ |
1166 |
tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
1167 |
} |
1168 |
|
1169 |
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1170 |
{ |
1171 |
if (arg2 == 0) { |
1172 |
tcg_gen_mov_i64(ret, arg1); |
1173 |
} else {
|
1174 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1175 |
tcg_gen_shl_i64(ret, arg1, t0); |
1176 |
tcg_temp_free_i64(t0); |
1177 |
} |
1178 |
} |
1179 |
|
1180 |
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1181 |
{ |
1182 |
tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
1183 |
} |
1184 |
|
1185 |
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1186 |
{ |
1187 |
if (arg2 == 0) { |
1188 |
tcg_gen_mov_i64(ret, arg1); |
1189 |
} else {
|
1190 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1191 |
tcg_gen_shr_i64(ret, arg1, t0); |
1192 |
tcg_temp_free_i64(t0); |
1193 |
} |
1194 |
} |
1195 |
|
1196 |
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1197 |
{ |
1198 |
tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
1199 |
} |
1200 |
|
1201 |
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1202 |
{ |
1203 |
if (arg2 == 0) { |
1204 |
tcg_gen_mov_i64(ret, arg1); |
1205 |
} else {
|
1206 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1207 |
tcg_gen_sar_i64(ret, arg1, t0); |
1208 |
tcg_temp_free_i64(t0); |
1209 |
} |
1210 |
} |
1211 |
|
1212 |
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
1213 |
TCGv_i64 arg2, int label_index)
|
1214 |
{ |
1215 |
tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
1216 |
} |
1217 |
|
1218 |
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
1219 |
TCGv_i64 arg1, TCGv_i64 arg2) |
1220 |
{ |
1221 |
tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
1222 |
} |
1223 |
|
1224 |
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1225 |
{ |
1226 |
tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
1227 |
} |
1228 |
|
1229 |
#ifdef TCG_TARGET_HAS_div_i64
|
1230 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1231 |
{ |
1232 |
tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
1233 |
} |
1234 |
|
1235 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1236 |
{ |
1237 |
tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
1238 |
} |
1239 |
|
1240 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1241 |
{ |
1242 |
tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
1243 |
} |
1244 |
|
1245 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1246 |
{ |
1247 |
tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
1248 |
} |
1249 |
#elif defined(TCG_TARGET_HAS_div2_i64)
|
1250 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1251 |
{ |
1252 |
TCGv_i64 t0; |
1253 |
t0 = tcg_temp_new_i64(); |
1254 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1255 |
tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
1256 |
tcg_temp_free_i64(t0); |
1257 |
} |
1258 |
|
1259 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1260 |
{ |
1261 |
TCGv_i64 t0; |
1262 |
t0 = tcg_temp_new_i64(); |
1263 |
tcg_gen_sari_i64(t0, arg1, 63);
|
1264 |
tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
1265 |
tcg_temp_free_i64(t0); |
1266 |
} |
1267 |
|
1268 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1269 |
{ |
1270 |
TCGv_i64 t0; |
1271 |
t0 = tcg_temp_new_i64(); |
1272 |
tcg_gen_movi_i64(t0, 0);
|
1273 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
1274 |
tcg_temp_free_i64(t0); |
1275 |
} |
1276 |
|
1277 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1278 |
{ |
1279 |
TCGv_i64 t0; |
1280 |
t0 = tcg_temp_new_i64(); |
1281 |
tcg_gen_movi_i64(t0, 0);
|
1282 |
tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
1283 |
tcg_temp_free_i64(t0); |
1284 |
} |
1285 |
#else
|
1286 |
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1287 |
{ |
1288 |
int sizemask = 0; |
1289 |
/* Return value and both arguments are 64-bit and signed. */
|
1290 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
1291 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1292 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1293 |
|
1294 |
tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
1295 |
} |
1296 |
|
1297 |
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1298 |
{ |
1299 |
int sizemask = 0; |
1300 |
/* Return value and both arguments are 64-bit and signed. */
|
1301 |
sizemask |= tcg_gen_sizemask(0, 1, 1); |
1302 |
sizemask |= tcg_gen_sizemask(1, 1, 1); |
1303 |
sizemask |= tcg_gen_sizemask(2, 1, 1); |
1304 |
|
1305 |
tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
1306 |
} |
1307 |
|
1308 |
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1309 |
{ |
1310 |
int sizemask = 0; |
1311 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1312 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1313 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1314 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1315 |
|
1316 |
tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
1317 |
} |
1318 |
|
1319 |
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1320 |
{ |
1321 |
int sizemask = 0; |
1322 |
/* Return value and both arguments are 64-bit and unsigned. */
|
1323 |
sizemask |= tcg_gen_sizemask(0, 1, 0); |
1324 |
sizemask |= tcg_gen_sizemask(1, 1, 0); |
1325 |
sizemask |= tcg_gen_sizemask(2, 1, 0); |
1326 |
|
1327 |
tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
1328 |
} |
1329 |
#endif
|
1330 |
|
1331 |
#endif
|
1332 |
|
1333 |
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1334 |
{ |
1335 |
/* some cases can be optimized here */
|
1336 |
if (arg2 == 0) { |
1337 |
tcg_gen_mov_i64(ret, arg1); |
1338 |
} else {
|
1339 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1340 |
tcg_gen_add_i64(ret, arg1, t0); |
1341 |
tcg_temp_free_i64(t0); |
1342 |
} |
1343 |
} |
1344 |
|
1345 |
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
1346 |
{ |
1347 |
TCGv_i64 t0 = tcg_const_i64(arg1); |
1348 |
tcg_gen_sub_i64(ret, t0, arg2); |
1349 |
tcg_temp_free_i64(t0); |
1350 |
} |
1351 |
|
1352 |
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1353 |
{ |
1354 |
/* some cases can be optimized here */
|
1355 |
if (arg2 == 0) { |
1356 |
tcg_gen_mov_i64(ret, arg1); |
1357 |
} else {
|
1358 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1359 |
tcg_gen_sub_i64(ret, arg1, t0); |
1360 |
tcg_temp_free_i64(t0); |
1361 |
} |
1362 |
} |
1363 |
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
1364 |
int64_t arg2, int label_index)
|
1365 |
{ |
1366 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1367 |
tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
1368 |
tcg_temp_free_i64(t0); |
1369 |
} |
1370 |
|
1371 |
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
1372 |
TCGv_i64 arg1, int64_t arg2) |
1373 |
{ |
1374 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1375 |
tcg_gen_setcond_i64(cond, ret, arg1, t0); |
1376 |
tcg_temp_free_i64(t0); |
1377 |
} |
1378 |
|
1379 |
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1380 |
{ |
1381 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
1382 |
tcg_gen_mul_i64(ret, arg1, t0); |
1383 |
tcg_temp_free_i64(t0); |
1384 |
} |
1385 |
|
1386 |
|
1387 |
/***************************************/
|
1388 |
/* optional operations */
|
1389 |
|
1390 |
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1391 |
{ |
1392 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
1393 |
tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
1394 |
#else
|
1395 |
tcg_gen_shli_i32(ret, arg, 24);
|
1396 |
tcg_gen_sari_i32(ret, ret, 24);
|
1397 |
#endif
|
1398 |
} |
1399 |
|
1400 |
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
1401 |
{ |
1402 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
1403 |
tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
1404 |
#else
|
1405 |
tcg_gen_shli_i32(ret, arg, 16);
|
1406 |
tcg_gen_sari_i32(ret, ret, 16);
|
1407 |
#endif
|
1408 |
} |
1409 |
|
1410 |
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1411 |
{ |
1412 |
#ifdef TCG_TARGET_HAS_ext8u_i32
|
1413 |
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
1414 |
#else
|
1415 |
tcg_gen_andi_i32(ret, arg, 0xffu);
|
1416 |
#endif
|
1417 |
} |
1418 |
|
1419 |
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
1420 |
{ |
1421 |
#ifdef TCG_TARGET_HAS_ext16u_i32
|
1422 |
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
1423 |
#else
|
1424 |
tcg_gen_andi_i32(ret, arg, 0xffffu);
|
1425 |
#endif
|
1426 |
} |
1427 |
|
1428 |
/* Note: we assume the two high bytes are set to zero */
|
1429 |
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
1430 |
{ |
1431 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
1432 |
tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
1433 |
#else
|
1434 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
1435 |
|
1436 |
tcg_gen_ext8u_i32(t0, arg); |
1437 |
tcg_gen_shli_i32(t0, t0, 8);
|
1438 |
tcg_gen_shri_i32(ret, arg, 8);
|
1439 |
tcg_gen_or_i32(ret, ret, t0); |
1440 |
tcg_temp_free_i32(t0); |
1441 |
#endif
|
1442 |
} |
1443 |
|
1444 |
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
1445 |
{ |
1446 |
#ifdef TCG_TARGET_HAS_bswap32_i32
|
1447 |
tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
1448 |
#else
|
1449 |
TCGv_i32 t0, t1; |
1450 |
t0 = tcg_temp_new_i32(); |
1451 |
t1 = tcg_temp_new_i32(); |
1452 |
|
1453 |
tcg_gen_shli_i32(t0, arg, 24);
|
1454 |
|
1455 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
1456 |
tcg_gen_shli_i32(t1, t1, 8);
|
1457 |
tcg_gen_or_i32(t0, t0, t1); |
1458 |
|
1459 |
tcg_gen_shri_i32(t1, arg, 8);
|
1460 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
1461 |
tcg_gen_or_i32(t0, t0, t1); |
1462 |
|
1463 |
tcg_gen_shri_i32(t1, arg, 24);
|
1464 |
tcg_gen_or_i32(ret, t0, t1); |
1465 |
tcg_temp_free_i32(t0); |
1466 |
tcg_temp_free_i32(t1); |
1467 |
#endif
|
1468 |
} |
1469 |
|
1470 |
#if TCG_TARGET_REG_BITS == 32 |
1471 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1472 |
{ |
1473 |
tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1474 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1475 |
} |
1476 |
|
1477 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1478 |
{ |
1479 |
tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1480 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1481 |
} |
1482 |
|
1483 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1484 |
{ |
1485 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1486 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1487 |
} |
1488 |
|
1489 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1490 |
{ |
1491 |
tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1492 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1493 |
} |
1494 |
|
1495 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1496 |
{ |
1497 |
tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1498 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1499 |
} |
1500 |
|
1501 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1502 |
{ |
1503 |
tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1504 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1505 |
} |
1506 |
|
1507 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1508 |
{ |
1509 |
tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
1510 |
} |
1511 |
|
1512 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1513 |
{ |
1514 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1515 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1516 |
} |
1517 |
|
1518 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1519 |
{ |
1520 |
tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
1521 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
1522 |
} |
1523 |
|
1524 |
/* Note: we assume the six high bytes are set to zero */
|
1525 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1526 |
{ |
1527 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1528 |
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1529 |
} |
1530 |
|
1531 |
/* Note: we assume the four high bytes are set to zero */
|
1532 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1533 |
{ |
1534 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1535 |
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1536 |
} |
1537 |
|
1538 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1539 |
{ |
1540 |
TCGv_i32 t0, t1; |
1541 |
t0 = tcg_temp_new_i32(); |
1542 |
t1 = tcg_temp_new_i32(); |
1543 |
|
1544 |
tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
1545 |
tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
1546 |
tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
1547 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1548 |
tcg_temp_free_i32(t0); |
1549 |
tcg_temp_free_i32(t1); |
1550 |
} |
1551 |
#else
|
1552 |
|
1553 |
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1554 |
{ |
1555 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
1556 |
tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
1557 |
#else
|
1558 |
tcg_gen_shli_i64(ret, arg, 56);
|
1559 |
tcg_gen_sari_i64(ret, ret, 56);
|
1560 |
#endif
|
1561 |
} |
1562 |
|
1563 |
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1564 |
{ |
1565 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
1566 |
tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
1567 |
#else
|
1568 |
tcg_gen_shli_i64(ret, arg, 48);
|
1569 |
tcg_gen_sari_i64(ret, ret, 48);
|
1570 |
#endif
|
1571 |
} |
1572 |
|
1573 |
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
1574 |
{ |
1575 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
1576 |
tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
1577 |
#else
|
1578 |
tcg_gen_shli_i64(ret, arg, 32);
|
1579 |
tcg_gen_sari_i64(ret, ret, 32);
|
1580 |
#endif
|
1581 |
} |
1582 |
|
1583 |
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1584 |
{ |
1585 |
#ifdef TCG_TARGET_HAS_ext8u_i64
|
1586 |
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
1587 |
#else
|
1588 |
tcg_gen_andi_i64(ret, arg, 0xffu);
|
1589 |
#endif
|
1590 |
} |
1591 |
|
1592 |
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1593 |
{ |
1594 |
#ifdef TCG_TARGET_HAS_ext16u_i64
|
1595 |
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
1596 |
#else
|
1597 |
tcg_gen_andi_i64(ret, arg, 0xffffu);
|
1598 |
#endif
|
1599 |
} |
1600 |
|
1601 |
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
1602 |
{ |
1603 |
#ifdef TCG_TARGET_HAS_ext32u_i64
|
1604 |
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
1605 |
#else
|
1606 |
tcg_gen_andi_i64(ret, arg, 0xffffffffu);
|
1607 |
#endif
|
1608 |
} |
1609 |
|
1610 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1611 |
registers. This will probably break MIPS64 targets. */
|
1612 |
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
1613 |
{ |
1614 |
tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
1615 |
} |
1616 |
|
1617 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1618 |
registers */
|
1619 |
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1620 |
{ |
1621 |
tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1622 |
} |
1623 |
|
1624 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1625 |
registers */
|
1626 |
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
1627 |
{ |
1628 |
tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
1629 |
} |
1630 |
|
1631 |
/* Note: we assume the six high bytes are set to zero */
|
1632 |
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
1633 |
{ |
1634 |
#ifdef TCG_TARGET_HAS_bswap16_i64
|
1635 |
tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
1636 |
#else
|
1637 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1638 |
|
1639 |
tcg_gen_ext8u_i64(t0, arg); |
1640 |
tcg_gen_shli_i64(t0, t0, 8);
|
1641 |
tcg_gen_shri_i64(ret, arg, 8);
|
1642 |
tcg_gen_or_i64(ret, ret, t0); |
1643 |
tcg_temp_free_i64(t0); |
1644 |
#endif
|
1645 |
} |
1646 |
|
1647 |
/* Note: we assume the four high bytes are set to zero */
|
1648 |
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
1649 |
{ |
1650 |
#ifdef TCG_TARGET_HAS_bswap32_i64
|
1651 |
tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
1652 |
#else
|
1653 |
TCGv_i64 t0, t1; |
1654 |
t0 = tcg_temp_new_i64(); |
1655 |
t1 = tcg_temp_new_i64(); |
1656 |
|
1657 |
tcg_gen_shli_i64(t0, arg, 24);
|
1658 |
tcg_gen_ext32u_i64(t0, t0); |
1659 |
|
1660 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1661 |
tcg_gen_shli_i64(t1, t1, 8);
|
1662 |
tcg_gen_or_i64(t0, t0, t1); |
1663 |
|
1664 |
tcg_gen_shri_i64(t1, arg, 8);
|
1665 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1666 |
tcg_gen_or_i64(t0, t0, t1); |
1667 |
|
1668 |
tcg_gen_shri_i64(t1, arg, 24);
|
1669 |
tcg_gen_or_i64(ret, t0, t1); |
1670 |
tcg_temp_free_i64(t0); |
1671 |
tcg_temp_free_i64(t1); |
1672 |
#endif
|
1673 |
} |
1674 |
|
1675 |
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
1676 |
{ |
1677 |
#ifdef TCG_TARGET_HAS_bswap64_i64
|
1678 |
tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
1679 |
#else
|
1680 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
1681 |
TCGv_i64 t1 = tcg_temp_new_i64(); |
1682 |
|
1683 |
tcg_gen_shli_i64(t0, arg, 56);
|
1684 |
|
1685 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1686 |
tcg_gen_shli_i64(t1, t1, 40);
|
1687 |
tcg_gen_or_i64(t0, t0, t1); |
1688 |
|
1689 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1690 |
tcg_gen_shli_i64(t1, t1, 24);
|
1691 |
tcg_gen_or_i64(t0, t0, t1); |
1692 |
|
1693 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1694 |
tcg_gen_shli_i64(t1, t1, 8);
|
1695 |
tcg_gen_or_i64(t0, t0, t1); |
1696 |
|
1697 |
tcg_gen_shri_i64(t1, arg, 8);
|
1698 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1699 |
tcg_gen_or_i64(t0, t0, t1); |
1700 |
|
1701 |
tcg_gen_shri_i64(t1, arg, 24);
|
1702 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1703 |
tcg_gen_or_i64(t0, t0, t1); |
1704 |
|
1705 |
tcg_gen_shri_i64(t1, arg, 40);
|
1706 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1707 |
tcg_gen_or_i64(t0, t0, t1); |
1708 |
|
1709 |
tcg_gen_shri_i64(t1, arg, 56);
|
1710 |
tcg_gen_or_i64(ret, t0, t1); |
1711 |
tcg_temp_free_i64(t0); |
1712 |
tcg_temp_free_i64(t1); |
1713 |
#endif
|
1714 |
} |
1715 |
|
1716 |
#endif
|
1717 |
|
1718 |
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
1719 |
{ |
1720 |
#ifdef TCG_TARGET_HAS_neg_i32
|
1721 |
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
1722 |
#else
|
1723 |
TCGv_i32 t0 = tcg_const_i32(0);
|
1724 |
tcg_gen_sub_i32(ret, t0, arg); |
1725 |
tcg_temp_free_i32(t0); |
1726 |
#endif
|
1727 |
} |
1728 |
|
1729 |
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
1730 |
{ |
1731 |
#ifdef TCG_TARGET_HAS_neg_i64
|
1732 |
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
1733 |
#else
|
1734 |
TCGv_i64 t0 = tcg_const_i64(0);
|
1735 |
tcg_gen_sub_i64(ret, t0, arg); |
1736 |
tcg_temp_free_i64(t0); |
1737 |
#endif
|
1738 |
} |
1739 |
|
1740 |
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
1741 |
{ |
1742 |
#ifdef TCG_TARGET_HAS_not_i32
|
1743 |
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
1744 |
#else
|
1745 |
tcg_gen_xori_i32(ret, arg, -1);
|
1746 |
#endif
|
1747 |
} |
1748 |
|
1749 |
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
1750 |
{ |
1751 |
#ifdef TCG_TARGET_HAS_not_i64
|
1752 |
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
1753 |
#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32 |
1754 |
tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
1755 |
tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
1756 |
#else
|
1757 |
tcg_gen_xori_i64(ret, arg, -1);
|
1758 |
#endif
|
1759 |
} |
1760 |
|
1761 |
static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
1762 |
{ |
1763 |
tcg_gen_op1_i32(INDEX_op_discard, arg); |
1764 |
} |
1765 |
|
1766 |
#if TCG_TARGET_REG_BITS == 32 |
1767 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1768 |
{ |
1769 |
tcg_gen_discard_i32(TCGV_LOW(arg)); |
1770 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1771 |
} |
1772 |
#else
|
1773 |
static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
1774 |
{ |
1775 |
tcg_gen_op1_i64(INDEX_op_discard, arg); |
1776 |
} |
1777 |
#endif
|
1778 |
|
1779 |
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
1780 |
{ |
1781 |
#if TCG_TARGET_REG_BITS == 32 |
1782 |
tcg_gen_mov_i32(TCGV_LOW(dest), low); |
1783 |
tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
1784 |
#else
|
1785 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1786 |
/* This extension is only needed for type correctness.
|
1787 |
We may be able to do better given target specific information. */
|
1788 |
tcg_gen_extu_i32_i64(tmp, high); |
1789 |
tcg_gen_shli_i64(tmp, tmp, 32);
|
1790 |
tcg_gen_extu_i32_i64(dest, low); |
1791 |
tcg_gen_or_i64(dest, dest, tmp); |
1792 |
tcg_temp_free_i64(tmp); |
1793 |
#endif
|
1794 |
} |
1795 |
|
1796 |
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
1797 |
{ |
1798 |
#if TCG_TARGET_REG_BITS == 32 |
1799 |
tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
1800 |
#else
|
1801 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
1802 |
tcg_gen_ext32u_i64(dest, low); |
1803 |
tcg_gen_shli_i64(tmp, high, 32);
|
1804 |
tcg_gen_or_i64(dest, dest, tmp); |
1805 |
tcg_temp_free_i64(tmp); |
1806 |
#endif
|
1807 |
} |
1808 |
|
1809 |
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1810 |
{ |
1811 |
#ifdef TCG_TARGET_HAS_andc_i32
|
1812 |
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
1813 |
#else
|
1814 |
TCGv_i32 t0; |
1815 |
t0 = tcg_temp_new_i32(); |
1816 |
tcg_gen_not_i32(t0, arg2); |
1817 |
tcg_gen_and_i32(ret, arg1, t0); |
1818 |
tcg_temp_free_i32(t0); |
1819 |
#endif
|
1820 |
} |
1821 |
|
1822 |
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1823 |
{ |
1824 |
#ifdef TCG_TARGET_HAS_andc_i64
|
1825 |
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
1826 |
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 |
1827 |
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1828 |
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1829 |
#else
|
1830 |
TCGv_i64 t0; |
1831 |
t0 = tcg_temp_new_i64(); |
1832 |
tcg_gen_not_i64(t0, arg2); |
1833 |
tcg_gen_and_i64(ret, arg1, t0); |
1834 |
tcg_temp_free_i64(t0); |
1835 |
#endif
|
1836 |
} |
1837 |
|
1838 |
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1839 |
{ |
1840 |
#ifdef TCG_TARGET_HAS_eqv_i32
|
1841 |
tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
1842 |
#else
|
1843 |
tcg_gen_xor_i32(ret, arg1, arg2); |
1844 |
tcg_gen_not_i32(ret, ret); |
1845 |
#endif
|
1846 |
} |
1847 |
|
1848 |
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1849 |
{ |
1850 |
#ifdef TCG_TARGET_HAS_eqv_i64
|
1851 |
tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
1852 |
#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32 |
1853 |
tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1854 |
tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1855 |
#else
|
1856 |
tcg_gen_xor_i64(ret, arg1, arg2); |
1857 |
tcg_gen_not_i64(ret, ret); |
1858 |
#endif
|
1859 |
} |
1860 |
|
1861 |
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1862 |
{ |
1863 |
#ifdef TCG_TARGET_HAS_nand_i32
|
1864 |
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); |
1865 |
#else
|
1866 |
tcg_gen_and_i32(ret, arg1, arg2); |
1867 |
tcg_gen_not_i32(ret, ret); |
1868 |
#endif
|
1869 |
} |
1870 |
|
1871 |
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1872 |
{ |
1873 |
#ifdef TCG_TARGET_HAS_nand_i64
|
1874 |
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); |
1875 |
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32 |
1876 |
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1877 |
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1878 |
#else
|
1879 |
tcg_gen_and_i64(ret, arg1, arg2); |
1880 |
tcg_gen_not_i64(ret, ret); |
1881 |
#endif
|
1882 |
} |
1883 |
|
1884 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1885 |
{ |
1886 |
#ifdef TCG_TARGET_HAS_nor_i32
|
1887 |
tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); |
1888 |
#else
|
1889 |
tcg_gen_or_i32(ret, arg1, arg2); |
1890 |
tcg_gen_not_i32(ret, ret); |
1891 |
#endif
|
1892 |
} |
1893 |
|
1894 |
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1895 |
{ |
1896 |
#ifdef TCG_TARGET_HAS_nor_i64
|
1897 |
tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); |
1898 |
#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32 |
1899 |
tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1900 |
tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1901 |
#else
|
1902 |
tcg_gen_or_i64(ret, arg1, arg2); |
1903 |
tcg_gen_not_i64(ret, ret); |
1904 |
#endif
|
1905 |
} |
1906 |
|
1907 |
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1908 |
{ |
1909 |
#ifdef TCG_TARGET_HAS_orc_i32
|
1910 |
tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
1911 |
#else
|
1912 |
TCGv_i32 t0; |
1913 |
t0 = tcg_temp_new_i32(); |
1914 |
tcg_gen_not_i32(t0, arg2); |
1915 |
tcg_gen_or_i32(ret, arg1, t0); |
1916 |
tcg_temp_free_i32(t0); |
1917 |
#endif
|
1918 |
} |
1919 |
|
1920 |
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1921 |
{ |
1922 |
#ifdef TCG_TARGET_HAS_orc_i64
|
1923 |
tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
1924 |
#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32 |
1925 |
tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
1926 |
tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
1927 |
#else
|
1928 |
TCGv_i64 t0; |
1929 |
t0 = tcg_temp_new_i64(); |
1930 |
tcg_gen_not_i64(t0, arg2); |
1931 |
tcg_gen_or_i64(ret, arg1, t0); |
1932 |
tcg_temp_free_i64(t0); |
1933 |
#endif
|
1934 |
} |
1935 |
|
1936 |
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
1937 |
{ |
1938 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1939 |
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
1940 |
#else
|
1941 |
TCGv_i32 t0, t1; |
1942 |
|
1943 |
t0 = tcg_temp_new_i32(); |
1944 |
t1 = tcg_temp_new_i32(); |
1945 |
tcg_gen_shl_i32(t0, arg1, arg2); |
1946 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
1947 |
tcg_gen_shr_i32(t1, arg1, t1); |
1948 |
tcg_gen_or_i32(ret, t0, t1); |
1949 |
tcg_temp_free_i32(t0); |
1950 |
tcg_temp_free_i32(t1); |
1951 |
#endif
|
1952 |
} |
1953 |
|
1954 |
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
1955 |
{ |
1956 |
#ifdef TCG_TARGET_HAS_rot_i64
|
1957 |
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
1958 |
#else
|
1959 |
TCGv_i64 t0, t1; |
1960 |
|
1961 |
t0 = tcg_temp_new_i64(); |
1962 |
t1 = tcg_temp_new_i64(); |
1963 |
tcg_gen_shl_i64(t0, arg1, arg2); |
1964 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
1965 |
tcg_gen_shr_i64(t1, arg1, t1); |
1966 |
tcg_gen_or_i64(ret, t0, t1); |
1967 |
tcg_temp_free_i64(t0); |
1968 |
tcg_temp_free_i64(t1); |
1969 |
#endif
|
1970 |
} |
1971 |
|
1972 |
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
1973 |
{ |
1974 |
/* some cases can be optimized here */
|
1975 |
if (arg2 == 0) { |
1976 |
tcg_gen_mov_i32(ret, arg1); |
1977 |
} else {
|
1978 |
#ifdef TCG_TARGET_HAS_rot_i32
|
1979 |
TCGv_i32 t0 = tcg_const_i32(arg2); |
1980 |
tcg_gen_rotl_i32(ret, arg1, t0); |
1981 |
tcg_temp_free_i32(t0); |
1982 |
#else
|
1983 |
TCGv_i32 t0, t1; |
1984 |
t0 = tcg_temp_new_i32(); |
1985 |
t1 = tcg_temp_new_i32(); |
1986 |
tcg_gen_shli_i32(t0, arg1, arg2); |
1987 |
tcg_gen_shri_i32(t1, arg1, 32 - arg2);
|
1988 |
tcg_gen_or_i32(ret, t0, t1); |
1989 |
tcg_temp_free_i32(t0); |
1990 |
tcg_temp_free_i32(t1); |
1991 |
#endif
|
1992 |
} |
1993 |
} |
1994 |
|
1995 |
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
1996 |
{ |
1997 |
/* some cases can be optimized here */
|
1998 |
if (arg2 == 0) { |
1999 |
tcg_gen_mov_i64(ret, arg1); |
2000 |
} else {
|
2001 |
#ifdef TCG_TARGET_HAS_rot_i64
|
2002 |
TCGv_i64 t0 = tcg_const_i64(arg2); |
2003 |
tcg_gen_rotl_i64(ret, arg1, t0); |
2004 |
tcg_temp_free_i64(t0); |
2005 |
#else
|
2006 |
TCGv_i64 t0, t1; |
2007 |
t0 = tcg_temp_new_i64(); |
2008 |
t1 = tcg_temp_new_i64(); |
2009 |
tcg_gen_shli_i64(t0, arg1, arg2); |
2010 |
tcg_gen_shri_i64(t1, arg1, 64 - arg2);
|
2011 |
tcg_gen_or_i64(ret, t0, t1); |
2012 |
tcg_temp_free_i64(t0); |
2013 |
tcg_temp_free_i64(t1); |
2014 |
#endif
|
2015 |
} |
2016 |
} |
2017 |
|
2018 |
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
2019 |
{ |
2020 |
#ifdef TCG_TARGET_HAS_rot_i32
|
2021 |
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
2022 |
#else
|
2023 |
TCGv_i32 t0, t1; |
2024 |
|
2025 |
t0 = tcg_temp_new_i32(); |
2026 |
t1 = tcg_temp_new_i32(); |
2027 |
tcg_gen_shr_i32(t0, arg1, arg2); |
2028 |
tcg_gen_subfi_i32(t1, 32, arg2);
|
2029 |
tcg_gen_shl_i32(t1, arg1, t1); |
2030 |
tcg_gen_or_i32(ret, t0, t1); |
2031 |
tcg_temp_free_i32(t0); |
2032 |
tcg_temp_free_i32(t1); |
2033 |
#endif
|
2034 |
} |
2035 |
|
2036 |
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
2037 |
{ |
2038 |
#ifdef TCG_TARGET_HAS_rot_i64
|
2039 |
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
2040 |
#else
|
2041 |
TCGv_i64 t0, t1; |
2042 |
|
2043 |
t0 = tcg_temp_new_i64(); |
2044 |
t1 = tcg_temp_new_i64(); |
2045 |
tcg_gen_shr_i64(t0, arg1, arg2); |
2046 |
tcg_gen_subfi_i64(t1, 64, arg2);
|
2047 |
tcg_gen_shl_i64(t1, arg1, t1); |
2048 |
tcg_gen_or_i64(ret, t0, t1); |
2049 |
tcg_temp_free_i64(t0); |
2050 |
tcg_temp_free_i64(t1); |
2051 |
#endif
|
2052 |
} |
2053 |
|
2054 |
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
2055 |
{ |
2056 |
/* some cases can be optimized here */
|
2057 |
if (arg2 == 0) { |
2058 |
tcg_gen_mov_i32(ret, arg1); |
2059 |
} else {
|
2060 |
tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
|
2061 |
} |
2062 |
} |
2063 |
|
2064 |
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
2065 |
{ |
2066 |
/* some cases can be optimized here */
|
2067 |
if (arg2 == 0) { |
2068 |
tcg_gen_mov_i64(ret, arg1); |
2069 |
} else {
|
2070 |
tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
|
2071 |
} |
2072 |
} |
2073 |
|
2074 |
/***************************************/
|
2075 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
2076 |
type. */
|
2077 |
#ifndef TARGET_LONG_BITS
|
2078 |
#error must include QEMU headers
|
2079 |
#endif
|
2080 |
|
2081 |
#if TARGET_LONG_BITS == 32 |
2082 |
#define TCGv TCGv_i32
|
2083 |
#define tcg_temp_new() tcg_temp_new_i32()
|
2084 |
#define tcg_global_reg_new tcg_global_reg_new_i32
|
2085 |
#define tcg_global_mem_new tcg_global_mem_new_i32
|
2086 |
#define tcg_temp_local_new() tcg_temp_local_new_i32()
|
2087 |
#define tcg_temp_free tcg_temp_free_i32
|
2088 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
|
2089 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
|
2090 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
|
2091 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
|
2092 |
#else
|
2093 |
#define TCGv TCGv_i64
|
2094 |
#define tcg_temp_new() tcg_temp_new_i64()
|
2095 |
#define tcg_global_reg_new tcg_global_reg_new_i64
|
2096 |
#define tcg_global_mem_new tcg_global_mem_new_i64
|
2097 |
#define tcg_temp_local_new() tcg_temp_local_new_i64()
|
2098 |
#define tcg_temp_free tcg_temp_free_i64
|
2099 |
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
|
2100 |
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
|
2101 |
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
|
2102 |
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
|
2103 |
#endif
|
2104 |
|
2105 |
/* debug info: write the PC of the corresponding QEMU CPU instruction */
|
2106 |
static inline void tcg_gen_debug_insn_start(uint64_t pc) |
2107 |
{ |
2108 |
/* XXX: must really use a 32 bit size for TCGArg in all cases */
|
2109 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
2110 |
tcg_gen_op2ii(INDEX_op_debug_insn_start, |
2111 |
(uint32_t)(pc), (uint32_t)(pc >> 32));
|
2112 |
#else
|
2113 |
tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
2114 |
#endif
|
2115 |
} |
2116 |
|
2117 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
2118 |
{ |
2119 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
2120 |
} |
2121 |
|
2122 |
static inline void tcg_gen_goto_tb(int idx) |
2123 |
{ |
2124 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
2125 |
} |
2126 |
|
2127 |
#if TCG_TARGET_REG_BITS == 32 |
2128 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2129 |
{ |
2130 |
#if TARGET_LONG_BITS == 32 |
2131 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2132 |
#else
|
2133 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
2134 |
TCGV_HIGH(addr), mem_index); |
2135 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2136 |
#endif
|
2137 |
} |
2138 |
|
2139 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2140 |
{ |
2141 |
#if TARGET_LONG_BITS == 32 |
2142 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2143 |
#else
|
2144 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
2145 |
TCGV_HIGH(addr), mem_index); |
2146 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2147 |
#endif
|
2148 |
} |
2149 |
|
2150 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2151 |
{ |
2152 |
#if TARGET_LONG_BITS == 32 |
2153 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2154 |
#else
|
2155 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
2156 |
TCGV_HIGH(addr), mem_index); |
2157 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2158 |
#endif
|
2159 |
} |
2160 |
|
2161 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2162 |
{ |
2163 |
#if TARGET_LONG_BITS == 32 |
2164 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2165 |
#else
|
2166 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
2167 |
TCGV_HIGH(addr), mem_index); |
2168 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2169 |
#endif
|
2170 |
} |
2171 |
|
2172 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2173 |
{ |
2174 |
#if TARGET_LONG_BITS == 32 |
2175 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2176 |
#else
|
2177 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
2178 |
TCGV_HIGH(addr), mem_index); |
2179 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
2180 |
#endif
|
2181 |
} |
2182 |
|
2183 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2184 |
{ |
2185 |
#if TARGET_LONG_BITS == 32 |
2186 |
tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2187 |
#else
|
2188 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
2189 |
TCGV_HIGH(addr), mem_index); |
2190 |
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
|
2191 |
#endif
|
2192 |
} |
2193 |
|
2194 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2195 |
{ |
2196 |
#if TARGET_LONG_BITS == 32 |
2197 |
tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
2198 |
#else
|
2199 |
tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
2200 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2201 |
#endif
|
2202 |
} |
2203 |
|
2204 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2205 |
{ |
2206 |
#if TARGET_LONG_BITS == 32 |
2207 |
tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
2208 |
#else
|
2209 |
tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
2210 |
TCGV_HIGH(addr), mem_index); |
2211 |
#endif
|
2212 |
} |
2213 |
|
2214 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2215 |
{ |
2216 |
#if TARGET_LONG_BITS == 32 |
2217 |
tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
2218 |
#else
|
2219 |
tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
2220 |
TCGV_HIGH(addr), mem_index); |
2221 |
#endif
|
2222 |
} |
2223 |
|
2224 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2225 |
{ |
2226 |
#if TARGET_LONG_BITS == 32 |
2227 |
tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
2228 |
#else
|
2229 |
tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
2230 |
TCGV_HIGH(addr), mem_index); |
2231 |
#endif
|
2232 |
} |
2233 |
|
2234 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2235 |
{ |
2236 |
#if TARGET_LONG_BITS == 32 |
2237 |
tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
2238 |
mem_index); |
2239 |
#else
|
2240 |
tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
2241 |
TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
2242 |
#endif
|
2243 |
} |
2244 |
|
2245 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
2246 |
#define tcg_gen_discard_ptr tcg_gen_discard_i32
|
2247 |
|
2248 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2249 |
|
2250 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
2251 |
{ |
2252 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
2253 |
} |
2254 |
|
2255 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
2256 |
{ |
2257 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
2258 |
} |
2259 |
|
2260 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
2261 |
{ |
2262 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
2263 |
} |
2264 |
|
2265 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
2266 |
{ |
2267 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
2268 |
} |
2269 |
|
2270 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
2271 |
{ |
2272 |
#if TARGET_LONG_BITS == 32 |
2273 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2274 |
#else
|
2275 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
2276 |
#endif
|
2277 |
} |
2278 |
|
2279 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
2280 |
{ |
2281 |
#if TARGET_LONG_BITS == 32 |
2282 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
2283 |
#else
|
2284 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
2285 |
#endif
|
2286 |
} |
2287 |
|
2288 |
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
2289 |
{ |
2290 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
2291 |
} |
2292 |
|
2293 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
2294 |
{ |
2295 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
2296 |
} |
2297 |
|
2298 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
2299 |
{ |
2300 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
2301 |
} |
2302 |
|
2303 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
2304 |
{ |
2305 |
tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
2306 |
} |
2307 |
|
2308 |
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
2309 |
{ |
2310 |
tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
2311 |
} |
2312 |
|
2313 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
2314 |
#define tcg_gen_discard_ptr tcg_gen_discard_i64
|
2315 |
|
2316 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
2317 |
|
2318 |
#if TARGET_LONG_BITS == 64 |
2319 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
2320 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
2321 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
2322 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
2323 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
2324 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
2325 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
2326 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
2327 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
2328 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
2329 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
2330 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
2331 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
2332 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
2333 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
2334 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
2335 |
#define tcg_gen_neg_tl tcg_gen_neg_i64
|
2336 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
|
2337 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
2338 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
2339 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
2340 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
2341 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
2342 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
2343 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
2344 |
#define tcg_gen_not_tl tcg_gen_not_i64
|
2345 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
2346 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
2347 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
2348 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
2349 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
2350 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
2351 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
2352 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
|
2353 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
|
2354 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
|
2355 |
#define tcg_gen_mul_tl tcg_gen_mul_i64
|
2356 |
#define tcg_gen_muli_tl tcg_gen_muli_i64
|
2357 |
#define tcg_gen_div_tl tcg_gen_div_i64
|
2358 |
#define tcg_gen_rem_tl tcg_gen_rem_i64
|
2359 |
#define tcg_gen_divu_tl tcg_gen_divu_i64
|
2360 |
#define tcg_gen_remu_tl tcg_gen_remu_i64
|
2361 |
#define tcg_gen_discard_tl tcg_gen_discard_i64
|
2362 |
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
|
2363 |
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
|
2364 |
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
|
2365 |
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
|
2366 |
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
|
2367 |
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
|
2368 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
|
2369 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
|
2370 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
|
2371 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
|
2372 |
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
|
2373 |
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
|
2374 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
|
2375 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
|
2376 |
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
|
2377 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
|
2378 |
#define tcg_gen_andc_tl tcg_gen_andc_i64
|
2379 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
|
2380 |
#define tcg_gen_nand_tl tcg_gen_nand_i64
|
2381 |
#define tcg_gen_nor_tl tcg_gen_nor_i64
|
2382 |
#define tcg_gen_orc_tl tcg_gen_orc_i64
|
2383 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
|
2384 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
|
2385 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
|
2386 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
|
2387 |
#define tcg_const_tl tcg_const_i64
|
2388 |
#define tcg_const_local_tl tcg_const_local_i64
|
2389 |
#else
|
2390 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
2391 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
2392 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
2393 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
2394 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
2395 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
2396 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
2397 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
2398 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
2399 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
2400 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
2401 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
2402 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
2403 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
2404 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
2405 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
2406 |
#define tcg_gen_neg_tl tcg_gen_neg_i32
|
2407 |
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
|
2408 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
2409 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
2410 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
2411 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
2412 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
2413 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
2414 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
2415 |
#define tcg_gen_not_tl tcg_gen_not_i32
|
2416 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
2417 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
2418 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
2419 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
2420 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
2421 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
2422 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
2423 |
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
|
2424 |
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
|
2425 |
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
|
2426 |
#define tcg_gen_mul_tl tcg_gen_mul_i32
|
2427 |
#define tcg_gen_muli_tl tcg_gen_muli_i32
|
2428 |
#define tcg_gen_div_tl tcg_gen_div_i32
|
2429 |
#define tcg_gen_rem_tl tcg_gen_rem_i32
|
2430 |
#define tcg_gen_divu_tl tcg_gen_divu_i32
|
2431 |
#define tcg_gen_remu_tl tcg_gen_remu_i32
|
2432 |
#define tcg_gen_discard_tl tcg_gen_discard_i32
|
2433 |
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
|
2434 |
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
|
2435 |
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
|
2436 |
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
|
2437 |
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
|
2438 |
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
|
2439 |
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
|
2440 |
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
|
2441 |
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
|
2442 |
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
|
2443 |
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
|
2444 |
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
|
2445 |
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
|
2446 |
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
|
2447 |
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
|
2448 |
#define tcg_gen_andc_tl tcg_gen_andc_i32
|
2449 |
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
|
2450 |
#define tcg_gen_nand_tl tcg_gen_nand_i32
|
2451 |
#define tcg_gen_nor_tl tcg_gen_nor_i32
|
2452 |
#define tcg_gen_orc_tl tcg_gen_orc_i32
|
2453 |
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
|
2454 |
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
|
2455 |
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
|
2456 |
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
|
2457 |
#define tcg_const_tl tcg_const_i32
|
2458 |
#define tcg_const_local_tl tcg_const_local_i32
|
2459 |
#endif
|
2460 |
|
2461 |
#if TCG_TARGET_REG_BITS == 32 |
2462 |
#define tcg_gen_add_ptr tcg_gen_add_i32
|
2463 |
#define tcg_gen_addi_ptr tcg_gen_addi_i32
|
2464 |
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
|
2465 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
2466 |
#define tcg_gen_add_ptr tcg_gen_add_i64
|
2467 |
#define tcg_gen_addi_ptr tcg_gen_addi_i64
|
2468 |
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
|
2469 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |