root / hw / mips_mipssim.c @ a6307b08
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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | a79ee211 | ths | *
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7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
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8 | a79ee211 | ths | *
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9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
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12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
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15 | a79ee211 | ths | *
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16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
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17 | a79ee211 | ths | * all copies or substantial portions of the Software.
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18 | a79ee211 | ths | *
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19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | a79ee211 | ths | * THE SOFTWARE.
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26 | f0fc6f8f | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "mips.h" |
29 | 87ecb68b | pbrook | #include "pc.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | bba831e8 | Paul Brook | #include "mips-bios.h" |
35 | f0fc6f8f | ths | |
36 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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37 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
38 | f0fc6f8f | ths | #else
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39 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
40 | f0fc6f8f | ths | #endif
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41 | f0fc6f8f | ths | |
42 | f0fc6f8f | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
43 | f0fc6f8f | ths | |
44 | 7df526e3 | ths | static struct _loaderparams { |
45 | 7df526e3 | ths | int ram_size;
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46 | 7df526e3 | ths | const char *kernel_filename; |
47 | 7df526e3 | ths | const char *kernel_cmdline; |
48 | 7df526e3 | ths | const char *initrd_filename; |
49 | 7df526e3 | ths | } loaderparams; |
50 | 7df526e3 | ths | |
51 | f0fc6f8f | ths | static void load_kernel (CPUState *env) |
52 | f0fc6f8f | ths | { |
53 | f0fc6f8f | ths | int64_t entry, kernel_low, kernel_high; |
54 | f0fc6f8f | ths | long kernel_size;
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55 | f0fc6f8f | ths | long initrd_size;
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56 | f0fc6f8f | ths | ram_addr_t initrd_offset; |
57 | f0fc6f8f | ths | |
58 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
59 | b55266b5 | blueswir1 | (uint64_t *)&entry, (uint64_t *)&kernel_low, |
60 | b55266b5 | blueswir1 | (uint64_t *)&kernel_high); |
61 | f0fc6f8f | ths | if (kernel_size >= 0) { |
62 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
63 | f0fc6f8f | ths | entry = (int32_t)entry; |
64 | b5dc7732 | ths | env->active_tc.PC = entry; |
65 | f0fc6f8f | ths | } else {
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66 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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67 | 7df526e3 | ths | loaderparams.kernel_filename); |
68 | f0fc6f8f | ths | exit(1);
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69 | f0fc6f8f | ths | } |
70 | f0fc6f8f | ths | |
71 | f0fc6f8f | ths | /* load initrd */
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72 | f0fc6f8f | ths | initrd_size = 0;
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73 | f0fc6f8f | ths | initrd_offset = 0;
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74 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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75 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
76 | f0fc6f8f | ths | if (initrd_size > 0) { |
77 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
78 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
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79 | f0fc6f8f | ths | fprintf(stderr, |
80 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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81 | 7df526e3 | ths | loaderparams.initrd_filename); |
82 | f0fc6f8f | ths | exit(1);
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83 | f0fc6f8f | ths | } |
84 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
85 | dcac9679 | pbrook | initrd_offset, loaderparams.ram_size - initrd_offset); |
86 | f0fc6f8f | ths | } |
87 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
88 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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89 | 7df526e3 | ths | loaderparams.initrd_filename); |
90 | f0fc6f8f | ths | exit(1);
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91 | f0fc6f8f | ths | } |
92 | f0fc6f8f | ths | } |
93 | f0fc6f8f | ths | } |
94 | f0fc6f8f | ths | |
95 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
96 | f0fc6f8f | ths | { |
97 | f0fc6f8f | ths | CPUState *env = opaque; |
98 | f0fc6f8f | ths | cpu_reset(env); |
99 | f0fc6f8f | ths | |
100 | 7df526e3 | ths | if (loaderparams.kernel_filename)
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101 | f0fc6f8f | ths | load_kernel (env); |
102 | f0fc6f8f | ths | } |
103 | f0fc6f8f | ths | |
104 | f0fc6f8f | ths | static void |
105 | fbe1b595 | Paul Brook | mips_mipssim_init (ram_addr_t ram_size, |
106 | 3023f332 | aliguori | const char *boot_device, |
107 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
108 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
109 | f0fc6f8f | ths | { |
110 | 5cea8590 | Paul Brook | char *filename;
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111 | dcac9679 | pbrook | ram_addr_t ram_offset; |
112 | dcac9679 | pbrook | ram_addr_t bios_offset; |
113 | f0fc6f8f | ths | CPUState *env; |
114 | b5334159 | ths | int bios_size;
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115 | f0fc6f8f | ths | |
116 | f0fc6f8f | ths | /* Init CPUs. */
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117 | f0fc6f8f | ths | if (cpu_model == NULL) { |
118 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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119 | f0fc6f8f | ths | cpu_model = "5Kf";
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120 | f0fc6f8f | ths | #else
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121 | f0fc6f8f | ths | cpu_model = "24Kf";
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122 | f0fc6f8f | ths | #endif
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123 | f0fc6f8f | ths | } |
124 | aaed909a | bellard | env = cpu_init(cpu_model); |
125 | aaed909a | bellard | if (!env) {
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126 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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127 | aaed909a | bellard | exit(1);
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128 | aaed909a | bellard | } |
129 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, env); |
130 | f0fc6f8f | ths | |
131 | f0fc6f8f | ths | /* Allocate RAM. */
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132 | dcac9679 | pbrook | ram_offset = qemu_ram_alloc(ram_size); |
133 | dcac9679 | pbrook | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
134 | f0fc6f8f | ths | |
135 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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136 | dcac9679 | pbrook | |
137 | dcac9679 | pbrook | /* Map the BIOS / boot exception handler. */
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138 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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139 | dcac9679 | pbrook | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
140 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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141 | f0fc6f8f | ths | if (bios_name == NULL) |
142 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
143 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
144 | 5cea8590 | Paul Brook | if (filename) {
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145 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
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146 | 5cea8590 | Paul Brook | qemu_free(filename); |
147 | 5cea8590 | Paul Brook | } else {
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148 | 5cea8590 | Paul Brook | bios_size = -1;
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149 | 5cea8590 | Paul Brook | } |
150 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
151 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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152 | f0fc6f8f | ths | fprintf(stderr, |
153 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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154 | 5cea8590 | Paul Brook | filename); |
155 | f0fc6f8f | ths | exit(1);
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156 | f0fc6f8f | ths | } else {
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157 | b5334159 | ths | /* We have a boot vector start address. */
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158 | b5dc7732 | ths | env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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159 | f0fc6f8f | ths | } |
160 | f0fc6f8f | ths | |
161 | f0fc6f8f | ths | if (kernel_filename) {
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162 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
163 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
164 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
165 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
166 | f0fc6f8f | ths | load_kernel(env); |
167 | f0fc6f8f | ths | } |
168 | f0fc6f8f | ths | |
169 | f0fc6f8f | ths | /* Init CPU internal devices. */
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170 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
171 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
172 | f0fc6f8f | ths | |
173 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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174 | f0fc6f8f | ths | isa_mmio_init(0x1fd00000, 0x00010000); |
175 | f0fc6f8f | ths | |
176 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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177 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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178 | f0fc6f8f | ths | if (serial_hds[0]) |
179 | b6cd0ea1 | aurel32 | serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
180 | f0fc6f8f | ths | |
181 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
182 | 0ae18cee | aliguori | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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183 | 0ae18cee | aliguori | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
184 | f0fc6f8f | ths | } |
185 | f0fc6f8f | ths | |
186 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_mipssim_machine = {
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187 | eec2743e | ths | .name = "mipssim",
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188 | eec2743e | ths | .desc = "MIPS MIPSsim platform",
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189 | eec2743e | ths | .init = mips_mipssim_init, |
190 | f0fc6f8f | ths | }; |
191 | f80f9ec9 | Anthony Liguori | |
192 | f80f9ec9 | Anthony Liguori | static void mips_mipssim_machine_init(void) |
193 | f80f9ec9 | Anthony Liguori | { |
194 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_mipssim_machine); |
195 | f80f9ec9 | Anthony Liguori | } |
196 | f80f9ec9 | Anthony Liguori | |
197 | f80f9ec9 | Anthony Liguori | machine_init(mips_mipssim_machine_init); |