root / hw / pflash_cfi02.c @ a6307b08
History | View | Annotate | Download (19.1 kB)
1 | 29133e9a | bellard | /*
|
---|---|---|---|
2 | 29133e9a | bellard | * CFI parallel flash with AMD command set emulation
|
3 | 5fafdf24 | ths | *
|
4 | 29133e9a | bellard | * Copyright (c) 2005 Jocelyn Mayer
|
5 | 29133e9a | bellard | *
|
6 | 29133e9a | bellard | * This library is free software; you can redistribute it and/or
|
7 | 29133e9a | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 29133e9a | bellard | * License as published by the Free Software Foundation; either
|
9 | 29133e9a | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 29133e9a | bellard | *
|
11 | 29133e9a | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 29133e9a | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 29133e9a | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 29133e9a | bellard | * Lesser General Public License for more details.
|
15 | 29133e9a | bellard | *
|
16 | 29133e9a | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | 29133e9a | bellard | */
|
19 | 29133e9a | bellard | |
20 | 29133e9a | bellard | /*
|
21 | 29133e9a | bellard | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
|
22 | 29133e9a | bellard | * Supported commands/modes are:
|
23 | 29133e9a | bellard | * - flash read
|
24 | 29133e9a | bellard | * - flash write
|
25 | 29133e9a | bellard | * - flash ID read
|
26 | 29133e9a | bellard | * - sector erase
|
27 | 29133e9a | bellard | * - chip erase
|
28 | 29133e9a | bellard | * - unlock bypass command
|
29 | 29133e9a | bellard | * - CFI queries
|
30 | 29133e9a | bellard | *
|
31 | 29133e9a | bellard | * It does not support flash interleaving.
|
32 | 29133e9a | bellard | * It does not implement boot blocs with reduced size
|
33 | 29133e9a | bellard | * It does not implement software data protection as found in many real chips
|
34 | 29133e9a | bellard | * It does not implement erase suspend/resume commands
|
35 | 29133e9a | bellard | * It does not implement multiple sectors erase
|
36 | 29133e9a | bellard | */
|
37 | 29133e9a | bellard | |
38 | 87ecb68b | pbrook | #include "hw.h" |
39 | 87ecb68b | pbrook | #include "flash.h" |
40 | 87ecb68b | pbrook | #include "qemu-timer.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | 29133e9a | bellard | |
43 | 29133e9a | bellard | //#define PFLASH_DEBUG
|
44 | 29133e9a | bellard | #ifdef PFLASH_DEBUG
|
45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
|
46 | 29133e9a | bellard | do { \
|
47 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
48 | 29133e9a | bellard | } while (0) |
49 | 29133e9a | bellard | #else
|
50 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
51 | 29133e9a | bellard | #endif
|
52 | 29133e9a | bellard | |
53 | 29133e9a | bellard | struct pflash_t {
|
54 | 29133e9a | bellard | BlockDriverState *bs; |
55 | 71db710f | blueswir1 | target_phys_addr_t base; |
56 | 71db710f | blueswir1 | uint32_t sector_len; |
57 | 4fbd24ba | balrog | uint32_t chip_len; |
58 | 4fbd24ba | balrog | int mappings;
|
59 | 29133e9a | bellard | int width;
|
60 | 29133e9a | bellard | int wcycle; /* if 0, the flash is read normally */ |
61 | 29133e9a | bellard | int bypass;
|
62 | 29133e9a | bellard | int ro;
|
63 | 29133e9a | bellard | uint8_t cmd; |
64 | 29133e9a | bellard | uint8_t status; |
65 | 29133e9a | bellard | uint16_t ident[4];
|
66 | 6725070d | balrog | uint16_t unlock_addr[2];
|
67 | 29133e9a | bellard | uint8_t cfi_len; |
68 | 29133e9a | bellard | uint8_t cfi_table[0x52];
|
69 | 29133e9a | bellard | QEMUTimer *timer; |
70 | 29133e9a | bellard | ram_addr_t off; |
71 | 29133e9a | bellard | int fl_mem;
|
72 | 9c9bb6c8 | balrog | int rom_mode;
|
73 | 29133e9a | bellard | void *storage;
|
74 | 29133e9a | bellard | }; |
75 | 29133e9a | bellard | |
76 | 4fbd24ba | balrog | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
77 | 4fbd24ba | balrog | { |
78 | 4fbd24ba | balrog | unsigned long phys_offset = pfl->fl_mem; |
79 | 4fbd24ba | balrog | int i;
|
80 | 4fbd24ba | balrog | |
81 | 4fbd24ba | balrog | if (rom_mode)
|
82 | 4fbd24ba | balrog | phys_offset |= pfl->off | IO_MEM_ROMD; |
83 | 9c9bb6c8 | balrog | pfl->rom_mode = rom_mode; |
84 | 4fbd24ba | balrog | |
85 | 4fbd24ba | balrog | for (i = 0; i < pfl->mappings; i++) |
86 | 4fbd24ba | balrog | cpu_register_physical_memory(pfl->base + i * pfl->chip_len, |
87 | 4fbd24ba | balrog | pfl->chip_len, phys_offset); |
88 | 4fbd24ba | balrog | } |
89 | 4fbd24ba | balrog | |
90 | 29133e9a | bellard | static void pflash_timer (void *opaque) |
91 | 29133e9a | bellard | { |
92 | 29133e9a | bellard | pflash_t *pfl = opaque; |
93 | 29133e9a | bellard | |
94 | 29133e9a | bellard | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
|
95 | 29133e9a | bellard | /* Reset flash */
|
96 | 29133e9a | bellard | pfl->status ^= 0x80;
|
97 | 29133e9a | bellard | if (pfl->bypass) {
|
98 | 29133e9a | bellard | pfl->wcycle = 2;
|
99 | 29133e9a | bellard | } else {
|
100 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
|
101 | 29133e9a | bellard | pfl->wcycle = 0;
|
102 | 29133e9a | bellard | } |
103 | 29133e9a | bellard | pfl->cmd = 0;
|
104 | 29133e9a | bellard | } |
105 | 29133e9a | bellard | |
106 | 71db710f | blueswir1 | static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) |
107 | 29133e9a | bellard | { |
108 | 71db710f | blueswir1 | uint32_t boff; |
109 | 29133e9a | bellard | uint32_t ret; |
110 | 29133e9a | bellard | uint8_t *p; |
111 | 29133e9a | bellard | |
112 | e96efcfc | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset); |
113 | 29133e9a | bellard | ret = -1;
|
114 | 9c9bb6c8 | balrog | if (pfl->rom_mode) {
|
115 | 9c9bb6c8 | balrog | /* Lazy reset of to ROMD mode */
|
116 | 9c9bb6c8 | balrog | if (pfl->wcycle == 0) |
117 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 1);
|
118 | 0f459d16 | pbrook | } |
119 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
|
120 | 29133e9a | bellard | boff = offset & 0xFF;
|
121 | 29133e9a | bellard | if (pfl->width == 2) |
122 | 29133e9a | bellard | boff = boff >> 1;
|
123 | 29133e9a | bellard | else if (pfl->width == 4) |
124 | 29133e9a | bellard | boff = boff >> 2;
|
125 | 29133e9a | bellard | switch (pfl->cmd) {
|
126 | 29133e9a | bellard | default:
|
127 | 29133e9a | bellard | /* This should never happen : reset state & treat it as a read*/
|
128 | 29133e9a | bellard | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
|
129 | 29133e9a | bellard | pfl->wcycle = 0;
|
130 | 29133e9a | bellard | pfl->cmd = 0;
|
131 | 29133e9a | bellard | case 0x80: |
132 | 29133e9a | bellard | /* We accept reads during second unlock sequence... */
|
133 | 29133e9a | bellard | case 0x00: |
134 | 29133e9a | bellard | flash_read:
|
135 | 29133e9a | bellard | /* Flash area read */
|
136 | 29133e9a | bellard | p = pfl->storage; |
137 | 29133e9a | bellard | switch (width) {
|
138 | 29133e9a | bellard | case 1: |
139 | 29133e9a | bellard | ret = p[offset]; |
140 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
|
141 | 29133e9a | bellard | break;
|
142 | 29133e9a | bellard | case 2: |
143 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
144 | 29133e9a | bellard | ret = p[offset] << 8;
|
145 | 29133e9a | bellard | ret |= p[offset + 1];
|
146 | 29133e9a | bellard | #else
|
147 | 29133e9a | bellard | ret = p[offset]; |
148 | 29133e9a | bellard | ret |= p[offset + 1] << 8; |
149 | 29133e9a | bellard | #endif
|
150 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
|
151 | 29133e9a | bellard | break;
|
152 | 29133e9a | bellard | case 4: |
153 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
154 | 29133e9a | bellard | ret = p[offset] << 24;
|
155 | 29133e9a | bellard | ret |= p[offset + 1] << 16; |
156 | 29133e9a | bellard | ret |= p[offset + 2] << 8; |
157 | 29133e9a | bellard | ret |= p[offset + 3];
|
158 | 29133e9a | bellard | #else
|
159 | 29133e9a | bellard | ret = p[offset]; |
160 | 29133e9a | bellard | ret |= p[offset + 1] << 8; |
161 | 29133e9a | bellard | ret |= p[offset + 2] << 16; |
162 | 29133e9a | bellard | ret |= p[offset + 3] << 24; |
163 | 29133e9a | bellard | #endif
|
164 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
|
165 | 29133e9a | bellard | break;
|
166 | 29133e9a | bellard | } |
167 | 29133e9a | bellard | break;
|
168 | 29133e9a | bellard | case 0x90: |
169 | 29133e9a | bellard | /* flash ID read */
|
170 | 29133e9a | bellard | switch (boff) {
|
171 | 29133e9a | bellard | case 0x00: |
172 | 29133e9a | bellard | case 0x01: |
173 | 29133e9a | bellard | ret = pfl->ident[boff & 0x01];
|
174 | 29133e9a | bellard | break;
|
175 | 29133e9a | bellard | case 0x02: |
176 | 29133e9a | bellard | ret = 0x00; /* Pretend all sectors are unprotected */ |
177 | 29133e9a | bellard | break;
|
178 | 29133e9a | bellard | case 0x0E: |
179 | 29133e9a | bellard | case 0x0F: |
180 | 29133e9a | bellard | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
181 | 29133e9a | bellard | goto flash_read;
|
182 | 29133e9a | bellard | ret = pfl->ident[2 + (boff & 0x01)]; |
183 | 29133e9a | bellard | break;
|
184 | 29133e9a | bellard | default:
|
185 | 29133e9a | bellard | goto flash_read;
|
186 | 29133e9a | bellard | } |
187 | e96efcfc | j_mayer | DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret); |
188 | 29133e9a | bellard | break;
|
189 | 29133e9a | bellard | case 0xA0: |
190 | 29133e9a | bellard | case 0x10: |
191 | 29133e9a | bellard | case 0x30: |
192 | 29133e9a | bellard | /* Status register read */
|
193 | 29133e9a | bellard | ret = pfl->status; |
194 | 29133e9a | bellard | DPRINTF("%s: status %x\n", __func__, ret);
|
195 | 29133e9a | bellard | /* Toggle bit 6 */
|
196 | 29133e9a | bellard | pfl->status ^= 0x40;
|
197 | 29133e9a | bellard | break;
|
198 | 29133e9a | bellard | case 0x98: |
199 | 29133e9a | bellard | /* CFI query mode */
|
200 | 29133e9a | bellard | if (boff > pfl->cfi_len)
|
201 | 29133e9a | bellard | ret = 0;
|
202 | 29133e9a | bellard | else
|
203 | 29133e9a | bellard | ret = pfl->cfi_table[boff]; |
204 | 29133e9a | bellard | break;
|
205 | 29133e9a | bellard | } |
206 | 29133e9a | bellard | |
207 | 29133e9a | bellard | return ret;
|
208 | 29133e9a | bellard | } |
209 | 29133e9a | bellard | |
210 | 29133e9a | bellard | /* update flash content on disk */
|
211 | 5fafdf24 | ths | static void pflash_update(pflash_t *pfl, int offset, |
212 | 29133e9a | bellard | int size)
|
213 | 29133e9a | bellard | { |
214 | 29133e9a | bellard | int offset_end;
|
215 | 29133e9a | bellard | if (pfl->bs) {
|
216 | 29133e9a | bellard | offset_end = offset + size; |
217 | 29133e9a | bellard | /* round to sectors */
|
218 | 29133e9a | bellard | offset = offset >> 9;
|
219 | 29133e9a | bellard | offset_end = (offset_end + 511) >> 9; |
220 | 5fafdf24 | ths | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
|
221 | 29133e9a | bellard | offset_end - offset); |
222 | 29133e9a | bellard | } |
223 | 29133e9a | bellard | } |
224 | 29133e9a | bellard | |
225 | 71db710f | blueswir1 | static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, |
226 | 29133e9a | bellard | int width)
|
227 | 29133e9a | bellard | { |
228 | 71db710f | blueswir1 | uint32_t boff; |
229 | 29133e9a | bellard | uint8_t *p; |
230 | 29133e9a | bellard | uint8_t cmd; |
231 | 29133e9a | bellard | |
232 | 95d1f3ed | j_mayer | cmd = value; |
233 | 95d1f3ed | j_mayer | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
234 | 95d1f3ed | j_mayer | #if 0
|
235 | 95d1f3ed | j_mayer | DPRINTF("%s: flash reset asked (%02x %02x)\n",
|
236 | 95d1f3ed | j_mayer | __func__, pfl->cmd, cmd);
|
237 | 95d1f3ed | j_mayer | #endif
|
238 | 95d1f3ed | j_mayer | goto reset_flash;
|
239 | 95d1f3ed | j_mayer | } |
240 | 95d1f3ed | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__, |
241 | 95d1f3ed | j_mayer | offset, value, width, pfl->wcycle); |
242 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
|
243 | 3b46e624 | ths | |
244 | e96efcfc | j_mayer | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__, |
245 | e96efcfc | j_mayer | offset, value, width); |
246 | 29133e9a | bellard | boff = offset & (pfl->sector_len - 1);
|
247 | 29133e9a | bellard | if (pfl->width == 2) |
248 | 29133e9a | bellard | boff = boff >> 1;
|
249 | 29133e9a | bellard | else if (pfl->width == 4) |
250 | 29133e9a | bellard | boff = boff >> 2;
|
251 | 29133e9a | bellard | switch (pfl->wcycle) {
|
252 | 29133e9a | bellard | case 0: |
253 | 9c9bb6c8 | balrog | /* Set the device in I/O access mode if required */
|
254 | 9c9bb6c8 | balrog | if (pfl->rom_mode)
|
255 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 0);
|
256 | 29133e9a | bellard | /* We're in read mode */
|
257 | 29133e9a | bellard | check_unlock0:
|
258 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) { |
259 | 29133e9a | bellard | enter_CFI_mode:
|
260 | 29133e9a | bellard | /* Enter CFI query mode */
|
261 | 29133e9a | bellard | pfl->wcycle = 7;
|
262 | 29133e9a | bellard | pfl->cmd = 0x98;
|
263 | 29133e9a | bellard | return;
|
264 | 29133e9a | bellard | } |
265 | 6725070d | balrog | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
266 | e96efcfc | j_mayer | DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n", |
267 | 6725070d | balrog | __func__, boff, cmd, pfl->unlock_addr[0]);
|
268 | 29133e9a | bellard | goto reset_flash;
|
269 | 29133e9a | bellard | } |
270 | 29133e9a | bellard | DPRINTF("%s: unlock sequence started\n", __func__);
|
271 | 29133e9a | bellard | break;
|
272 | 29133e9a | bellard | case 1: |
273 | 29133e9a | bellard | /* We started an unlock sequence */
|
274 | 29133e9a | bellard | check_unlock1:
|
275 | 6725070d | balrog | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
276 | e96efcfc | j_mayer | DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__, |
277 | e96efcfc | j_mayer | boff, cmd); |
278 | 29133e9a | bellard | goto reset_flash;
|
279 | 29133e9a | bellard | } |
280 | 29133e9a | bellard | DPRINTF("%s: unlock sequence done\n", __func__);
|
281 | 29133e9a | bellard | break;
|
282 | 29133e9a | bellard | case 2: |
283 | 29133e9a | bellard | /* We finished an unlock sequence */
|
284 | 6725070d | balrog | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
285 | e96efcfc | j_mayer | DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__, |
286 | e96efcfc | j_mayer | boff, cmd); |
287 | 29133e9a | bellard | goto reset_flash;
|
288 | 29133e9a | bellard | } |
289 | 29133e9a | bellard | switch (cmd) {
|
290 | 29133e9a | bellard | case 0x20: |
291 | 29133e9a | bellard | pfl->bypass = 1;
|
292 | 29133e9a | bellard | goto do_bypass;
|
293 | 29133e9a | bellard | case 0x80: |
294 | 29133e9a | bellard | case 0x90: |
295 | 29133e9a | bellard | case 0xA0: |
296 | 29133e9a | bellard | pfl->cmd = cmd; |
297 | 29133e9a | bellard | DPRINTF("%s: starting command %02x\n", __func__, cmd);
|
298 | 29133e9a | bellard | break;
|
299 | 29133e9a | bellard | default:
|
300 | 29133e9a | bellard | DPRINTF("%s: unknown command %02x\n", __func__, cmd);
|
301 | 29133e9a | bellard | goto reset_flash;
|
302 | 29133e9a | bellard | } |
303 | 29133e9a | bellard | break;
|
304 | 29133e9a | bellard | case 3: |
305 | 29133e9a | bellard | switch (pfl->cmd) {
|
306 | 29133e9a | bellard | case 0x80: |
307 | 29133e9a | bellard | /* We need another unlock sequence */
|
308 | 29133e9a | bellard | goto check_unlock0;
|
309 | 29133e9a | bellard | case 0xA0: |
310 | e96efcfc | j_mayer | DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n", |
311 | 29133e9a | bellard | __func__, offset, value, width); |
312 | 29133e9a | bellard | p = pfl->storage; |
313 | 29133e9a | bellard | switch (width) {
|
314 | 29133e9a | bellard | case 1: |
315 | 29133e9a | bellard | p[offset] &= value; |
316 | 29133e9a | bellard | pflash_update(pfl, offset, 1);
|
317 | 29133e9a | bellard | break;
|
318 | 29133e9a | bellard | case 2: |
319 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
320 | 29133e9a | bellard | p[offset] &= value >> 8;
|
321 | 29133e9a | bellard | p[offset + 1] &= value;
|
322 | 29133e9a | bellard | #else
|
323 | 29133e9a | bellard | p[offset] &= value; |
324 | 29133e9a | bellard | p[offset + 1] &= value >> 8; |
325 | 29133e9a | bellard | #endif
|
326 | 29133e9a | bellard | pflash_update(pfl, offset, 2);
|
327 | 29133e9a | bellard | break;
|
328 | 29133e9a | bellard | case 4: |
329 | 29133e9a | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
330 | 29133e9a | bellard | p[offset] &= value >> 24;
|
331 | 29133e9a | bellard | p[offset + 1] &= value >> 16; |
332 | 29133e9a | bellard | p[offset + 2] &= value >> 8; |
333 | 29133e9a | bellard | p[offset + 3] &= value;
|
334 | 29133e9a | bellard | #else
|
335 | 29133e9a | bellard | p[offset] &= value; |
336 | 29133e9a | bellard | p[offset + 1] &= value >> 8; |
337 | 29133e9a | bellard | p[offset + 2] &= value >> 16; |
338 | 29133e9a | bellard | p[offset + 3] &= value >> 24; |
339 | 29133e9a | bellard | #endif
|
340 | 29133e9a | bellard | pflash_update(pfl, offset, 4);
|
341 | 29133e9a | bellard | break;
|
342 | 29133e9a | bellard | } |
343 | 29133e9a | bellard | pfl->status = 0x00 | ~(value & 0x80); |
344 | 29133e9a | bellard | /* Let's pretend write is immediate */
|
345 | 29133e9a | bellard | if (pfl->bypass)
|
346 | 29133e9a | bellard | goto do_bypass;
|
347 | 29133e9a | bellard | goto reset_flash;
|
348 | 29133e9a | bellard | case 0x90: |
349 | 29133e9a | bellard | if (pfl->bypass && cmd == 0x00) { |
350 | 29133e9a | bellard | /* Unlock bypass reset */
|
351 | 29133e9a | bellard | goto reset_flash;
|
352 | 29133e9a | bellard | } |
353 | 29133e9a | bellard | /* We can enter CFI query mode from autoselect mode */
|
354 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) |
355 | 29133e9a | bellard | goto enter_CFI_mode;
|
356 | 29133e9a | bellard | /* No break here */
|
357 | 29133e9a | bellard | default:
|
358 | 29133e9a | bellard | DPRINTF("%s: invalid write for command %02x\n",
|
359 | 29133e9a | bellard | __func__, pfl->cmd); |
360 | 29133e9a | bellard | goto reset_flash;
|
361 | 29133e9a | bellard | } |
362 | 29133e9a | bellard | case 4: |
363 | 29133e9a | bellard | switch (pfl->cmd) {
|
364 | 29133e9a | bellard | case 0xA0: |
365 | 29133e9a | bellard | /* Ignore writes while flash data write is occuring */
|
366 | 29133e9a | bellard | /* As we suppose write is immediate, this should never happen */
|
367 | 29133e9a | bellard | return;
|
368 | 29133e9a | bellard | case 0x80: |
369 | 29133e9a | bellard | goto check_unlock1;
|
370 | 29133e9a | bellard | default:
|
371 | 29133e9a | bellard | /* Should never happen */
|
372 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
373 | 29133e9a | bellard | __func__, pfl->cmd); |
374 | 29133e9a | bellard | goto reset_flash;
|
375 | 29133e9a | bellard | } |
376 | 29133e9a | bellard | break;
|
377 | 29133e9a | bellard | case 5: |
378 | 29133e9a | bellard | switch (cmd) {
|
379 | 29133e9a | bellard | case 0x10: |
380 | 6725070d | balrog | if (boff != pfl->unlock_addr[0]) { |
381 | e96efcfc | j_mayer | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n", |
382 | 29133e9a | bellard | __func__, offset); |
383 | 29133e9a | bellard | goto reset_flash;
|
384 | 29133e9a | bellard | } |
385 | 29133e9a | bellard | /* Chip erase */
|
386 | 29133e9a | bellard | DPRINTF("%s: start chip erase\n", __func__);
|
387 | 4fbd24ba | balrog | memset(pfl->storage, 0xFF, pfl->chip_len);
|
388 | 29133e9a | bellard | pfl->status = 0x00;
|
389 | 4fbd24ba | balrog | pflash_update(pfl, 0, pfl->chip_len);
|
390 | 29133e9a | bellard | /* Let's wait 5 seconds before chip erase is done */
|
391 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
392 | 29133e9a | bellard | qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
|
393 | 29133e9a | bellard | break;
|
394 | 29133e9a | bellard | case 0x30: |
395 | 29133e9a | bellard | /* Sector erase */
|
396 | 29133e9a | bellard | p = pfl->storage; |
397 | 29133e9a | bellard | offset &= ~(pfl->sector_len - 1);
|
398 | e96efcfc | j_mayer | DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__, |
399 | e96efcfc | j_mayer | offset); |
400 | 29133e9a | bellard | memset(p + offset, 0xFF, pfl->sector_len);
|
401 | 29133e9a | bellard | pflash_update(pfl, offset, pfl->sector_len); |
402 | 29133e9a | bellard | pfl->status = 0x00;
|
403 | 29133e9a | bellard | /* Let's wait 1/2 second before sector erase is done */
|
404 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
405 | 29133e9a | bellard | qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
|
406 | 29133e9a | bellard | break;
|
407 | 29133e9a | bellard | default:
|
408 | 29133e9a | bellard | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
409 | 29133e9a | bellard | goto reset_flash;
|
410 | 29133e9a | bellard | } |
411 | 29133e9a | bellard | pfl->cmd = cmd; |
412 | 29133e9a | bellard | break;
|
413 | 29133e9a | bellard | case 6: |
414 | 29133e9a | bellard | switch (pfl->cmd) {
|
415 | 29133e9a | bellard | case 0x10: |
416 | 29133e9a | bellard | /* Ignore writes during chip erase */
|
417 | 29133e9a | bellard | return;
|
418 | 29133e9a | bellard | case 0x30: |
419 | 29133e9a | bellard | /* Ignore writes during sector erase */
|
420 | 29133e9a | bellard | return;
|
421 | 29133e9a | bellard | default:
|
422 | 29133e9a | bellard | /* Should never happen */
|
423 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
424 | 29133e9a | bellard | __func__, pfl->cmd); |
425 | 29133e9a | bellard | goto reset_flash;
|
426 | 29133e9a | bellard | } |
427 | 29133e9a | bellard | break;
|
428 | 29133e9a | bellard | case 7: /* Special value for CFI queries */ |
429 | 29133e9a | bellard | DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
430 | 29133e9a | bellard | goto reset_flash;
|
431 | 29133e9a | bellard | default:
|
432 | 29133e9a | bellard | /* Should never happen */
|
433 | 29133e9a | bellard | DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
434 | 29133e9a | bellard | goto reset_flash;
|
435 | 29133e9a | bellard | } |
436 | 29133e9a | bellard | pfl->wcycle++; |
437 | 29133e9a | bellard | |
438 | 29133e9a | bellard | return;
|
439 | 29133e9a | bellard | |
440 | 29133e9a | bellard | /* Reset flash */
|
441 | 29133e9a | bellard | reset_flash:
|
442 | 29133e9a | bellard | pfl->bypass = 0;
|
443 | 29133e9a | bellard | pfl->wcycle = 0;
|
444 | 29133e9a | bellard | pfl->cmd = 0;
|
445 | 29133e9a | bellard | return;
|
446 | 29133e9a | bellard | |
447 | 29133e9a | bellard | do_bypass:
|
448 | 29133e9a | bellard | pfl->wcycle = 2;
|
449 | 29133e9a | bellard | pfl->cmd = 0;
|
450 | 29133e9a | bellard | return;
|
451 | 29133e9a | bellard | } |
452 | 29133e9a | bellard | |
453 | 29133e9a | bellard | |
454 | 29133e9a | bellard | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
455 | 29133e9a | bellard | { |
456 | 29133e9a | bellard | return pflash_read(opaque, addr, 1); |
457 | 29133e9a | bellard | } |
458 | 29133e9a | bellard | |
459 | 29133e9a | bellard | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
460 | 29133e9a | bellard | { |
461 | 29133e9a | bellard | pflash_t *pfl = opaque; |
462 | 29133e9a | bellard | |
463 | 29133e9a | bellard | return pflash_read(pfl, addr, 2); |
464 | 29133e9a | bellard | } |
465 | 29133e9a | bellard | |
466 | 29133e9a | bellard | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
467 | 29133e9a | bellard | { |
468 | 29133e9a | bellard | pflash_t *pfl = opaque; |
469 | 29133e9a | bellard | |
470 | 29133e9a | bellard | return pflash_read(pfl, addr, 4); |
471 | 29133e9a | bellard | } |
472 | 29133e9a | bellard | |
473 | 29133e9a | bellard | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
474 | 29133e9a | bellard | uint32_t value) |
475 | 29133e9a | bellard | { |
476 | 29133e9a | bellard | pflash_write(opaque, addr, value, 1);
|
477 | 29133e9a | bellard | } |
478 | 29133e9a | bellard | |
479 | 29133e9a | bellard | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
480 | 29133e9a | bellard | uint32_t value) |
481 | 29133e9a | bellard | { |
482 | 29133e9a | bellard | pflash_t *pfl = opaque; |
483 | 29133e9a | bellard | |
484 | 29133e9a | bellard | pflash_write(pfl, addr, value, 2);
|
485 | 29133e9a | bellard | } |
486 | 29133e9a | bellard | |
487 | 29133e9a | bellard | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
488 | 29133e9a | bellard | uint32_t value) |
489 | 29133e9a | bellard | { |
490 | 29133e9a | bellard | pflash_t *pfl = opaque; |
491 | 29133e9a | bellard | |
492 | 29133e9a | bellard | pflash_write(pfl, addr, value, 4);
|
493 | 29133e9a | bellard | } |
494 | 29133e9a | bellard | |
495 | 29133e9a | bellard | static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
496 | 29133e9a | bellard | &pflash_writeb, |
497 | 29133e9a | bellard | &pflash_writew, |
498 | 29133e9a | bellard | &pflash_writel, |
499 | 29133e9a | bellard | }; |
500 | 29133e9a | bellard | |
501 | 29133e9a | bellard | static CPUReadMemoryFunc *pflash_read_ops[] = {
|
502 | 29133e9a | bellard | &pflash_readb, |
503 | 29133e9a | bellard | &pflash_readw, |
504 | 29133e9a | bellard | &pflash_readl, |
505 | 29133e9a | bellard | }; |
506 | 29133e9a | bellard | |
507 | 29133e9a | bellard | /* Count trailing zeroes of a 32 bits quantity */
|
508 | 29133e9a | bellard | static int ctz32 (uint32_t n) |
509 | 29133e9a | bellard | { |
510 | 29133e9a | bellard | int ret;
|
511 | 29133e9a | bellard | |
512 | 29133e9a | bellard | ret = 0;
|
513 | 29133e9a | bellard | if (!(n & 0xFFFF)) { |
514 | 29133e9a | bellard | ret += 16;
|
515 | 29133e9a | bellard | n = n >> 16;
|
516 | 29133e9a | bellard | } |
517 | 29133e9a | bellard | if (!(n & 0xFF)) { |
518 | 29133e9a | bellard | ret += 8;
|
519 | 29133e9a | bellard | n = n >> 8;
|
520 | 29133e9a | bellard | } |
521 | 29133e9a | bellard | if (!(n & 0xF)) { |
522 | 29133e9a | bellard | ret += 4;
|
523 | 29133e9a | bellard | n = n >> 4;
|
524 | 29133e9a | bellard | } |
525 | 29133e9a | bellard | if (!(n & 0x3)) { |
526 | 29133e9a | bellard | ret += 2;
|
527 | 29133e9a | bellard | n = n >> 2;
|
528 | 29133e9a | bellard | } |
529 | 29133e9a | bellard | if (!(n & 0x1)) { |
530 | 29133e9a | bellard | ret++; |
531 | 29133e9a | bellard | n = n >> 1;
|
532 | 29133e9a | bellard | } |
533 | 29133e9a | bellard | #if 0 /* This is not necessary as n is never 0 */
|
534 | 29133e9a | bellard | if (!n)
|
535 | 29133e9a | bellard | ret++;
|
536 | 29133e9a | bellard | #endif
|
537 | 29133e9a | bellard | |
538 | 29133e9a | bellard | return ret;
|
539 | 29133e9a | bellard | } |
540 | 29133e9a | bellard | |
541 | 88eeee0a | balrog | pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
542 | cf6d9118 | balrog | BlockDriverState *bs, uint32_t sector_len, |
543 | 4fbd24ba | balrog | int nb_blocs, int nb_mappings, int width, |
544 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
545 | 6725070d | balrog | uint16_t id2, uint16_t id3, |
546 | 6725070d | balrog | uint16_t unlock_addr0, uint16_t unlock_addr1) |
547 | 29133e9a | bellard | { |
548 | 29133e9a | bellard | pflash_t *pfl; |
549 | 4fbd24ba | balrog | int32_t chip_len; |
550 | 29133e9a | bellard | |
551 | 4fbd24ba | balrog | chip_len = sector_len * nb_blocs; |
552 | 29133e9a | bellard | /* XXX: to be fixed */
|
553 | 95d1f3ed | j_mayer | #if 0
|
554 | 29133e9a | bellard | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
555 | 29133e9a | bellard | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
556 | 29133e9a | bellard | return NULL;
|
557 | 95d1f3ed | j_mayer | #endif
|
558 | 29133e9a | bellard | pfl = qemu_mallocz(sizeof(pflash_t));
|
559 | 5c130f65 | pbrook | /* FIXME: Allocate ram ourselves. */
|
560 | 5c130f65 | pbrook | pfl->storage = qemu_get_ram_ptr(off); |
561 | 1eed09cb | Avi Kivity | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops, |
562 | 95d1f3ed | j_mayer | pfl); |
563 | 29133e9a | bellard | pfl->off = off; |
564 | 4fbd24ba | balrog | pfl->base = base; |
565 | 4fbd24ba | balrog | pfl->chip_len = chip_len; |
566 | 4fbd24ba | balrog | pfl->mappings = nb_mappings; |
567 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
|
568 | 29133e9a | bellard | pfl->bs = bs; |
569 | 29133e9a | bellard | if (pfl->bs) {
|
570 | 29133e9a | bellard | /* read the initial flash content */
|
571 | 4fbd24ba | balrog | bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
572 | 29133e9a | bellard | } |
573 | 29133e9a | bellard | #if 0 /* XXX: there should be a bit to set up read-only,
|
574 | 29133e9a | bellard | * the same way the hardware does (with WP pin).
|
575 | 29133e9a | bellard | */
|
576 | 29133e9a | bellard | pfl->ro = 1;
|
577 | 29133e9a | bellard | #else
|
578 | 29133e9a | bellard | pfl->ro = 0;
|
579 | 29133e9a | bellard | #endif
|
580 | 29133e9a | bellard | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
581 | 29133e9a | bellard | pfl->sector_len = sector_len; |
582 | 29133e9a | bellard | pfl->width = width; |
583 | 29133e9a | bellard | pfl->wcycle = 0;
|
584 | 29133e9a | bellard | pfl->cmd = 0;
|
585 | 29133e9a | bellard | pfl->status = 0;
|
586 | 29133e9a | bellard | pfl->ident[0] = id0;
|
587 | 29133e9a | bellard | pfl->ident[1] = id1;
|
588 | 29133e9a | bellard | pfl->ident[2] = id2;
|
589 | 29133e9a | bellard | pfl->ident[3] = id3;
|
590 | 6725070d | balrog | pfl->unlock_addr[0] = unlock_addr0;
|
591 | 6725070d | balrog | pfl->unlock_addr[1] = unlock_addr1;
|
592 | 29133e9a | bellard | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
593 | 29133e9a | bellard | pfl->cfi_len = 0x52;
|
594 | 29133e9a | bellard | /* Standard "QRY" string */
|
595 | 29133e9a | bellard | pfl->cfi_table[0x10] = 'Q'; |
596 | 29133e9a | bellard | pfl->cfi_table[0x11] = 'R'; |
597 | 29133e9a | bellard | pfl->cfi_table[0x12] = 'Y'; |
598 | 29133e9a | bellard | /* Command set (AMD/Fujitsu) */
|
599 | 29133e9a | bellard | pfl->cfi_table[0x13] = 0x02; |
600 | 29133e9a | bellard | pfl->cfi_table[0x14] = 0x00; |
601 | 78556820 | edgar_igl | /* Primary extended table address */
|
602 | 78556820 | edgar_igl | pfl->cfi_table[0x15] = 0x31; |
603 | 29133e9a | bellard | pfl->cfi_table[0x16] = 0x00; |
604 | 29133e9a | bellard | /* Alternate command set (none) */
|
605 | 29133e9a | bellard | pfl->cfi_table[0x17] = 0x00; |
606 | 29133e9a | bellard | pfl->cfi_table[0x18] = 0x00; |
607 | 29133e9a | bellard | /* Alternate extended table (none) */
|
608 | 29133e9a | bellard | pfl->cfi_table[0x19] = 0x00; |
609 | 29133e9a | bellard | pfl->cfi_table[0x1A] = 0x00; |
610 | 29133e9a | bellard | /* Vcc min */
|
611 | 29133e9a | bellard | pfl->cfi_table[0x1B] = 0x27; |
612 | 29133e9a | bellard | /* Vcc max */
|
613 | 29133e9a | bellard | pfl->cfi_table[0x1C] = 0x36; |
614 | 29133e9a | bellard | /* Vpp min (no Vpp pin) */
|
615 | 29133e9a | bellard | pfl->cfi_table[0x1D] = 0x00; |
616 | 29133e9a | bellard | /* Vpp max (no Vpp pin) */
|
617 | 29133e9a | bellard | pfl->cfi_table[0x1E] = 0x00; |
618 | 29133e9a | bellard | /* Reserved */
|
619 | 29133e9a | bellard | pfl->cfi_table[0x1F] = 0x07; |
620 | 78556820 | edgar_igl | /* Timeout for min size buffer write (NA) */
|
621 | 78556820 | edgar_igl | pfl->cfi_table[0x20] = 0x00; |
622 | 29133e9a | bellard | /* Typical timeout for block erase (512 ms) */
|
623 | 29133e9a | bellard | pfl->cfi_table[0x21] = 0x09; |
624 | 29133e9a | bellard | /* Typical timeout for full chip erase (4096 ms) */
|
625 | 29133e9a | bellard | pfl->cfi_table[0x22] = 0x0C; |
626 | 29133e9a | bellard | /* Reserved */
|
627 | 29133e9a | bellard | pfl->cfi_table[0x23] = 0x01; |
628 | 78556820 | edgar_igl | /* Max timeout for buffer write (NA) */
|
629 | 78556820 | edgar_igl | pfl->cfi_table[0x24] = 0x00; |
630 | 29133e9a | bellard | /* Max timeout for block erase */
|
631 | 29133e9a | bellard | pfl->cfi_table[0x25] = 0x0A; |
632 | 29133e9a | bellard | /* Max timeout for chip erase */
|
633 | 29133e9a | bellard | pfl->cfi_table[0x26] = 0x0D; |
634 | 29133e9a | bellard | /* Device size */
|
635 | 78556820 | edgar_igl | pfl->cfi_table[0x27] = ctz32(chip_len);
|
636 | 29133e9a | bellard | /* Flash device interface (8 & 16 bits) */
|
637 | 29133e9a | bellard | pfl->cfi_table[0x28] = 0x02; |
638 | 29133e9a | bellard | pfl->cfi_table[0x29] = 0x00; |
639 | 29133e9a | bellard | /* Max number of bytes in multi-bytes write */
|
640 | 95d1f3ed | j_mayer | /* XXX: disable buffered write as it's not supported */
|
641 | 95d1f3ed | j_mayer | // pfl->cfi_table[0x2A] = 0x05;
|
642 | 95d1f3ed | j_mayer | pfl->cfi_table[0x2A] = 0x00; |
643 | 29133e9a | bellard | pfl->cfi_table[0x2B] = 0x00; |
644 | 29133e9a | bellard | /* Number of erase block regions (uniform) */
|
645 | 29133e9a | bellard | pfl->cfi_table[0x2C] = 0x01; |
646 | 29133e9a | bellard | /* Erase block region 1 */
|
647 | 29133e9a | bellard | pfl->cfi_table[0x2D] = nb_blocs - 1; |
648 | 29133e9a | bellard | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
649 | 29133e9a | bellard | pfl->cfi_table[0x2F] = sector_len >> 8; |
650 | 29133e9a | bellard | pfl->cfi_table[0x30] = sector_len >> 16; |
651 | 29133e9a | bellard | |
652 | 78556820 | edgar_igl | /* Extended */
|
653 | 78556820 | edgar_igl | pfl->cfi_table[0x31] = 'P'; |
654 | 78556820 | edgar_igl | pfl->cfi_table[0x32] = 'R'; |
655 | 78556820 | edgar_igl | pfl->cfi_table[0x33] = 'I'; |
656 | 78556820 | edgar_igl | |
657 | 78556820 | edgar_igl | pfl->cfi_table[0x34] = '1'; |
658 | 78556820 | edgar_igl | pfl->cfi_table[0x35] = '0'; |
659 | 78556820 | edgar_igl | |
660 | 78556820 | edgar_igl | pfl->cfi_table[0x36] = 0x00; |
661 | 78556820 | edgar_igl | pfl->cfi_table[0x37] = 0x00; |
662 | 78556820 | edgar_igl | pfl->cfi_table[0x38] = 0x00; |
663 | 78556820 | edgar_igl | pfl->cfi_table[0x39] = 0x00; |
664 | 78556820 | edgar_igl | |
665 | 78556820 | edgar_igl | pfl->cfi_table[0x3a] = 0x00; |
666 | 78556820 | edgar_igl | |
667 | 78556820 | edgar_igl | pfl->cfi_table[0x3b] = 0x00; |
668 | 78556820 | edgar_igl | pfl->cfi_table[0x3c] = 0x00; |
669 | 78556820 | edgar_igl | |
670 | 29133e9a | bellard | return pfl;
|
671 | 29133e9a | bellard | } |