root / target-sparc / translate.c @ a7ec4229
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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | #include <stdarg.h> |
23 | 7a3f1944 | bellard | #include <stdlib.h> |
24 | 7a3f1944 | bellard | #include <stdio.h> |
25 | 7a3f1944 | bellard | #include <string.h> |
26 | 7a3f1944 | bellard | #include <inttypes.h> |
27 | 7a3f1944 | bellard | |
28 | 7a3f1944 | bellard | #include "cpu.h" |
29 | 7a3f1944 | bellard | #include "exec-all.h" |
30 | 7a3f1944 | bellard | #include "disas.h" |
31 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | 7a3f1944 | bellard | |
34 | 7a3f1944 | bellard | #define DEBUG_DISAS
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35 | 7a3f1944 | bellard | |
36 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
37 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
38 | 72cbca10 | bellard | according to jump_pc[T2] */
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39 | 72cbca10 | bellard | |
40 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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41 | d987963a | blueswir1 | static TCGv cpu_env, cpu_regwptr;
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42 | 77f193da | blueswir1 | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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43 | 48d5c82b | blueswir1 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
44 | 255e1fcb | blueswir1 | static TCGv cpu_y;
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45 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
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46 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
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47 | 255e1fcb | blueswir1 | #endif
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48 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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49 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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50 | 255e1fcb | blueswir1 | static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr;
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51 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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52 | 255e1fcb | blueswir1 | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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53 | 255e1fcb | blueswir1 | #else
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54 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
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55 | dc99a3f2 | blueswir1 | #endif
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56 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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57 | 8911f501 | blueswir1 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
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58 | 714547bb | blueswir1 | /* Floating point registers */
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59 | 714547bb | blueswir1 | static TCGv cpu_fpr[TARGET_FPREGS];
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60 | 1a2fb1c0 | blueswir1 | |
61 | 2e70f6ef | pbrook | #include "gen-icount.h" |
62 | 2e70f6ef | pbrook | |
63 | 7a3f1944 | bellard | typedef struct DisasContext { |
64 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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65 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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66 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
67 | cf495bcf | bellard | int is_br;
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68 | e8af50a3 | bellard | int mem_idx;
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69 | a80dde08 | bellard | int fpu_enabled;
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70 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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71 | cf495bcf | bellard | struct TranslationBlock *tb;
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72 | 5578ceab | blueswir1 | sparc_def_t *def; |
73 | 7a3f1944 | bellard | } DisasContext; |
74 | 7a3f1944 | bellard | |
75 | 3475187d | bellard | // This function uses non-native bit order
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76 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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77 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
78 | 7a3f1944 | bellard | |
79 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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80 | 3475187d | bellard | #define GET_FIELD_SP(X, FROM, TO) \
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81 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
82 | 3475187d | bellard | |
83 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
84 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
85 | 3475187d | bellard | |
86 | 3475187d | bellard | #ifdef TARGET_SPARC64
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87 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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88 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
89 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
90 | 3475187d | bellard | #else
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91 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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92 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
93 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
94 | 3475187d | bellard | #endif
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95 | 3475187d | bellard | |
96 | 3475187d | bellard | static int sign_extend(int x, int len) |
97 | 3475187d | bellard | { |
98 | 3475187d | bellard | len = 32 - len;
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99 | 3475187d | bellard | return (x << len) >> len;
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100 | 3475187d | bellard | } |
101 | 3475187d | bellard | |
102 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
103 | 7a3f1944 | bellard | |
104 | ff07ec83 | blueswir1 | /* floating point registers moves */
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105 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
106 | ff07ec83 | blueswir1 | { |
107 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
108 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
109 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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110 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
111 | ff07ec83 | blueswir1 | } |
112 | ff07ec83 | blueswir1 | |
113 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
114 | ff07ec83 | blueswir1 | { |
115 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
116 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
117 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
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118 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
119 | ff07ec83 | blueswir1 | } |
120 | ff07ec83 | blueswir1 | |
121 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
122 | ff07ec83 | blueswir1 | { |
123 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
124 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
125 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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126 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
127 | ff07ec83 | blueswir1 | } |
128 | ff07ec83 | blueswir1 | |
129 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
130 | ff07ec83 | blueswir1 | { |
131 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
132 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
133 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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134 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
135 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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136 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
137 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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138 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
139 | ff07ec83 | blueswir1 | } |
140 | ff07ec83 | blueswir1 | |
141 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
142 | ff07ec83 | blueswir1 | { |
143 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
144 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
145 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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146 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
147 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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148 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
149 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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150 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
151 | ff07ec83 | blueswir1 | } |
152 | ff07ec83 | blueswir1 | |
153 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
154 | ff07ec83 | blueswir1 | { |
155 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
156 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
157 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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158 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
159 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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160 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
161 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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162 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
163 | ff07ec83 | blueswir1 | } |
164 | 1f587329 | blueswir1 | |
165 | 81ad8ba2 | blueswir1 | /* moves */
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166 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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167 | 3475187d | bellard | #define supervisor(dc) 0 |
168 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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169 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
170 | 81ad8ba2 | blueswir1 | #endif
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171 | 3475187d | bellard | #else
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172 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
173 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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174 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
175 | 6f27aba6 | blueswir1 | #else
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176 | 3475187d | bellard | #endif
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177 | 81ad8ba2 | blueswir1 | #endif
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178 | 81ad8ba2 | blueswir1 | |
179 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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180 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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181 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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182 | 1a2fb1c0 | blueswir1 | #else
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183 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
184 | 2cade6a3 | blueswir1 | #endif
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185 | 1a2fb1c0 | blueswir1 | #endif
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186 | 3391c818 | blueswir1 | |
187 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
188 | 2cade6a3 | blueswir1 | { |
189 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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190 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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191 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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192 | 2cade6a3 | blueswir1 | #endif
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193 | 2cade6a3 | blueswir1 | } |
194 | 2cade6a3 | blueswir1 | |
195 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
196 | 81ad8ba2 | blueswir1 | { |
197 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
198 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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199 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
200 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
201 | 1a2fb1c0 | blueswir1 | else {
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202 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
203 | 81ad8ba2 | blueswir1 | } |
204 | 81ad8ba2 | blueswir1 | } |
205 | 81ad8ba2 | blueswir1 | |
206 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
207 | 81ad8ba2 | blueswir1 | { |
208 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
209 | 1a2fb1c0 | blueswir1 | return;
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210 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
211 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
212 | 1a2fb1c0 | blueswir1 | else {
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213 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
214 | 81ad8ba2 | blueswir1 | } |
215 | 81ad8ba2 | blueswir1 | } |
216 | 81ad8ba2 | blueswir1 | |
217 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
218 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
219 | 6e256c93 | bellard | { |
220 | 6e256c93 | bellard | TranslationBlock *tb; |
221 | 6e256c93 | bellard | |
222 | 6e256c93 | bellard | tb = s->tb; |
223 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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224 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
225 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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226 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
227 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
228 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
229 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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230 | 6e256c93 | bellard | } else {
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231 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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232 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
233 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
234 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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235 | 6e256c93 | bellard | } |
236 | 6e256c93 | bellard | } |
237 | 6e256c93 | bellard | |
238 | 19f329ad | blueswir1 | // XXX suboptimal
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239 | 19f329ad | blueswir1 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
240 | 19f329ad | blueswir1 | { |
241 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
242 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
243 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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244 | 19f329ad | blueswir1 | } |
245 | 19f329ad | blueswir1 | |
246 | 19f329ad | blueswir1 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
247 | 19f329ad | blueswir1 | { |
248 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
249 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
250 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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251 | 19f329ad | blueswir1 | } |
252 | 19f329ad | blueswir1 | |
253 | 19f329ad | blueswir1 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
254 | 19f329ad | blueswir1 | { |
255 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
256 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
257 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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258 | 19f329ad | blueswir1 | } |
259 | 19f329ad | blueswir1 | |
260 | 19f329ad | blueswir1 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
261 | 19f329ad | blueswir1 | { |
262 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
263 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
264 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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265 | 19f329ad | blueswir1 | } |
266 | 19f329ad | blueswir1 | |
267 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_icc(void) |
268 | dc99a3f2 | blueswir1 | { |
269 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_psr, 0);
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270 | ce5b3c3d | blueswir1 | } |
271 | ce5b3c3d | blueswir1 | |
272 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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273 | ce5b3c3d | blueswir1 | static inline void gen_cc_clear_xcc(void) |
274 | ce5b3c3d | blueswir1 | { |
275 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_xcc, 0);
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276 | dc99a3f2 | blueswir1 | } |
277 | ce5b3c3d | blueswir1 | #endif
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278 | dc99a3f2 | blueswir1 | |
279 | dc99a3f2 | blueswir1 | /* old op:
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280 | dc99a3f2 | blueswir1 | if (!T0)
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281 | dc99a3f2 | blueswir1 | env->psr |= PSR_ZERO;
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282 | dc99a3f2 | blueswir1 | if ((int32_t) T0 < 0)
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283 | dc99a3f2 | blueswir1 | env->psr |= PSR_NEG;
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284 | dc99a3f2 | blueswir1 | */
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285 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_icc(TCGv dst) |
286 | dc99a3f2 | blueswir1 | { |
287 | 8911f501 | blueswir1 | TCGv r_temp; |
288 | dc99a3f2 | blueswir1 | int l1, l2;
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289 | dc99a3f2 | blueswir1 | |
290 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
291 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
292 | 8911f501 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
293 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
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294 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
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295 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
296 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
297 | bdf46ea2 | blueswir1 | tcg_gen_ext_i32_tl(r_temp, dst); |
298 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
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299 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
300 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
301 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
302 | ce5b3c3d | blueswir1 | } |
303 | ce5b3c3d | blueswir1 | |
304 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
305 | ce5b3c3d | blueswir1 | static inline void gen_cc_NZ_xcc(TCGv dst) |
306 | ce5b3c3d | blueswir1 | { |
307 | ce5b3c3d | blueswir1 | int l1, l2;
|
308 | ce5b3c3d | blueswir1 | |
309 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
310 | ce5b3c3d | blueswir1 | l2 = gen_new_label(); |
311 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
|
312 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
313 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
314 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
|
315 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
316 | ce5b3c3d | blueswir1 | gen_set_label(l2); |
317 | dc99a3f2 | blueswir1 | } |
318 | ce5b3c3d | blueswir1 | #endif
|
319 | dc99a3f2 | blueswir1 | |
320 | dc99a3f2 | blueswir1 | /* old op:
|
321 | dc99a3f2 | blueswir1 | if (T0 < src1)
|
322 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
323 | dc99a3f2 | blueswir1 | */
|
324 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
325 | dc99a3f2 | blueswir1 | { |
326 | 2ae72bce | blueswir1 | TCGv r_temp1, r_temp2; |
327 | dc99a3f2 | blueswir1 | int l1;
|
328 | dc99a3f2 | blueswir1 | |
329 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
330 | 2ae72bce | blueswir1 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
331 | 2ae72bce | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
332 | 2ae72bce | blueswir1 | tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
|
333 | 2ae72bce | blueswir1 | tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
|
334 | 2ae72bce | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
335 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
336 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
337 | 2ae72bce | blueswir1 | tcg_temp_free(r_temp1); |
338 | 2ae72bce | blueswir1 | tcg_temp_free(r_temp2); |
339 | ce5b3c3d | blueswir1 | } |
340 | ce5b3c3d | blueswir1 | |
341 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
342 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
343 | ce5b3c3d | blueswir1 | { |
344 | ce5b3c3d | blueswir1 | int l1;
|
345 | dc99a3f2 | blueswir1 | |
346 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
347 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
348 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
349 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
350 | dc99a3f2 | blueswir1 | } |
351 | ce5b3c3d | blueswir1 | #endif
|
352 | dc99a3f2 | blueswir1 | |
353 | dc99a3f2 | blueswir1 | /* old op:
|
354 | dc99a3f2 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
|
355 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
356 | dc99a3f2 | blueswir1 | */
|
357 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
358 | dc99a3f2 | blueswir1 | { |
359 | 0425bee5 | blueswir1 | TCGv r_temp; |
360 | dc99a3f2 | blueswir1 | |
361 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
362 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
363 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
364 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
365 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
366 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
367 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
368 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
369 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
370 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
371 | ce5b3c3d | blueswir1 | } |
372 | ce5b3c3d | blueswir1 | |
373 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
374 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
375 | ce5b3c3d | blueswir1 | { |
376 | ce5b3c3d | blueswir1 | TCGv r_temp; |
377 | ce5b3c3d | blueswir1 | |
378 | ce5b3c3d | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
379 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
380 | ce5b3c3d | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
381 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
382 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
383 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
384 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
385 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
386 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
387 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
388 | dc99a3f2 | blueswir1 | } |
389 | ce5b3c3d | blueswir1 | #endif
|
390 | dc99a3f2 | blueswir1 | |
391 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
392 | dc99a3f2 | blueswir1 | { |
393 | 2ea815ca | blueswir1 | TCGv r_temp, r_const; |
394 | dc99a3f2 | blueswir1 | int l1;
|
395 | dc99a3f2 | blueswir1 | |
396 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
397 | dc99a3f2 | blueswir1 | |
398 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
399 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
400 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
401 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
402 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
403 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
404 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
405 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
406 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
407 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
408 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
409 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
410 | dc99a3f2 | blueswir1 | } |
411 | dc99a3f2 | blueswir1 | |
412 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
413 | dc99a3f2 | blueswir1 | { |
414 | dc99a3f2 | blueswir1 | int l1;
|
415 | dc99a3f2 | blueswir1 | |
416 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
417 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
418 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
419 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
420 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
421 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
422 | dc99a3f2 | blueswir1 | } |
423 | dc99a3f2 | blueswir1 | |
424 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
425 | dc99a3f2 | blueswir1 | { |
426 | dc99a3f2 | blueswir1 | int l1;
|
427 | 2ea815ca | blueswir1 | TCGv r_const; |
428 | dc99a3f2 | blueswir1 | |
429 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
430 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
431 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
432 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
433 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
434 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
435 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
436 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
437 | dc99a3f2 | blueswir1 | } |
438 | dc99a3f2 | blueswir1 | |
439 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
440 | dc99a3f2 | blueswir1 | { |
441 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
442 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
443 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
444 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
445 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
446 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
447 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
448 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
449 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
450 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
451 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
452 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
453 | ce5b3c3d | blueswir1 | #endif
|
454 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
455 | dc99a3f2 | blueswir1 | } |
456 | dc99a3f2 | blueswir1 | |
457 | 4af984a7 | blueswir1 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
458 | dc99a3f2 | blueswir1 | { |
459 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
460 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
461 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
462 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
463 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
464 | 5c6a0628 | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
465 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
466 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
467 | 5c6a0628 | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
468 | ce5b3c3d | blueswir1 | #endif
|
469 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
470 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
471 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
472 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
473 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
474 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
475 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
476 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
477 | ce5b3c3d | blueswir1 | #endif
|
478 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
479 | dc99a3f2 | blueswir1 | } |
480 | dc99a3f2 | blueswir1 | |
481 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
482 | dc99a3f2 | blueswir1 | { |
483 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
484 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
485 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
486 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
487 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
488 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
489 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
490 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
491 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
492 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
493 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
494 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
495 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
496 | ce5b3c3d | blueswir1 | #endif
|
497 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
498 | dc99a3f2 | blueswir1 | } |
499 | dc99a3f2 | blueswir1 | |
500 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
501 | dc99a3f2 | blueswir1 | { |
502 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
503 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
504 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
505 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
506 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
507 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
508 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
509 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
510 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
511 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
512 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
513 | ba28189b | blueswir1 | gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src); |
514 | ba28189b | blueswir1 | gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
515 | ce5b3c3d | blueswir1 | #endif
|
516 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
517 | dc99a3f2 | blueswir1 | } |
518 | dc99a3f2 | blueswir1 | |
519 | dc99a3f2 | blueswir1 | /* old op:
|
520 | dc99a3f2 | blueswir1 | if (src1 < T1)
|
521 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
522 | dc99a3f2 | blueswir1 | */
|
523 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
524 | dc99a3f2 | blueswir1 | { |
525 | 8911f501 | blueswir1 | TCGv r_temp1, r_temp2; |
526 | dc99a3f2 | blueswir1 | int l1;
|
527 | dc99a3f2 | blueswir1 | |
528 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
529 | 8911f501 | blueswir1 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
530 | 8911f501 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
531 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
|
532 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
|
533 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
534 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
535 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
536 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp1); |
537 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
538 | ce5b3c3d | blueswir1 | } |
539 | ce5b3c3d | blueswir1 | |
540 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
541 | ce5b3c3d | blueswir1 | static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
542 | ce5b3c3d | blueswir1 | { |
543 | ce5b3c3d | blueswir1 | int l1;
|
544 | dc99a3f2 | blueswir1 | |
545 | ce5b3c3d | blueswir1 | l1 = gen_new_label(); |
546 | ce5b3c3d | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); |
547 | ce5b3c3d | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
548 | ce5b3c3d | blueswir1 | gen_set_label(l1); |
549 | dc99a3f2 | blueswir1 | } |
550 | ce5b3c3d | blueswir1 | #endif
|
551 | dc99a3f2 | blueswir1 | |
552 | dc99a3f2 | blueswir1 | /* old op:
|
553 | dc99a3f2 | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
|
554 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
555 | dc99a3f2 | blueswir1 | */
|
556 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
557 | dc99a3f2 | blueswir1 | { |
558 | 0425bee5 | blueswir1 | TCGv r_temp; |
559 | dc99a3f2 | blueswir1 | |
560 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
561 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
562 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
563 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
564 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
565 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
|
566 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
567 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
568 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
569 | ce5b3c3d | blueswir1 | } |
570 | ce5b3c3d | blueswir1 | |
571 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
572 | ce5b3c3d | blueswir1 | static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
573 | ce5b3c3d | blueswir1 | { |
574 | ce5b3c3d | blueswir1 | TCGv r_temp; |
575 | ce5b3c3d | blueswir1 | |
576 | ce5b3c3d | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
577 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
578 | ce5b3c3d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
579 | ce5b3c3d | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
580 | ce5b3c3d | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
581 | 653ccb80 | blueswir1 | tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
|
582 | 653ccb80 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
583 | 653ccb80 | blueswir1 | tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
584 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
585 | dc99a3f2 | blueswir1 | } |
586 | ce5b3c3d | blueswir1 | #endif
|
587 | dc99a3f2 | blueswir1 | |
588 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
589 | dc99a3f2 | blueswir1 | { |
590 | 2ea815ca | blueswir1 | TCGv r_temp, r_const; |
591 | dc99a3f2 | blueswir1 | int l1;
|
592 | dc99a3f2 | blueswir1 | |
593 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
594 | dc99a3f2 | blueswir1 | |
595 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
596 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
597 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
598 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
599 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
600 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
601 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
602 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
603 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
604 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
605 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
606 | dc99a3f2 | blueswir1 | } |
607 | dc99a3f2 | blueswir1 | |
608 | 4af984a7 | blueswir1 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
609 | dc99a3f2 | blueswir1 | { |
610 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
611 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
612 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
613 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
614 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
615 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
616 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
617 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
618 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
619 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
620 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
621 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
622 | ce5b3c3d | blueswir1 | #endif
|
623 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
624 | dc99a3f2 | blueswir1 | } |
625 | dc99a3f2 | blueswir1 | |
626 | 4af984a7 | blueswir1 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
627 | dc99a3f2 | blueswir1 | { |
628 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
629 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
630 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
631 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
632 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
633 | 5c6a0628 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
634 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
635 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
636 | 5c6a0628 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
637 | ce5b3c3d | blueswir1 | #endif
|
638 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
639 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
640 | ba28189b | blueswir1 | gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); |
641 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
642 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
643 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
644 | ba28189b | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); |
645 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
646 | ce5b3c3d | blueswir1 | #endif
|
647 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
648 | dc99a3f2 | blueswir1 | } |
649 | dc99a3f2 | blueswir1 | |
650 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
651 | dc99a3f2 | blueswir1 | { |
652 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
653 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
654 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
655 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
656 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
657 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
658 | ba28189b | blueswir1 | gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
659 | 6f551262 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); |
660 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
661 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
662 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
663 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
664 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
665 | ce5b3c3d | blueswir1 | #endif
|
666 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
667 | dc99a3f2 | blueswir1 | } |
668 | dc99a3f2 | blueswir1 | |
669 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
670 | dc99a3f2 | blueswir1 | { |
671 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
672 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
673 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
674 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
675 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
676 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
677 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
678 | 6f551262 | blueswir1 | gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); |
679 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
680 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
681 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
682 | 6f551262 | blueswir1 | gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); |
683 | ba28189b | blueswir1 | gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
684 | ce5b3c3d | blueswir1 | #endif
|
685 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
686 | dc99a3f2 | blueswir1 | } |
687 | dc99a3f2 | blueswir1 | |
688 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
689 | d9bdab86 | blueswir1 | { |
690 | 105a1f04 | blueswir1 | TCGv r_temp; |
691 | 6f551262 | blueswir1 | int l1;
|
692 | d9bdab86 | blueswir1 | |
693 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
694 | d9bdab86 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
695 | d9bdab86 | blueswir1 | |
696 | d9bdab86 | blueswir1 | /* old op:
|
697 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
698 | d9bdab86 | blueswir1 | T1 = 0;
|
699 | d9bdab86 | blueswir1 | */
|
700 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
701 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
702 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
703 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
704 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
705 | 6f551262 | blueswir1 | gen_set_label(l1); |
706 | d9bdab86 | blueswir1 | |
707 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
708 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
709 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
710 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
711 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
712 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
713 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
714 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
715 | d9bdab86 | blueswir1 | |
716 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
717 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
718 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
719 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
720 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
721 | d9bdab86 | blueswir1 | |
722 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
723 | d9bdab86 | blueswir1 | // src1 = T0;
|
724 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
725 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
726 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
727 | d9bdab86 | blueswir1 | |
728 | d9bdab86 | blueswir1 | /* do addition and update flags */
|
729 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
730 | d9bdab86 | blueswir1 | |
731 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
732 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
733 | ba28189b | blueswir1 | gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
734 | ba28189b | blueswir1 | gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
735 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
736 | d9bdab86 | blueswir1 | } |
737 | d9bdab86 | blueswir1 | |
738 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
739 | 8879d139 | blueswir1 | { |
740 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
741 | 8879d139 | blueswir1 | |
742 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
743 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
744 | 8879d139 | blueswir1 | |
745 | b991c385 | blueswir1 | tcg_gen_extu_i32_i64(r_temp, src2); |
746 | b991c385 | blueswir1 | tcg_gen_extu_i32_i64(r_temp2, src1); |
747 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
748 | 8879d139 | blueswir1 | |
749 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
750 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
751 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
752 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
753 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
754 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
755 | 8879d139 | blueswir1 | #else
|
756 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
757 | 8879d139 | blueswir1 | #endif
|
758 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
759 | 8879d139 | blueswir1 | } |
760 | 8879d139 | blueswir1 | |
761 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
762 | 8879d139 | blueswir1 | { |
763 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
764 | 8879d139 | blueswir1 | |
765 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
766 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
767 | 8879d139 | blueswir1 | |
768 | b991c385 | blueswir1 | tcg_gen_ext_i32_i64(r_temp, src2); |
769 | b991c385 | blueswir1 | tcg_gen_ext_i32_i64(r_temp2, src1); |
770 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
771 | 8879d139 | blueswir1 | |
772 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
773 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
774 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
775 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
776 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
777 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
778 | 8879d139 | blueswir1 | #else
|
779 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
780 | 8879d139 | blueswir1 | #endif
|
781 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp2); |
782 | 8879d139 | blueswir1 | } |
783 | 8879d139 | blueswir1 | |
784 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
785 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
786 | 1a7b60e7 | blueswir1 | { |
787 | 2ea815ca | blueswir1 | TCGv r_const; |
788 | 1a7b60e7 | blueswir1 | int l1;
|
789 | 1a7b60e7 | blueswir1 | |
790 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
791 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
792 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
793 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
794 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
795 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
796 | 1a7b60e7 | blueswir1 | } |
797 | 1a7b60e7 | blueswir1 | |
798 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
799 | 1a7b60e7 | blueswir1 | { |
800 | 1a7b60e7 | blueswir1 | int l1, l2;
|
801 | 1a7b60e7 | blueswir1 | |
802 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
803 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
804 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
805 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
806 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
807 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
808 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
809 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
810 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
811 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
812 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
813 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
814 | 1a7b60e7 | blueswir1 | } |
815 | 1a7b60e7 | blueswir1 | #endif
|
816 | 1a7b60e7 | blueswir1 | |
817 | 4af984a7 | blueswir1 | static inline void gen_op_div_cc(TCGv dst) |
818 | dc99a3f2 | blueswir1 | { |
819 | dc99a3f2 | blueswir1 | int l1;
|
820 | dc99a3f2 | blueswir1 | |
821 | ba28189b | blueswir1 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
822 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
823 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
824 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
825 | 5c6a0628 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
|
826 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
827 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
828 | dc99a3f2 | blueswir1 | } |
829 | dc99a3f2 | blueswir1 | |
830 | 4af984a7 | blueswir1 | static inline void gen_op_logic_cc(TCGv dst) |
831 | dc99a3f2 | blueswir1 | { |
832 | ba28189b | blueswir1 | tcg_gen_mov_tl(cpu_cc_dst, dst); |
833 | ba28189b | blueswir1 | |
834 | ce5b3c3d | blueswir1 | gen_cc_clear_icc(); |
835 | ba28189b | blueswir1 | gen_cc_NZ_icc(cpu_cc_dst); |
836 | ce5b3c3d | blueswir1 | #ifdef TARGET_SPARC64
|
837 | ce5b3c3d | blueswir1 | gen_cc_clear_xcc(); |
838 | ba28189b | blueswir1 | gen_cc_NZ_xcc(cpu_cc_dst); |
839 | ce5b3c3d | blueswir1 | #endif
|
840 | dc99a3f2 | blueswir1 | } |
841 | dc99a3f2 | blueswir1 | |
842 | 19f329ad | blueswir1 | // 1
|
843 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
844 | 19f329ad | blueswir1 | { |
845 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
846 | 19f329ad | blueswir1 | } |
847 | 19f329ad | blueswir1 | |
848 | 19f329ad | blueswir1 | // Z
|
849 | 19f329ad | blueswir1 | static inline void gen_op_eval_be(TCGv dst, TCGv src) |
850 | 19f329ad | blueswir1 | { |
851 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
852 | 19f329ad | blueswir1 | } |
853 | 19f329ad | blueswir1 | |
854 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
855 | 19f329ad | blueswir1 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) |
856 | 19f329ad | blueswir1 | { |
857 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
858 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
859 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
860 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
861 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
862 | 19f329ad | blueswir1 | } |
863 | 19f329ad | blueswir1 | |
864 | 19f329ad | blueswir1 | // N ^ V
|
865 | 19f329ad | blueswir1 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) |
866 | 19f329ad | blueswir1 | { |
867 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
868 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
869 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
870 | 19f329ad | blueswir1 | } |
871 | 19f329ad | blueswir1 | |
872 | 19f329ad | blueswir1 | // C | Z
|
873 | 19f329ad | blueswir1 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) |
874 | 19f329ad | blueswir1 | { |
875 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
876 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
877 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
878 | 19f329ad | blueswir1 | } |
879 | 19f329ad | blueswir1 | |
880 | 19f329ad | blueswir1 | // C
|
881 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) |
882 | 19f329ad | blueswir1 | { |
883 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
884 | 19f329ad | blueswir1 | } |
885 | 19f329ad | blueswir1 | |
886 | 19f329ad | blueswir1 | // V
|
887 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) |
888 | 19f329ad | blueswir1 | { |
889 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
890 | 19f329ad | blueswir1 | } |
891 | 19f329ad | blueswir1 | |
892 | 19f329ad | blueswir1 | // 0
|
893 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
894 | 19f329ad | blueswir1 | { |
895 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
896 | 19f329ad | blueswir1 | } |
897 | 19f329ad | blueswir1 | |
898 | 19f329ad | blueswir1 | // N
|
899 | 19f329ad | blueswir1 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) |
900 | 19f329ad | blueswir1 | { |
901 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
902 | 19f329ad | blueswir1 | } |
903 | 19f329ad | blueswir1 | |
904 | 19f329ad | blueswir1 | // !Z
|
905 | 19f329ad | blueswir1 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) |
906 | 19f329ad | blueswir1 | { |
907 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
908 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
909 | 19f329ad | blueswir1 | } |
910 | 19f329ad | blueswir1 | |
911 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
912 | 19f329ad | blueswir1 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) |
913 | 19f329ad | blueswir1 | { |
914 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
915 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
916 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
917 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
918 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
919 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
920 | 19f329ad | blueswir1 | } |
921 | 19f329ad | blueswir1 | |
922 | 19f329ad | blueswir1 | // !(N ^ V)
|
923 | 19f329ad | blueswir1 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) |
924 | 19f329ad | blueswir1 | { |
925 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
926 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
927 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
928 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
929 | 19f329ad | blueswir1 | } |
930 | 19f329ad | blueswir1 | |
931 | 19f329ad | blueswir1 | // !(C | Z)
|
932 | 19f329ad | blueswir1 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) |
933 | 19f329ad | blueswir1 | { |
934 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
935 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
936 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
937 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
938 | 19f329ad | blueswir1 | } |
939 | 19f329ad | blueswir1 | |
940 | 19f329ad | blueswir1 | // !C
|
941 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) |
942 | 19f329ad | blueswir1 | { |
943 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
944 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
945 | 19f329ad | blueswir1 | } |
946 | 19f329ad | blueswir1 | |
947 | 19f329ad | blueswir1 | // !N
|
948 | 19f329ad | blueswir1 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) |
949 | 19f329ad | blueswir1 | { |
950 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
951 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
952 | 19f329ad | blueswir1 | } |
953 | 19f329ad | blueswir1 | |
954 | 19f329ad | blueswir1 | // !V
|
955 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) |
956 | 19f329ad | blueswir1 | { |
957 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
958 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
959 | 19f329ad | blueswir1 | } |
960 | 19f329ad | blueswir1 | |
961 | 19f329ad | blueswir1 | /*
|
962 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
963 | 19f329ad | blueswir1 | 0 =
|
964 | 19f329ad | blueswir1 | 1 <
|
965 | 19f329ad | blueswir1 | 2 >
|
966 | 19f329ad | blueswir1 | 3 unordered
|
967 | 19f329ad | blueswir1 | */
|
968 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
969 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
970 | 19f329ad | blueswir1 | { |
971 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
972 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
973 | 19f329ad | blueswir1 | } |
974 | 19f329ad | blueswir1 | |
975 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
976 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
977 | 19f329ad | blueswir1 | { |
978 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
979 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
980 | 19f329ad | blueswir1 | } |
981 | 19f329ad | blueswir1 | |
982 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
983 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
984 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
985 | 19f329ad | blueswir1 | { |
986 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
987 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
988 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
989 | 19f329ad | blueswir1 | } |
990 | 19f329ad | blueswir1 | |
991 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
992 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
993 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
994 | 19f329ad | blueswir1 | { |
995 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
996 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
997 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
998 | 19f329ad | blueswir1 | } |
999 | 19f329ad | blueswir1 | |
1000 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
1001 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
1002 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1003 | 19f329ad | blueswir1 | { |
1004 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1005 | 19f329ad | blueswir1 | } |
1006 | 19f329ad | blueswir1 | |
1007 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
1008 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
1009 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1010 | 19f329ad | blueswir1 | { |
1011 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1012 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1013 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1014 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1015 | 19f329ad | blueswir1 | } |
1016 | 19f329ad | blueswir1 | |
1017 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
1018 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
1019 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1020 | 19f329ad | blueswir1 | { |
1021 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1022 | 19f329ad | blueswir1 | } |
1023 | 19f329ad | blueswir1 | |
1024 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
1025 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
1026 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1027 | 19f329ad | blueswir1 | { |
1028 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1029 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1030 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1031 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1032 | 19f329ad | blueswir1 | } |
1033 | 19f329ad | blueswir1 | |
1034 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
1035 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
1036 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1037 | 19f329ad | blueswir1 | { |
1038 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1039 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1040 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1041 | 19f329ad | blueswir1 | } |
1042 | 19f329ad | blueswir1 | |
1043 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
1044 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
1045 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1046 | 19f329ad | blueswir1 | { |
1047 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1048 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1049 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1050 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1051 | 19f329ad | blueswir1 | } |
1052 | 19f329ad | blueswir1 | |
1053 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
1054 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
1055 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1056 | 19f329ad | blueswir1 | { |
1057 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1058 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1059 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1060 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1061 | 19f329ad | blueswir1 | } |
1062 | 19f329ad | blueswir1 | |
1063 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
1064 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
1065 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1066 | 19f329ad | blueswir1 | { |
1067 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1068 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1069 | 19f329ad | blueswir1 | } |
1070 | 19f329ad | blueswir1 | |
1071 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
1072 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
1073 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1074 | 19f329ad | blueswir1 | { |
1075 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1076 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1077 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1078 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1079 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1080 | 19f329ad | blueswir1 | } |
1081 | 19f329ad | blueswir1 | |
1082 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
1083 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
1084 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1085 | 19f329ad | blueswir1 | { |
1086 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1087 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1088 | 19f329ad | blueswir1 | } |
1089 | 19f329ad | blueswir1 | |
1090 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
1091 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
1092 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1093 | 19f329ad | blueswir1 | { |
1094 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1095 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1096 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1097 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1098 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1099 | 19f329ad | blueswir1 | } |
1100 | 19f329ad | blueswir1 | |
1101 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1102 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1103 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1104 | 19f329ad | blueswir1 | { |
1105 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1106 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1107 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1108 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1109 | 19f329ad | blueswir1 | } |
1110 | 19f329ad | blueswir1 | |
1111 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1112 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1113 | 83469015 | bellard | { |
1114 | 83469015 | bellard | int l1;
|
1115 | 83469015 | bellard | |
1116 | 83469015 | bellard | l1 = gen_new_label(); |
1117 | 83469015 | bellard | |
1118 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1119 | 83469015 | bellard | |
1120 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1121 | 83469015 | bellard | |
1122 | 83469015 | bellard | gen_set_label(l1); |
1123 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1124 | 83469015 | bellard | } |
1125 | 83469015 | bellard | |
1126 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1127 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1128 | 83469015 | bellard | { |
1129 | 83469015 | bellard | int l1;
|
1130 | 83469015 | bellard | |
1131 | 83469015 | bellard | l1 = gen_new_label(); |
1132 | 83469015 | bellard | |
1133 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1134 | 83469015 | bellard | |
1135 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1136 | 83469015 | bellard | |
1137 | 83469015 | bellard | gen_set_label(l1); |
1138 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1139 | 83469015 | bellard | } |
1140 | 83469015 | bellard | |
1141 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1142 | 19f329ad | blueswir1 | TCGv r_cond) |
1143 | 83469015 | bellard | { |
1144 | 83469015 | bellard | int l1, l2;
|
1145 | 83469015 | bellard | |
1146 | 83469015 | bellard | l1 = gen_new_label(); |
1147 | 83469015 | bellard | l2 = gen_new_label(); |
1148 | 19f329ad | blueswir1 | |
1149 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1150 | 83469015 | bellard | |
1151 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
1152 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1153 | 83469015 | bellard | |
1154 | 83469015 | bellard | gen_set_label(l1); |
1155 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
1156 | 83469015 | bellard | gen_set_label(l2); |
1157 | 83469015 | bellard | } |
1158 | 83469015 | bellard | |
1159 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
1160 | 4af984a7 | blueswir1 | have been set for a jump */
|
1161 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
1162 | 83469015 | bellard | { |
1163 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1164 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1165 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1166 | 83469015 | bellard | } |
1167 | 83469015 | bellard | } |
1168 | 83469015 | bellard | |
1169 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
1170 | 72cbca10 | bellard | { |
1171 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1172 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1173 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1174 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1175 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
1176 | 72cbca10 | bellard | } |
1177 | 72cbca10 | bellard | } |
1178 | 72cbca10 | bellard | |
1179 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
1180 | 72cbca10 | bellard | { |
1181 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1182 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
1183 | 72cbca10 | bellard | } |
1184 | 72cbca10 | bellard | |
1185 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
1186 | 0bee699e | bellard | { |
1187 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1188 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1189 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1190 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1191 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1192 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1193 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1194 | 0bee699e | bellard | } else {
|
1195 | 0bee699e | bellard | dc->pc = dc->npc; |
1196 | 0bee699e | bellard | } |
1197 | 0bee699e | bellard | } |
1198 | 0bee699e | bellard | |
1199 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1200 | 38bc628b | blueswir1 | { |
1201 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1202 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1203 | 38bc628b | blueswir1 | } |
1204 | 38bc628b | blueswir1 | |
1205 | 19f329ad | blueswir1 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1206 | 19f329ad | blueswir1 | { |
1207 | 19f329ad | blueswir1 | TCGv r_src; |
1208 | 3475187d | bellard | |
1209 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1210 | 19f329ad | blueswir1 | if (cc)
|
1211 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1212 | 19f329ad | blueswir1 | else
|
1213 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1214 | 3475187d | bellard | #else
|
1215 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1216 | 3475187d | bellard | #endif
|
1217 | 19f329ad | blueswir1 | switch (cond) {
|
1218 | 19f329ad | blueswir1 | case 0x0: |
1219 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1220 | 19f329ad | blueswir1 | break;
|
1221 | 19f329ad | blueswir1 | case 0x1: |
1222 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1223 | 19f329ad | blueswir1 | break;
|
1224 | 19f329ad | blueswir1 | case 0x2: |
1225 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1226 | 19f329ad | blueswir1 | break;
|
1227 | 19f329ad | blueswir1 | case 0x3: |
1228 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1229 | 19f329ad | blueswir1 | break;
|
1230 | 19f329ad | blueswir1 | case 0x4: |
1231 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1232 | 19f329ad | blueswir1 | break;
|
1233 | 19f329ad | blueswir1 | case 0x5: |
1234 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1235 | 19f329ad | blueswir1 | break;
|
1236 | 19f329ad | blueswir1 | case 0x6: |
1237 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1238 | 19f329ad | blueswir1 | break;
|
1239 | 19f329ad | blueswir1 | case 0x7: |
1240 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1241 | 19f329ad | blueswir1 | break;
|
1242 | 19f329ad | blueswir1 | case 0x8: |
1243 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1244 | 19f329ad | blueswir1 | break;
|
1245 | 19f329ad | blueswir1 | case 0x9: |
1246 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1247 | 19f329ad | blueswir1 | break;
|
1248 | 19f329ad | blueswir1 | case 0xa: |
1249 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1250 | 19f329ad | blueswir1 | break;
|
1251 | 19f329ad | blueswir1 | case 0xb: |
1252 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1253 | 19f329ad | blueswir1 | break;
|
1254 | 19f329ad | blueswir1 | case 0xc: |
1255 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1256 | 19f329ad | blueswir1 | break;
|
1257 | 19f329ad | blueswir1 | case 0xd: |
1258 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1259 | 19f329ad | blueswir1 | break;
|
1260 | 19f329ad | blueswir1 | case 0xe: |
1261 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1262 | 19f329ad | blueswir1 | break;
|
1263 | 19f329ad | blueswir1 | case 0xf: |
1264 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1265 | 19f329ad | blueswir1 | break;
|
1266 | 19f329ad | blueswir1 | } |
1267 | 19f329ad | blueswir1 | } |
1268 | 7a3f1944 | bellard | |
1269 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1270 | e8af50a3 | bellard | { |
1271 | 19f329ad | blueswir1 | unsigned int offset; |
1272 | 19f329ad | blueswir1 | |
1273 | 19f329ad | blueswir1 | switch (cc) {
|
1274 | 19f329ad | blueswir1 | default:
|
1275 | 19f329ad | blueswir1 | case 0x0: |
1276 | 19f329ad | blueswir1 | offset = 0;
|
1277 | 19f329ad | blueswir1 | break;
|
1278 | 19f329ad | blueswir1 | case 0x1: |
1279 | 19f329ad | blueswir1 | offset = 32 - 10; |
1280 | 19f329ad | blueswir1 | break;
|
1281 | 19f329ad | blueswir1 | case 0x2: |
1282 | 19f329ad | blueswir1 | offset = 34 - 10; |
1283 | 19f329ad | blueswir1 | break;
|
1284 | 19f329ad | blueswir1 | case 0x3: |
1285 | 19f329ad | blueswir1 | offset = 36 - 10; |
1286 | 19f329ad | blueswir1 | break;
|
1287 | 19f329ad | blueswir1 | } |
1288 | 19f329ad | blueswir1 | |
1289 | 19f329ad | blueswir1 | switch (cond) {
|
1290 | 19f329ad | blueswir1 | case 0x0: |
1291 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1292 | 19f329ad | blueswir1 | break;
|
1293 | 19f329ad | blueswir1 | case 0x1: |
1294 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1295 | 19f329ad | blueswir1 | break;
|
1296 | 19f329ad | blueswir1 | case 0x2: |
1297 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1298 | 19f329ad | blueswir1 | break;
|
1299 | 19f329ad | blueswir1 | case 0x3: |
1300 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1301 | 19f329ad | blueswir1 | break;
|
1302 | 19f329ad | blueswir1 | case 0x4: |
1303 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1304 | 19f329ad | blueswir1 | break;
|
1305 | 19f329ad | blueswir1 | case 0x5: |
1306 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1307 | 19f329ad | blueswir1 | break;
|
1308 | 19f329ad | blueswir1 | case 0x6: |
1309 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1310 | 19f329ad | blueswir1 | break;
|
1311 | 19f329ad | blueswir1 | case 0x7: |
1312 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1313 | 19f329ad | blueswir1 | break;
|
1314 | 19f329ad | blueswir1 | case 0x8: |
1315 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1316 | 19f329ad | blueswir1 | break;
|
1317 | 19f329ad | blueswir1 | case 0x9: |
1318 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1319 | 19f329ad | blueswir1 | break;
|
1320 | 19f329ad | blueswir1 | case 0xa: |
1321 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1322 | 19f329ad | blueswir1 | break;
|
1323 | 19f329ad | blueswir1 | case 0xb: |
1324 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1325 | 19f329ad | blueswir1 | break;
|
1326 | 19f329ad | blueswir1 | case 0xc: |
1327 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1328 | 19f329ad | blueswir1 | break;
|
1329 | 19f329ad | blueswir1 | case 0xd: |
1330 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1331 | 19f329ad | blueswir1 | break;
|
1332 | 19f329ad | blueswir1 | case 0xe: |
1333 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1334 | 19f329ad | blueswir1 | break;
|
1335 | 19f329ad | blueswir1 | case 0xf: |
1336 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1337 | 19f329ad | blueswir1 | break;
|
1338 | 19f329ad | blueswir1 | } |
1339 | e8af50a3 | bellard | } |
1340 | 00f219bf | blueswir1 | |
1341 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1342 | 00f219bf | blueswir1 | // Inverted logic
|
1343 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1344 | 00f219bf | blueswir1 | -1,
|
1345 | 00f219bf | blueswir1 | TCG_COND_NE, |
1346 | 00f219bf | blueswir1 | TCG_COND_GT, |
1347 | 00f219bf | blueswir1 | TCG_COND_GE, |
1348 | 00f219bf | blueswir1 | -1,
|
1349 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1350 | 00f219bf | blueswir1 | TCG_COND_LE, |
1351 | 00f219bf | blueswir1 | TCG_COND_LT, |
1352 | 00f219bf | blueswir1 | }; |
1353 | 19f329ad | blueswir1 | |
1354 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1355 | 19f329ad | blueswir1 | { |
1356 | 19f329ad | blueswir1 | int l1;
|
1357 | 19f329ad | blueswir1 | |
1358 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1359 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1360 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1361 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1362 | 19f329ad | blueswir1 | gen_set_label(l1); |
1363 | 19f329ad | blueswir1 | } |
1364 | 3475187d | bellard | #endif
|
1365 | cf495bcf | bellard | |
1366 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1367 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1368 | 4af984a7 | blueswir1 | TCGv r_cond) |
1369 | 7a3f1944 | bellard | { |
1370 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1371 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1372 | 5fafdf24 | ths | |
1373 | cf495bcf | bellard | if (cond == 0x0) { |
1374 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1375 | 0f8a249a | blueswir1 | if (a) {
|
1376 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1377 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1378 | 0f8a249a | blueswir1 | } else {
|
1379 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1380 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1381 | 0f8a249a | blueswir1 | } |
1382 | cf495bcf | bellard | } else if (cond == 0x8) { |
1383 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1384 | 0f8a249a | blueswir1 | if (a) {
|
1385 | 0f8a249a | blueswir1 | dc->pc = target; |
1386 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1387 | 0f8a249a | blueswir1 | } else {
|
1388 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1389 | 0f8a249a | blueswir1 | dc->npc = target; |
1390 | 0f8a249a | blueswir1 | } |
1391 | cf495bcf | bellard | } else {
|
1392 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1393 | 4af984a7 | blueswir1 | gen_cond(r_cond, cc, cond); |
1394 | 0f8a249a | blueswir1 | if (a) {
|
1395 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1396 | cf495bcf | bellard | dc->is_br = 1;
|
1397 | 0f8a249a | blueswir1 | } else {
|
1398 | cf495bcf | bellard | dc->pc = dc->npc; |
1399 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1400 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1401 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1402 | 0f8a249a | blueswir1 | } |
1403 | cf495bcf | bellard | } |
1404 | 7a3f1944 | bellard | } |
1405 | 7a3f1944 | bellard | |
1406 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1407 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1408 | 4af984a7 | blueswir1 | TCGv r_cond) |
1409 | e8af50a3 | bellard | { |
1410 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1411 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1412 | af7bf89b | bellard | |
1413 | e8af50a3 | bellard | if (cond == 0x0) { |
1414 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1415 | 0f8a249a | blueswir1 | if (a) {
|
1416 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1417 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1418 | 0f8a249a | blueswir1 | } else {
|
1419 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1420 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1421 | 0f8a249a | blueswir1 | } |
1422 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1423 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1424 | 0f8a249a | blueswir1 | if (a) {
|
1425 | 0f8a249a | blueswir1 | dc->pc = target; |
1426 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1427 | 0f8a249a | blueswir1 | } else {
|
1428 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1429 | 0f8a249a | blueswir1 | dc->npc = target; |
1430 | 0f8a249a | blueswir1 | } |
1431 | e8af50a3 | bellard | } else {
|
1432 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1433 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1434 | 0f8a249a | blueswir1 | if (a) {
|
1435 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1436 | e8af50a3 | bellard | dc->is_br = 1;
|
1437 | 0f8a249a | blueswir1 | } else {
|
1438 | e8af50a3 | bellard | dc->pc = dc->npc; |
1439 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1440 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1441 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1442 | 0f8a249a | blueswir1 | } |
1443 | e8af50a3 | bellard | } |
1444 | e8af50a3 | bellard | } |
1445 | e8af50a3 | bellard | |
1446 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1447 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1448 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1449 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1450 | 7a3f1944 | bellard | { |
1451 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1452 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1453 | 3475187d | bellard | |
1454 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1455 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1456 | 3475187d | bellard | if (a) {
|
1457 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1458 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1459 | 3475187d | bellard | } else {
|
1460 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1461 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1462 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1463 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1464 | 3475187d | bellard | } |
1465 | 7a3f1944 | bellard | } |
1466 | 7a3f1944 | bellard | |
1467 | 3475187d | bellard | static GenOpFunc * const gen_fcmpd[4] = { |
1468 | 7e8c2b6c | blueswir1 | helper_fcmpd, |
1469 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc1, |
1470 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc2, |
1471 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc3, |
1472 | 3475187d | bellard | }; |
1473 | 417454b0 | blueswir1 | |
1474 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpq[4] = { |
1475 | 7e8c2b6c | blueswir1 | helper_fcmpq, |
1476 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc1, |
1477 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc2, |
1478 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc3, |
1479 | 1f587329 | blueswir1 | }; |
1480 | 1f587329 | blueswir1 | |
1481 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmped[4] = { |
1482 | 7e8c2b6c | blueswir1 | helper_fcmped, |
1483 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc1, |
1484 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc2, |
1485 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc3, |
1486 | 417454b0 | blueswir1 | }; |
1487 | 417454b0 | blueswir1 | |
1488 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpeq[4] = { |
1489 | 7e8c2b6c | blueswir1 | helper_fcmpeq, |
1490 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc1, |
1491 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc2, |
1492 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc3, |
1493 | 1f587329 | blueswir1 | }; |
1494 | 7e8c2b6c | blueswir1 | |
1495 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1496 | 7e8c2b6c | blueswir1 | { |
1497 | 714547bb | blueswir1 | switch (fccno) {
|
1498 | 714547bb | blueswir1 | case 0: |
1499 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2); |
1500 | 714547bb | blueswir1 | break;
|
1501 | 714547bb | blueswir1 | case 1: |
1502 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmps_fcc1, r_rs1, r_rs2); |
1503 | 714547bb | blueswir1 | break;
|
1504 | 714547bb | blueswir1 | case 2: |
1505 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmps_fcc2, r_rs1, r_rs2); |
1506 | 714547bb | blueswir1 | break;
|
1507 | 714547bb | blueswir1 | case 3: |
1508 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmps_fcc3, r_rs1, r_rs2); |
1509 | 714547bb | blueswir1 | break;
|
1510 | 714547bb | blueswir1 | } |
1511 | 7e8c2b6c | blueswir1 | } |
1512 | 7e8c2b6c | blueswir1 | |
1513 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1514 | 7e8c2b6c | blueswir1 | { |
1515 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); |
1516 | 7e8c2b6c | blueswir1 | } |
1517 | 7e8c2b6c | blueswir1 | |
1518 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1519 | 7e8c2b6c | blueswir1 | { |
1520 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); |
1521 | 7e8c2b6c | blueswir1 | } |
1522 | 7e8c2b6c | blueswir1 | |
1523 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1524 | 7e8c2b6c | blueswir1 | { |
1525 | 714547bb | blueswir1 | switch (fccno) {
|
1526 | 714547bb | blueswir1 | case 0: |
1527 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2); |
1528 | 714547bb | blueswir1 | break;
|
1529 | 714547bb | blueswir1 | case 1: |
1530 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmpes_fcc1, r_rs1, r_rs2); |
1531 | 714547bb | blueswir1 | break;
|
1532 | 714547bb | blueswir1 | case 2: |
1533 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmpes_fcc2, r_rs1, r_rs2); |
1534 | 714547bb | blueswir1 | break;
|
1535 | 714547bb | blueswir1 | case 3: |
1536 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmpes_fcc3, r_rs1, r_rs2); |
1537 | 714547bb | blueswir1 | break;
|
1538 | 714547bb | blueswir1 | } |
1539 | 7e8c2b6c | blueswir1 | } |
1540 | 7e8c2b6c | blueswir1 | |
1541 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1542 | 7e8c2b6c | blueswir1 | { |
1543 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmped[fccno]); |
1544 | 7e8c2b6c | blueswir1 | } |
1545 | 7e8c2b6c | blueswir1 | |
1546 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1547 | 7e8c2b6c | blueswir1 | { |
1548 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); |
1549 | 7e8c2b6c | blueswir1 | } |
1550 | 7e8c2b6c | blueswir1 | |
1551 | 7e8c2b6c | blueswir1 | #else
|
1552 | 7e8c2b6c | blueswir1 | |
1553 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1554 | 7e8c2b6c | blueswir1 | { |
1555 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2); |
1556 | 7e8c2b6c | blueswir1 | } |
1557 | 7e8c2b6c | blueswir1 | |
1558 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1559 | 7e8c2b6c | blueswir1 | { |
1560 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpd); |
1561 | 7e8c2b6c | blueswir1 | } |
1562 | 7e8c2b6c | blueswir1 | |
1563 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1564 | 7e8c2b6c | blueswir1 | { |
1565 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpq); |
1566 | 7e8c2b6c | blueswir1 | } |
1567 | 7e8c2b6c | blueswir1 | |
1568 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1569 | 7e8c2b6c | blueswir1 | { |
1570 | 714547bb | blueswir1 | tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2); |
1571 | 7e8c2b6c | blueswir1 | } |
1572 | 7e8c2b6c | blueswir1 | |
1573 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1574 | 7e8c2b6c | blueswir1 | { |
1575 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmped); |
1576 | 7e8c2b6c | blueswir1 | } |
1577 | 7e8c2b6c | blueswir1 | |
1578 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1579 | 7e8c2b6c | blueswir1 | { |
1580 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq); |
1581 | 7e8c2b6c | blueswir1 | } |
1582 | 7e8c2b6c | blueswir1 | #endif
|
1583 | 7e8c2b6c | blueswir1 | |
1584 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1585 | 134d77a1 | blueswir1 | { |
1586 | 2ea815ca | blueswir1 | TCGv r_const; |
1587 | 2ea815ca | blueswir1 | |
1588 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1589 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1590 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1591 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
1592 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1593 | 134d77a1 | blueswir1 | } |
1594 | 134d77a1 | blueswir1 | |
1595 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1596 | a80dde08 | bellard | { |
1597 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1598 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1599 | 2ea815ca | blueswir1 | TCGv r_const; |
1600 | 2ea815ca | blueswir1 | |
1601 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1602 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1603 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
1604 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1605 | a80dde08 | bellard | dc->is_br = 1;
|
1606 | a80dde08 | bellard | return 1; |
1607 | a80dde08 | bellard | } |
1608 | a80dde08 | bellard | #endif
|
1609 | a80dde08 | bellard | return 0; |
1610 | a80dde08 | bellard | } |
1611 | a80dde08 | bellard | |
1612 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1613 | 7e8c2b6c | blueswir1 | { |
1614 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1615 | 7e8c2b6c | blueswir1 | } |
1616 | 7e8c2b6c | blueswir1 | |
1617 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1618 | 7e8c2b6c | blueswir1 | { |
1619 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_clear_float_exceptions); |
1620 | 7e8c2b6c | blueswir1 | } |
1621 | 7e8c2b6c | blueswir1 | |
1622 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1623 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1624 | 0425bee5 | blueswir1 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1625 | 1a2fb1c0 | blueswir1 | { |
1626 | 95f9397c | blueswir1 | int asi;
|
1627 | 0425bee5 | blueswir1 | TCGv r_asi; |
1628 | 1a2fb1c0 | blueswir1 | |
1629 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1630 | 0425bee5 | blueswir1 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1631 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1632 | 1a2fb1c0 | blueswir1 | } else {
|
1633 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1634 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1635 | 1a2fb1c0 | blueswir1 | } |
1636 | 0425bee5 | blueswir1 | return r_asi;
|
1637 | 0425bee5 | blueswir1 | } |
1638 | 0425bee5 | blueswir1 | |
1639 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1640 | 77f193da | blueswir1 | int sign)
|
1641 | 0425bee5 | blueswir1 | { |
1642 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1643 | 0425bee5 | blueswir1 | |
1644 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1645 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1646 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1647 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); |
1648 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1649 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1650 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1651 | 1a2fb1c0 | blueswir1 | } |
1652 | 1a2fb1c0 | blueswir1 | |
1653 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1654 | 1a2fb1c0 | blueswir1 | { |
1655 | 2ea815ca | blueswir1 | TCGv r_asi, r_size; |
1656 | 1a2fb1c0 | blueswir1 | |
1657 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1658 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1659 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); |
1660 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1661 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1662 | 1a2fb1c0 | blueswir1 | } |
1663 | 1a2fb1c0 | blueswir1 | |
1664 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1665 | 1a2fb1c0 | blueswir1 | { |
1666 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_rd; |
1667 | 1a2fb1c0 | blueswir1 | |
1668 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1669 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1670 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1671 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); |
1672 | 2ea815ca | blueswir1 | tcg_temp_free(r_rd); |
1673 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1674 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1675 | 1a2fb1c0 | blueswir1 | } |
1676 | 1a2fb1c0 | blueswir1 | |
1677 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1678 | 1a2fb1c0 | blueswir1 | { |
1679 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_rd; |
1680 | 1a2fb1c0 | blueswir1 | |
1681 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1682 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1683 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1684 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); |
1685 | 2ea815ca | blueswir1 | tcg_temp_free(r_rd); |
1686 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1687 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1688 | 1a2fb1c0 | blueswir1 | } |
1689 | 1a2fb1c0 | blueswir1 | |
1690 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1691 | 1a2fb1c0 | blueswir1 | { |
1692 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1693 | 1a2fb1c0 | blueswir1 | |
1694 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1695 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1696 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1697 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1698 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1699 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
1700 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1701 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1702 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1703 | 1a2fb1c0 | blueswir1 | } |
1704 | 1a2fb1c0 | blueswir1 | |
1705 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1706 | 1a2fb1c0 | blueswir1 | { |
1707 | db166940 | blueswir1 | TCGv r_asi, r_rd; |
1708 | 1a2fb1c0 | blueswir1 | |
1709 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1710 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1711 | db166940 | blueswir1 | tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd); |
1712 | db166940 | blueswir1 | tcg_temp_free(r_rd); |
1713 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1714 | 0425bee5 | blueswir1 | } |
1715 | 0425bee5 | blueswir1 | |
1716 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1717 | 0425bee5 | blueswir1 | { |
1718 | a7ec4229 | blueswir1 | TCGv r_low, r_asi, r_size; |
1719 | a7ec4229 | blueswir1 | |
1720 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1721 | a7ec4229 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_I32); |
1722 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(r_low, cpu_tmp0); |
1723 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, hi); |
1724 | a7ec4229 | blueswir1 | tcg_gen_concat_i32_i64(cpu_tmp64, r_low, cpu_tmp32); |
1725 | a7ec4229 | blueswir1 | tcg_temp_free(r_low); |
1726 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1727 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1728 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1729 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1730 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1731 | 1a2fb1c0 | blueswir1 | } |
1732 | 1a2fb1c0 | blueswir1 | |
1733 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1734 | 77f193da | blueswir1 | int rd)
|
1735 | 1a2fb1c0 | blueswir1 | { |
1736 | 1a2fb1c0 | blueswir1 | TCGv r_val1, r_asi; |
1737 | 1a2fb1c0 | blueswir1 | |
1738 | ef28fd86 | blueswir1 | r_val1 = tcg_temp_new(TCG_TYPE_TL); |
1739 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1740 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1741 | 4af984a7 | blueswir1 | tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); |
1742 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1743 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1744 | 1a2fb1c0 | blueswir1 | } |
1745 | 1a2fb1c0 | blueswir1 | |
1746 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1747 | 77f193da | blueswir1 | int rd)
|
1748 | 1a2fb1c0 | blueswir1 | { |
1749 | 8911f501 | blueswir1 | TCGv r_asi; |
1750 | 1a2fb1c0 | blueswir1 | |
1751 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1752 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1753 | 4af984a7 | blueswir1 | tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); |
1754 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1755 | 1a2fb1c0 | blueswir1 | } |
1756 | 1a2fb1c0 | blueswir1 | |
1757 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1758 | 1a2fb1c0 | blueswir1 | |
1759 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1760 | 77f193da | blueswir1 | int sign)
|
1761 | 1a2fb1c0 | blueswir1 | { |
1762 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1763 | 1a2fb1c0 | blueswir1 | |
1764 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1765 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1766 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1767 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1768 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1769 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1770 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1771 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1772 | 1a2fb1c0 | blueswir1 | } |
1773 | 1a2fb1c0 | blueswir1 | |
1774 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1775 | 1a2fb1c0 | blueswir1 | { |
1776 | 2ea815ca | blueswir1 | TCGv r_asi, r_size; |
1777 | 1a2fb1c0 | blueswir1 | |
1778 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1779 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1780 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1781 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1782 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1783 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1784 | 1a2fb1c0 | blueswir1 | } |
1785 | 1a2fb1c0 | blueswir1 | |
1786 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1787 | 1a2fb1c0 | blueswir1 | { |
1788 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1789 | 1a2fb1c0 | blueswir1 | |
1790 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1791 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1792 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1793 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1794 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1795 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
1796 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1797 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1798 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1799 | 1a2fb1c0 | blueswir1 | } |
1800 | 1a2fb1c0 | blueswir1 | |
1801 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1802 | 1a2fb1c0 | blueswir1 | { |
1803 | 2ea815ca | blueswir1 | TCGv r_asi, r_size, r_sign; |
1804 | 1a2fb1c0 | blueswir1 | |
1805 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1806 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1807 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1808 | 2ea815ca | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
1809 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1810 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1811 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1812 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1813 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1814 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1815 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1816 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1817 | 0425bee5 | blueswir1 | } |
1818 | 0425bee5 | blueswir1 | |
1819 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1820 | 0425bee5 | blueswir1 | { |
1821 | a7ec4229 | blueswir1 | TCGv r_low, r_asi, r_size; |
1822 | a7ec4229 | blueswir1 | |
1823 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1824 | a7ec4229 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_I32); |
1825 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(r_low, cpu_tmp0); |
1826 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, hi); |
1827 | a7ec4229 | blueswir1 | tcg_gen_concat_i32_i64(cpu_tmp64, r_low, cpu_tmp32); |
1828 | a7ec4229 | blueswir1 | tcg_temp_free(r_low); |
1829 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1830 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1831 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
1832 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1833 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1834 | 1a2fb1c0 | blueswir1 | } |
1835 | 1a2fb1c0 | blueswir1 | #endif
|
1836 | 1a2fb1c0 | blueswir1 | |
1837 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1838 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1839 | 1a2fb1c0 | blueswir1 | { |
1840 | 2ea815ca | blueswir1 | TCGv r_val, r_asi, r_size; |
1841 | 1a2fb1c0 | blueswir1 | |
1842 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1843 | 1a2fb1c0 | blueswir1 | |
1844 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1845 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1846 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1847 | 2ea815ca | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); |
1848 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1849 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1850 | 2ea815ca | blueswir1 | tcg_temp_free(r_val); |
1851 | 1a2fb1c0 | blueswir1 | } |
1852 | 1a2fb1c0 | blueswir1 | #endif
|
1853 | 1a2fb1c0 | blueswir1 | |
1854 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1855 | 9322a4bf | blueswir1 | { |
1856 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1857 | 9322a4bf | blueswir1 | unsigned int rs1; |
1858 | 9322a4bf | blueswir1 | |
1859 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1860 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1861 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1862 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1863 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1864 | 9322a4bf | blueswir1 | else
|
1865 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1866 | 9322a4bf | blueswir1 | return r_rs1;
|
1867 | 9322a4bf | blueswir1 | } |
1868 | 9322a4bf | blueswir1 | |
1869 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1870 | a49d9390 | blueswir1 | { |
1871 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1872 | a49d9390 | blueswir1 | unsigned int rs2; |
1873 | a49d9390 | blueswir1 | |
1874 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1875 | a49d9390 | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
1876 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl((int)rs2); // XXX how to free? |
1877 | a49d9390 | blueswir1 | } else { /* register */ |
1878 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1879 | a49d9390 | blueswir1 | if (rs2 == 0) |
1880 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1881 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1882 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1883 | a49d9390 | blueswir1 | else
|
1884 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1885 | a49d9390 | blueswir1 | } |
1886 | a49d9390 | blueswir1 | return r_rs2;
|
1887 | a49d9390 | blueswir1 | } |
1888 | a49d9390 | blueswir1 | |
1889 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1890 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1891 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1892 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1893 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1894 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1895 | 64a88d5d | blueswir1 | |
1896 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1897 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1898 | cf495bcf | bellard | { |
1899 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1900 | 7a3f1944 | bellard | |
1901 | a8c768c0 | blueswir1 | if (unlikely(loglevel & CPU_LOG_TB_OP))
|
1902 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1903 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1904 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1905 | 7a3f1944 | bellard | |
1906 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1907 | 6ae20372 | blueswir1 | |
1908 | 5c6a0628 | blueswir1 | cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
|
1909 | 5c6a0628 | blueswir1 | cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
|
1910 | 6ae20372 | blueswir1 | |
1911 | cf495bcf | bellard | switch (opc) {
|
1912 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1913 | 0f8a249a | blueswir1 | { |
1914 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1915 | 0f8a249a | blueswir1 | int32_t target; |
1916 | 0f8a249a | blueswir1 | switch (xop) {
|
1917 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1918 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1919 | 0f8a249a | blueswir1 | { |
1920 | 0f8a249a | blueswir1 | int cc;
|
1921 | 0f8a249a | blueswir1 | |
1922 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1923 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1924 | 0f8a249a | blueswir1 | target <<= 2;
|
1925 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1926 | 0f8a249a | blueswir1 | if (cc == 0) |
1927 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1928 | 0f8a249a | blueswir1 | else if (cc == 2) |
1929 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1930 | 0f8a249a | blueswir1 | else
|
1931 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1932 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1933 | 0f8a249a | blueswir1 | } |
1934 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1935 | 0f8a249a | blueswir1 | { |
1936 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1937 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1938 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1939 | 0f8a249a | blueswir1 | target <<= 2;
|
1940 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1941 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1942 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1943 | 0f8a249a | blueswir1 | } |
1944 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1945 | 0f8a249a | blueswir1 | { |
1946 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1947 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1948 | a80dde08 | bellard | goto jmp_insn;
|
1949 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1950 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1951 | 0f8a249a | blueswir1 | target <<= 2;
|
1952 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1953 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1954 | 0f8a249a | blueswir1 | } |
1955 | a4d17f19 | blueswir1 | #else
|
1956 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1957 | 0f8a249a | blueswir1 | { |
1958 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1959 | 0f8a249a | blueswir1 | } |
1960 | 0f8a249a | blueswir1 | #endif
|
1961 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1962 | 0f8a249a | blueswir1 | { |
1963 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1964 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1965 | 0f8a249a | blueswir1 | target <<= 2;
|
1966 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1967 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1968 | 0f8a249a | blueswir1 | } |
1969 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1970 | 0f8a249a | blueswir1 | { |
1971 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1972 | a80dde08 | bellard | goto jmp_insn;
|
1973 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1974 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1975 | 0f8a249a | blueswir1 | target <<= 2;
|
1976 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1977 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1978 | 0f8a249a | blueswir1 | } |
1979 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1980 | 0f8a249a | blueswir1 | if (rd) { // nop |
1981 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1982 | 2ea815ca | blueswir1 | TCGv r_const; |
1983 | 2ea815ca | blueswir1 | |
1984 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
1985 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1986 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1987 | 0f8a249a | blueswir1 | } |
1988 | 0f8a249a | blueswir1 | break;
|
1989 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1990 | 0f8a249a | blueswir1 | default:
|
1991 | 3475187d | bellard | goto illegal_insn;
|
1992 | 0f8a249a | blueswir1 | } |
1993 | 0f8a249a | blueswir1 | break;
|
1994 | 0f8a249a | blueswir1 | } |
1995 | 0f8a249a | blueswir1 | break;
|
1996 | cf495bcf | bellard | case 1: |
1997 | 0f8a249a | blueswir1 | /*CALL*/ {
|
1998 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1999 | 2ea815ca | blueswir1 | TCGv r_const; |
2000 | cf495bcf | bellard | |
2001 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2002 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
2003 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2004 | 0f8a249a | blueswir1 | target += dc->pc; |
2005 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
2006 | 0f8a249a | blueswir1 | dc->npc = target; |
2007 | 0f8a249a | blueswir1 | } |
2008 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2009 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2010 | 0f8a249a | blueswir1 | { |
2011 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2012 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2013 | cf495bcf | bellard | int cond;
|
2014 | 3475187d | bellard | |
2015 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2016 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
2017 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
2018 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
2019 | cf495bcf | bellard | } else {
|
2020 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2021 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2022 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2023 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2024 | 6f551262 | blueswir1 | } else
|
2025 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
2026 | cf495bcf | bellard | } |
2027 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
2028 | cf495bcf | bellard | if (cond == 0x8) { |
2029 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2030 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_trap, cpu_dst); |
2031 | af7bf89b | bellard | } else if (cond != 0) { |
2032 | 748b9d8e | blueswir1 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
2033 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2034 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2035 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2036 | 748b9d8e | blueswir1 | |
2037 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2038 | 0f8a249a | blueswir1 | if (cc == 0) |
2039 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2040 | 0f8a249a | blueswir1 | else if (cc == 2) |
2041 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
2042 | 0f8a249a | blueswir1 | else
|
2043 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2044 | 3475187d | bellard | #else
|
2045 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2046 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2047 | 3475187d | bellard | #endif
|
2048 | 6ae20372 | blueswir1 | tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
2049 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
2050 | cf495bcf | bellard | } |
2051 | a80dde08 | bellard | gen_op_next_insn(); |
2052 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2053 | a80dde08 | bellard | dc->is_br = 1;
|
2054 | a80dde08 | bellard | goto jmp_insn;
|
2055 | cf495bcf | bellard | } else if (xop == 0x28) { |
2056 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2057 | cf495bcf | bellard | switch(rs1) {
|
2058 | cf495bcf | bellard | case 0: /* rdy */ |
2059 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2060 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2061 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2062 | 65fe7b09 | blueswir1 | II */
|
2063 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2064 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2065 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2066 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2067 | 65fe7b09 | blueswir1 | microSPARC II */
|
2068 | 65fe7b09 | blueswir1 | #endif
|
2069 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
2070 | cf495bcf | bellard | break;
|
2071 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2072 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2073 | 6ae20372 | blueswir1 | tcg_gen_helper_1_0(helper_rdccr, cpu_dst); |
2074 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2075 | 3475187d | bellard | break;
|
2076 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2077 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
2078 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2079 | 3475187d | bellard | break;
|
2080 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2081 | ccd4a219 | blueswir1 | { |
2082 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2083 | ccd4a219 | blueswir1 | |
2084 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2085 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2086 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2087 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
2088 | ccd4a219 | blueswir1 | r_tickptr); |
2089 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2090 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2091 | ccd4a219 | blueswir1 | } |
2092 | 3475187d | bellard | break;
|
2093 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2094 | 2ea815ca | blueswir1 | { |
2095 | 2ea815ca | blueswir1 | TCGv r_const; |
2096 | 2ea815ca | blueswir1 | |
2097 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2098 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2099 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2100 | 2ea815ca | blueswir1 | } |
2101 | 0f8a249a | blueswir1 | break;
|
2102 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2103 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
2104 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2105 | 3475187d | bellard | break;
|
2106 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2107 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2108 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2109 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2110 | 725cb90b | bellard | goto jmp_insn;
|
2111 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
2112 | 725cb90b | bellard | break;
|
2113 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2114 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
2115 | 83469015 | bellard | break;
|
2116 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2117 | ccd4a219 | blueswir1 | { |
2118 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2119 | ccd4a219 | blueswir1 | |
2120 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2121 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2122 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2123 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
2124 | ccd4a219 | blueswir1 | r_tickptr); |
2125 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2126 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2127 | ccd4a219 | blueswir1 | } |
2128 | 83469015 | bellard | break;
|
2129 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2130 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
2131 | 83469015 | bellard | break;
|
2132 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2133 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2134 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2135 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2136 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2137 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
2138 | 3475187d | bellard | #endif
|
2139 | 3475187d | bellard | default:
|
2140 | cf495bcf | bellard | goto illegal_insn;
|
2141 | cf495bcf | bellard | } |
2142 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2143 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2144 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2145 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2146 | 0f8a249a | blueswir1 | goto priv_insn;
|
2147 | 6ae20372 | blueswir1 | tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); |
2148 | e9ebed4d | blueswir1 | #else
|
2149 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2150 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2151 | e9ebed4d | blueswir1 | goto priv_insn;
|
2152 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2153 | e9ebed4d | blueswir1 | switch (rs1) {
|
2154 | e9ebed4d | blueswir1 | case 0: // hpstate |
2155 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2156 | e9ebed4d | blueswir1 | break;
|
2157 | e9ebed4d | blueswir1 | case 1: // htstate |
2158 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2159 | e9ebed4d | blueswir1 | break;
|
2160 | e9ebed4d | blueswir1 | case 3: // hintp |
2161 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
2162 | e9ebed4d | blueswir1 | break;
|
2163 | e9ebed4d | blueswir1 | case 5: // htba |
2164 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
2165 | e9ebed4d | blueswir1 | break;
|
2166 | e9ebed4d | blueswir1 | case 6: // hver |
2167 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
2168 | e9ebed4d | blueswir1 | break;
|
2169 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2170 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
2171 | e9ebed4d | blueswir1 | break;
|
2172 | e9ebed4d | blueswir1 | default:
|
2173 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2174 | e9ebed4d | blueswir1 | } |
2175 | e9ebed4d | blueswir1 | #endif
|
2176 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2177 | e8af50a3 | bellard | break;
|
2178 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2179 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2180 | 0f8a249a | blueswir1 | goto priv_insn;
|
2181 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2182 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2183 | 0f8a249a | blueswir1 | switch (rs1) {
|
2184 | 0f8a249a | blueswir1 | case 0: // tpc |
2185 | 375ee38b | blueswir1 | { |
2186 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2187 | 375ee38b | blueswir1 | |
2188 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2189 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2190 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2191 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2192 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2193 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2194 | 375ee38b | blueswir1 | } |
2195 | 0f8a249a | blueswir1 | break;
|
2196 | 0f8a249a | blueswir1 | case 1: // tnpc |
2197 | 375ee38b | blueswir1 | { |
2198 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2199 | 375ee38b | blueswir1 | |
2200 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2201 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2202 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2203 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2204 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2205 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2206 | 375ee38b | blueswir1 | } |
2207 | 0f8a249a | blueswir1 | break;
|
2208 | 0f8a249a | blueswir1 | case 2: // tstate |
2209 | 375ee38b | blueswir1 | { |
2210 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2211 | 375ee38b | blueswir1 | |
2212 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2213 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2214 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2215 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2216 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2217 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2218 | 375ee38b | blueswir1 | } |
2219 | 0f8a249a | blueswir1 | break;
|
2220 | 0f8a249a | blueswir1 | case 3: // tt |
2221 | 375ee38b | blueswir1 | { |
2222 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2223 | 375ee38b | blueswir1 | |
2224 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2225 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2226 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2227 | ece43b8d | blueswir1 | tcg_gen_ld_i32(cpu_tmp0, r_tsptr, |
2228 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2229 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
2230 | 375ee38b | blueswir1 | } |
2231 | 0f8a249a | blueswir1 | break;
|
2232 | 0f8a249a | blueswir1 | case 4: // tick |
2233 | ccd4a219 | blueswir1 | { |
2234 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2235 | ccd4a219 | blueswir1 | |
2236 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2237 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2238 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2239 | ece43b8d | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, |
2240 | ccd4a219 | blueswir1 | r_tickptr); |
2241 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2242 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
2243 | ccd4a219 | blueswir1 | } |
2244 | 0f8a249a | blueswir1 | break;
|
2245 | 0f8a249a | blueswir1 | case 5: // tba |
2246 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2247 | 0f8a249a | blueswir1 | break;
|
2248 | 0f8a249a | blueswir1 | case 6: // pstate |
2249 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2250 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2251 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2252 | 0f8a249a | blueswir1 | break;
|
2253 | 0f8a249a | blueswir1 | case 7: // tl |
2254 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2255 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2256 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2257 | 0f8a249a | blueswir1 | break;
|
2258 | 0f8a249a | blueswir1 | case 8: // pil |
2259 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2260 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2261 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2262 | 0f8a249a | blueswir1 | break;
|
2263 | 0f8a249a | blueswir1 | case 9: // cwp |
2264 | ece43b8d | blueswir1 | tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0); |
2265 | 0f8a249a | blueswir1 | break;
|
2266 | 0f8a249a | blueswir1 | case 10: // cansave |
2267 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2268 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2269 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2270 | 0f8a249a | blueswir1 | break;
|
2271 | 0f8a249a | blueswir1 | case 11: // canrestore |
2272 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2273 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2274 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2275 | 0f8a249a | blueswir1 | break;
|
2276 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2277 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2278 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2279 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2280 | 0f8a249a | blueswir1 | break;
|
2281 | 0f8a249a | blueswir1 | case 13: // otherwin |
2282 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2283 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2284 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2285 | 0f8a249a | blueswir1 | break;
|
2286 | 0f8a249a | blueswir1 | case 14: // wstate |
2287 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2288 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2289 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2290 | 0f8a249a | blueswir1 | break;
|
2291 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2292 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2293 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2294 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2295 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2296 | e9ebed4d | blueswir1 | break;
|
2297 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2298 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2299 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2300 | e9ebed4d | blueswir1 | goto priv_insn;
|
2301 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr); |
2302 | e9ebed4d | blueswir1 | break;
|
2303 | 0f8a249a | blueswir1 | case 31: // ver |
2304 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2305 | 0f8a249a | blueswir1 | break;
|
2306 | 0f8a249a | blueswir1 | case 15: // fq |
2307 | 0f8a249a | blueswir1 | default:
|
2308 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2309 | 0f8a249a | blueswir1 | } |
2310 | 3475187d | bellard | #else
|
2311 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2312 | 3475187d | bellard | #endif
|
2313 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2314 | e8af50a3 | bellard | break;
|
2315 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2316 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2317 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2318 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_flushw); |
2319 | 3475187d | bellard | #else
|
2320 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2321 | 0f8a249a | blueswir1 | goto priv_insn;
|
2322 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2323 | 3475187d | bellard | #endif
|
2324 | e8af50a3 | bellard | break;
|
2325 | e8af50a3 | bellard | #endif
|
2326 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2327 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2328 | a80dde08 | bellard | goto jmp_insn;
|
2329 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2330 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2331 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2332 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2333 | 0f8a249a | blueswir1 | switch (xop) {
|
2334 | 0f8a249a | blueswir1 | case 0x1: /* fmovs */ |
2335 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2336 | 0f8a249a | blueswir1 | break;
|
2337 | 0f8a249a | blueswir1 | case 0x5: /* fnegs */ |
2338 | 714547bb | blueswir1 | tcg_gen_helper_1_1(helper_fnegs, cpu_fpr[rd], |
2339 | 714547bb | blueswir1 | cpu_fpr[rs2]); |
2340 | 0f8a249a | blueswir1 | break;
|
2341 | 0f8a249a | blueswir1 | case 0x9: /* fabss */ |
2342 | 714547bb | blueswir1 | tcg_gen_helper_1_1(helper_fabss, cpu_fpr[rd], |
2343 | 714547bb | blueswir1 | cpu_fpr[rs2]); |
2344 | 0f8a249a | blueswir1 | break;
|
2345 | 0f8a249a | blueswir1 | case 0x29: /* fsqrts */ |
2346 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FSQRT); |
2347 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2348 | 714547bb | blueswir1 | tcg_gen_helper_1_1(helper_fsqrts, cpu_tmp32, |
2349 | 714547bb | blueswir1 | cpu_fpr[rs2]); |
2350 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2351 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2352 | 0f8a249a | blueswir1 | break;
|
2353 | 0f8a249a | blueswir1 | case 0x2a: /* fsqrtd */ |
2354 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FSQRT); |
2355 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2356 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2357 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtd); |
2358 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2359 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2360 | 0f8a249a | blueswir1 | break;
|
2361 | 0f8a249a | blueswir1 | case 0x2b: /* fsqrtq */ |
2362 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2363 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2364 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2365 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtq); |
2366 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2367 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2368 | 1f587329 | blueswir1 | break;
|
2369 | 714547bb | blueswir1 | case 0x41: /* fadds */ |
2370 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2371 | 714547bb | blueswir1 | tcg_gen_helper_1_2(helper_fadds, cpu_tmp32, |
2372 | 714547bb | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
2373 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2374 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2375 | 0f8a249a | blueswir1 | break;
|
2376 | 0f8a249a | blueswir1 | case 0x42: |
2377 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2378 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2379 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2380 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddd); |
2381 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2382 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2383 | 0f8a249a | blueswir1 | break;
|
2384 | 0f8a249a | blueswir1 | case 0x43: /* faddq */ |
2385 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2386 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2387 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2388 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2389 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddq); |
2390 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2391 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2392 | 1f587329 | blueswir1 | break;
|
2393 | 714547bb | blueswir1 | case 0x45: /* fsubs */ |
2394 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2395 | 714547bb | blueswir1 | tcg_gen_helper_1_2(helper_fsubs, cpu_tmp32, |
2396 | 714547bb | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
2397 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2398 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2399 | 0f8a249a | blueswir1 | break;
|
2400 | 0f8a249a | blueswir1 | case 0x46: |
2401 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2402 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2403 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2404 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubd); |
2405 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2406 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2407 | 0f8a249a | blueswir1 | break;
|
2408 | 0f8a249a | blueswir1 | case 0x47: /* fsubq */ |
2409 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2410 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2411 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2412 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2413 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubq); |
2414 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2415 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2416 | 1f587329 | blueswir1 | break;
|
2417 | 64a88d5d | blueswir1 | case 0x49: /* fmuls */ |
2418 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2419 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2420 | 714547bb | blueswir1 | tcg_gen_helper_1_2(helper_fmuls, cpu_tmp32, |
2421 | 714547bb | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
2422 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2423 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2424 | 0f8a249a | blueswir1 | break;
|
2425 | 64a88d5d | blueswir1 | case 0x4a: /* fmuld */ |
2426 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2427 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2428 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2429 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2430 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld); |
2431 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2432 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2433 | 0f8a249a | blueswir1 | break;
|
2434 | 0f8a249a | blueswir1 | case 0x4b: /* fmulq */ |
2435 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2436 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FMUL); |
2437 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2438 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2439 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2440 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmulq); |
2441 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2442 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2443 | 1f587329 | blueswir1 | break;
|
2444 | 714547bb | blueswir1 | case 0x4d: /* fdivs */ |
2445 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2446 | 714547bb | blueswir1 | tcg_gen_helper_1_2(helper_fdivs, cpu_tmp32, |
2447 | 714547bb | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
2448 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2449 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2450 | 0f8a249a | blueswir1 | break;
|
2451 | 0f8a249a | blueswir1 | case 0x4e: |
2452 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2453 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2454 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2455 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivd); |
2456 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2457 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2458 | 0f8a249a | blueswir1 | break;
|
2459 | 0f8a249a | blueswir1 | case 0x4f: /* fdivq */ |
2460 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2461 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2462 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2463 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2464 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivq); |
2465 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2466 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2467 | 1f587329 | blueswir1 | break;
|
2468 | d84763bc | blueswir1 | case 0x69: /* fsmuld */ |
2469 | e30b4678 | blueswir1 | CHECK_FPU_FEATURE(dc, FSMULD); |
2470 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2471 | d84763bc | blueswir1 | tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1], |
2472 | d84763bc | blueswir1 | cpu_fpr[rs2]); |
2473 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2474 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2475 | 0f8a249a | blueswir1 | break;
|
2476 | 0f8a249a | blueswir1 | case 0x6e: /* fdmulq */ |
2477 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2478 | 1f587329 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2479 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2480 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2481 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdmulq); |
2482 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2483 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2484 | 1f587329 | blueswir1 | break;
|
2485 | 714547bb | blueswir1 | case 0xc4: /* fitos */ |
2486 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2487 | 714547bb | blueswir1 | tcg_gen_helper_1_1(helper_fitos, cpu_tmp32, |
2488 | 714547bb | blueswir1 | cpu_fpr[rs2]); |
2489 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2490 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2491 | 0f8a249a | blueswir1 | break;
|
2492 | d84763bc | blueswir1 | case 0xc6: /* fdtos */ |
2493 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2494 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2495 | d84763bc | blueswir1 | tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32); |
2496 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2497 | d84763bc | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2498 | 0f8a249a | blueswir1 | break;
|
2499 | 0f8a249a | blueswir1 | case 0xc7: /* fqtos */ |
2500 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2501 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2502 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2503 | c5d04e99 | blueswir1 | tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32); |
2504 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2505 | c5d04e99 | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2506 | 1f587329 | blueswir1 | break;
|
2507 | d84763bc | blueswir1 | case 0xc8: /* fitod */ |
2508 | d84763bc | blueswir1 | tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]); |
2509 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2510 | 0f8a249a | blueswir1 | break;
|
2511 | d84763bc | blueswir1 | case 0xc9: /* fstod */ |
2512 | d84763bc | blueswir1 | tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]); |
2513 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2514 | 0f8a249a | blueswir1 | break;
|
2515 | 0f8a249a | blueswir1 | case 0xcb: /* fqtod */ |
2516 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2517 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2518 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2519 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtod); |
2520 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2521 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2522 | 1f587329 | blueswir1 | break;
|
2523 | 0f8a249a | blueswir1 | case 0xcc: /* fitoq */ |
2524 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2525 | c5d04e99 | blueswir1 | tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]); |
2526 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2527 | 1f587329 | blueswir1 | break;
|
2528 | 0f8a249a | blueswir1 | case 0xcd: /* fstoq */ |
2529 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2530 | c5d04e99 | blueswir1 | tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]); |
2531 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2532 | 1f587329 | blueswir1 | break;
|
2533 | 0f8a249a | blueswir1 | case 0xce: /* fdtoq */ |
2534 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2535 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2536 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoq); |
2537 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2538 | 1f587329 | blueswir1 | break;
|
2539 | 714547bb | blueswir1 | case 0xd1: /* fstoi */ |
2540 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2541 | 714547bb | blueswir1 | tcg_gen_helper_1_1(helper_fstoi, cpu_tmp32, |
2542 | 714547bb | blueswir1 | cpu_fpr[rs2]); |
2543 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2544 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2545 | 0f8a249a | blueswir1 | break;
|
2546 | d84763bc | blueswir1 | case 0xd2: /* fdtoi */ |
2547 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2548 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2549 | d84763bc | blueswir1 | tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32); |
2550 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2551 | d84763bc | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2552 | 0f8a249a | blueswir1 | break;
|
2553 | 0f8a249a | blueswir1 | case 0xd3: /* fqtoi */ |
2554 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2555 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2556 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2557 | c5d04e99 | blueswir1 | tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32); |
2558 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2559 | c5d04e99 | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2560 | 1f587329 | blueswir1 | break;
|
2561 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2562 | 0f8a249a | blueswir1 | case 0x2: /* V9 fmovd */ |
2563 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], |
2564 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
2565 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2566 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
2567 | 0f8a249a | blueswir1 | break;
|
2568 | 1f587329 | blueswir1 | case 0x3: /* V9 fmovq */ |
2569 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2570 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], |
2571 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); |
2572 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2573 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]);
|
2574 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2575 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]);
|
2576 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2577 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]);
|
2578 | 1f587329 | blueswir1 | break;
|
2579 | 0f8a249a | blueswir1 | case 0x6: /* V9 fnegd */ |
2580 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2581 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegd); |
2582 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2583 | 0f8a249a | blueswir1 | break;
|
2584 | 1f587329 | blueswir1 | case 0x7: /* V9 fnegq */ |
2585 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2586 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2587 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegq); |
2588 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2589 | 1f587329 | blueswir1 | break;
|
2590 | 0f8a249a | blueswir1 | case 0xa: /* V9 fabsd */ |
2591 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2592 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsd); |
2593 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2594 | 0f8a249a | blueswir1 | break;
|
2595 | 1f587329 | blueswir1 | case 0xb: /* V9 fabsq */ |
2596 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2597 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2598 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsq); |
2599 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2600 | 1f587329 | blueswir1 | break;
|
2601 | 0f8a249a | blueswir1 | case 0x81: /* V9 fstox */ |
2602 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2603 | d84763bc | blueswir1 | tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]); |
2604 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2605 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2606 | 0f8a249a | blueswir1 | break;
|
2607 | 0f8a249a | blueswir1 | case 0x82: /* V9 fdtox */ |
2608 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2609 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2610 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtox); |
2611 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2612 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2613 | 0f8a249a | blueswir1 | break;
|
2614 | 1f587329 | blueswir1 | case 0x83: /* V9 fqtox */ |
2615 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2616 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2617 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2618 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtox); |
2619 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2620 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2621 | 1f587329 | blueswir1 | break;
|
2622 | 0f8a249a | blueswir1 | case 0x84: /* V9 fxtos */ |
2623 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2624 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2625 | d84763bc | blueswir1 | tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32); |
2626 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2627 | d84763bc | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2628 | 0f8a249a | blueswir1 | break;
|
2629 | 0f8a249a | blueswir1 | case 0x88: /* V9 fxtod */ |
2630 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2631 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2632 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtod); |
2633 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2634 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2635 | 0f8a249a | blueswir1 | break;
|
2636 | 0f8a249a | blueswir1 | case 0x8c: /* V9 fxtoq */ |
2637 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2638 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2639 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2640 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtoq); |
2641 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2642 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2643 | 1f587329 | blueswir1 | break;
|
2644 | 1f587329 | blueswir1 | #endif
|
2645 | 0f8a249a | blueswir1 | default:
|
2646 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2647 | 0f8a249a | blueswir1 | } |
2648 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2649 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2650 | 0f8a249a | blueswir1 | int cond;
|
2651 | 3475187d | bellard | #endif
|
2652 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2653 | a80dde08 | bellard | goto jmp_insn;
|
2654 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2655 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2656 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2657 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2658 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2659 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2660 | dcf24905 | blueswir1 | int l1;
|
2661 | dcf24905 | blueswir1 | |
2662 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2663 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2664 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2665 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2666 | cb63669a | pbrook | 0, l1);
|
2667 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2668 | dcf24905 | blueswir1 | gen_set_label(l1); |
2669 | 0f8a249a | blueswir1 | break;
|
2670 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2671 | dcf24905 | blueswir1 | int l1;
|
2672 | dcf24905 | blueswir1 | |
2673 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2674 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2675 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2676 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2677 | cb63669a | pbrook | 0, l1);
|
2678 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2679 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2680 | dcf24905 | blueswir1 | gen_set_label(l1); |
2681 | 0f8a249a | blueswir1 | break;
|
2682 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2683 | dcf24905 | blueswir1 | int l1;
|
2684 | dcf24905 | blueswir1 | |
2685 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2686 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2687 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2688 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2689 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2690 | cb63669a | pbrook | 0, l1);
|
2691 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2692 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2693 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2694 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2695 | dcf24905 | blueswir1 | gen_set_label(l1); |
2696 | 1f587329 | blueswir1 | break;
|
2697 | 0f8a249a | blueswir1 | } |
2698 | 0f8a249a | blueswir1 | #endif
|
2699 | 0f8a249a | blueswir1 | switch (xop) {
|
2700 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2701 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2702 | 19f329ad | blueswir1 | { \ |
2703 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2704 | 19f329ad | blueswir1 | int l1; \
|
2705 | 19f329ad | blueswir1 | \ |
2706 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2707 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2708 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2709 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2710 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2711 | cb63669a | pbrook | 0, l1); \
|
2712 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2713 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2714 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2715 | 714547bb | blueswir1 | } |
2716 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2717 | 714547bb | blueswir1 | { \ |
2718 | 714547bb | blueswir1 | TCGv r_cond; \ |
2719 | 714547bb | blueswir1 | int l1; \
|
2720 | 714547bb | blueswir1 | \ |
2721 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2722 | 714547bb | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2723 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2724 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2725 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2726 | 714547bb | blueswir1 | 0, l1); \
|
2727 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2728 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2729 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2730 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2731 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2732 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2733 | 714547bb | blueswir1 | } |
2734 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2735 | 714547bb | blueswir1 | { \ |
2736 | 714547bb | blueswir1 | TCGv r_cond; \ |
2737 | 714547bb | blueswir1 | int l1; \
|
2738 | 714547bb | blueswir1 | \ |
2739 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2740 | 714547bb | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2741 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2742 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2743 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2744 | 714547bb | blueswir1 | 0, l1); \
|
2745 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2746 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2747 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2748 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2749 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2750 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2751 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2752 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2753 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2754 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2755 | 19f329ad | blueswir1 | } |
2756 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2757 | 714547bb | blueswir1 | FMOVSCC(0);
|
2758 | 0f8a249a | blueswir1 | break;
|
2759 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2760 | 714547bb | blueswir1 | FMOVDCC(0);
|
2761 | 0f8a249a | blueswir1 | break;
|
2762 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2763 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2764 | 714547bb | blueswir1 | FMOVQCC(0);
|
2765 | 1f587329 | blueswir1 | break;
|
2766 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2767 | 714547bb | blueswir1 | FMOVSCC(1);
|
2768 | 0f8a249a | blueswir1 | break;
|
2769 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2770 | 714547bb | blueswir1 | FMOVDCC(1);
|
2771 | 0f8a249a | blueswir1 | break;
|
2772 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2773 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2774 | 714547bb | blueswir1 | FMOVQCC(1);
|
2775 | 1f587329 | blueswir1 | break;
|
2776 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2777 | 714547bb | blueswir1 | FMOVSCC(2);
|
2778 | 0f8a249a | blueswir1 | break;
|
2779 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2780 | 714547bb | blueswir1 | FMOVDCC(2);
|
2781 | 0f8a249a | blueswir1 | break;
|
2782 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2783 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2784 | 714547bb | blueswir1 | FMOVQCC(2);
|
2785 | 1f587329 | blueswir1 | break;
|
2786 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2787 | 714547bb | blueswir1 | FMOVSCC(3);
|
2788 | 0f8a249a | blueswir1 | break;
|
2789 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2790 | 714547bb | blueswir1 | FMOVDCC(3);
|
2791 | 0f8a249a | blueswir1 | break;
|
2792 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2793 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2794 | 714547bb | blueswir1 | FMOVQCC(3);
|
2795 | 1f587329 | blueswir1 | break;
|
2796 | 714547bb | blueswir1 | #undef FMOVSCC
|
2797 | 714547bb | blueswir1 | #undef FMOVDCC
|
2798 | 714547bb | blueswir1 | #undef FMOVQCC
|
2799 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, icc) \
|
2800 | 19f329ad | blueswir1 | { \ |
2801 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2802 | 19f329ad | blueswir1 | int l1; \
|
2803 | 19f329ad | blueswir1 | \ |
2804 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2805 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2806 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2807 | 19f329ad | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2808 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2809 | cb63669a | pbrook | 0, l1); \
|
2810 | 77f193da | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0) \ |
2811 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rs2))); \ |
2812 | 77f193da | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ |
2813 | 77f193da | blueswir1 | (glue(size_FDQ, FPREG(rd))); \ |
2814 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2815 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2816 | 19f329ad | blueswir1 | } |
2817 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2818 | 714547bb | blueswir1 | { \ |
2819 | 714547bb | blueswir1 | TCGv r_cond; \ |
2820 | 714547bb | blueswir1 | int l1; \
|
2821 | 714547bb | blueswir1 | \ |
2822 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2823 | 714547bb | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2824 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2825 | 714547bb | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2826 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2827 | 714547bb | blueswir1 | 0, l1); \
|
2828 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2829 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2830 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2831 | 714547bb | blueswir1 | } |
2832 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2833 | 714547bb | blueswir1 | { \ |
2834 | 714547bb | blueswir1 | TCGv r_cond; \ |
2835 | 714547bb | blueswir1 | int l1; \
|
2836 | 714547bb | blueswir1 | \ |
2837 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2838 | 714547bb | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2839 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2840 | 714547bb | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2841 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2842 | 714547bb | blueswir1 | 0, l1); \
|
2843 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2844 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2845 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2846 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2847 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2848 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2849 | 714547bb | blueswir1 | } |
2850 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2851 | 714547bb | blueswir1 | { \ |
2852 | 714547bb | blueswir1 | TCGv r_cond; \ |
2853 | 714547bb | blueswir1 | int l1; \
|
2854 | 714547bb | blueswir1 | \ |
2855 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2856 | 714547bb | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2857 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2858 | 714547bb | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2859 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2860 | 714547bb | blueswir1 | 0, l1); \
|
2861 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2862 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2863 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2864 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2865 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2866 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2867 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2868 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2869 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2870 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2871 | 714547bb | blueswir1 | } |
2872 | 19f329ad | blueswir1 | |
2873 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2874 | 714547bb | blueswir1 | FMOVSCC(0);
|
2875 | 0f8a249a | blueswir1 | break;
|
2876 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2877 | 714547bb | blueswir1 | FMOVDCC(0);
|
2878 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2879 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2880 | 714547bb | blueswir1 | FMOVQCC(0);
|
2881 | 1f587329 | blueswir1 | break;
|
2882 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2883 | 714547bb | blueswir1 | FMOVSCC(1);
|
2884 | 0f8a249a | blueswir1 | break;
|
2885 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2886 | 714547bb | blueswir1 | FMOVDCC(1);
|
2887 | 0f8a249a | blueswir1 | break;
|
2888 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2889 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2890 | 714547bb | blueswir1 | FMOVQCC(1);
|
2891 | 1f587329 | blueswir1 | break;
|
2892 | 714547bb | blueswir1 | #undef FMOVSCC
|
2893 | 714547bb | blueswir1 | #undef FMOVDCC
|
2894 | 714547bb | blueswir1 | #undef FMOVQCC
|
2895 | 1f587329 | blueswir1 | #endif
|
2896 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2897 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2898 | 0f8a249a | blueswir1 | break;
|
2899 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2900 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2901 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2902 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2903 | 0f8a249a | blueswir1 | break;
|
2904 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2905 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2906 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2907 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2908 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2909 | 1f587329 | blueswir1 | break;
|
2910 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2911 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2912 | 0f8a249a | blueswir1 | break;
|
2913 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2914 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2915 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2916 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2917 | 0f8a249a | blueswir1 | break;
|
2918 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2919 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2920 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2921 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2922 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2923 | 1f587329 | blueswir1 | break;
|
2924 | 0f8a249a | blueswir1 | default:
|
2925 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2926 | 0f8a249a | blueswir1 | } |
2927 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2928 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2929 | e80cfcfc | bellard | |
2930 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2931 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2932 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2933 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2934 | 2ea815ca | blueswir1 | TCGv r_const; |
2935 | 2ea815ca | blueswir1 | |
2936 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2937 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
2938 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2939 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2940 | 0f8a249a | blueswir1 | } else { /* register */ |
2941 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2942 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2943 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2944 | 0f8a249a | blueswir1 | } |
2945 | 0f8a249a | blueswir1 | } else {
|
2946 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2947 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2948 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2949 | 6ae20372 | blueswir1 | tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
|
2950 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2951 | 0f8a249a | blueswir1 | } else { /* register */ |
2952 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2953 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2954 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2955 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2956 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2957 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2958 | 6f551262 | blueswir1 | } else
|
2959 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2960 | 0f8a249a | blueswir1 | } |
2961 | 0f8a249a | blueswir1 | } |
2962 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2963 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2964 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2965 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2966 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2967 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2968 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
2969 | 1a2fb1c0 | blueswir1 | } else {
|
2970 | 01b1fa6d | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
|
2971 | 1a2fb1c0 | blueswir1 | } |
2972 | 0f8a249a | blueswir1 | } else { /* register */ |
2973 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2974 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2975 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2976 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2977 | 1a2fb1c0 | blueswir1 | } else {
|
2978 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2979 | 1a2fb1c0 | blueswir1 | } |
2980 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2981 | 83469015 | bellard | } |
2982 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2983 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2984 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2985 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2986 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2987 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2988 | 6ae20372 | blueswir1 | tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
2989 | 1a2fb1c0 | blueswir1 | } else {
|
2990 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2991 | 6ae20372 | blueswir1 | tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
|
2992 | 1a2fb1c0 | blueswir1 | } |
2993 | 0f8a249a | blueswir1 | } else { /* register */ |
2994 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2995 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2996 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2997 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2998 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2999 | 1a2fb1c0 | blueswir1 | } else {
|
3000 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3001 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3002 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3003 | 1a2fb1c0 | blueswir1 | } |
3004 | 83469015 | bellard | } |
3005 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3006 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
3007 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3008 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3009 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
3010 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3011 | 6ae20372 | blueswir1 | tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
|
3012 | 1a2fb1c0 | blueswir1 | } else {
|
3013 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3014 | 6ae20372 | blueswir1 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); |
3015 | 6ae20372 | blueswir1 | tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
|
3016 | 1a2fb1c0 | blueswir1 | } |
3017 | 0f8a249a | blueswir1 | } else { /* register */ |
3018 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3019 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3020 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3021 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3022 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3023 | 1a2fb1c0 | blueswir1 | } else {
|
3024 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3025 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3026 | 01b1fa6d | blueswir1 | tcg_gen_ext_i32_i64(cpu_dst, cpu_dst); |
3027 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3028 | 1a2fb1c0 | blueswir1 | } |
3029 | 83469015 | bellard | } |
3030 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3031 | 83469015 | bellard | #endif
|
3032 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
3033 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3034 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3035 | cf495bcf | bellard | if (xop < 0x20) { |
3036 | cf495bcf | bellard | switch (xop & ~0x10) { |
3037 | cf495bcf | bellard | case 0x0: |
3038 | cf495bcf | bellard | if (xop & 0x10) |
3039 | 6ae20372 | blueswir1 | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
3040 | cf495bcf | bellard | else
|
3041 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3042 | cf495bcf | bellard | break;
|
3043 | cf495bcf | bellard | case 0x1: |
3044 | 6ae20372 | blueswir1 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
3045 | cf495bcf | bellard | if (xop & 0x10) |
3046 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3047 | cf495bcf | bellard | break;
|
3048 | cf495bcf | bellard | case 0x2: |
3049 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3050 | 0f8a249a | blueswir1 | if (xop & 0x10) |
3051 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3052 | 0f8a249a | blueswir1 | break;
|
3053 | cf495bcf | bellard | case 0x3: |
3054 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3055 | cf495bcf | bellard | if (xop & 0x10) |
3056 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3057 | cf495bcf | bellard | break;
|
3058 | cf495bcf | bellard | case 0x4: |
3059 | cf495bcf | bellard | if (xop & 0x10) |
3060 | 6ae20372 | blueswir1 | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3061 | cf495bcf | bellard | else
|
3062 | 6ae20372 | blueswir1 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
3063 | cf495bcf | bellard | break;
|
3064 | cf495bcf | bellard | case 0x5: |
3065 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3066 | 6ae20372 | blueswir1 | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3067 | cf495bcf | bellard | if (xop & 0x10) |
3068 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3069 | cf495bcf | bellard | break;
|
3070 | cf495bcf | bellard | case 0x6: |
3071 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3072 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3073 | cf495bcf | bellard | if (xop & 0x10) |
3074 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3075 | cf495bcf | bellard | break;
|
3076 | cf495bcf | bellard | case 0x7: |
3077 | 6ae20372 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
|
3078 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3079 | cf495bcf | bellard | if (xop & 0x10) |
3080 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3081 | cf495bcf | bellard | break;
|
3082 | cf495bcf | bellard | case 0x8: |
3083 | cf495bcf | bellard | if (xop & 0x10) |
3084 | 6ae20372 | blueswir1 | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
3085 | 38bc628b | blueswir1 | else {
|
3086 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3087 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3088 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3089 | 38bc628b | blueswir1 | } |
3090 | cf495bcf | bellard | break;
|
3091 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3092 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3093 | 6ae20372 | blueswir1 | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
3094 | ded3ab80 | pbrook | break;
|
3095 | ded3ab80 | pbrook | #endif
|
3096 | cf495bcf | bellard | case 0xa: |
3097 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3098 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3099 | cf495bcf | bellard | if (xop & 0x10) |
3100 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3101 | cf495bcf | bellard | break;
|
3102 | cf495bcf | bellard | case 0xb: |
3103 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3104 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3105 | cf495bcf | bellard | if (xop & 0x10) |
3106 | 6ae20372 | blueswir1 | gen_op_logic_cc(cpu_dst); |
3107 | cf495bcf | bellard | break;
|
3108 | cf495bcf | bellard | case 0xc: |
3109 | cf495bcf | bellard | if (xop & 0x10) |
3110 | 6ae20372 | blueswir1 | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3111 | 38bc628b | blueswir1 | else {
|
3112 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3113 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3114 | 6ae20372 | blueswir1 | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3115 | 38bc628b | blueswir1 | } |
3116 | cf495bcf | bellard | break;
|
3117 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3118 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3119 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3120 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3121 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3122 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3123 | ded3ab80 | pbrook | break;
|
3124 | ded3ab80 | pbrook | #endif
|
3125 | cf495bcf | bellard | case 0xe: |
3126 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3127 | 77f193da | blueswir1 | tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, |
3128 | 77f193da | blueswir1 | cpu_src2); |
3129 | cf495bcf | bellard | if (xop & 0x10) |
3130 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3131 | cf495bcf | bellard | break;
|
3132 | cf495bcf | bellard | case 0xf: |
3133 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3134 | 77f193da | blueswir1 | tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, |
3135 | 77f193da | blueswir1 | cpu_src2); |
3136 | cf495bcf | bellard | if (xop & 0x10) |
3137 | 6ae20372 | blueswir1 | gen_op_div_cc(cpu_dst); |
3138 | cf495bcf | bellard | break;
|
3139 | cf495bcf | bellard | default:
|
3140 | cf495bcf | bellard | goto illegal_insn;
|
3141 | cf495bcf | bellard | } |
3142 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3143 | cf495bcf | bellard | } else {
|
3144 | cf495bcf | bellard | switch (xop) {
|
3145 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3146 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3147 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3148 | 0f8a249a | blueswir1 | break;
|
3149 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3150 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3151 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3152 | 0f8a249a | blueswir1 | break;
|
3153 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3154 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3155 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3156 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3157 | 0f8a249a | blueswir1 | break;
|
3158 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3159 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3160 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3161 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3162 | 0f8a249a | blueswir1 | break;
|
3163 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3164 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3165 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3166 | cf495bcf | bellard | break;
|
3167 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3168 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3169 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3170 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3171 | e35298cd | blueswir1 | tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3172 | e35298cd | blueswir1 | } else { /* register */ |
3173 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3174 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3175 | e35298cd | blueswir1 | } |
3176 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3177 | cf495bcf | bellard | break;
|
3178 | 83469015 | bellard | case 0x26: /* srl */ |
3179 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3180 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3181 | e35298cd | blueswir1 | tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3182 | e35298cd | blueswir1 | } else { /* register */ |
3183 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3184 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3185 | e35298cd | blueswir1 | } |
3186 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3187 | cf495bcf | bellard | break;
|
3188 | 83469015 | bellard | case 0x27: /* sra */ |
3189 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3190 | e35298cd | blueswir1 | rs2 = GET_FIELDs(insn, 20, 31); |
3191 | e35298cd | blueswir1 | tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
|
3192 | e35298cd | blueswir1 | } else { /* register */ |
3193 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3194 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3195 | e35298cd | blueswir1 | } |
3196 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3197 | cf495bcf | bellard | break;
|
3198 | 83469015 | bellard | #endif
|
3199 | cf495bcf | bellard | case 0x30: |
3200 | cf495bcf | bellard | { |
3201 | cf495bcf | bellard | switch(rd) {
|
3202 | 3475187d | bellard | case 0: /* wry */ |
3203 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3204 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3205 | cf495bcf | bellard | break;
|
3206 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3207 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3208 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3209 | 65fe7b09 | blueswir1 | on the microSPARC
|
3210 | 65fe7b09 | blueswir1 | II */
|
3211 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3212 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3213 | 65fe7b09 | blueswir1 | manual, nop on the
|
3214 | 65fe7b09 | blueswir1 | microSPARC II */
|
3215 | 65fe7b09 | blueswir1 | break;
|
3216 | 65fe7b09 | blueswir1 | #else
|
3217 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3218 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3219 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_wrccr, cpu_dst); |
3220 | 0f8a249a | blueswir1 | break;
|
3221 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3222 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3223 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3224 | 0f8a249a | blueswir1 | break;
|
3225 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3226 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3227 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3228 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3229 | 3299908c | blueswir1 | gen_op_next_insn(); |
3230 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3231 | 3299908c | blueswir1 | dc->is_br = 1;
|
3232 | 0f8a249a | blueswir1 | break;
|
3233 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3234 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3235 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3236 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3237 | 3475187d | bellard | #endif
|
3238 | 0f8a249a | blueswir1 | break;
|
3239 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3240 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3241 | 725cb90b | bellard | goto jmp_insn;
|
3242 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3243 | 0f8a249a | blueswir1 | break;
|
3244 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3245 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3246 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3247 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3248 | 83469015 | bellard | #endif
|
3249 | ccd4a219 | blueswir1 | { |
3250 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3251 | ccd4a219 | blueswir1 | |
3252 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3253 | 6ae20372 | blueswir1 | cpu_src2); |
3254 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3255 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3256 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3257 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3258 | 255e1fcb | blueswir1 | r_tickptr, cpu_tick_cmpr); |
3259 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3260 | ccd4a219 | blueswir1 | } |
3261 | 0f8a249a | blueswir1 | break;
|
3262 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3263 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3264 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3265 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3266 | 83469015 | bellard | #endif
|
3267 | ccd4a219 | blueswir1 | { |
3268 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3269 | ccd4a219 | blueswir1 | |
3270 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3271 | 6ae20372 | blueswir1 | cpu_src2); |
3272 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3273 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3274 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3275 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3276 | 6ae20372 | blueswir1 | r_tickptr, cpu_dst); |
3277 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3278 | ccd4a219 | blueswir1 | } |
3279 | 0f8a249a | blueswir1 | break;
|
3280 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3281 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3282 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3283 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3284 | 3475187d | bellard | #endif
|
3285 | ccd4a219 | blueswir1 | { |
3286 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3287 | ccd4a219 | blueswir1 | |
3288 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3289 | 6ae20372 | blueswir1 | cpu_src2); |
3290 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3291 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3292 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3293 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3294 | 255e1fcb | blueswir1 | r_tickptr, cpu_stick_cmpr); |
3295 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3296 | ccd4a219 | blueswir1 | } |
3297 | 0f8a249a | blueswir1 | break;
|
3298 | 83469015 | bellard | |
3299 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3300 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3301 | 77f193da | blueswir1 | Counter */
|
3302 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3303 | 0f8a249a | blueswir1 | case 0x14: /* Softint set */ |
3304 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear */ |
3305 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
3306 | 83469015 | bellard | #endif
|
3307 | 3475187d | bellard | default:
|
3308 | cf495bcf | bellard | goto illegal_insn;
|
3309 | cf495bcf | bellard | } |
3310 | cf495bcf | bellard | } |
3311 | cf495bcf | bellard | break;
|
3312 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3313 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3314 | e8af50a3 | bellard | { |
3315 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3316 | 0f8a249a | blueswir1 | goto priv_insn;
|
3317 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3318 | 0f8a249a | blueswir1 | switch (rd) {
|
3319 | 0f8a249a | blueswir1 | case 0: |
3320 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_saved); |
3321 | 0f8a249a | blueswir1 | break;
|
3322 | 0f8a249a | blueswir1 | case 1: |
3323 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restored); |
3324 | 0f8a249a | blueswir1 | break;
|
3325 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3326 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3327 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3328 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3329 | e9ebed4d | blueswir1 | // XXX
|
3330 | 0f8a249a | blueswir1 | default:
|
3331 | 3475187d | bellard | goto illegal_insn;
|
3332 | 3475187d | bellard | } |
3333 | 3475187d | bellard | #else
|
3334 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3335 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); |
3336 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3337 | 9e61bde5 | bellard | gen_op_next_insn(); |
3338 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3339 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3340 | 3475187d | bellard | #endif
|
3341 | e8af50a3 | bellard | } |
3342 | e8af50a3 | bellard | break;
|
3343 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3344 | e8af50a3 | bellard | { |
3345 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3346 | 0f8a249a | blueswir1 | goto priv_insn;
|
3347 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3348 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3349 | 0f8a249a | blueswir1 | switch (rd) {
|
3350 | 0f8a249a | blueswir1 | case 0: // tpc |
3351 | 375ee38b | blueswir1 | { |
3352 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3353 | 375ee38b | blueswir1 | |
3354 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3355 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3356 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3357 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3358 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3359 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3360 | 375ee38b | blueswir1 | } |
3361 | 0f8a249a | blueswir1 | break;
|
3362 | 0f8a249a | blueswir1 | case 1: // tnpc |
3363 | 375ee38b | blueswir1 | { |
3364 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3365 | 375ee38b | blueswir1 | |
3366 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3367 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3368 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3369 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3370 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3371 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3372 | 375ee38b | blueswir1 | } |
3373 | 0f8a249a | blueswir1 | break;
|
3374 | 0f8a249a | blueswir1 | case 2: // tstate |
3375 | 375ee38b | blueswir1 | { |
3376 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3377 | 375ee38b | blueswir1 | |
3378 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3379 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3380 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3381 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3382 | 77f193da | blueswir1 | offsetof(trap_state, |
3383 | 77f193da | blueswir1 | tstate)); |
3384 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3385 | 375ee38b | blueswir1 | } |
3386 | 0f8a249a | blueswir1 | break;
|
3387 | 0f8a249a | blueswir1 | case 3: // tt |
3388 | 375ee38b | blueswir1 | { |
3389 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3390 | 375ee38b | blueswir1 | |
3391 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3392 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3393 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3394 | ece43b8d | blueswir1 | tcg_gen_st_i32(cpu_tmp0, r_tsptr, |
3395 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3396 | 2ea815ca | blueswir1 | tcg_temp_free(r_tsptr); |
3397 | 375ee38b | blueswir1 | } |
3398 | 0f8a249a | blueswir1 | break;
|
3399 | 0f8a249a | blueswir1 | case 4: // tick |
3400 | ccd4a219 | blueswir1 | { |
3401 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3402 | ccd4a219 | blueswir1 | |
3403 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3404 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3405 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3406 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3407 | ece43b8d | blueswir1 | r_tickptr, cpu_tmp0); |
3408 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3409 | ccd4a219 | blueswir1 | } |
3410 | 0f8a249a | blueswir1 | break;
|
3411 | 0f8a249a | blueswir1 | case 5: // tba |
3412 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3413 | 0f8a249a | blueswir1 | break;
|
3414 | 0f8a249a | blueswir1 | case 6: // pstate |
3415 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3416 | ece43b8d | blueswir1 | tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0); |
3417 | ded3ab80 | pbrook | gen_op_next_insn(); |
3418 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3419 | ded3ab80 | pbrook | dc->is_br = 1;
|
3420 | 0f8a249a | blueswir1 | break;
|
3421 | 0f8a249a | blueswir1 | case 7: // tl |
3422 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3423 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3424 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3425 | 0f8a249a | blueswir1 | break;
|
3426 | 0f8a249a | blueswir1 | case 8: // pil |
3427 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3428 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3429 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3430 | 77f193da | blueswir1 | psrpil)); |
3431 | 0f8a249a | blueswir1 | break;
|
3432 | 0f8a249a | blueswir1 | case 9: // cwp |
3433 | ece43b8d | blueswir1 | tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0); |
3434 | 0f8a249a | blueswir1 | break;
|
3435 | 0f8a249a | blueswir1 | case 10: // cansave |
3436 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3437 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3438 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3439 | 77f193da | blueswir1 | cansave)); |
3440 | 0f8a249a | blueswir1 | break;
|
3441 | 0f8a249a | blueswir1 | case 11: // canrestore |
3442 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3443 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3444 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3445 | 77f193da | blueswir1 | canrestore)); |
3446 | 0f8a249a | blueswir1 | break;
|
3447 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3448 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3449 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3450 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3451 | 77f193da | blueswir1 | cleanwin)); |
3452 | 0f8a249a | blueswir1 | break;
|
3453 | 0f8a249a | blueswir1 | case 13: // otherwin |
3454 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3455 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3456 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3457 | 77f193da | blueswir1 | otherwin)); |
3458 | 0f8a249a | blueswir1 | break;
|
3459 | 0f8a249a | blueswir1 | case 14: // wstate |
3460 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3461 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3462 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3463 | 77f193da | blueswir1 | wstate)); |
3464 | 0f8a249a | blueswir1 | break;
|
3465 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3466 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3467 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3468 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3469 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3470 | e9ebed4d | blueswir1 | break;
|
3471 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3472 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3473 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3474 | e9ebed4d | blueswir1 | goto priv_insn;
|
3475 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0); |
3476 | e9ebed4d | blueswir1 | break;
|
3477 | 0f8a249a | blueswir1 | default:
|
3478 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3479 | 0f8a249a | blueswir1 | } |
3480 | 3475187d | bellard | #else
|
3481 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3482 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3483 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3484 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3485 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3486 | 3475187d | bellard | #endif
|
3487 | e8af50a3 | bellard | } |
3488 | e8af50a3 | bellard | break;
|
3489 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3490 | e8af50a3 | bellard | { |
3491 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3492 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3493 | 0f8a249a | blueswir1 | goto priv_insn;
|
3494 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3495 | e9ebed4d | blueswir1 | #else
|
3496 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3497 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3498 | e9ebed4d | blueswir1 | goto priv_insn;
|
3499 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3500 | e9ebed4d | blueswir1 | switch (rd) {
|
3501 | e9ebed4d | blueswir1 | case 0: // hpstate |
3502 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3503 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3504 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3505 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3506 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3507 | e9ebed4d | blueswir1 | break;
|
3508 | e9ebed4d | blueswir1 | case 1: // htstate |
3509 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3510 | e9ebed4d | blueswir1 | break;
|
3511 | e9ebed4d | blueswir1 | case 3: // hintp |
3512 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3513 | e9ebed4d | blueswir1 | break;
|
3514 | e9ebed4d | blueswir1 | case 5: // htba |
3515 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3516 | e9ebed4d | blueswir1 | break;
|
3517 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3518 | ccd4a219 | blueswir1 | { |
3519 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3520 | ccd4a219 | blueswir1 | |
3521 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3522 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3523 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3524 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3525 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3526 | 255e1fcb | blueswir1 | r_tickptr, cpu_hstick_cmpr); |
3527 | 2ea815ca | blueswir1 | tcg_temp_free(r_tickptr); |
3528 | ccd4a219 | blueswir1 | } |
3529 | e9ebed4d | blueswir1 | break;
|
3530 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3531 | e9ebed4d | blueswir1 | default:
|
3532 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3533 | e9ebed4d | blueswir1 | } |
3534 | e9ebed4d | blueswir1 | #endif
|
3535 | e8af50a3 | bellard | } |
3536 | e8af50a3 | bellard | break;
|
3537 | e8af50a3 | bellard | #endif
|
3538 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3539 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3540 | 0f8a249a | blueswir1 | { |
3541 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3542 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3543 | 748b9d8e | blueswir1 | TCGv r_cond; |
3544 | 00f219bf | blueswir1 | int l1;
|
3545 | 00f219bf | blueswir1 | |
3546 | 748b9d8e | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
3547 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3548 | 0f8a249a | blueswir1 | if (cc == 0) |
3549 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
3550 | 0f8a249a | blueswir1 | else if (cc == 2) |
3551 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
3552 | 0f8a249a | blueswir1 | else
|
3553 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3554 | 0f8a249a | blueswir1 | } else {
|
3555 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3556 | 0f8a249a | blueswir1 | } |
3557 | 00f219bf | blueswir1 | |
3558 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3559 | 00f219bf | blueswir1 | |
3560 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3561 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3562 | 2ea815ca | blueswir1 | TCGv r_const; |
3563 | 2ea815ca | blueswir1 | |
3564 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
3565 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
3566 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3567 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3568 | 00f219bf | blueswir1 | } else {
|
3569 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3570 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3571 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3572 | 00f219bf | blueswir1 | } |
3573 | 00f219bf | blueswir1 | gen_set_label(l1); |
3574 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3575 | 0f8a249a | blueswir1 | break;
|
3576 | 0f8a249a | blueswir1 | } |
3577 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3578 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3579 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3580 | 0f8a249a | blueswir1 | break;
|
3581 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3582 | 0f8a249a | blueswir1 | { |
3583 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3584 | 6ae20372 | blueswir1 | tcg_gen_helper_1_1(helper_popc, cpu_dst, |
3585 | 6ae20372 | blueswir1 | cpu_src2); |
3586 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3587 | 0f8a249a | blueswir1 | } |
3588 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3589 | 0f8a249a | blueswir1 | { |
3590 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3591 | 00f219bf | blueswir1 | int l1;
|
3592 | 00f219bf | blueswir1 | |
3593 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3594 | 00f219bf | blueswir1 | |
3595 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3596 | 00f219bf | blueswir1 | |
3597 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3598 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3599 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3600 | 2ea815ca | blueswir1 | TCGv r_const; |
3601 | 2ea815ca | blueswir1 | |
3602 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
3603 | 2ea815ca | blueswir1 | r_const = tcg_const_tl((int)rs2);
|
3604 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3605 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3606 | 00f219bf | blueswir1 | } else {
|
3607 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3608 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3609 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3610 | 0f8a249a | blueswir1 | } |
3611 | 00f219bf | blueswir1 | gen_set_label(l1); |
3612 | 0f8a249a | blueswir1 | break;
|
3613 | 0f8a249a | blueswir1 | } |
3614 | 0f8a249a | blueswir1 | #endif
|
3615 | 0f8a249a | blueswir1 | default:
|
3616 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3617 | 0f8a249a | blueswir1 | } |
3618 | 0f8a249a | blueswir1 | } |
3619 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3620 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3621 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3622 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3623 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3624 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3625 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3626 | 3299908c | blueswir1 | |
3627 | 3299908c | blueswir1 | switch (opf) {
|
3628 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3629 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3630 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3631 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3632 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3633 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3634 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3635 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3636 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3637 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3638 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3639 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3640 | e9ebed4d | blueswir1 | // XXX
|
3641 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3642 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3643 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3644 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3645 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3646 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3647 | 6ae20372 | blueswir1 | cpu_src2); |
3648 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3649 | e9ebed4d | blueswir1 | break;
|
3650 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3651 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3652 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3653 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3654 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3655 | 6ae20372 | blueswir1 | cpu_src2); |
3656 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3657 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3658 | e9ebed4d | blueswir1 | break;
|
3659 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3660 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3661 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3662 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3663 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, |
3664 | 6ae20372 | blueswir1 | cpu_src2); |
3665 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3666 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3667 | e9ebed4d | blueswir1 | break;
|
3668 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3669 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3670 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3671 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3672 | 6ae20372 | blueswir1 | tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, |
3673 | 6ae20372 | blueswir1 | cpu_src2); |
3674 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3675 | 3299908c | blueswir1 | break;
|
3676 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3677 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3678 | 3299908c | blueswir1 | // XXX
|
3679 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3680 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3681 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3682 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3683 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3684 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple16); |
3685 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3686 | e9ebed4d | blueswir1 | break;
|
3687 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3688 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3689 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3690 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3691 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne16); |
3692 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3693 | 3299908c | blueswir1 | break;
|
3694 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3695 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3696 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3697 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3698 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple32); |
3699 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3700 | e9ebed4d | blueswir1 | break;
|
3701 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3702 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3703 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3704 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3705 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne32); |
3706 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3707 | e9ebed4d | blueswir1 | break;
|
3708 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3709 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3710 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3711 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3712 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt16); |
3713 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3714 | e9ebed4d | blueswir1 | break;
|
3715 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3716 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3717 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3718 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3719 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq16); |
3720 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3721 | e9ebed4d | blueswir1 | break;
|
3722 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3723 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3724 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3725 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3726 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt32); |
3727 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3728 | e9ebed4d | blueswir1 | break;
|
3729 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3730 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3731 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3732 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3733 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq32); |
3734 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3735 | e9ebed4d | blueswir1 | break;
|
3736 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3737 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3738 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3739 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3740 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16); |
3741 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3742 | e9ebed4d | blueswir1 | break;
|
3743 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3744 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3745 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3746 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3747 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16au); |
3748 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3749 | e9ebed4d | blueswir1 | break;
|
3750 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3751 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3752 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3753 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3754 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16al); |
3755 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3756 | e9ebed4d | blueswir1 | break;
|
3757 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3758 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3759 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3760 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3761 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8sux16); |
3762 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3763 | e9ebed4d | blueswir1 | break;
|
3764 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3765 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3766 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3767 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3768 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
3769 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3770 | e9ebed4d | blueswir1 | break;
|
3771 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3772 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3773 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3774 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3775 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
3776 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3777 | e9ebed4d | blueswir1 | break;
|
3778 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3779 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3780 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3781 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3782 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
3783 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3784 | e9ebed4d | blueswir1 | break;
|
3785 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3786 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3787 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3788 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3789 | e9ebed4d | blueswir1 | // XXX
|
3790 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3791 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3792 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3793 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3794 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3795 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faligndata); |
3796 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3797 | 3299908c | blueswir1 | break;
|
3798 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3799 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3800 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3801 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3802 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpmerge); |
3803 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3804 | e9ebed4d | blueswir1 | break;
|
3805 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3806 | e9ebed4d | blueswir1 | // XXX
|
3807 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3808 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3809 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3810 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3811 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3812 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fexpand); |
3813 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3814 | e9ebed4d | blueswir1 | break;
|
3815 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3816 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3817 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3818 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3819 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16); |
3820 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3821 | e9ebed4d | blueswir1 | break;
|
3822 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3823 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3824 | 1d01299d | blueswir1 | tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd], |
3825 | 1d01299d | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
3826 | e9ebed4d | blueswir1 | break;
|
3827 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3828 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3829 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3830 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3831 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3832 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3833 | e9ebed4d | blueswir1 | break;
|
3834 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3835 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3836 | 1d01299d | blueswir1 | tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd], |
3837 | 1d01299d | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
3838 | e9ebed4d | blueswir1 | break;
|
3839 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3840 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3841 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3842 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3843 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16); |
3844 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3845 | e9ebed4d | blueswir1 | break;
|
3846 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3847 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3848 | 1d01299d | blueswir1 | tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd], |
3849 | 1d01299d | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
3850 | e9ebed4d | blueswir1 | break;
|
3851 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3852 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3853 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3854 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3855 | 510aba20 | blueswir1 | tcg_gen_helper_0_0(helper_fpsub32); |
3856 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3857 | e9ebed4d | blueswir1 | break;
|
3858 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3859 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3860 | 1d01299d | blueswir1 | tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd], |
3861 | 1d01299d | blueswir1 | cpu_fpr[rs1], cpu_fpr[rs2]); |
3862 | e9ebed4d | blueswir1 | break;
|
3863 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3864 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3865 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
3866 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
3867 | 3299908c | blueswir1 | break;
|
3868 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3869 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3870 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
3871 | 3299908c | blueswir1 | break;
|
3872 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3873 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3874 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3875 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3876 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
|
3877 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3878 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3879 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); |
3880 | e9ebed4d | blueswir1 | break;
|
3881 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3882 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3883 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3884 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
|
3885 | e9ebed4d | blueswir1 | break;
|
3886 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3887 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3888 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
|
3889 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3890 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3891 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); |
3892 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3893 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3894 | e9ebed4d | blueswir1 | break;
|
3895 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3896 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3897 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
|
3898 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); |
3899 | e9ebed4d | blueswir1 | break;
|
3900 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3901 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3902 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3903 | e2ea21b3 | blueswir1 | -1);
|
3904 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
|
3905 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1], -1); |
3906 | e9ebed4d | blueswir1 | break;
|
3907 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3908 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3909 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1);
|
3910 | e9ebed4d | blueswir1 | break;
|
3911 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3912 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3913 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3914 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3915 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3916 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3917 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3918 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3919 | e9ebed4d | blueswir1 | break;
|
3920 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3921 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3922 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
3923 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
3924 | e9ebed4d | blueswir1 | break;
|
3925 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3926 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3927 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3928 | e2ea21b3 | blueswir1 | -1);
|
3929 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
|
3930 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1], -1); |
3931 | e9ebed4d | blueswir1 | break;
|
3932 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3933 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3934 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1);
|
3935 | e9ebed4d | blueswir1 | break;
|
3936 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3937 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3938 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3939 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3940 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
3941 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3942 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3943 | e9ebed4d | blueswir1 | break;
|
3944 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3945 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3946 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3947 | e9ebed4d | blueswir1 | break;
|
3948 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3949 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3950 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3951 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3952 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
|
3953 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3954 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3955 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); |
3956 | e9ebed4d | blueswir1 | break;
|
3957 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3958 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3959 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3960 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
|
3961 | e9ebed4d | blueswir1 | break;
|
3962 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3963 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3964 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3965 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3966 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
3967 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3968 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3969 | e9ebed4d | blueswir1 | break;
|
3970 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3971 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3972 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3973 | e9ebed4d | blueswir1 | break;
|
3974 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3975 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3976 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3977 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3978 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3979 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
3980 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3981 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3982 | e9ebed4d | blueswir1 | break;
|
3983 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3984 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3985 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
3986 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
3987 | e9ebed4d | blueswir1 | break;
|
3988 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3989 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3990 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3991 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
3992 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3993 | 3299908c | blueswir1 | break;
|
3994 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3995 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3996 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3997 | 3299908c | blueswir1 | break;
|
3998 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3999 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4000 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
|
4001 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
4002 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4003 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); |
4004 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
4005 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4006 | e9ebed4d | blueswir1 | break;
|
4007 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
4008 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4009 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
|
4010 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); |
4011 | e9ebed4d | blueswir1 | break;
|
4012 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
4013 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4014 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
4015 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4016 | 3299908c | blueswir1 | break;
|
4017 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
4018 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4019 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
4020 | 3299908c | blueswir1 | break;
|
4021 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
4022 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4023 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
4024 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
4025 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4026 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
4027 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
4028 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4029 | e9ebed4d | blueswir1 | break;
|
4030 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
4031 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4032 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
4033 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
4034 | e9ebed4d | blueswir1 | break;
|
4035 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
4036 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4037 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4038 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4039 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
4040 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4041 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4042 | e9ebed4d | blueswir1 | break;
|
4043 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
4044 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4045 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4046 | e9ebed4d | blueswir1 | break;
|
4047 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
4048 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4049 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
4050 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
4051 | 3299908c | blueswir1 | break;
|
4052 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
4053 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4054 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
4055 | 3299908c | blueswir1 | break;
|
4056 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
4057 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
4058 | e9ebed4d | blueswir1 | // XXX
|
4059 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4060 | 3299908c | blueswir1 | default:
|
4061 | 3299908c | blueswir1 | goto illegal_insn;
|
4062 | 3299908c | blueswir1 | } |
4063 | 3299908c | blueswir1 | #else
|
4064 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4065 | 3299908c | blueswir1 | #endif
|
4066 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
4067 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
4068 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4069 | fcc72045 | blueswir1 | #else
|
4070 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4071 | fcc72045 | blueswir1 | #endif
|
4072 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4073 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4074 | 2ea815ca | blueswir1 | TCGv r_const; |
4075 | 2ea815ca | blueswir1 | |
4076 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4077 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4078 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4079 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4080 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
|
4081 | 0f8a249a | blueswir1 | } else { /* register */ |
4082 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4083 | 0f8a249a | blueswir1 | if (rs2) {
|
4084 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4085 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4086 | 6f551262 | blueswir1 | } else
|
4087 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4088 | 3475187d | bellard | } |
4089 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4090 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4091 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4092 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); |
4093 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4094 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4095 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4096 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4097 | 3475187d | bellard | #endif
|
4098 | 0f8a249a | blueswir1 | } else {
|
4099 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4100 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4101 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4102 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
|
4103 | 0f8a249a | blueswir1 | } else { /* register */ |
4104 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4105 | 0f8a249a | blueswir1 | if (rs2) {
|
4106 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4107 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4108 | 6f551262 | blueswir1 | } else
|
4109 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4110 | cf495bcf | bellard | } |
4111 | 0f8a249a | blueswir1 | switch (xop) {
|
4112 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4113 | 0f8a249a | blueswir1 | { |
4114 | 2ea815ca | blueswir1 | TCGv r_const; |
4115 | 2ea815ca | blueswir1 | |
4116 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
4117 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
4118 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4119 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4120 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4121 | 77f193da | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
4122 | 2ea815ca | blueswir1 | r_const); |
4123 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4124 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4125 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4126 | 0f8a249a | blueswir1 | } |
4127 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4128 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4129 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4130 | 0f8a249a | blueswir1 | { |
4131 | 2ea815ca | blueswir1 | TCGv r_const; |
4132 | 2ea815ca | blueswir1 | |
4133 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4134 | 0f8a249a | blueswir1 | goto priv_insn;
|
4135 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4136 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4137 | 77f193da | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
4138 | 2ea815ca | blueswir1 | r_const); |
4139 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4140 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4141 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4142 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_rett); |
4143 | 0f8a249a | blueswir1 | } |
4144 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4145 | 0f8a249a | blueswir1 | #endif
|
4146 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4147 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4148 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4149 | 6ae20372 | blueswir1 | tcg_gen_helper_0_1(helper_flush, cpu_dst); |
4150 | 0f8a249a | blueswir1 | break;
|
4151 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4152 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4153 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_save); |
4154 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4155 | 0f8a249a | blueswir1 | break;
|
4156 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4157 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4158 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4159 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4160 | 0f8a249a | blueswir1 | break;
|
4161 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4162 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4163 | 0f8a249a | blueswir1 | { |
4164 | 0f8a249a | blueswir1 | switch (rd) {
|
4165 | 0f8a249a | blueswir1 | case 0: |
4166 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4167 | 0f8a249a | blueswir1 | goto priv_insn;
|
4168 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4169 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4170 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_done); |
4171 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4172 | 0f8a249a | blueswir1 | case 1: |
4173 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4174 | 0f8a249a | blueswir1 | goto priv_insn;
|
4175 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4176 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4177 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_retry); |
4178 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4179 | 0f8a249a | blueswir1 | default:
|
4180 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4181 | 0f8a249a | blueswir1 | } |
4182 | 0f8a249a | blueswir1 | } |
4183 | 0f8a249a | blueswir1 | break;
|
4184 | 0f8a249a | blueswir1 | #endif
|
4185 | 0f8a249a | blueswir1 | default:
|
4186 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4187 | 0f8a249a | blueswir1 | } |
4188 | cf495bcf | bellard | } |
4189 | 0f8a249a | blueswir1 | break;
|
4190 | 0f8a249a | blueswir1 | } |
4191 | 0f8a249a | blueswir1 | break;
|
4192 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4193 | 0f8a249a | blueswir1 | { |
4194 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4195 | 9322a4bf | blueswir1 | |
4196 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4197 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4198 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4199 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4200 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4201 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4202 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4203 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
|
4204 | 0f8a249a | blueswir1 | } else { /* register */ |
4205 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4206 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4207 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4208 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4209 | 6f551262 | blueswir1 | } else
|
4210 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4211 | 0f8a249a | blueswir1 | } |
4212 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4213 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4214 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4215 | 0f8a249a | blueswir1 | switch (xop) {
|
4216 | 1a2fb1c0 | blueswir1 | case 0x0: /* load unsigned word */ |
4217 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4218 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4219 | 0f8a249a | blueswir1 | break;
|
4220 | 0f8a249a | blueswir1 | case 0x1: /* load unsigned byte */ |
4221 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4222 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4223 | 0f8a249a | blueswir1 | break;
|
4224 | 0f8a249a | blueswir1 | case 0x2: /* load unsigned halfword */ |
4225 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4226 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4227 | 0f8a249a | blueswir1 | break;
|
4228 | 0f8a249a | blueswir1 | case 0x3: /* load double word */ |
4229 | 0f8a249a | blueswir1 | if (rd & 1) |
4230 | d4218d99 | blueswir1 | goto illegal_insn;
|
4231 | 1a2fb1c0 | blueswir1 | else {
|
4232 | 2ea815ca | blueswir1 | TCGv r_const; |
4233 | 2ea815ca | blueswir1 | |
4234 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4235 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4236 | d987963a | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4237 | 2ea815ca | blueswir1 | r_const); // XXX remove
|
4238 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4239 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4240 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4241 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4242 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4243 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4244 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4245 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4246 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4247 | 1a2fb1c0 | blueswir1 | } |
4248 | 0f8a249a | blueswir1 | break;
|
4249 | 0f8a249a | blueswir1 | case 0x9: /* load signed byte */ |
4250 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4251 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4252 | 0f8a249a | blueswir1 | break;
|
4253 | 0f8a249a | blueswir1 | case 0xa: /* load signed halfword */ |
4254 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4255 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4256 | 0f8a249a | blueswir1 | break;
|
4257 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4258 | 2ea815ca | blueswir1 | { |
4259 | 2ea815ca | blueswir1 | TCGv r_const; |
4260 | 2ea815ca | blueswir1 | |
4261 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4262 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4263 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4264 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4265 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4266 | 2ea815ca | blueswir1 | } |
4267 | 0f8a249a | blueswir1 | break;
|
4268 | 77f193da | blueswir1 | case 0x0f: /* swap register with memory. Also |
4269 | 77f193da | blueswir1 | atomically */
|
4270 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4271 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4272 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4273 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4274 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4275 | 6ae20372 | blueswir1 | tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32); |
4276 | 0f8a249a | blueswir1 | break;
|
4277 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4278 | 0f8a249a | blueswir1 | case 0x10: /* load word alternate */ |
4279 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4280 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4281 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4282 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4283 | 0f8a249a | blueswir1 | goto priv_insn;
|
4284 | 6ea4a6c8 | blueswir1 | #endif
|
4285 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4286 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4287 | 0f8a249a | blueswir1 | break;
|
4288 | 0f8a249a | blueswir1 | case 0x11: /* load unsigned byte alternate */ |
4289 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4290 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4291 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4292 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4293 | 0f8a249a | blueswir1 | goto priv_insn;
|
4294 | 0f8a249a | blueswir1 | #endif
|
4295 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4296 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4297 | 0f8a249a | blueswir1 | break;
|
4298 | 0f8a249a | blueswir1 | case 0x12: /* load unsigned halfword alternate */ |
4299 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4300 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4301 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4302 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4303 | 0f8a249a | blueswir1 | goto priv_insn;
|
4304 | 6ea4a6c8 | blueswir1 | #endif
|
4305 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4306 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4307 | 0f8a249a | blueswir1 | break;
|
4308 | 0f8a249a | blueswir1 | case 0x13: /* load double word alternate */ |
4309 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4310 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4311 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4312 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4313 | 0f8a249a | blueswir1 | goto priv_insn;
|
4314 | 3475187d | bellard | #endif
|
4315 | 0f8a249a | blueswir1 | if (rd & 1) |
4316 | d4218d99 | blueswir1 | goto illegal_insn;
|
4317 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4318 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4319 | db166940 | blueswir1 | goto skip_move;
|
4320 | 0f8a249a | blueswir1 | case 0x19: /* load signed byte alternate */ |
4321 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4322 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4323 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4324 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4325 | 0f8a249a | blueswir1 | goto priv_insn;
|
4326 | 0f8a249a | blueswir1 | #endif
|
4327 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4328 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4329 | 0f8a249a | blueswir1 | break;
|
4330 | 0f8a249a | blueswir1 | case 0x1a: /* load signed halfword alternate */ |
4331 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4332 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4333 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4334 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4335 | 0f8a249a | blueswir1 | goto priv_insn;
|
4336 | 6ea4a6c8 | blueswir1 | #endif
|
4337 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4338 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4339 | 0f8a249a | blueswir1 | break;
|
4340 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4341 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4342 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4343 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4344 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4345 | 0f8a249a | blueswir1 | goto priv_insn;
|
4346 | 0f8a249a | blueswir1 | #endif
|
4347 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4348 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4349 | 0f8a249a | blueswir1 | break;
|
4350 | 77f193da | blueswir1 | case 0x1f: /* swap reg with alt. memory. Also |
4351 | 77f193da | blueswir1 | atomically */
|
4352 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4353 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4354 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4355 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4356 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4357 | 0f8a249a | blueswir1 | goto priv_insn;
|
4358 | 6ea4a6c8 | blueswir1 | #endif
|
4359 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4360 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4361 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4362 | 0f8a249a | blueswir1 | break;
|
4363 | 3475187d | bellard | |
4364 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4365 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4366 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4367 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4368 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4369 | 3475187d | bellard | #endif
|
4370 | 3475187d | bellard | #endif
|
4371 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4372 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4373 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4374 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4375 | 0f8a249a | blueswir1 | break;
|
4376 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4377 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4378 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4379 | 0f8a249a | blueswir1 | break;
|
4380 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4381 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4382 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4383 | 0f8a249a | blueswir1 | break;
|
4384 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4385 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4386 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4387 | 0f8a249a | blueswir1 | break;
|
4388 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4389 | 0f8a249a | blueswir1 | goto skip_move;
|
4390 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4391 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4392 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4393 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4394 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4395 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4396 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4397 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4398 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4399 | 0f8a249a | blueswir1 | goto skip_move;
|
4400 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4401 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4402 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4403 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4404 | 1f587329 | blueswir1 | goto skip_move;
|
4405 | 1f587329 | blueswir1 | #endif
|
4406 | 0f8a249a | blueswir1 | default:
|
4407 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4408 | 0f8a249a | blueswir1 | } |
4409 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4410 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4411 | 0f8a249a | blueswir1 | skip_move: ;
|
4412 | 3475187d | bellard | #endif
|
4413 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4414 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4415 | a80dde08 | bellard | goto jmp_insn;
|
4416 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4417 | 0f8a249a | blueswir1 | switch (xop) {
|
4418 | 0f8a249a | blueswir1 | case 0x20: /* load fpreg */ |
4419 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4420 | 714547bb | blueswir1 | tcg_gen_qemu_ld32u(cpu_fpr[rd], cpu_addr, dc->mem_idx); |
4421 | 0f8a249a | blueswir1 | break;
|
4422 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4423 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4424 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4425 | 3a3b925d | blueswir1 | if (rd == 1) { |
4426 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4427 | 3a3b925d | blueswir1 | tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64); |
4428 | 3a3b925d | blueswir1 | } else
|
4429 | 3a3b925d | blueswir1 | #else
|
4430 | 3a3b925d | blueswir1 | { |
4431 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4432 | 3a3b925d | blueswir1 | tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32); |
4433 | 3a3b925d | blueswir1 | } |
4434 | 3a3b925d | blueswir1 | #endif
|
4435 | 0f8a249a | blueswir1 | break;
|
4436 | 0f8a249a | blueswir1 | case 0x22: /* load quad fpreg */ |
4437 | 2ea815ca | blueswir1 | { |
4438 | 2ea815ca | blueswir1 | TCGv r_const; |
4439 | 2ea815ca | blueswir1 | |
4440 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4441 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4442 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); |
4443 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4444 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4445 | 2ea815ca | blueswir1 | } |
4446 | 1f587329 | blueswir1 | break;
|
4447 | 0f8a249a | blueswir1 | case 0x23: /* load double fpreg */ |
4448 | 2ea815ca | blueswir1 | { |
4449 | 2ea815ca | blueswir1 | TCGv r_const; |
4450 | 2ea815ca | blueswir1 | |
4451 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4452 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); |
4453 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4454 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4455 | 2ea815ca | blueswir1 | } |
4456 | 0f8a249a | blueswir1 | break;
|
4457 | 0f8a249a | blueswir1 | default:
|
4458 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4459 | 0f8a249a | blueswir1 | } |
4460 | 0f8a249a | blueswir1 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
4461 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4462 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4463 | 0f8a249a | blueswir1 | switch (xop) {
|
4464 | 1a2fb1c0 | blueswir1 | case 0x4: /* store word */ |
4465 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4466 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4467 | 0f8a249a | blueswir1 | break;
|
4468 | 1a2fb1c0 | blueswir1 | case 0x5: /* store byte */ |
4469 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4470 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4471 | 0f8a249a | blueswir1 | break;
|
4472 | 1a2fb1c0 | blueswir1 | case 0x6: /* store halfword */ |
4473 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4474 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4475 | 0f8a249a | blueswir1 | break;
|
4476 | 1a2fb1c0 | blueswir1 | case 0x7: /* store double word */ |
4477 | 0f8a249a | blueswir1 | if (rd & 1) |
4478 | d4218d99 | blueswir1 | goto illegal_insn;
|
4479 | 1a2fb1c0 | blueswir1 | else {
|
4480 | 2ea815ca | blueswir1 | TCGv r_low, r_const; |
4481 | 1a2fb1c0 | blueswir1 | |
4482 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4483 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4484 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4485 | c2bc0e38 | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4486 | 2ea815ca | blueswir1 | r_const); // XXX remove
|
4487 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4488 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4489 | a7ec4229 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_I32); |
4490 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(r_low, cpu_tmp0); |
4491 | a7ec4229 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_val); |
4492 | a7ec4229 | blueswir1 | tcg_gen_concat_i32_i64(cpu_tmp64, r_low, cpu_tmp32); |
4493 | 2ea815ca | blueswir1 | tcg_temp_free(r_low); |
4494 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4495 | 7fa76c0b | blueswir1 | } |
4496 | 0f8a249a | blueswir1 | break;
|
4497 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4498 | 1a2fb1c0 | blueswir1 | case 0x14: /* store word alternate */ |
4499 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4500 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4501 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4502 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4503 | 0f8a249a | blueswir1 | goto priv_insn;
|
4504 | 3475187d | bellard | #endif
|
4505 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4506 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4507 | d39c0b99 | bellard | break;
|
4508 | 1a2fb1c0 | blueswir1 | case 0x15: /* store byte alternate */ |
4509 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4510 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4511 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4512 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4513 | 0f8a249a | blueswir1 | goto priv_insn;
|
4514 | 3475187d | bellard | #endif
|
4515 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4516 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4517 | d39c0b99 | bellard | break;
|
4518 | 1a2fb1c0 | blueswir1 | case 0x16: /* store halfword alternate */ |
4519 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4520 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4521 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4522 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4523 | 0f8a249a | blueswir1 | goto priv_insn;
|
4524 | 3475187d | bellard | #endif
|
4525 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4526 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4527 | d39c0b99 | bellard | break;
|
4528 | 1a2fb1c0 | blueswir1 | case 0x17: /* store double word alternate */ |
4529 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4530 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4531 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4532 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4533 | 0f8a249a | blueswir1 | goto priv_insn;
|
4534 | 3475187d | bellard | #endif
|
4535 | 0f8a249a | blueswir1 | if (rd & 1) |
4536 | d4218d99 | blueswir1 | goto illegal_insn;
|
4537 | 1a2fb1c0 | blueswir1 | else {
|
4538 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4539 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4540 | 1a2fb1c0 | blueswir1 | } |
4541 | d39c0b99 | bellard | break;
|
4542 | e80cfcfc | bellard | #endif
|
4543 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4544 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4545 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4546 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4547 | 0f8a249a | blueswir1 | break;
|
4548 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4549 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4550 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4551 | 0f8a249a | blueswir1 | break;
|
4552 | 3475187d | bellard | #endif
|
4553 | 0f8a249a | blueswir1 | default:
|
4554 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4555 | 0f8a249a | blueswir1 | } |
4556 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4557 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4558 | a80dde08 | bellard | goto jmp_insn;
|
4559 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4560 | 0f8a249a | blueswir1 | switch (xop) {
|
4561 | ce8536e2 | blueswir1 | case 0x24: /* store fpreg */ |
4562 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4563 | 714547bb | blueswir1 | tcg_gen_qemu_st32(cpu_fpr[rd], cpu_addr, dc->mem_idx); |
4564 | 0f8a249a | blueswir1 | break;
|
4565 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4566 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4567 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4568 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4569 | 3a3b925d | blueswir1 | if (rd == 1) |
4570 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4571 | 3a3b925d | blueswir1 | else {
|
4572 | 3a3b925d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64); |
4573 | 3a3b925d | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4574 | 3a3b925d | blueswir1 | } |
4575 | 3a3b925d | blueswir1 | #else
|
4576 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4577 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4578 | 3a3b925d | blueswir1 | #endif
|
4579 | 0f8a249a | blueswir1 | break;
|
4580 | 1f587329 | blueswir1 | case 0x26: |
4581 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4582 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4583 | 2ea815ca | blueswir1 | { |
4584 | 2ea815ca | blueswir1 | TCGv r_const; |
4585 | 2ea815ca | blueswir1 | |
4586 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4587 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4588 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4589 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); |
4590 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4591 | 2ea815ca | blueswir1 | } |
4592 | 1f587329 | blueswir1 | break;
|
4593 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4594 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4595 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4596 | 1f587329 | blueswir1 | goto illegal_insn;
|
4597 | 1f587329 | blueswir1 | #else
|
4598 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4599 | 0f8a249a | blueswir1 | goto priv_insn;
|
4600 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4601 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4602 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4603 | 0f8a249a | blueswir1 | #endif
|
4604 | 1f587329 | blueswir1 | #endif
|
4605 | 7fa76c0b | blueswir1 | case 0x27: /* store double fpreg */ |
4606 | 2ea815ca | blueswir1 | { |
4607 | 2ea815ca | blueswir1 | TCGv r_const; |
4608 | 2ea815ca | blueswir1 | |
4609 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4610 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4611 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); |
4612 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4613 | 2ea815ca | blueswir1 | } |
4614 | 0f8a249a | blueswir1 | break;
|
4615 | 0f8a249a | blueswir1 | default:
|
4616 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4617 | 0f8a249a | blueswir1 | } |
4618 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4619 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4620 | 0f8a249a | blueswir1 | switch (xop) {
|
4621 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4622 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4623 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4624 | 0f8a249a | blueswir1 | break;
|
4625 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4626 | 2ea815ca | blueswir1 | { |
4627 | 2ea815ca | blueswir1 | TCGv r_const; |
4628 | 2ea815ca | blueswir1 | |
4629 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4630 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4631 | 2ea815ca | blueswir1 | tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
4632 | 2ea815ca | blueswir1 | r_const); |
4633 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4634 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4635 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4636 | 2ea815ca | blueswir1 | } |
4637 | 1f587329 | blueswir1 | break;
|
4638 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4639 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4640 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4641 | 0f8a249a | blueswir1 | break;
|
4642 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4643 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4644 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4645 | 0f8a249a | blueswir1 | break;
|
4646 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4647 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4648 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4649 | 0f8a249a | blueswir1 | break;
|
4650 | a4d17f19 | blueswir1 | #else
|
4651 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4652 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4653 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4654 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4655 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4656 | 0f8a249a | blueswir1 | #endif
|
4657 | 0f8a249a | blueswir1 | default:
|
4658 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4659 | 0f8a249a | blueswir1 | } |
4660 | e8af50a3 | bellard | } |
4661 | 0f8a249a | blueswir1 | else
|
4662 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4663 | 0f8a249a | blueswir1 | } |
4664 | 0f8a249a | blueswir1 | break;
|
4665 | cf495bcf | bellard | } |
4666 | cf495bcf | bellard | /* default case for non jump instructions */
|
4667 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4668 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4669 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4670 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4671 | 72cbca10 | bellard | /* we can do a static jump */
|
4672 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4673 | 72cbca10 | bellard | dc->is_br = 1;
|
4674 | 72cbca10 | bellard | } else {
|
4675 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4676 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4677 | cf495bcf | bellard | } |
4678 | e80cfcfc | bellard | jmp_insn:
|
4679 | cf495bcf | bellard | return;
|
4680 | cf495bcf | bellard | illegal_insn:
|
4681 | 2ea815ca | blueswir1 | { |
4682 | 2ea815ca | blueswir1 | TCGv r_const; |
4683 | 2ea815ca | blueswir1 | |
4684 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4685 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4686 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4687 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4688 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4689 | 2ea815ca | blueswir1 | } |
4690 | e8af50a3 | bellard | return;
|
4691 | 64a88d5d | blueswir1 | unimp_flush:
|
4692 | 2ea815ca | blueswir1 | { |
4693 | 2ea815ca | blueswir1 | TCGv r_const; |
4694 | 2ea815ca | blueswir1 | |
4695 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4696 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4697 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4698 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4699 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4700 | 2ea815ca | blueswir1 | } |
4701 | 64a88d5d | blueswir1 | return;
|
4702 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4703 | e8af50a3 | bellard | priv_insn:
|
4704 | 2ea815ca | blueswir1 | { |
4705 | 2ea815ca | blueswir1 | TCGv r_const; |
4706 | 2ea815ca | blueswir1 | |
4707 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4708 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4709 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4710 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4711 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4712 | 2ea815ca | blueswir1 | } |
4713 | e80cfcfc | bellard | return;
|
4714 | 64a88d5d | blueswir1 | #endif
|
4715 | e80cfcfc | bellard | nfpu_insn:
|
4716 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4717 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4718 | e80cfcfc | bellard | dc->is_br = 1;
|
4719 | fcc72045 | blueswir1 | return;
|
4720 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4721 | 9143e598 | blueswir1 | nfq_insn:
|
4722 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4723 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4724 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4725 | 9143e598 | blueswir1 | return;
|
4726 | 9143e598 | blueswir1 | #endif
|
4727 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4728 | fcc72045 | blueswir1 | ncp_insn:
|
4729 | 2ea815ca | blueswir1 | { |
4730 | 2ea815ca | blueswir1 | TCGv r_const; |
4731 | 2ea815ca | blueswir1 | |
4732 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4733 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4734 | 2ea815ca | blueswir1 | tcg_gen_helper_0_1(raise_exception, r_const); |
4735 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4736 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4737 | 2ea815ca | blueswir1 | } |
4738 | fcc72045 | blueswir1 | return;
|
4739 | fcc72045 | blueswir1 | #endif
|
4740 | 7a3f1944 | bellard | } |
4741 | 7a3f1944 | bellard | |
4742 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4743 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4744 | 7a3f1944 | bellard | { |
4745 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4746 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4747 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4748 | e8af50a3 | bellard | int j, lj = -1; |
4749 | 2e70f6ef | pbrook | int num_insns;
|
4750 | 2e70f6ef | pbrook | int max_insns;
|
4751 | cf495bcf | bellard | |
4752 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4753 | cf495bcf | bellard | dc->tb = tb; |
4754 | 72cbca10 | bellard | pc_start = tb->pc; |
4755 | cf495bcf | bellard | dc->pc = pc_start; |
4756 | e80cfcfc | bellard | last_pc = dc->pc; |
4757 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4758 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4759 | 5578ceab | blueswir1 | dc->def = env->def; |
4760 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4761 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4762 | 5578ceab | blueswir1 | else
|
4763 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4764 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4765 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4766 | 2cade6a3 | blueswir1 | #endif
|
4767 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4768 | cf495bcf | bellard | |
4769 | 1a2fb1c0 | blueswir1 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
4770 | 8911f501 | blueswir1 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4771 | 8911f501 | blueswir1 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
4772 | d987963a | blueswir1 | |
4773 | d987963a | blueswir1 | cpu_dst = tcg_temp_local_new(TCG_TYPE_TL); |
4774 | d987963a | blueswir1 | |
4775 | d987963a | blueswir1 | // loads and stores
|
4776 | 3f0436fe | blueswir1 | cpu_val = tcg_temp_local_new(TCG_TYPE_TL); |
4777 | d987963a | blueswir1 | cpu_addr = tcg_temp_local_new(TCG_TYPE_TL); |
4778 | 1a2fb1c0 | blueswir1 | |
4779 | 2e70f6ef | pbrook | num_insns = 0;
|
4780 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4781 | 2e70f6ef | pbrook | if (max_insns == 0) |
4782 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4783 | 2e70f6ef | pbrook | gen_icount_start(); |
4784 | cf495bcf | bellard | do {
|
4785 | e8af50a3 | bellard | if (env->nb_breakpoints > 0) { |
4786 | e8af50a3 | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
4787 | e8af50a3 | bellard | if (env->breakpoints[j] == dc->pc) {
|
4788 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4789 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4790 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_debug); |
4791 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4792 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4793 | e80cfcfc | bellard | goto exit_gen_loop;
|
4794 | e8af50a3 | bellard | } |
4795 | e8af50a3 | bellard | } |
4796 | e8af50a3 | bellard | } |
4797 | e8af50a3 | bellard | if (spc) {
|
4798 | e8af50a3 | bellard | if (loglevel > 0) |
4799 | e8af50a3 | bellard | fprintf(logfile, "Search PC...\n");
|
4800 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4801 | e8af50a3 | bellard | if (lj < j) {
|
4802 | e8af50a3 | bellard | lj++; |
4803 | e8af50a3 | bellard | while (lj < j)
|
4804 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4805 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4806 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4807 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4808 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4809 | e8af50a3 | bellard | } |
4810 | e8af50a3 | bellard | } |
4811 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4812 | 2e70f6ef | pbrook | gen_io_start(); |
4813 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4814 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4815 | 2e70f6ef | pbrook | num_insns++; |
4816 | 0f8a249a | blueswir1 | |
4817 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4818 | 0f8a249a | blueswir1 | break;
|
4819 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4820 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4821 | 0f8a249a | blueswir1 | break;
|
4822 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4823 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4824 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4825 | d39c0b99 | bellard | break;
|
4826 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4827 | e80cfcfc | bellard | generate an exception */
|
4828 | e80cfcfc | bellard | if (env->singlestep_enabled) {
|
4829 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4830 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4831 | e80cfcfc | bellard | break;
|
4832 | e80cfcfc | bellard | } |
4833 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4834 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4835 | 2e70f6ef | pbrook | num_insns < max_insns); |
4836 | e80cfcfc | bellard | |
4837 | e80cfcfc | bellard | exit_gen_loop:
|
4838 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4839 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4840 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4841 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp64); |
4842 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp32); |
4843 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4844 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4845 | 2e70f6ef | pbrook | gen_io_end(); |
4846 | 72cbca10 | bellard | if (!dc->is_br) {
|
4847 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4848 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4849 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4850 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4851 | 72cbca10 | bellard | } else {
|
4852 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4853 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4854 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4855 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4856 | 72cbca10 | bellard | } |
4857 | 72cbca10 | bellard | } |
4858 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4859 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4860 | e8af50a3 | bellard | if (spc) {
|
4861 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4862 | e8af50a3 | bellard | lj++; |
4863 | e8af50a3 | bellard | while (lj <= j)
|
4864 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4865 | e8af50a3 | bellard | #if 0
|
4866 | e8af50a3 | bellard | if (loglevel > 0) {
|
4867 | e8af50a3 | bellard | page_dump(logfile);
|
4868 | e8af50a3 | bellard | }
|
4869 | e8af50a3 | bellard | #endif
|
4870 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4871 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4872 | e8af50a3 | bellard | } else {
|
4873 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4874 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4875 | e8af50a3 | bellard | } |
4876 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4877 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
4878 | 0f8a249a | blueswir1 | fprintf(logfile, "--------------\n");
|
4879 | 0f8a249a | blueswir1 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
4880 | 0f8a249a | blueswir1 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
4881 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
4882 | cf495bcf | bellard | } |
4883 | 7a3f1944 | bellard | #endif
|
4884 | 7a3f1944 | bellard | } |
4885 | 7a3f1944 | bellard | |
4886 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4887 | 7a3f1944 | bellard | { |
4888 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4889 | 7a3f1944 | bellard | } |
4890 | 7a3f1944 | bellard | |
4891 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4892 | 7a3f1944 | bellard | { |
4893 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4894 | 7a3f1944 | bellard | } |
4895 | 7a3f1944 | bellard | |
4896 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4897 | e80cfcfc | bellard | { |
4898 | f5069b26 | blueswir1 | unsigned int i; |
4899 | c48fcb47 | blueswir1 | static int inited; |
4900 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4901 | f5069b26 | blueswir1 | NULL, // g0 not used |
4902 | f5069b26 | blueswir1 | "g1",
|
4903 | f5069b26 | blueswir1 | "g2",
|
4904 | f5069b26 | blueswir1 | "g3",
|
4905 | f5069b26 | blueswir1 | "g4",
|
4906 | f5069b26 | blueswir1 | "g5",
|
4907 | f5069b26 | blueswir1 | "g6",
|
4908 | f5069b26 | blueswir1 | "g7",
|
4909 | f5069b26 | blueswir1 | }; |
4910 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
4911 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
4912 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
4913 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
4914 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
4915 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
4916 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
4917 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
4918 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
4919 | 714547bb | blueswir1 | }; |
4920 | aaed909a | bellard | |
4921 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4922 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4923 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4924 | 1a2fb1c0 | blueswir1 | |
4925 | 1a2fb1c0 | blueswir1 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
4926 | db4a4ea4 | blueswir1 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4927 | db4a4ea4 | blueswir1 | offsetof(CPUState, regwptr), |
4928 | db4a4ea4 | blueswir1 | "regwptr");
|
4929 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4930 | dc99a3f2 | blueswir1 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4931 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, xcc), |
4932 | dc99a3f2 | blueswir1 | "xcc");
|
4933 | 255e1fcb | blueswir1 | cpu_asi = tcg_global_mem_new(TCG_TYPE_I32, |
4934 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, asi), |
4935 | 255e1fcb | blueswir1 | "asi");
|
4936 | 255e1fcb | blueswir1 | cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32, |
4937 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, fprs), |
4938 | 255e1fcb | blueswir1 | "fprs");
|
4939 | 255e1fcb | blueswir1 | cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL, |
4940 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, gsr), |
4941 | 255e1fcb | blueswir1 | "gsr");
|
4942 | 255e1fcb | blueswir1 | cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
4943 | 255e1fcb | blueswir1 | TCG_AREG0, |
4944 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
4945 | 255e1fcb | blueswir1 | "tick_cmpr");
|
4946 | 255e1fcb | blueswir1 | cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
4947 | 255e1fcb | blueswir1 | TCG_AREG0, |
4948 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
4949 | 255e1fcb | blueswir1 | "stick_cmpr");
|
4950 | 255e1fcb | blueswir1 | cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
4951 | 255e1fcb | blueswir1 | TCG_AREG0, |
4952 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
4953 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
4954 | 255e1fcb | blueswir1 | cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4955 | 255e1fcb | blueswir1 | offsetof(CPUState, hintp), |
4956 | 255e1fcb | blueswir1 | "hintp");
|
4957 | 255e1fcb | blueswir1 | cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4958 | 255e1fcb | blueswir1 | offsetof(CPUState, htba), |
4959 | 255e1fcb | blueswir1 | "htba");
|
4960 | 255e1fcb | blueswir1 | cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4961 | 255e1fcb | blueswir1 | offsetof(CPUState, hver), |
4962 | 255e1fcb | blueswir1 | "hver");
|
4963 | 255e1fcb | blueswir1 | cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4964 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
4965 | 255e1fcb | blueswir1 | cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4966 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
4967 | 255e1fcb | blueswir1 | #else
|
4968 | 255e1fcb | blueswir1 | cpu_wim = tcg_global_mem_new(TCG_TYPE_I32, |
4969 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, wim), |
4970 | 255e1fcb | blueswir1 | "wim");
|
4971 | 1a2fb1c0 | blueswir1 | #endif
|
4972 | 7c60cc4b | bellard | cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
4973 | 77f193da | blueswir1 | TCG_AREG0, offsetof(CPUState, cond), |
4974 | 77f193da | blueswir1 | "cond");
|
4975 | dc99a3f2 | blueswir1 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4976 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_src), |
4977 | dc99a3f2 | blueswir1 | "cc_src");
|
4978 | d9bdab86 | blueswir1 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4979 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4980 | d9bdab86 | blueswir1 | "cc_src2");
|
4981 | dc99a3f2 | blueswir1 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4982 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_dst), |
4983 | dc99a3f2 | blueswir1 | "cc_dst");
|
4984 | dc99a3f2 | blueswir1 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
4985 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, psr), |
4986 | dc99a3f2 | blueswir1 | "psr");
|
4987 | 87e92502 | blueswir1 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4988 | 87e92502 | blueswir1 | TCG_AREG0, offsetof(CPUState, fsr), |
4989 | 87e92502 | blueswir1 | "fsr");
|
4990 | 48d5c82b | blueswir1 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4991 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, pc), |
4992 | 48d5c82b | blueswir1 | "pc");
|
4993 | 48d5c82b | blueswir1 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, |
4994 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, npc), |
4995 | 48d5c82b | blueswir1 | "npc");
|
4996 | 255e1fcb | blueswir1 | cpu_y = tcg_global_mem_new(TCG_TYPE_TL, |
4997 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, y), "y");
|
4998 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
4999 | 255e1fcb | blueswir1 | cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL, |
5000 | 255e1fcb | blueswir1 | TCG_AREG0, offsetof(CPUState, tbr), |
5001 | 255e1fcb | blueswir1 | "tbr");
|
5002 | 255e1fcb | blueswir1 | #endif
|
5003 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
5004 | f5069b26 | blueswir1 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
5005 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
5006 | f5069b26 | blueswir1 | gregnames[i]); |
5007 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
5008 | 714547bb | blueswir1 | cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
5009 | 714547bb | blueswir1 | offsetof(CPUState, fpr[i]), |
5010 | 714547bb | blueswir1 | fregnames[i]); |
5011 | 714547bb | blueswir1 | |
5012 | c9e03d8f | blueswir1 | /* register helpers */
|
5013 | c9e03d8f | blueswir1 | |
5014 | c9e03d8f | blueswir1 | #undef DEF_HELPER
|
5015 | c9e03d8f | blueswir1 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
5016 | c9e03d8f | blueswir1 | #include "helper.h" |
5017 | 1a2fb1c0 | blueswir1 | } |
5018 | 658138bc | bellard | } |
5019 | d2856f1a | aurel32 | |
5020 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
5021 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
5022 | d2856f1a | aurel32 | { |
5023 | d2856f1a | aurel32 | target_ulong npc; |
5024 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
5025 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
5026 | d2856f1a | aurel32 | if (npc == 1) { |
5027 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
5028 | d2856f1a | aurel32 | } else if (npc == 2) { |
5029 | d2856f1a | aurel32 | target_ulong t2 = (target_ulong)(unsigned long)puc; |
5030 | d2856f1a | aurel32 | /* jump PC: use T2 and the jump targets of the translation */
|
5031 | d2856f1a | aurel32 | if (t2)
|
5032 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
5033 | d2856f1a | aurel32 | else
|
5034 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
5035 | d2856f1a | aurel32 | } else {
|
5036 | d2856f1a | aurel32 | env->npc = npc; |
5037 | d2856f1a | aurel32 | } |
5038 | d2856f1a | aurel32 | } |