Revision a815b166
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 1956 | 1956 |
* |
| 1957 | 1957 |
***************************************/ |
| 1958 | 1958 |
|
| 1959 |
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) |
|
| 1959 |
static uint64_t cirrus_vga_mem_read(void *opaque, |
|
| 1960 |
target_phys_addr_t addr, |
|
| 1961 |
uint32_t size) |
|
| 1960 | 1962 |
{
|
| 1961 | 1963 |
CirrusVGAState *s = opaque; |
| 1962 | 1964 |
unsigned bank_index; |
| ... | ... | |
| 1967 | 1969 |
return vga_mem_readb(s, addr); |
| 1968 | 1970 |
} |
| 1969 | 1971 |
|
| 1970 |
addr &= 0x1ffff; |
|
| 1971 |
|
|
| 1972 | 1972 |
if (addr < 0x10000) {
|
| 1973 | 1973 |
/* XXX handle bitblt */ |
| 1974 | 1974 |
/* video memory */ |
| ... | ... | |
| 2000 | 2000 |
return val; |
| 2001 | 2001 |
} |
| 2002 | 2002 |
|
| 2003 |
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
|
| 2004 |
{
|
|
| 2005 |
uint32_t v; |
|
| 2006 |
|
|
| 2007 |
v = cirrus_vga_mem_readb(opaque, addr); |
|
| 2008 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
|
| 2009 |
return v; |
|
| 2010 |
} |
|
| 2011 |
|
|
| 2012 |
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
|
| 2013 |
{
|
|
| 2014 |
uint32_t v; |
|
| 2015 |
|
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| 2016 |
v = cirrus_vga_mem_readb(opaque, addr); |
|
| 2017 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
|
| 2018 |
v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
|
| 2019 |
v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
|
| 2020 |
return v; |
|
| 2021 |
} |
|
| 2022 |
|
|
| 2023 |
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
|
| 2024 |
uint32_t mem_value) |
|
| 2003 |
static void cirrus_vga_mem_write(void *opaque, |
|
| 2004 |
target_phys_addr_t addr, |
|
| 2005 |
uint64_t mem_value, |
|
| 2006 |
uint32_t size) |
|
| 2025 | 2007 |
{
|
| 2026 | 2008 |
CirrusVGAState *s = opaque; |
| 2027 | 2009 |
unsigned bank_index; |
| ... | ... | |
| 2033 | 2015 |
return; |
| 2034 | 2016 |
} |
| 2035 | 2017 |
|
| 2036 |
addr &= 0x1ffff; |
|
| 2037 |
|
|
| 2038 | 2018 |
if (addr < 0x10000) {
|
| 2039 | 2019 |
if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
| 2040 | 2020 |
/* bitblt */ |
| ... | ... | |
| 2084 | 2064 |
} |
| 2085 | 2065 |
} |
| 2086 | 2066 |
|
| 2087 |
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
|
| 2088 |
{
|
|
| 2089 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff); |
|
| 2090 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
|
| 2091 |
} |
|
| 2092 |
|
|
| 2093 |
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
|
| 2094 |
{
|
|
| 2095 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff); |
|
| 2096 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
|
| 2097 |
cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
|
| 2098 |
cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
|
| 2099 |
} |
|
| 2100 |
|
|
| 2101 |
static uint64_t cirrus_vga_mem_read(void *opaque, |
|
| 2102 |
target_phys_addr_t addr, |
|
| 2103 |
uint32_t size) |
|
| 2104 |
{
|
|
| 2105 |
CirrusVGAState *s = opaque; |
|
| 2106 |
|
|
| 2107 |
switch (size) {
|
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| 2108 |
case 1: return cirrus_vga_mem_readb(s, addr); |
|
| 2109 |
case 2: return cirrus_vga_mem_readw(s, addr); |
|
| 2110 |
case 4: return cirrus_vga_mem_readl(s, addr); |
|
| 2111 |
default: abort(); |
|
| 2112 |
} |
|
| 2113 |
} |
|
| 2114 |
|
|
| 2115 |
static void cirrus_vga_mem_write(void *opaque, target_phys_addr_t addr, |
|
| 2116 |
uint64_t data, unsigned size) |
|
| 2117 |
{
|
|
| 2118 |
CirrusVGAState *s = opaque; |
|
| 2119 |
|
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| 2120 |
switch (size) {
|
|
| 2121 |
case 1: return cirrus_vga_mem_writeb(s, addr, data); |
|
| 2122 |
case 2: return cirrus_vga_mem_writew(s, addr, data); |
|
| 2123 |
case 4: return cirrus_vga_mem_writel(s, addr, data); |
|
| 2124 |
default: abort(); |
|
| 2125 |
} |
|
| 2126 |
}; |
|
| 2127 |
|
|
| 2128 | 2067 |
static const MemoryRegionOps cirrus_vga_mem_ops = {
|
| 2129 | 2068 |
.read = cirrus_vga_mem_read, |
| 2130 | 2069 |
.write = cirrus_vga_mem_write, |
| 2131 | 2070 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2071 |
.impl = {
|
|
| 2072 |
.min_access_size = 1, |
|
| 2073 |
.max_access_size = 1, |
|
| 2074 |
}, |
|
| 2132 | 2075 |
}; |
| 2133 | 2076 |
|
| 2134 | 2077 |
/*************************************** |
Also available in: Unified diff