Archipelago » qemu

Don't use Linux kernel internal types like u32, __u32 or __le32.

for PCI addresses.  In addition, ram_addr_t is a QEMU internal address

space that maps guest RAM physical addresses into an intermediate

address space that can map to host virtual address spaces.  Generally

/* Return the physical page corresponding to a virtual one. Use it

   only for debugging because no protection checks are done. Return -1

   if no page found. */

/* memory API */

/* CPU interfaces that are target independent.  */

#ifndef NEED_CPU_H

#include "poison.h"

/* memory API */

void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);

/* This should only be used for ram local to a device.  */

ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);

void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);

                            int len, int is_write);

                                            void *buf, int len)

{

    cpu_physical_memory_rw(addr, buf, len, 0);

}

                                             const void *buf, int len)

{

    cpu_physical_memory_rw(addr, (void *)buf, len, 1);

}

                              int is_write);

void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));

void cpu_unregister_map_client(void *cookie);

/* Coalesced MMIO regions are areas where write operations can be reordered.

 * This usually implies that write operations are side-effect free.  This allows

 */

void qemu_flush_coalesced_mmio_buffer(void);

#ifdef NEED_CPU_H

#endif

                                   const uint8_t *buf, int len);

extern struct MemoryRegion io_mem_ram;

#include <signal.h>

#include "osdep.h"

#include "qemu-queue.h"

#ifndef TARGET_LONG_BITS

#error TARGET_LONG_BITS must be defined before including this header

#define CPU_COMMON_TLB \

    /* The meaning of the MMU modes is defined in the target code. */   \

    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \

    target_ulong tlb_flush_addr;                                        \

    target_ulong tlb_flush_mask;

   is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the

   supplied size is only used by tlb_flush_page.  */

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  int mmu_idx, target_ulong size)

{

    MemoryRegionSection *section;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,

                           uintptr_t length);

MemoryRegionSection *phys_page_find(struct AddressSpaceDispatch *d,

void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);

void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);

extern int tlb_flush_count;

/* exec.c */

void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);

                                                   MemoryRegionSection *section,

                                                   target_ulong vaddr,

                                                   int prot,

                                                   target_ulong *address);

bool memory_region_is_unassigned(MemoryRegion *mr);

#if defined(CONFIG_USER_ONLY)

typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);

#else

#endif

struct syminfo {

bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,

                            DMADirection dir)

{

#ifdef DEBUG_IOMMU

    fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT

int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,

                        void *buf, dma_addr_t len, DMADirection dir)

{

    int err;

#ifdef DEBUG_IOMMU

int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,

                         dma_addr_t len)

{

    int err;

#ifdef DEBUG_IOMMU

                           DMADirection dir)

{

    int err;

    void *buf;

    if (dma->map) {

typedef int DMATranslateFunc(DMAContext *dma,

                             dma_addr_t addr,

                             DMADirection dir);

typedef void* DMAMapFunc(DMAContext *dma,

                         dma_addr_t addr,

                                   DMADirection dir)

{

    if (!dma_has_iommu(dma)) {

        void *p;

        p = address_space_map(dma->as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);

                                    DMADirection dir, dma_addr_t access_len)

{

    if (!dma_has_iommu(dma)) {

                            dir == DMA_DIRECTION_FROM_DEVICE, access_len);

    } else {

        iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);

#include "elf.h"

#include "cpu.h"

#include "cpu-all.h"

#include "monitor.h"

#include "kvm.h"

#include "dump.h"

    bool have_section;

    bool resume;

    size_t note_size;

    int fd;

    RAMBlock *block;

}

static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,

{

    Elf64_Phdr phdr;

    int ret;

}

static int write_elf32_load(DumpState *s, MemoryMapping *memory_mapping,

{

    Elf32_Phdr phdr;

    int ret;

{

    Elf64_Phdr phdr;

    int endian = s->dump_info.d_endian;

    int ret;

    memset(&phdr, 0, sizeof(Elf64_Phdr));

static int write_elf32_note(DumpState *s)

{

    Elf32_Phdr phdr;

    int endian = s->dump_info.d_endian;

    int ret;

}

/* get the memory's offset in the vmcore */

                                     DumpState *s)

{

    RAMBlock *block;

    int64_t size_in_block, start;

    if (s->has_filter) {

static int write_elf_loads(DumpState *s)

{

    MemoryMapping *memory_mapping;

    uint32_t phdr_index = 1;

    int ret;

void tlb_flush_page(CPUArchState *env, target_ulong addr);

void tlb_flush(CPUArchState *env, int flush_global);

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  int mmu_idx, target_ulong size);

#else

static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)

{

#if !defined(CONFIG_USER_ONLY)

                     unsigned size);

                  uint64_t value, unsigned size);

void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,

}

                                int level)

{

    PhysPageEntry *p;

    int i;

    if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {

        lp->ptr = phys_map_node_alloc();

}

static void phys_page_set(AddressSpaceDispatch *d,

                          uint16_t leaf)

{

    /* Wildly overreserve - it doesn't matter much. */

    phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);

}

{

    PhysPageEntry lp = d->phys_map;

    PhysPageEntry *p;

    tb_invalidate_phys_page_range(pc, pc + 1, 0);

}

#else

{

    ram_addr_t ram_addr;

    MemoryRegionSection *section;

    return ret;

}

                                                   MemoryRegionSection *section,

                                                   target_ulong vaddr,

                                                   int prot,

                                                   target_ulong *address)

{

    CPUWatchpoint *wp;

    if (memory_region_is_ram(section->mr)) {

#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)

typedef struct subpage_t {

    MemoryRegion iomem;

    uint16_t sub_section[TARGET_PAGE_SIZE];

} subpage_t;

static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,

                             uint16_t section);

static void destroy_page_desc(uint16_t section_index)

{

    MemoryRegionSection *section = &phys_sections[section_index];

static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)

{

    subpage_t *subpage;

        & TARGET_PAGE_MASK;

    MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);

    MemoryRegionSection subsection = {

        .offset_within_address_space = base,

        .size = TARGET_PAGE_SIZE,

    };

    assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);

static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)

{

    ram_addr_t size = section->size;

    uint16_t section_index = phys_section_add(section);

    assert(size);

    return ram_addr;

}

                                    unsigned size)

{

#ifdef DEBUG_UNASSIGNED

    return 0;

}

                                 uint64_t val, unsigned size)

{

#ifdef DEBUG_UNASSIGNED

    .endianness = DEVICE_NATIVE_ENDIAN,

};

                               unsigned size)

{

    abort();

}

                            uint64_t value, unsigned size)

{

    abort();

    .endianness = DEVICE_NATIVE_ENDIAN,

};

                               uint64_t val, unsigned size)

{

    int dirty_flags;

/* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,

   so these check for a hit then pass through to the normal out-of-line

   phys routines.  */

                               unsigned size)

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);

    }

}

                            uint64_t val, unsigned size)

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);

    .endianness = DEVICE_NATIVE_ENDIAN,

};

                             unsigned len)

{

    subpage_t *mmio = opaque;

    return io_mem_read(section->mr, addr, len);

}

                          uint64_t value, unsigned len)

{

    subpage_t *mmio = opaque;

    .endianness = DEVICE_NATIVE_ENDIAN,

};

                                 unsigned size)

{

    ram_addr_t raddr = addr;

    }

}

                              uint64_t value, unsigned size)

{

    ram_addr_t raddr = addr;

    return 0;

}

{

    subpage_t *mmio;

    return phys_section_add(&section);

}

{

    return phys_sections[index & ~TARGET_PAGE_MASK].mr;

}

#else

{

    if (!cpu_physical_memory_is_dirty(addr)) {

        /* invalidate code */

    xen_modified_memory(addr, length);

}

                      int len, bool is_write)

{

    AddressSpaceDispatch *d = as->dispatch;

    int l;

    uint8_t *ptr;

    uint32_t val;

    MemoryRegionSection *section;

    while (len > 0) {

        if (is_write) {

            if (!memory_region_is_ram(section->mr)) {

                addr1 = memory_region_section_addr(section, addr);

                /* XXX: could force cpu_single_env to NULL to avoid

                   potential bugs */

        } else {

            if (!(memory_region_is_ram(section->mr) ||

                  memory_region_is_romd(section->mr))) {

                /* I/O case */

                addr1 = memory_region_section_addr(section, addr);

                if (l >= 4 && ((addr1 & 3) == 0)) {

    }

}

                         const uint8_t *buf, int len)

{

    address_space_rw(as, addr, (uint8_t *)buf, len, true);

 * @addr: address within that address space

 * @buf: buffer with the data transferred

 */

{

    address_space_rw(as, addr, buf, len, false);

}

                            int len, int is_write)

{

    return address_space_rw(&address_space_memory, addr, buf, len, is_write);

}

/* used for ROM loading : can write in RAM and ROM */

                                   const uint8_t *buf, int len)

{

    AddressSpaceDispatch *d = address_space_memory.dispatch;

    int l;

    uint8_t *ptr;

    MemoryRegionSection *section;

    while (len > 0) {

typedef struct {

    void *buffer;

} BounceBuffer;

static BounceBuffer bounce;

 * likely to succeed.

 */

void *address_space_map(AddressSpace *as,

                        bool is_write)

{

    AddressSpaceDispatch *d = as->dispatch;

    int l;

    MemoryRegionSection *section;

    ram_addr_t raddr = RAM_ADDR_MAX;

    ram_addr_t rlen;

 * Will also mark the memory as dirty if is_write == 1.  access_len gives

 * the amount of memory that was actually read or written by the caller.

 */

{

    if (buffer != bounce.buffer) {

        if (is_write) {

    cpu_notify_map_clients();

}

                              int is_write)

{

    return address_space_map(&address_space_memory, addr, plen, is_write);

}

{

    return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);

}

/* warning: addr must be aligned */

                                         enum device_endian endian)

{

    uint8_t *ptr;

    return val;

}

{

    return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);

}

{

    return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);

}

{

    return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);

}

/* warning: addr must be aligned */

                                         enum device_endian endian)

{

    uint8_t *ptr;

    return val;

}

{

    return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);

}

{

    return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);

}

{

    return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);

}

/* XXX: optimize */

{

    uint8_t val;

    cpu_physical_memory_read(addr, &val, 1);

}

/* warning: addr must be aligned */

                                          enum device_endian endian)

{

    uint8_t *ptr;

    return val;

}

{

    return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);

}

{

    return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);

}

{

    return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);

}

/* warning: addr must be aligned. The ram page is not masked as dirty

   and the code inside is not invalidated. It is useful if the dirty

   bits are used to track modified PTEs */

{

    uint8_t *ptr;

    MemoryRegionSection *section;

    }

}

{

    uint8_t *ptr;

    MemoryRegionSection *section;

}

/* warning: addr must be aligned */

                                     enum device_endian endian)

{

    uint8_t *ptr;

    }

}

{

    stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);

}

{

    stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);

}

{

    stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);

}

/* XXX: optimize */

{

    uint8_t v = val;

    cpu_physical_memory_write(addr, &v, 1);

}

/* warning: addr must be aligned */

                                     enum device_endian endian)

{

    uint8_t *ptr;

    }

}

{

    stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);

}

{

    stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);

}

{

    stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);

}

/* XXX: optimize */

{

    val = tswap64(val);

    cpu_physical_memory_write(addr, &val, 8);

}

{

    val = cpu_to_le64(val);

    cpu_physical_memory_write(addr, &val, 8);

}

{

    val = cpu_to_be64(val);

    cpu_physical_memory_write(addr, &val, 8);

                        uint8_t *buf, int len, int is_write)

{

    int l;

    target_ulong page;

    while (len > 0) {

#endif

#ifndef CONFIG_USER_ONLY

{

    MemoryRegionSection *section;

    uint32_t num_irq;

} a9mp_priv_state;

                            unsigned size)

{

    a9mp_priv_state *s = (a9mp_priv_state *)opaque;

    }

}

                         uint64_t value, unsigned size)

{

    a9mp_priv_state *s = (a9mp_priv_state *)opaque;

/* PCI IO reads/writes, to byte-word addressable memory.  */

/* ??? Doesn't handle multiple PCI busses.  */

{

    switch (size) {

    case 1:

    abort();

}

                        uint64_t val, unsigned size)

{

    switch (size) {

};

/* PCI config space reads/writes, to byte-word addressable memory.  */

                              unsigned size)

{

    PCIBus *b = opaque;

    return pci_data_read(b, addr, size);

}

                           uint64_t val, unsigned size)

{

    PCIBus *b = opaque;

/* PCI/EISA Interrupt Acknowledge Cycle.  */

{

    return pic_read_irq(isa_pic);

}

                          uint64_t val, unsigned size)

{

    qemu_log("pci: special write cycle");

    }

}

{

    CPUAlphaState *env = cpu_single_env;

    TyphoonState *s = opaque;

    return ret;

}

{

    /* Skip this.  It's all related to DRAM timing and setup.  */

    return 0;

}

{

    TyphoonState *s = opaque;

    uint64_t ret = 0;

    return ret;

}

                        uint64_t v32, unsigned size)

{

    TyphoonState *s = opaque;

    }

}

                        uint64_t val, unsigned size)

{

    /* Skip this.  It's all related to DRAM timing and setup.  */

}

                        uint64_t v32, unsigned size)

{

    TyphoonState *s = opaque;

    CPUM68KState *env;

    int kernel_size;

    uint64_t elf_entry;

    MemoryRegion *address_space_mem = get_system_memory();

    MemoryRegion *ram = g_new(MemoryRegion, 1);

    MemoryRegion *sram = g_new(MemoryRegion, 1);

static void pci_apb_set_irq(void *opaque, int irq_num, int level);

                               uint64_t val, unsigned size)

{

    APBState *s = opaque;

}

static uint64_t apb_config_readl (void *opaque,

{

    APBState *s = opaque;

    uint32_t val;

    .endianness = DEVICE_NATIVE_ENDIAN,

};

                                 uint64_t val, unsigned size)

{

    APBState *s = opaque;

    pci_data_write(s->bus, addr, val, size);

}

                                    unsigned size)

{

    uint32_t ret;

    return ret;

}

                                  uint32_t val)

{

    cpu_outb(addr & IOPORTS_MASK, val);

}

                                  uint32_t val)

{

    cpu_outw(addr & IOPORTS_MASK, bswap16(val));

}

                                uint32_t val)

{

    cpu_outl(addr & IOPORTS_MASK, bswap32(val));

}

{

    uint32_t val;

    return val;

}

{

    uint32_t val;

    return val;

}

{

    uint32_t val;

    return 0;

}

                     qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,

                     qemu_irq **pbm_irqs)

{

#include "qemu-common.h"

                     qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,

                     qemu_irq **pbm_irqs);

#endif

    apic_timer_update(s, s->next_time);

}

{

    return 0;

}

{

    return 0;

}

{

}

{

}

{

    DeviceState *d;

    APICCommonState *s;

    return val;

}

{

    uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;

    uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;

    apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);

}

{

    DeviceState *d;

    APICCommonState *s;

    }

}

{

    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);

    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);

    uint32_t vapic_control;

    DeviceState *vapic;

};

typedef struct VAPICState {

void apic_report_irq_delivered(int delivered);

bool apic_next_timer(APICCommonState *s, int64_t current_time);

void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);

void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,

                             TPRAccess access);

    const char *kernel_cmdline;

    const char *initrd_filename;

    const char *dtb_filename;

    /* multicore boards that use the default secondary core boot functions

     * need to put the address of the secondary boot code, the boot reg,

     * and the GIC address in the next 3 values, respectively. boards that

     * have their own boot functions can use these values as they want.

     */

    int nb_cpus;

    int board_id;

    int (*atag_board)(const struct arm_boot_info *info, void *p);

                                     const struct arm_boot_info *info);

    /* Used internally by arm_boot.c */

    int is_linux;

};

void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);

/* Per-CPU private memory mapped IO.  */

                                unsigned size)

{

    mpcore_priv_state *s = (mpcore_priv_state *)opaque;

    }

}

                             uint64_t value, unsigned size)

{

    mpcore_priv_state *s = (mpcore_priv_state *)opaque;

     * at 0x200, 0x300...

     */

    for (i = 0; i < (s->num_cpu + 1); i++) {

        memory_region_add_subregion(&s->container, offset,

                                    sysbus_mmio_get_region(gicbusdev, i + 1));

    }

     */

    for (i = 0; i < (s->num_cpu + 1) * 2; i++) {

        /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */

        memory_region_add_subregion(&s->container, offset,

                                    sysbus_mmio_get_region(busdev, i));

    }

static void set_kernel_args(const struct arm_boot_info *info)

{

    int initrd_size = info->initrd_size;

    p = base + KERNEL_ARGS_ADDR;

    /* ATAG_CORE */

static void set_kernel_args_old(const struct arm_boot_info *info)

{

    const char *s;

    int initrd_size = info->initrd_size;

    /* see linux/include/asm-arm/setup.h */

    p = base + KERNEL_ARGS_ADDR;

    }

}

{

#ifdef CONFIG_FDT

    uint32_t *mem_reg_property;

    int n;

    int is_linux = 0;

    uint64_t elf_entry;

    int big_endian;

    QemuOpts *machine_opts;

         */

        if (info->dtb_filename) {

            /* Place the DTB after the initrd in memory */

                                                             + INITRD_LOAD_ADDR

                                                             + initrd_size);

            if (load_dtb(dtb_start, info)) {

    }

}