Revision a8170e5e hw/integratorcp.c
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
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static uint64_t integratorcm_read(void *opaque, hwaddr offset,
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unsigned size) |
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
| ... | ... | |
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hw_error("Core module interrupt\n");
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} |
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static void integratorcm_write(void *opaque, target_phys_addr_t offset,
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static void integratorcm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size) |
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
| ... | ... | |
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icp_pic_update(s); |
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} |
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static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
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static uint64_t icp_pic_read(void *opaque, hwaddr offset,
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unsigned size) |
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
| ... | ... | |
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} |
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} |
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static void icp_pic_write(void *opaque, target_phys_addr_t offset,
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static void icp_pic_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size) |
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
| ... | ... | |
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/* CP control registers. */ |
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static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
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static uint64_t icp_control_read(void *opaque, hwaddr offset,
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unsigned size) |
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{
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switch (offset >> 2) {
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} |
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} |
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static void icp_control_write(void *opaque, target_phys_addr_t offset,
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static void icp_control_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size) |
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{
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switch (offset >> 2) {
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static void icp_control_init(target_phys_addr_t base)
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static void icp_control_init(hwaddr base)
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{
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MemoryRegion *io; |
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