Revision a8170e5e hw/pflash_cfi01.c
| b/hw/pflash_cfi01.c | ||
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| 61 | 61 |
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| 62 | 62 |
struct pflash_t {
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| 63 | 63 |
BlockDriverState *bs; |
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target_phys_addr_t base;
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target_phys_addr_t sector_len;
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target_phys_addr_t total_len;
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hwaddr base;
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hwaddr sector_len;
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hwaddr total_len;
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| 67 | 67 |
int width; |
| 68 | 68 |
int wcycle; /* if 0, the flash is read normally */ |
| 69 | 69 |
int bypass; |
| ... | ... | |
| 73 | 73 |
uint16_t ident[4]; |
| 74 | 74 |
uint8_t cfi_len; |
| 75 | 75 |
uint8_t cfi_table[0x52]; |
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target_phys_addr_t counter;
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hwaddr counter;
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| 77 | 77 |
unsigned int writeblock_size; |
| 78 | 78 |
QEMUTimer *timer; |
| 79 | 79 |
MemoryRegion mem; |
| ... | ... | |
| 96 | 96 |
pfl->cmd = 0; |
| 97 | 97 |
} |
| 98 | 98 |
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
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int width, int be) |
| 101 | 101 |
{
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target_phys_addr_t boff;
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hwaddr boff;
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uint32_t ret; |
| 104 | 104 |
uint8_t *p; |
| 105 | 105 |
|
| ... | ... | |
| 211 | 211 |
} |
| 212 | 212 |
} |
| 213 | 213 |
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static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
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static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
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uint32_t value, int width, int be) |
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{
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uint8_t *p = pfl->storage; |
| ... | ... | |
| 249 | 249 |
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| 250 | 250 |
} |
| 251 | 251 |
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static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
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static void pflash_write(pflash_t *pfl, hwaddr offset,
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uint32_t value, int width, int be) |
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{
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uint8_t *p; |
| ... | ... | |
| 389 | 389 |
pfl->status |= 0x80; |
| 390 | 390 |
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if (!pfl->counter) {
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target_phys_addr_t mask = pfl->writeblock_size - 1;
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hwaddr mask = pfl->writeblock_size - 1;
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mask = ~mask; |
| 394 | 394 |
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DPRINTF("%s: block write finished\n", __func__);
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| ... | ... | |
| 445 | 445 |
} |
| 446 | 446 |
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static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
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{
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return pflash_read(opaque, addr, 1, 1); |
| 451 | 451 |
} |
| 452 | 452 |
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static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
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{
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return pflash_read(opaque, addr, 1, 0); |
| 456 | 456 |
} |
| 457 | 457 |
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static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
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{
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pflash_t *pfl = opaque; |
| 461 | 461 |
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return pflash_read(pfl, addr, 2, 1); |
| 463 | 463 |
} |
| 464 | 464 |
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static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
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{
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pflash_t *pfl = opaque; |
| 468 | 468 |
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return pflash_read(pfl, addr, 2, 0); |
| 470 | 470 |
} |
| 471 | 471 |
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static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
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{
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pflash_t *pfl = opaque; |
| 475 | 475 |
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return pflash_read(pfl, addr, 4, 1); |
| 477 | 477 |
} |
| 478 | 478 |
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static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
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static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
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{
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pflash_t *pfl = opaque; |
| 482 | 482 |
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return pflash_read(pfl, addr, 4, 0); |
| 484 | 484 |
} |
| 485 | 485 |
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static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
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static void pflash_writeb_be(void *opaque, hwaddr addr,
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uint32_t value) |
| 488 | 488 |
{
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pflash_write(opaque, addr, value, 1, 1); |
| 490 | 490 |
} |
| 491 | 491 |
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static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
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static void pflash_writeb_le(void *opaque, hwaddr addr,
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uint32_t value) |
| 494 | 494 |
{
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pflash_write(opaque, addr, value, 1, 0); |
| 496 | 496 |
} |
| 497 | 497 |
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static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
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static void pflash_writew_be(void *opaque, hwaddr addr,
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uint32_t value) |
| 500 | 500 |
{
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pflash_t *pfl = opaque; |
| ... | ... | |
| 503 | 503 |
pflash_write(pfl, addr, value, 2, 1); |
| 504 | 504 |
} |
| 505 | 505 |
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static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
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static void pflash_writew_le(void *opaque, hwaddr addr,
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uint32_t value) |
| 508 | 508 |
{
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pflash_t *pfl = opaque; |
| ... | ... | |
| 511 | 511 |
pflash_write(pfl, addr, value, 2, 0); |
| 512 | 512 |
} |
| 513 | 513 |
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static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
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static void pflash_writel_be(void *opaque, hwaddr addr,
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uint32_t value) |
| 516 | 516 |
{
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pflash_t *pfl = opaque; |
| ... | ... | |
| 519 | 519 |
pflash_write(pfl, addr, value, 4, 1); |
| 520 | 520 |
} |
| 521 | 521 |
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static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
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static void pflash_writel_le(void *opaque, hwaddr addr,
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| 523 | 523 |
uint32_t value) |
| 524 | 524 |
{
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pflash_t *pfl = opaque; |
| ... | ... | |
| 543 | 543 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 544 | 544 |
}; |
| 545 | 545 |
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pflash_t *pflash_cfi01_register(target_phys_addr_t base,
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pflash_t *pflash_cfi01_register(hwaddr base,
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| 547 | 547 |
DeviceState *qdev, const char *name, |
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target_phys_addr_t size,
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hwaddr size,
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| 549 | 549 |
BlockDriverState *bs, uint32_t sector_len, |
| 550 | 550 |
int nb_blocs, int width, |
| 551 | 551 |
uint16_t id0, uint16_t id1, |
| 552 | 552 |
uint16_t id2, uint16_t id3, int be) |
| 553 | 553 |
{
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| 554 | 554 |
pflash_t *pfl; |
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target_phys_addr_t total_len;
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hwaddr total_len;
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| 556 | 556 |
int ret; |
| 557 | 557 |
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total_len = sector_len * nb_blocs; |
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