Revision a8170e5e hw/sun4m_iommu.c
| b/hw/sun4m_iommu.c | ||
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| 130 | 130 |
SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t regs[IOMMU_NREGS]; |
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target_phys_addr_t iostart;
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hwaddr iostart;
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qemu_irq irq; |
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uint32_t version; |
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} IOMMUState; |
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static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
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static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
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unsigned size) |
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{
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IOMMUState *s = opaque; |
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target_phys_addr_t saddr;
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hwaddr saddr;
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uint32_t ret; |
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saddr = addr >> 2; |
| ... | ... | |
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return ret; |
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} |
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static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
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static void iommu_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size) |
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{
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IOMMUState *s = opaque; |
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target_phys_addr_t saddr;
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hwaddr saddr;
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saddr = addr >> 2; |
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trace_sun4m_iommu_mem_writel(saddr, val); |
| ... | ... | |
| 249 | 249 |
}, |
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}; |
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static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
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static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
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{
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uint32_t ret; |
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target_phys_addr_t iopte;
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target_phys_addr_t pa = addr;
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hwaddr iopte;
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hwaddr pa = addr;
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iopte = s->regs[IOMMU_BASE] << 4; |
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addr &= ~s->iostart; |
| ... | ... | |
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return ret; |
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} |
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static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
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static hwaddr iommu_translate_pa(hwaddr addr,
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uint32_t pte) |
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{
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target_phys_addr_t pa;
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hwaddr pa;
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pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
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trace_sun4m_iommu_translate_pa(addr, pa, pte); |
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return pa; |
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} |
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static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
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static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
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int is_write) |
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{
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trace_sun4m_iommu_bad_addr(addr); |
| ... | ... | |
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qemu_irq_raise(s->irq); |
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} |
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
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uint8_t *buf, int len, int is_write) |
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{
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int l; |
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uint32_t flags; |
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target_phys_addr_t page, phys_addr;
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hwaddr page, phys_addr;
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| 295 | 295 |
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while (len > 0) {
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page = addr & IOMMU_PAGE_MASK; |
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