Archipelago » qemu

/*

 *  CRIS emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2008 AXIS Communications AB

 *  Written by Edgar E. Iglesias.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <assert.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "helper.h"

#include "crisv32-decode.h"

#define CRIS_STATS 0

#if CRIS_STATS

#define STATS(x) x

#else

#define STATS(x)

#endif

#define DISAS_CRIS 0

#if DISAS_CRIS

#define DIS(x) x

#else

#define DIS(x)

#endif

#define BUG() (gen_BUG(dc, __FILE__, __LINE__))

#define BUG_ON(x) ({if (x) BUG();})

#define DISAS_SWI 5

/* Used by the decoder.  */

#define EXTRACT_FIELD(src, start, end) \

            (((src) >> start) & ((1 << (end - start + 1)) - 1))

#define CC_MASK_NZ 0xc

#define CC_MASK_NZV 0xe

#define CC_MASK_NZVC 0xf

#define CC_MASK_RNZV 0x10e

TCGv cpu_env;

TCGv cpu_T[2];

TCGv cpu_R[16];

TCGv cpu_PR[16];

TCGv cc_src;

TCGv cc_dest;

TCGv cc_result;

TCGv cc_op;

TCGv cc_size;

TCGv cc_mask;

/* This is the state at translation time.  */

typedef struct DisasContext {

        CPUState *env;

        target_ulong pc, insn_pc;

        /* Decoder.  */

        uint32_t ir;

        uint32_t opcode;

        unsigned int op1;

        unsigned int op2;

        unsigned int zsize, zzsize;

        unsigned int mode;

        unsigned int postinc;

        int update_cc;

        int cc_op;

        int cc_size;

        uint32_t cc_mask;

        int flags_live;

        int flagx_live;

        int flags_x;

        uint32_t tb_entry_flags;

        int memidx; /* user or kernel mode.  */

        int is_jmp;

        int dyn_jmp;

        uint32_t delayed_pc;

        int delayed_branch;

        int bcc;

        uint32_t condlabel;

        struct TranslationBlock *tb;

        int singlestep_enabled;

} DisasContext;

void cris_prepare_jmp (DisasContext *dc, uint32_t dst);

static void gen_BUG(DisasContext *dc, char *file, int line)

{

        printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);

        fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);

        cpu_dump_state (dc->env, stdout, fprintf, 0);

        fflush(NULL);

        cris_prepare_jmp (dc, 0x70000000 + line);

}

#ifdef CONFIG_USER_ONLY

#define GEN_OP_LD(width, reg) \

  void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \

    gen_op_ld##width##_T0_##reg##_raw(); \

  }

#define GEN_OP_ST(width, reg) \

  void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \

    gen_op_st##width##_##reg##_T1_raw(); \

  }

#else

#define GEN_OP_LD(width, reg) \

  void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \

    if (dc->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \

    else gen_op_ld##width##_T0_##reg##_user();\

  }

#define GEN_OP_ST(width, reg) \

  void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \

    if (dc->memidx) gen_op_st##width##_##reg##_T1_kernel(); \

    else gen_op_st##width##_##reg##_T1_user();\

  }

#endif

GEN_OP_LD(ub, T0)

GEN_OP_LD(b, T0)

GEN_OP_ST(b, T0)

GEN_OP_LD(uw, T0)

GEN_OP_LD(w, T0)

GEN_OP_ST(w, T0)

GEN_OP_LD(l, T0)

GEN_OP_ST(l, T0)

const char *regnames[] =

{

        "$r0", "$r1", "$r2", "$r3",

        "$r4", "$r5", "$r6", "$r7",

        "$r8", "$r9", "$r10", "$r11",

        "$r12", "$r13", "$sp", "$acr",

};

const char *pregnames[] =

{

        "$bz", "$vr", "$pid", "$srs",

        "$wz", "$exs", "$eda", "$mof",

        "$dz", "$ebp", "$erp", "$srp",

        "$nrp", "$ccs", "$usp", "$spc",

};

/* We need this table to handle preg-moves with implicit width.  */

int preg_sizes[] = {

        1, /* bz.  */

        1, /* vr.  */

        4, /* pid.  */

        1, /* srs.  */

        2, /* wz.  */

        4, 4, 4,

        4, 4, 4, 4,

        4, 4, 4, 4,

};

#define t_gen_mov_TN_env(tn, member) \

 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))

#define t_gen_mov_env_TN(member, tn) \

 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))

#define t_gen_mov_TN_reg(tn, regno) \

 tcg_gen_mov_tl(tn, cpu_R[regno])

#define t_gen_mov_reg_TN(regno, tn) \

 tcg_gen_mov_tl(cpu_R[regno], tn)

static inline void _t_gen_mov_TN_env(TCGv tn, int offset)

{

        tcg_gen_ld_tl(tn, cpu_env, offset);

}

static inline void _t_gen_mov_env_TN(int offset, TCGv tn)

{

        tcg_gen_st_tl(tn, cpu_env, offset);

}

static inline void t_gen_mov_TN_preg(TCGv tn, int r)

{

        if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

                tcg_gen_mov_tl(tn, tcg_const_tl(0));

        else if (r == PR_VR)

                tcg_gen_mov_tl(tn, tcg_const_tl(32));

        else

                tcg_gen_mov_tl(tn, cpu_PR[r]);

}

static inline void t_gen_mov_preg_TN(int r, TCGv tn)

{

        if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

                return;

        else

                tcg_gen_mov_tl(cpu_PR[r], tn);

}

static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)

{

        tcg_gen_movi_tl(tn, val);

}

static void t_gen_lsl(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_shl_tl(d, a, b);

        tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_movi_tl(d, 0);

        gen_set_label(l1);

}

static void t_gen_lsr(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_shr_tl(d, a, b);

        tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_movi_tl(d, 0);

        gen_set_label(l1);

}

static void t_gen_asr(TCGv d, TCGv a, TCGv b)

{

        int l1;

        l1 = gen_new_label();

        /* Speculative shift. */

        tcg_gen_sar_tl(d, a, b);

        tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);

        /* Clear dst if shift operands were to large.  */

        tcg_gen_movi_tl(d, 0);

        tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_tl(0x80000000), l1);

        tcg_gen_movi_tl(d, 0xffffffff);

        gen_set_label(l1);

}

/* 64-bit signed mul, lower result in d and upper in d2.  */

static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)

{

        TCGv t0, t1;

        t0 = tcg_temp_new(TCG_TYPE_I64);

        t1 = tcg_temp_new(TCG_TYPE_I64);

        tcg_gen_ext32s_i64(t0, a);

        tcg_gen_ext32s_i64(t1, b);

        tcg_gen_mul_i64(t0, t0, t1);

        tcg_gen_trunc_i64_i32(d, t0);

        tcg_gen_shri_i64(t0, t0, 32);

        tcg_gen_trunc_i64_i32(d2, t0);

}

/* 64-bit unsigned muls, lower result in d and upper in d2.  */

static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)

{

        TCGv t0, t1;

        t0 = tcg_temp_new(TCG_TYPE_I64);

        t1 = tcg_temp_new(TCG_TYPE_I64);

        tcg_gen_extu_i32_i64(t0, a);

        tcg_gen_extu_i32_i64(t1, b);

        tcg_gen_mul_i64(t0, t0, t1);

        tcg_gen_trunc_i64_i32(d, t0);

        tcg_gen_shri_i64(t0, t0, 32);

        tcg_gen_trunc_i64_i32(d2, t0);

}

/* Extended arithmetics on CRIS.  */

static inline void t_gen_add_flag(TCGv d, int flag)

{

        TCGv c;

        c = tcg_temp_new(TCG_TYPE_TL);

        t_gen_mov_TN_preg(c, PR_CCS);

        /* Propagate carry into d.  */

        tcg_gen_andi_tl(c, c, 1 << flag);

        if (flag)

                tcg_gen_shri_tl(c, c, flag);

        tcg_gen_add_tl(d, d, c);

}

static inline void t_gen_addx_carry(TCGv d)

{

        TCGv x, c;

        x = tcg_temp_new(TCG_TYPE_TL);

        c = tcg_temp_new(TCG_TYPE_TL);

        t_gen_mov_TN_preg(x, PR_CCS);

        tcg_gen_mov_tl(c, x);

        /* Propagate carry into d if X is set. Branch free.  */

        tcg_gen_andi_tl(c, c, C_FLAG);

        tcg_gen_andi_tl(x, x, X_FLAG);

        tcg_gen_shri_tl(x, x, 4);

        tcg_gen_and_tl(x, x, c);

        tcg_gen_add_tl(d, d, x);        

}

static inline void t_gen_subx_carry(TCGv d)

{

        TCGv x, c;

        x = tcg_temp_new(TCG_TYPE_TL);

        c = tcg_temp_new(TCG_TYPE_TL);

        t_gen_mov_TN_preg(x, PR_CCS);

        tcg_gen_mov_tl(c, x);

        /* Propagate carry into d if X is set. Branch free.  */

        tcg_gen_andi_tl(c, c, C_FLAG);

        tcg_gen_andi_tl(x, x, X_FLAG);

        tcg_gen_shri_tl(x, x, 4);

        tcg_gen_and_tl(x, x, c);

        tcg_gen_sub_tl(d, d, x);

}

/* Swap the two bytes within each half word of the s operand.

   T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff)  */

static inline void t_gen_swapb(TCGv d, TCGv s)

{

        TCGv t, org_s;

        t = tcg_temp_new(TCG_TYPE_TL);

        org_s = tcg_temp_new(TCG_TYPE_TL);

        /* d and s may refer to the same object.  */

        tcg_gen_mov_tl(org_s, s);

        tcg_gen_shli_tl(t, org_s, 8);

        tcg_gen_andi_tl(d, t, 0xff00ff00);

        tcg_gen_shri_tl(t, org_s, 8);

        tcg_gen_andi_tl(t, t, 0x00ff00ff);

        tcg_gen_or_tl(d, d, t);

}

/* Swap the halfwords of the s operand.  */

static inline void t_gen_swapw(TCGv d, TCGv s)

{

        TCGv t;

        /* d and s refer the same object.  */

        t = tcg_temp_new(TCG_TYPE_TL);

        tcg_gen_mov_tl(t, s);

        tcg_gen_shli_tl(d, t, 16);

        tcg_gen_shri_tl(t, t, 16);

        tcg_gen_or_tl(d, d, t);

}

/* Reverse the within each byte.

   T0 = (((T0 << 7) & 0x80808080) |

   ((T0 << 5) & 0x40404040) |

   ((T0 << 3) & 0x20202020) |

   ((T0 << 1) & 0x10101010) |

   ((T0 >> 1) & 0x08080808) |

   ((T0 >> 3) & 0x04040404) |

   ((T0 >> 5) & 0x02020202) |

   ((T0 >> 7) & 0x01010101));

 */

static inline void t_gen_swapr(TCGv d, TCGv s)

{

        struct {

                int shift; /* LSL when positive, LSR when negative.  */

                uint32_t mask;

        } bitrev [] = {

                {7, 0x80808080},

                {5, 0x40404040},

                {3, 0x20202020},

                {1, 0x10101010},

                {-1, 0x08080808},

                {-3, 0x04040404},

                {-5, 0x02020202},

                {-7, 0x01010101}

        };

        int i;

        TCGv t, org_s;

        /* d and s refer the same object.  */

        t = tcg_temp_new(TCG_TYPE_TL);

        org_s = tcg_temp_new(TCG_TYPE_TL);

        tcg_gen_mov_tl(org_s, s);

        tcg_gen_shli_tl(t, org_s,  bitrev[0].shift);

        tcg_gen_andi_tl(d, t,  bitrev[0].mask);

        for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {

                if (bitrev[i].shift >= 0) {

                        tcg_gen_shli_tl(t, org_s,  bitrev[i].shift);

                } else {

                        tcg_gen_shri_tl(t, org_s,  -bitrev[i].shift);

                }

                tcg_gen_andi_tl(t, t,  bitrev[i].mask);

                tcg_gen_or_tl(d, d, t);

        }

}

static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)

{

        TranslationBlock *tb;

        tb = dc->tb;

        if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

                tcg_gen_goto_tb(n);

                tcg_gen_movi_tl(cpu_T[0], dest);

                t_gen_mov_env_TN(pc, cpu_T[0]);

                tcg_gen_exit_tb((long)tb + n);

        } else {

                t_gen_mov_env_TN(pc, cpu_T[0]);

                tcg_gen_exit_tb(0);

        }

}

/* Sign extend at translation time.  */

static int sign_extend(unsigned int val, unsigned int width)

{

        int sval;

        /* LSL.  */

        val <<= 31 - width;

        sval = val;

        /* ASR.  */

        sval >>= 31 - width;

        return sval;

}

static inline void cris_clear_x_flag(DisasContext *dc)

{

        if (!dc->flagx_live || dc->cc_op != CC_OP_FLAGS) {

                t_gen_mov_TN_preg(cpu_T[0], PR_CCS);

                tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ~X_FLAG);

                t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);

                dc->flagx_live = 1;

                dc->flags_x = 0;

        }

}

static void cris_evaluate_flags(DisasContext *dc)

{

        if (!dc->flags_live) {

                switch (dc->cc_op)

                {

                        case CC_OP_MCP:

                                gen_op_evaluate_flags_mcp ();

                                break;

                        case CC_OP_MULS:

                                gen_op_evaluate_flags_muls ();

                                break;

                        case CC_OP_MULU:

                                gen_op_evaluate_flags_mulu ();

                                break;

                        case CC_OP_MOVE:

                                switch (dc->cc_size)

                                {

                                        case 4:

                                                gen_op_evaluate_flags_move_4();

                                                break;

                                        case 2:

                                                gen_op_evaluate_flags_move_2();

                                                break;

                                        default:

                                                gen_op_evaluate_flags ();

                                                break;

                                }

                                break;

                        default:

                        {

                                switch (dc->cc_size)

                                {

                                        case 4:

                                                gen_op_evaluate_flags_alu_4 ();

                                                break;

                                        default:

                                                gen_op_evaluate_flags ();

                                                break;

                                }

                        }

                        break;

                }

                dc->flags_live = 1;

        }

}

static void cris_cc_mask(DisasContext *dc, unsigned int mask)

{

        uint32_t ovl;

        /* Check if we need to evaluate the condition codes due to 

           CC overlaying.  */

        ovl = (dc->cc_mask ^ mask) & ~mask;

        if (ovl) {

                /* TODO: optimize this case. It trigs all the time.  */

                cris_evaluate_flags (dc);

        }

        dc->cc_mask = mask;

        dc->update_cc = 1;

        if (mask == 0)

                dc->update_cc = 0;

        else

                dc->flags_live = 0;

}

static void cris_update_cc_op(DisasContext *dc, int op)

{

        dc->cc_op = op;

        dc->flags_live = 0;

        tcg_gen_movi_tl(cc_op, op);

}

static void cris_update_cc_size(DisasContext *dc, int size)

{

        dc->cc_size = size;

        tcg_gen_movi_tl(cc_size, size);

}

/* op is the operation.

   T0, T1 are the operands.

   dst is the destination reg.

*/

static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)

{

        int writeback = 1;

        if (dc->update_cc) {

                cris_update_cc_op(dc, op);

                cris_update_cc_size(dc, size);

                tcg_gen_mov_tl(cc_dest, cpu_T[0]);

                tcg_gen_movi_tl(cc_mask, dc->cc_mask);

                /* FIXME: This shouldn't be needed. But we don't pass the

                 tests without it. Investigate.  */

                t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));

                t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));

        }

        /* Emit the ALU insns.  */

        switch (op)

        {

                case CC_OP_ADD:

                        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        /* Extended arithmetics.  */

                        t_gen_addx_carry(cpu_T[0]);

                        break;

                case CC_OP_ADDC:

                        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        t_gen_add_flag(cpu_T[0], 0); /* C_FLAG.  */

                        break;

                case CC_OP_MCP:

                        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        t_gen_add_flag(cpu_T[0], 8); /* R_FLAG.  */

                        break;

                case CC_OP_SUB:

                        tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);

                        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);

                        /* CRIS flag evaluation needs ~src.  */

                        tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(cpu_T[0]);

                        break;

                case CC_OP_MOVE:

                        tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_OR:

                        tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_AND:

                        tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_XOR:

                        tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_LSL:

                        t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_LSR:

                        t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_ASR:

                        t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);

                        break;

                case CC_OP_NEG:

                        /* Hopefully the TCG backend recognizes this pattern

                           and makes a real neg out of it.  */

                        tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(cpu_T[0]);

                        break;

                case CC_OP_LZ:

                        gen_op_lz_T0_T1();

                        break;

                case CC_OP_BTST:

                        gen_op_btst_T0_T1();

                        writeback = 0;

                        break;

                case CC_OP_MULS:

                {

                        TCGv mof;

                        mof = tcg_temp_new(TCG_TYPE_TL);

                        t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);

                        t_gen_mov_preg_TN(PR_MOF, mof);

                }

                break;

                case CC_OP_MULU:

                {

                        TCGv mof;

                        mof = tcg_temp_new(TCG_TYPE_TL);

                        t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);

                        t_gen_mov_preg_TN(PR_MOF, mof);

                }

                break;

                case CC_OP_DSTEP:

                        gen_op_dstep_T0_T1();

                        break;

                case CC_OP_BOUND:

                {

                        int l1;

                        l1 = gen_new_label();

                        tcg_gen_brcond_tl(TCG_COND_LEU, 

                                          cpu_T[0], cpu_T[1], l1);

                        tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);

                        gen_set_label(l1);

                }

                break;

                case CC_OP_CMP:

                        tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);

                        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        /* CRIS flag evaluation needs ~src.  */

                        tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);

                        /* CRIS flag evaluation needs ~src.  */

                        tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);

                        /* Extended arithmetics.  */

                        t_gen_subx_carry(cpu_T[0]);

                        writeback = 0;

                        break;

                default:

                        fprintf (logfile, "illegal ALU op.\n");

                        BUG();

                        break;

        }

        if (dc->update_cc)

                tcg_gen_mov_tl(cc_src, cpu_T[1]);

        if (size == 1)

                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);

        else if (size == 2)

                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);

        /* Writeback.  */

        if (writeback) {

                if (size == 4)

                        t_gen_mov_reg_TN(rd, cpu_T[0]);

                else {

                        tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);

                        t_gen_mov_TN_reg(cpu_T[0], rd);

                        if (size == 1)

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);

                        else

                                tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);

                        tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

                        t_gen_mov_reg_TN(rd, cpu_T[0]);

                        tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);

                }

        }

        if (dc->update_cc)

                tcg_gen_mov_tl(cc_result, cpu_T[0]);

        {

                /* TODO: Optimize this.  */

                if (!dc->flagx_live)

                        cris_evaluate_flags(dc);

        }

}

static int arith_cc(DisasContext *dc)

{

        if (dc->update_cc) {

                switch (dc->cc_op) {

                        case CC_OP_ADD: return 1;

                        case CC_OP_SUB: return 1;

                        case CC_OP_LSL: return 1;

                        case CC_OP_LSR: return 1;

                        case CC_OP_ASR: return 1;

                        case CC_OP_CMP: return 1;

                        default:

                                return 0;

                }

        }

        return 0;

}

static void gen_tst_cc (DisasContext *dc, int cond)

{

        int arith_opt;

        /* TODO: optimize more condition codes.  */

        arith_opt = arith_cc(dc) && !dc->flags_live;

        switch (cond) {

                case CC_EQ:

                        if (arith_opt)

                                gen_op_tst_cc_eq_fast ();

                        else {

                                cris_evaluate_flags(dc);

                                gen_op_tst_cc_eq ();

                        }

                        break;

                case CC_NE:

                        if (arith_opt)

                                gen_op_tst_cc_ne_fast ();

                        else {

                                cris_evaluate_flags(dc);

                                gen_op_tst_cc_ne ();

                        }

                        break;

                case CC_CS:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_cs ();

                        break;

                case CC_CC:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_cc ();

                        break;

                case CC_VS:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_vs ();

                        break;

                case CC_VC:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_vc ();

                        break;

                case CC_PL:

                        if (arith_opt)

                                gen_op_tst_cc_pl_fast ();

                        else {

                                cris_evaluate_flags(dc);

                                gen_op_tst_cc_pl ();

                        }

                        break;

                case CC_MI:

                        if (arith_opt)

                                gen_op_tst_cc_mi_fast ();

                        else {

                                cris_evaluate_flags(dc);

                                gen_op_tst_cc_mi ();

                        }

                        break;

                case CC_LS:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_ls ();

                        break;

                case CC_HI:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_hi ();

                        break;

                case CC_GE:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_ge ();

                        break;

                case CC_LT:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_lt ();

                        break;

                case CC_GT:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_gt ();

                        break;

                case CC_LE:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_le ();

                        break;

                case CC_P:

                        cris_evaluate_flags(dc);

                        gen_op_tst_cc_p ();

                        break;

                case CC_A:

                        cris_evaluate_flags(dc);

                        gen_op_movl_T0_im (1);

                        break;

                default:

                        BUG();

                        break;

        };

}

static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)

{

        /* This helps us re-schedule the micro-code to insns in delay-slots

           before the actual jump.  */

        dc->delayed_branch = 2;

        dc->delayed_pc = dc->pc + offset;

        dc->bcc = cond;

        if (cond != CC_A)

        {

                gen_tst_cc (dc, cond);

                gen_op_evaluate_bcc ();

        }

        tcg_gen_movi_tl(cpu_T[0], dc->delayed_pc);

        t_gen_mov_env_TN(btarget, cpu_T[0]);

}

/* Dynamic jumps, when the dest is in a live reg for example.  */

void cris_prepare_dyn_jmp (DisasContext *dc)

{

        /* This helps us re-schedule the micro-code to insns in delay-slots

           before the actual jump.  */

        dc->delayed_branch = 2;

        dc->dyn_jmp = 1;

        dc->bcc = CC_A;

}

void cris_prepare_jmp (DisasContext *dc, uint32_t dst)

{

        /* This helps us re-schedule the micro-code to insns in delay-slots

           before the actual jump.  */

        dc->delayed_branch = 2;

        dc->delayed_pc = dst;

        dc->dyn_jmp = 0;

        dc->bcc = CC_A;

}

void gen_load_T0_T0 (DisasContext *dc, unsigned int size, int sign)

{

        if (size == 1) {

                if (sign)

                        gen_op_ldb_T0_T0(dc);

                else

                        gen_op_ldub_T0_T0(dc);

        }

        else if (size == 2) {

                if (sign)

                        gen_op_ldw_T0_T0(dc);

                else

                        gen_op_lduw_T0_T0(dc);

        }

        else {

                gen_op_ldl_T0_T0(dc);

        }

}

void gen_store_T0_T1 (DisasContext *dc, unsigned int size)

{

        /* Remember, operands are flipped. CRIS has reversed order.  */

        if (size == 1) {

                gen_op_stb_T0_T1(dc);

        }

        else if (size == 2) {

                gen_op_stw_T0_T1(dc);

        }

        else

                gen_op_stl_T0_T1(dc);

}

static inline void t_gen_sext(TCGv d, TCGv s, int size)

{

        if (size == 1)

                tcg_gen_ext8s_i32(d, s);

        else if (size == 2)

                tcg_gen_ext16s_i32(d, s);

}

static inline void t_gen_zext(TCGv d, TCGv s, int size)

{

        /* TCG-FIXME: this is not optimal. Many archs have fast zext insns.  */

        if (size == 1)

                tcg_gen_andi_i32(d, s, 0xff);

        else if (size == 2)

                tcg_gen_andi_i32(d, s, 0xffff);

}

#if DISAS_CRIS

static char memsize_char(int size)

{

        switch (size)

        {

                case 1: return 'b';  break;

                case 2: return 'w';  break;

                case 4: return 'd';  break;

                default:

                        return 'x';

                        break;

        }

}

#endif

static unsigned int memsize_z(DisasContext *dc)

{

        return dc->zsize + 1;

}

static unsigned int memsize_zz(DisasContext *dc)

{

        switch (dc->zzsize)

        {

                case 0: return 1;

                case 1: return 2;

                default:

                        return 4;

        }

}

static void do_postinc (DisasContext *dc, int size)

{

        if (!dc->postinc)

                return;

        t_gen_mov_TN_reg(cpu_T[0], dc->op1);

        tcg_gen_addi_tl(cpu_T[0], cpu_T[0], size);

        t_gen_mov_reg_TN(dc->op1, cpu_T[0]);

}

static void dec_prep_move_r(DisasContext *dc, int rs, int rd,

                            int size, int s_ext)

{

        t_gen_mov_TN_reg(cpu_T[1], rs);

        if (s_ext)

                t_gen_sext(cpu_T[1], cpu_T[1], size);

        else

                t_gen_zext(cpu_T[1], cpu_T[1], size);

}

/* Prepare T0 and T1 for a register alu operation.

   s_ext decides if the operand1 should be sign-extended or zero-extended when

   needed.  */

static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,

                          int size, int s_ext)

{

        dec_prep_move_r(dc, rs, rd, size, s_ext);

        t_gen_mov_TN_reg(cpu_T[0], rd);

        if (s_ext)

                t_gen_sext(cpu_T[0], cpu_T[0], size);

        else

                t_gen_zext(cpu_T[0], cpu_T[0], size);

}

/* Prepare T0 and T1 for a memory + alu operation.

   s_ext decides if the operand1 should be sign-extended or zero-extended when

   needed.  */

static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)

{

        unsigned int rs, rd;

        uint32_t imm;

        int is_imm;

        int insn_len = 2;

        rs = dc->op1;

        rd = dc->op2;

        is_imm = rs == 15 && dc->postinc;

        /* Load [$rs] onto T1.  */

        if (is_imm) {

                insn_len = 2 + memsize;

                if (memsize == 1)

                        insn_len++;

                imm = ldl_code(dc->pc + 2);

                if (memsize != 4) {

                        if (s_ext) {

                                imm = sign_extend(imm, (memsize * 8) - 1);

                        } else {

                                if (memsize == 1)

                                        imm &= 0xff;

                                else

                                        imm &= 0xffff;

                        }

                }

                DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",

                            imm, rd, s_ext, memsize));

                tcg_gen_movi_tl(cpu_T[1], imm);

                dc->postinc = 0;

        } else {

                t_gen_mov_TN_reg(cpu_T[0], rs);

                gen_load_T0_T0(dc, memsize, 0);

                tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);

                if (s_ext)

                        t_gen_sext(cpu_T[1], cpu_T[1], memsize);

                else

                        t_gen_zext(cpu_T[1], cpu_T[1], memsize);

        }

        /* put dest in T0.  */

        t_gen_mov_TN_reg(cpu_T[0], rd);

        return insn_len;

}

#if DISAS_CRIS

static const char *cc_name(int cc)

{

        static char *cc_names[16] = {

                "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",

                "ls", "hi", "ge", "lt", "gt", "le", "a", "p"

        };

        assert(cc < 16);

        return cc_names[cc];

}

#endif

static unsigned int dec_bccq(DisasContext *dc)

{

        int32_t offset;

        int sign;

        uint32_t cond = dc->op2;

        int tmp;

        offset = EXTRACT_FIELD (dc->ir, 1, 7);

        sign = EXTRACT_FIELD(dc->ir, 0, 0);

        offset *= 2;

        offset |= sign << 8;

        tmp = offset;

        offset = sign_extend(offset, 8);

        /* op2 holds the condition-code.  */

        cris_cc_mask(dc, 0);

        cris_prepare_cc_branch (dc, offset, cond);

        return 2;

}

static unsigned int dec_addoq(DisasContext *dc)

{

        uint32_t imm;

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);

        imm = sign_extend(dc->op1, 7);

        DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));

        cris_cc_mask(dc, 0);

        /* Fetch register operand,  */

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        tcg_gen_movi_tl(cpu_T[1], imm);

        crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);

        return 2;

}

static unsigned int dec_addq(DisasContext *dc)

{

        DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        cris_cc_mask(dc, CC_MASK_NZVC);

        /* Fetch register operand,  */

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        tcg_gen_movi_tl(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);

        return 2;

}

static unsigned int dec_moveq(DisasContext *dc)

{

        uint32_t imm;

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        imm = sign_extend(dc->op1, 5);

        DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));

        t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));

        return 2;

}

static unsigned int dec_subq(DisasContext *dc)

{

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZVC);

        /* Fetch register operand,  */

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);

        return 2;

}

static unsigned int dec_cmpq(DisasContext *dc)

{

        uint32_t imm;

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        imm = sign_extend(dc->op1, 5);

        DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZVC);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], imm);

        crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);

        return 2;

}

static unsigned int dec_andq(DisasContext *dc)

{

        uint32_t imm;

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        imm = sign_extend(dc->op1, 5);

        DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], imm);

        crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);

        return 2;

}

static unsigned int dec_orq(DisasContext *dc)

{

        uint32_t imm;

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);

        imm = sign_extend(dc->op1, 5);

        DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], imm);

        crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);

        return 2;

}

static unsigned int dec_btstq(DisasContext *dc)

{

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);

        DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);

        cris_update_cc_op(dc, CC_OP_FLAGS);

        t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);

        dc->flags_live = 1;

        return 2;

}

static unsigned int dec_asrq(DisasContext *dc)

{

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);

        DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);

        return 2;

}

static unsigned int dec_lslq(DisasContext *dc)

{

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);

        DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);

        return 2;

}

static unsigned int dec_lsrq(DisasContext *dc)

{

        dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);

        DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        t_gen_mov_TN_reg(cpu_T[0], dc->op2);

        t_gen_mov_TN_im(cpu_T[1], dc->op1);

        crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);

        return 2;

}

static unsigned int dec_move_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);

        crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);

        return 2;

}

static unsigned int dec_scc_r(DisasContext *dc)

{

        int cond = dc->op2;

        DIS(fprintf (logfile, "s%s $r%u\n",

                    cc_name(cond), dc->op1));

        if (cond != CC_A)

        {

                gen_tst_cc (dc, cond);

                tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);

        }

        else

                tcg_gen_movi_tl(cpu_T[1], 1);

        cris_cc_mask(dc, 0);

        crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);

        return 2;

}

static unsigned int dec_and_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);

        crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);

        return 2;

}

static unsigned int dec_lz_r(DisasContext *dc)

{

        DIS(fprintf (logfile, "lz $r%u, $r%u\n",

                    dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);

        crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);

        return 2;

}

static unsigned int dec_lsl_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);

        tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);

        crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);

        return 2;

}

static unsigned int dec_lsr_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);

        tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);

        crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);

        return 2;

}

static unsigned int dec_asr_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZ);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);

        tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);

        crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);

        return 2;

}

static unsigned int dec_muls_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZV);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);

        t_gen_sext(cpu_T[0], cpu_T[0], size);

        crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);

        return 2;

}

static unsigned int dec_mulu_r(DisasContext *dc)

{

        int size = memsize_zz(dc);

        DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",

                    memsize_char(size), dc->op1, dc->op2));

        cris_cc_mask(dc, CC_MASK_NZV);

        dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);

        t_gen_zext(cpu_T[0], cpu_T[0], size);