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/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/pci/pci.h" |
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#include "hw/pci-host/apb.h" |
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#include "hw/i386/pc.h" |
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#include "hw/char/serial.h" |
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#include "hw/timer/m48t59.h" |
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#include "hw/block/fdc.h" |
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#include "net/net.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/boards.h" |
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#include "hw/nvram/openbios_firmware_abi.h" |
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#include "hw/nvram/fw_cfg.h" |
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#include "hw/sysbus.h" |
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#include "hw/ide.h" |
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#include "hw/loader.h" |
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#include "elf.h" |
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#include "sysemu/blockdev.h" |
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#include "exec/address-spaces.h" |
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//#define DEBUG_IRQ
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//#define DEBUG_EBUS
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//#define DEBUG_TIMER
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|
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#ifdef DEBUG_IRQ
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#define CPUIRQ_DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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|
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#ifdef DEBUG_EBUS
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#define EBUS_DPRINTF(fmt, ...) \
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do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define EBUS_DPRINTF(fmt, ...)
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#endif
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|
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00404000 |
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#define CMDLINE_ADDR 0x003ff000 |
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#define PROM_SIZE_MAX (4 * 1024 * 1024) |
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#define PROM_VADDR 0x000ffd00000ULL |
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#define APB_SPECIAL_BASE 0x1fe00000000ULL |
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#define APB_MEM_BASE 0x1ff00000000ULL |
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#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
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#define PROM_FILENAME "openbios-sparc64" |
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#define NVRAM_SIZE 0x2000 |
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#define MAX_IDE_BUS 2 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
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|
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#define IVEC_MAX 0x40 |
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|
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#define TICK_MAX 0x7fffffffffffffffULL |
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|
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struct hwdef {
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const char * const default_cpu_model; |
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uint16_t machine_id; |
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uint64_t prom_addr; |
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uint64_t console_serial_base; |
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}; |
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|
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typedef struct EbusState { |
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PCIDevice pci_dev; |
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MemoryRegion bar0; |
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MemoryRegion bar1; |
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} EbusState; |
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|
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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|
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
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{ |
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} |
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|
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
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{ |
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0; |
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} |
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static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
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const char *arch, ram_addr_t RAM_size, |
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const char *boot_devices, |
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uint32_t kernel_image, uint32_t kernel_size, |
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const char *cmdline, |
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uint32_t initrd_image, uint32_t initrd_size, |
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uint32_t NVRAM_image, |
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int width, int height, int depth, |
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const uint8_t *macaddr)
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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return 0; |
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} |
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static uint64_t sun4u_load_kernel(const char *kernel_filename, |
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const char *initrd_filename, |
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ram_addr_t RAM_size, uint64_t *initrd_size, |
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uint64_t *initrd_addr, uint64_t *kernel_addr, |
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uint64_t *kernel_entry) |
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{ |
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int linux_boot;
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unsigned int i; |
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long kernel_size;
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uint8_t *ptr; |
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uint64_t kernel_top; |
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
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kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); |
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if (kernel_size < 0) { |
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*kernel_addr = KERNEL_LOAD_ADDR; |
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*kernel_entry = KERNEL_LOAD_ADDR; |
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
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TARGET_PAGE_SIZE); |
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} |
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if (kernel_size < 0) { |
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kernel_size = load_image_targphys(kernel_filename, |
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KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
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} |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd above kernel */
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*initrd_size = 0;
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if (initrd_filename) {
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*initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
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*initrd_size = load_image_targphys(initrd_filename, |
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*initrd_addr, |
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RAM_size - *initrd_addr); |
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if ((int)*initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} |
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if (*initrd_size > 0) { |
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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ptr = rom_ptr(*kernel_addr + i); |
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if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
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stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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stl_p(ptr + 28, *initrd_size);
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break;
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} |
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} |
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} |
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} |
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return kernel_size;
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} |
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void cpu_check_irqs(CPUSPARCState *env)
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{ |
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CPUState *cs; |
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uint32_t pil = env->pil_in | |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) { |
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return;
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} |
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cs = CPU(sparc_env_get_cpu(env)); |
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14; |
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} |
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/* The bit corresponding to psrpil is (1<< psrpil), the next bit
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is (2 << psrpil). */
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if (pil < (2 << env->psrpil)){ |
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
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} |
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return;
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} |
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|
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if (cpu_interrupts_enabled(env)) {
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|
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unsigned int i; |
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|
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for (i = 15; i > env->psrpil; i--) { |
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if (pil & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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|
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n",
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env->tl, cpu_tsptr(env)->tt, new_interrupt); |
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} else if (old_interrupt != new_interrupt) { |
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env->interrupt_index = new_interrupt; |
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt); |
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cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { |
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
313 |
} |
314 |
} |
315 |
|
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static void cpu_kick_irq(SPARCCPU *cpu) |
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{ |
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CPUState *cs = CPU(cpu); |
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CPUSPARCState *env = &cpu->env; |
320 |
|
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cs->halted = 0;
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cpu_check_irqs(env); |
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qemu_cpu_kick(cs); |
324 |
} |
325 |
|
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static void cpu_set_ivec_irq(void *opaque, int irq, int level) |
327 |
{ |
328 |
SPARCCPU *cpu = opaque; |
329 |
CPUSPARCState *env = &cpu->env; |
330 |
CPUState *cs; |
331 |
|
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if (level) {
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if (!(env->ivec_status & 0x20)) { |
334 |
CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
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cs = CPU(cpu); |
336 |
cs->halted = 0;
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env->interrupt_index = TT_IVEC; |
338 |
env->ivec_status |= 0x20;
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env->ivec_data[0] = (0x1f << 6) | irq; |
340 |
env->ivec_data[1] = 0; |
341 |
env->ivec_data[2] = 0; |
342 |
cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
343 |
} |
344 |
} else {
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if (env->ivec_status & 0x20) { |
346 |
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
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cs = CPU(cpu); |
348 |
env->ivec_status &= ~0x20;
|
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
350 |
} |
351 |
} |
352 |
} |
353 |
|
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typedef struct ResetData { |
355 |
SPARCCPU *cpu; |
356 |
uint64_t prom_addr; |
357 |
} ResetData; |
358 |
|
359 |
void cpu_put_timer(QEMUFile *f, CPUTimer *s)
|
360 |
{ |
361 |
qemu_put_be32s(f, &s->frequency); |
362 |
qemu_put_be32s(f, &s->disabled); |
363 |
qemu_put_be64s(f, &s->disabled_mask); |
364 |
qemu_put_sbe64s(f, &s->clock_offset); |
365 |
|
366 |
qemu_put_timer(f, s->qtimer); |
367 |
} |
368 |
|
369 |
void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
370 |
{ |
371 |
qemu_get_be32s(f, &s->frequency); |
372 |
qemu_get_be32s(f, &s->disabled); |
373 |
qemu_get_be64s(f, &s->disabled_mask); |
374 |
qemu_get_sbe64s(f, &s->clock_offset); |
375 |
|
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qemu_get_timer(f, s->qtimer); |
377 |
} |
378 |
|
379 |
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, |
380 |
QEMUBHFunc *cb, uint32_t frequency, |
381 |
uint64_t disabled_mask) |
382 |
{ |
383 |
CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
384 |
|
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timer->name = name; |
386 |
timer->frequency = frequency; |
387 |
timer->disabled_mask = disabled_mask; |
388 |
|
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timer->disabled = 1;
|
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timer->clock_offset = qemu_get_clock_ns(vm_clock); |
391 |
|
392 |
timer->qtimer = qemu_new_timer_ns(vm_clock, cb, cpu); |
393 |
|
394 |
return timer;
|
395 |
} |
396 |
|
397 |
static void cpu_timer_reset(CPUTimer *timer) |
398 |
{ |
399 |
timer->disabled = 1;
|
400 |
timer->clock_offset = qemu_get_clock_ns(vm_clock); |
401 |
|
402 |
qemu_del_timer(timer->qtimer); |
403 |
} |
404 |
|
405 |
static void main_cpu_reset(void *opaque) |
406 |
{ |
407 |
ResetData *s = (ResetData *)opaque; |
408 |
CPUSPARCState *env = &s->cpu->env; |
409 |
static unsigned int nr_resets; |
410 |
|
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cpu_reset(CPU(s->cpu)); |
412 |
|
413 |
cpu_timer_reset(env->tick); |
414 |
cpu_timer_reset(env->stick); |
415 |
cpu_timer_reset(env->hstick); |
416 |
|
417 |
env->gregs[1] = 0; // Memory start |
418 |
env->gregs[2] = ram_size; // Memory size |
419 |
env->gregs[3] = 0; // Machine description XXX |
420 |
if (nr_resets++ == 0) { |
421 |
/* Power on reset */
|
422 |
env->pc = s->prom_addr + 0x20ULL;
|
423 |
} else {
|
424 |
env->pc = s->prom_addr + 0x40ULL;
|
425 |
} |
426 |
env->npc = env->pc + 4;
|
427 |
} |
428 |
|
429 |
static void tick_irq(void *opaque) |
430 |
{ |
431 |
SPARCCPU *cpu = opaque; |
432 |
CPUSPARCState *env = &cpu->env; |
433 |
|
434 |
CPUTimer* timer = env->tick; |
435 |
|
436 |
if (timer->disabled) {
|
437 |
CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
438 |
return;
|
439 |
} else {
|
440 |
CPUIRQ_DPRINTF("tick: fire\n");
|
441 |
} |
442 |
|
443 |
env->softint |= SOFTINT_TIMER; |
444 |
cpu_kick_irq(cpu); |
445 |
} |
446 |
|
447 |
static void stick_irq(void *opaque) |
448 |
{ |
449 |
SPARCCPU *cpu = opaque; |
450 |
CPUSPARCState *env = &cpu->env; |
451 |
|
452 |
CPUTimer* timer = env->stick; |
453 |
|
454 |
if (timer->disabled) {
|
455 |
CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
456 |
return;
|
457 |
} else {
|
458 |
CPUIRQ_DPRINTF("stick: fire\n");
|
459 |
} |
460 |
|
461 |
env->softint |= SOFTINT_STIMER; |
462 |
cpu_kick_irq(cpu); |
463 |
} |
464 |
|
465 |
static void hstick_irq(void *opaque) |
466 |
{ |
467 |
SPARCCPU *cpu = opaque; |
468 |
CPUSPARCState *env = &cpu->env; |
469 |
|
470 |
CPUTimer* timer = env->hstick; |
471 |
|
472 |
if (timer->disabled) {
|
473 |
CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
474 |
return;
|
475 |
} else {
|
476 |
CPUIRQ_DPRINTF("hstick: fire\n");
|
477 |
} |
478 |
|
479 |
env->softint |= SOFTINT_STIMER; |
480 |
cpu_kick_irq(cpu); |
481 |
} |
482 |
|
483 |
static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
484 |
{ |
485 |
return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
486 |
} |
487 |
|
488 |
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
489 |
{ |
490 |
return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
491 |
} |
492 |
|
493 |
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
494 |
{ |
495 |
uint64_t real_count = count & ~timer->disabled_mask; |
496 |
uint64_t disabled_bit = count & timer->disabled_mask; |
497 |
|
498 |
int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
499 |
cpu_to_timer_ticks(real_count, timer->frequency); |
500 |
|
501 |
TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
502 |
timer->name, real_count, |
503 |
timer->disabled?"disabled":"enabled", timer); |
504 |
|
505 |
timer->disabled = disabled_bit ? 1 : 0; |
506 |
timer->clock_offset = vm_clock_offset; |
507 |
} |
508 |
|
509 |
uint64_t cpu_tick_get_count(CPUTimer *timer) |
510 |
{ |
511 |
uint64_t real_count = timer_to_cpu_ticks( |
512 |
qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
513 |
timer->frequency); |
514 |
|
515 |
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
516 |
timer->name, real_count, |
517 |
timer->disabled?"disabled":"enabled", timer); |
518 |
|
519 |
if (timer->disabled)
|
520 |
real_count |= timer->disabled_mask; |
521 |
|
522 |
return real_count;
|
523 |
} |
524 |
|
525 |
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
526 |
{ |
527 |
int64_t now = qemu_get_clock_ns(vm_clock); |
528 |
|
529 |
uint64_t real_limit = limit & ~timer->disabled_mask; |
530 |
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
531 |
|
532 |
int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
533 |
timer->clock_offset; |
534 |
|
535 |
if (expires < now) {
|
536 |
expires = now + 1;
|
537 |
} |
538 |
|
539 |
TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
540 |
"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
541 |
timer->name, real_limit, |
542 |
timer->disabled?"disabled":"enabled", |
543 |
timer, limit, |
544 |
timer_to_cpu_ticks(now - timer->clock_offset, |
545 |
timer->frequency), |
546 |
timer_to_cpu_ticks(expires - now, timer->frequency)); |
547 |
|
548 |
if (!real_limit) {
|
549 |
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
550 |
timer->name); |
551 |
qemu_del_timer(timer->qtimer); |
552 |
} else if (timer->disabled) { |
553 |
qemu_del_timer(timer->qtimer); |
554 |
} else {
|
555 |
qemu_mod_timer(timer->qtimer, expires); |
556 |
} |
557 |
} |
558 |
|
559 |
static void isa_irq_handler(void *opaque, int n, int level) |
560 |
{ |
561 |
static const int isa_irq_to_ivec[16] = { |
562 |
[1] = 0x29, /* keyboard */ |
563 |
[4] = 0x2b, /* serial */ |
564 |
[6] = 0x27, /* floppy */ |
565 |
[7] = 0x22, /* parallel */ |
566 |
[12] = 0x2a, /* mouse */ |
567 |
}; |
568 |
qemu_irq *irqs = opaque; |
569 |
int ivec;
|
570 |
|
571 |
assert(n < 16);
|
572 |
ivec = isa_irq_to_ivec[n]; |
573 |
EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
|
574 |
if (ivec) {
|
575 |
qemu_set_irq(irqs[ivec], level); |
576 |
} |
577 |
} |
578 |
|
579 |
/* EBUS (Eight bit bus) bridge */
|
580 |
static ISABus *
|
581 |
pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
|
582 |
{ |
583 |
qemu_irq *isa_irq; |
584 |
PCIDevice *pci_dev; |
585 |
ISABus *isa_bus; |
586 |
|
587 |
pci_dev = pci_create_simple(bus, devfn, "ebus");
|
588 |
isa_bus = DO_UPCAST(ISABus, qbus, |
589 |
qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
|
590 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
|
591 |
isa_bus_irqs(isa_bus, isa_irq); |
592 |
return isa_bus;
|
593 |
} |
594 |
|
595 |
static int |
596 |
pci_ebus_init1(PCIDevice *pci_dev) |
597 |
{ |
598 |
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
599 |
|
600 |
isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); |
601 |
|
602 |
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
603 |
pci_dev->config[0x05] = 0x00; |
604 |
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
605 |
pci_dev->config[0x07] = 0x03; // status = medium devsel |
606 |
pci_dev->config[0x09] = 0x00; // programming i/f |
607 |
pci_dev->config[0x0D] = 0x0a; // latency_timer |
608 |
|
609 |
isa_mmio_setup(&s->bar0, 0x1000000);
|
610 |
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
611 |
isa_mmio_setup(&s->bar1, 0x800000);
|
612 |
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
|
613 |
return 0; |
614 |
} |
615 |
|
616 |
static void ebus_class_init(ObjectClass *klass, void *data) |
617 |
{ |
618 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
619 |
|
620 |
k->init = pci_ebus_init1; |
621 |
k->vendor_id = PCI_VENDOR_ID_SUN; |
622 |
k->device_id = PCI_DEVICE_ID_SUN_EBUS; |
623 |
k->revision = 0x01;
|
624 |
k->class_id = PCI_CLASS_BRIDGE_OTHER; |
625 |
} |
626 |
|
627 |
static const TypeInfo ebus_info = { |
628 |
.name = "ebus",
|
629 |
.parent = TYPE_PCI_DEVICE, |
630 |
.instance_size = sizeof(EbusState),
|
631 |
.class_init = ebus_class_init, |
632 |
}; |
633 |
|
634 |
typedef struct PROMState { |
635 |
SysBusDevice busdev; |
636 |
MemoryRegion prom; |
637 |
} PROMState; |
638 |
|
639 |
static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
640 |
{ |
641 |
hwaddr *base_addr = (hwaddr *)opaque; |
642 |
return addr + *base_addr - PROM_VADDR;
|
643 |
} |
644 |
|
645 |
/* Boot PROM (OpenBIOS) */
|
646 |
static void prom_init(hwaddr addr, const char *bios_name) |
647 |
{ |
648 |
DeviceState *dev; |
649 |
SysBusDevice *s; |
650 |
char *filename;
|
651 |
int ret;
|
652 |
|
653 |
dev = qdev_create(NULL, "openprom"); |
654 |
qdev_init_nofail(dev); |
655 |
s = SYS_BUS_DEVICE(dev); |
656 |
|
657 |
sysbus_mmio_map(s, 0, addr);
|
658 |
|
659 |
/* load boot prom */
|
660 |
if (bios_name == NULL) { |
661 |
bios_name = PROM_FILENAME; |
662 |
} |
663 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
664 |
if (filename) {
|
665 |
ret = load_elf(filename, translate_prom_address, &addr, |
666 |
NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
667 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
668 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
669 |
} |
670 |
g_free(filename); |
671 |
} else {
|
672 |
ret = -1;
|
673 |
} |
674 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
675 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
676 |
exit(1);
|
677 |
} |
678 |
} |
679 |
|
680 |
static int prom_init1(SysBusDevice *dev) |
681 |
{ |
682 |
PROMState *s = FROM_SYSBUS(PROMState, dev); |
683 |
|
684 |
memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
|
685 |
vmstate_register_ram_global(&s->prom); |
686 |
memory_region_set_readonly(&s->prom, true);
|
687 |
sysbus_init_mmio(dev, &s->prom); |
688 |
return 0; |
689 |
} |
690 |
|
691 |
static Property prom_properties[] = {
|
692 |
{/* end of property list */},
|
693 |
}; |
694 |
|
695 |
static void prom_class_init(ObjectClass *klass, void *data) |
696 |
{ |
697 |
DeviceClass *dc = DEVICE_CLASS(klass); |
698 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
699 |
|
700 |
k->init = prom_init1; |
701 |
dc->props = prom_properties; |
702 |
} |
703 |
|
704 |
static const TypeInfo prom_info = { |
705 |
.name = "openprom",
|
706 |
.parent = TYPE_SYS_BUS_DEVICE, |
707 |
.instance_size = sizeof(PROMState),
|
708 |
.class_init = prom_class_init, |
709 |
}; |
710 |
|
711 |
|
712 |
typedef struct RamDevice |
713 |
{ |
714 |
SysBusDevice busdev; |
715 |
MemoryRegion ram; |
716 |
uint64_t size; |
717 |
} RamDevice; |
718 |
|
719 |
/* System RAM */
|
720 |
static int ram_init1(SysBusDevice *dev) |
721 |
{ |
722 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
723 |
|
724 |
memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
|
725 |
vmstate_register_ram_global(&d->ram); |
726 |
sysbus_init_mmio(dev, &d->ram); |
727 |
return 0; |
728 |
} |
729 |
|
730 |
static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
731 |
{ |
732 |
DeviceState *dev; |
733 |
SysBusDevice *s; |
734 |
RamDevice *d; |
735 |
|
736 |
/* allocate RAM */
|
737 |
dev = qdev_create(NULL, "memory"); |
738 |
s = SYS_BUS_DEVICE(dev); |
739 |
|
740 |
d = FROM_SYSBUS(RamDevice, s); |
741 |
d->size = RAM_size; |
742 |
qdev_init_nofail(dev); |
743 |
|
744 |
sysbus_mmio_map(s, 0, addr);
|
745 |
} |
746 |
|
747 |
static Property ram_properties[] = {
|
748 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
749 |
DEFINE_PROP_END_OF_LIST(), |
750 |
}; |
751 |
|
752 |
static void ram_class_init(ObjectClass *klass, void *data) |
753 |
{ |
754 |
DeviceClass *dc = DEVICE_CLASS(klass); |
755 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
756 |
|
757 |
k->init = ram_init1; |
758 |
dc->props = ram_properties; |
759 |
} |
760 |
|
761 |
static const TypeInfo ram_info = { |
762 |
.name = "memory",
|
763 |
.parent = TYPE_SYS_BUS_DEVICE, |
764 |
.instance_size = sizeof(RamDevice),
|
765 |
.class_init = ram_class_init, |
766 |
}; |
767 |
|
768 |
static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
769 |
{ |
770 |
SPARCCPU *cpu; |
771 |
CPUSPARCState *env; |
772 |
ResetData *reset_info; |
773 |
|
774 |
uint32_t tick_frequency = 100*1000000; |
775 |
uint32_t stick_frequency = 100*1000000; |
776 |
uint32_t hstick_frequency = 100*1000000; |
777 |
|
778 |
if (cpu_model == NULL) { |
779 |
cpu_model = hwdef->default_cpu_model; |
780 |
} |
781 |
cpu = cpu_sparc_init(cpu_model); |
782 |
if (cpu == NULL) { |
783 |
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
784 |
exit(1);
|
785 |
} |
786 |
env = &cpu->env; |
787 |
|
788 |
env->tick = cpu_timer_create("tick", cpu, tick_irq,
|
789 |
tick_frequency, TICK_NPT_MASK); |
790 |
|
791 |
env->stick = cpu_timer_create("stick", cpu, stick_irq,
|
792 |
stick_frequency, TICK_INT_DIS); |
793 |
|
794 |
env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
|
795 |
hstick_frequency, TICK_INT_DIS); |
796 |
|
797 |
reset_info = g_malloc0(sizeof(ResetData));
|
798 |
reset_info->cpu = cpu; |
799 |
reset_info->prom_addr = hwdef->prom_addr; |
800 |
qemu_register_reset(main_cpu_reset, reset_info); |
801 |
|
802 |
return cpu;
|
803 |
} |
804 |
|
805 |
static void sun4uv_init(MemoryRegion *address_space_mem, |
806 |
ram_addr_t RAM_size, |
807 |
const char *boot_devices, |
808 |
const char *kernel_filename, const char *kernel_cmdline, |
809 |
const char *initrd_filename, const char *cpu_model, |
810 |
const struct hwdef *hwdef) |
811 |
{ |
812 |
SPARCCPU *cpu; |
813 |
M48t59State *nvram; |
814 |
unsigned int i; |
815 |
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
816 |
PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
817 |
ISABus *isa_bus; |
818 |
qemu_irq *ivec_irqs, *pbm_irqs; |
819 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
820 |
DriveInfo *fd[MAX_FD]; |
821 |
FWCfgState *fw_cfg; |
822 |
|
823 |
/* init CPUs */
|
824 |
cpu = cpu_devinit(cpu_model, hwdef); |
825 |
|
826 |
/* set up devices */
|
827 |
ram_init(0, RAM_size);
|
828 |
|
829 |
prom_init(hwdef->prom_addr, bios_name); |
830 |
|
831 |
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); |
832 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, |
833 |
&pci_bus3, &pbm_irqs); |
834 |
pci_vga_init(pci_bus); |
835 |
|
836 |
// XXX Should be pci_bus3
|
837 |
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
|
838 |
|
839 |
i = 0;
|
840 |
if (hwdef->console_serial_base) {
|
841 |
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
842 |
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
843 |
i++; |
844 |
} |
845 |
for(; i < MAX_SERIAL_PORTS; i++) {
|
846 |
if (serial_hds[i]) {
|
847 |
serial_isa_init(isa_bus, i, serial_hds[i]); |
848 |
} |
849 |
} |
850 |
|
851 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
852 |
if (parallel_hds[i]) {
|
853 |
parallel_init(isa_bus, i, parallel_hds[i]); |
854 |
} |
855 |
} |
856 |
|
857 |
for(i = 0; i < nb_nics; i++) |
858 |
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
859 |
|
860 |
ide_drive_get(hd, MAX_IDE_BUS); |
861 |
|
862 |
pci_cmd646_ide_init(pci_bus, hd, 1);
|
863 |
|
864 |
isa_create_simple(isa_bus, "i8042");
|
865 |
for(i = 0; i < MAX_FD; i++) { |
866 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
867 |
} |
868 |
fdctrl_init_isa(isa_bus, fd); |
869 |
nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
870 |
|
871 |
initrd_size = 0;
|
872 |
initrd_addr = 0;
|
873 |
kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
874 |
ram_size, &initrd_size, &initrd_addr, |
875 |
&kernel_addr, &kernel_entry); |
876 |
|
877 |
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
878 |
kernel_addr, kernel_size, |
879 |
kernel_cmdline, |
880 |
initrd_addr, initrd_size, |
881 |
/* XXX: need an option to load a NVRAM image */
|
882 |
0,
|
883 |
graphic_width, graphic_height, graphic_depth, |
884 |
(uint8_t *)&nd_table[0].macaddr);
|
885 |
|
886 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
887 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
888 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
889 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
890 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
891 |
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
892 |
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
893 |
if (kernel_cmdline) {
|
894 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
895 |
strlen(kernel_cmdline) + 1);
|
896 |
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
897 |
} else {
|
898 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
899 |
} |
900 |
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
901 |
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
902 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
903 |
|
904 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
905 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
906 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
907 |
|
908 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
909 |
} |
910 |
|
911 |
enum {
|
912 |
sun4u_id = 0,
|
913 |
sun4v_id = 64,
|
914 |
niagara_id, |
915 |
}; |
916 |
|
917 |
static const struct hwdef hwdefs[] = { |
918 |
/* Sun4u generic PC-like machine */
|
919 |
{ |
920 |
.default_cpu_model = "TI UltraSparc IIi",
|
921 |
.machine_id = sun4u_id, |
922 |
.prom_addr = 0x1fff0000000ULL,
|
923 |
.console_serial_base = 0,
|
924 |
}, |
925 |
/* Sun4v generic PC-like machine */
|
926 |
{ |
927 |
.default_cpu_model = "Sun UltraSparc T1",
|
928 |
.machine_id = sun4v_id, |
929 |
.prom_addr = 0x1fff0000000ULL,
|
930 |
.console_serial_base = 0,
|
931 |
}, |
932 |
/* Sun4v generic Niagara machine */
|
933 |
{ |
934 |
.default_cpu_model = "Sun UltraSparc T1",
|
935 |
.machine_id = niagara_id, |
936 |
.prom_addr = 0xfff0000000ULL,
|
937 |
.console_serial_base = 0xfff0c2c000ULL,
|
938 |
}, |
939 |
}; |
940 |
|
941 |
/* Sun4u hardware initialisation */
|
942 |
static void sun4u_init(QEMUMachineInitArgs *args) |
943 |
{ |
944 |
ram_addr_t RAM_size = args->ram_size; |
945 |
const char *cpu_model = args->cpu_model; |
946 |
const char *kernel_filename = args->kernel_filename; |
947 |
const char *kernel_cmdline = args->kernel_cmdline; |
948 |
const char *initrd_filename = args->initrd_filename; |
949 |
const char *boot_devices = args->boot_device; |
950 |
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
951 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
952 |
} |
953 |
|
954 |
/* Sun4v hardware initialisation */
|
955 |
static void sun4v_init(QEMUMachineInitArgs *args) |
956 |
{ |
957 |
ram_addr_t RAM_size = args->ram_size; |
958 |
const char *cpu_model = args->cpu_model; |
959 |
const char *kernel_filename = args->kernel_filename; |
960 |
const char *kernel_cmdline = args->kernel_cmdline; |
961 |
const char *initrd_filename = args->initrd_filename; |
962 |
const char *boot_devices = args->boot_device; |
963 |
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
964 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
965 |
} |
966 |
|
967 |
/* Niagara hardware initialisation */
|
968 |
static void niagara_init(QEMUMachineInitArgs *args) |
969 |
{ |
970 |
ram_addr_t RAM_size = args->ram_size; |
971 |
const char *cpu_model = args->cpu_model; |
972 |
const char *kernel_filename = args->kernel_filename; |
973 |
const char *kernel_cmdline = args->kernel_cmdline; |
974 |
const char *initrd_filename = args->initrd_filename; |
975 |
const char *boot_devices = args->boot_device; |
976 |
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
977 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
978 |
} |
979 |
|
980 |
static QEMUMachine sun4u_machine = {
|
981 |
.name = "sun4u",
|
982 |
.desc = "Sun4u platform",
|
983 |
.init = sun4u_init, |
984 |
.max_cpus = 1, // XXX for now |
985 |
.is_default = 1,
|
986 |
DEFAULT_MACHINE_OPTIONS, |
987 |
}; |
988 |
|
989 |
static QEMUMachine sun4v_machine = {
|
990 |
.name = "sun4v",
|
991 |
.desc = "Sun4v platform",
|
992 |
.init = sun4v_init, |
993 |
.max_cpus = 1, // XXX for now |
994 |
DEFAULT_MACHINE_OPTIONS, |
995 |
}; |
996 |
|
997 |
static QEMUMachine niagara_machine = {
|
998 |
.name = "Niagara",
|
999 |
.desc = "Sun4v platform, Niagara",
|
1000 |
.init = niagara_init, |
1001 |
.max_cpus = 1, // XXX for now |
1002 |
DEFAULT_MACHINE_OPTIONS, |
1003 |
}; |
1004 |
|
1005 |
static void sun4u_register_types(void) |
1006 |
{ |
1007 |
type_register_static(&ebus_info); |
1008 |
type_register_static(&prom_info); |
1009 |
type_register_static(&ram_info); |
1010 |
} |
1011 |
|
1012 |
static void sun4u_machine_init(void) |
1013 |
{ |
1014 |
qemu_register_machine(&sun4u_machine); |
1015 |
qemu_register_machine(&sun4v_machine); |
1016 |
qemu_register_machine(&niagara_machine); |
1017 |
} |
1018 |
|
1019 |
type_init(sun4u_register_types) |
1020 |
machine_init(sun4u_machine_init); |