root / hw / g364fb.c @ a8a358bf
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1 | 1fc3d392 | aurel32 | /*
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2 | 1fc3d392 | aurel32 | * QEMU G364 framebuffer Emulator.
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3 | 1fc3d392 | aurel32 | *
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4 | 0add30cf | aurel32 | * Copyright (c) 2007-2009 Herve Poussineau
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5 | 1fc3d392 | aurel32 | *
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6 | 1fc3d392 | aurel32 | * This program is free software; you can redistribute it and/or
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7 | 1fc3d392 | aurel32 | * modify it under the terms of the GNU General Public License as
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8 | 1fc3d392 | aurel32 | * published by the Free Software Foundation; either version 2 of
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9 | 1fc3d392 | aurel32 | * the License, or (at your option) any later version.
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10 | 1fc3d392 | aurel32 | *
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11 | 1fc3d392 | aurel32 | * This program is distributed in the hope that it will be useful,
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12 | 1fc3d392 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 1fc3d392 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 1fc3d392 | aurel32 | * GNU General Public License for more details.
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15 | 1fc3d392 | aurel32 | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | 1fc3d392 | aurel32 | */
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19 | 1fc3d392 | aurel32 | |
20 | 1fc3d392 | aurel32 | #include "hw.h" |
21 | cd5158ea | aurel32 | #include "mips.h" |
22 | 1fc3d392 | aurel32 | #include "console.h" |
23 | 1fc3d392 | aurel32 | #include "pixel_ops.h" |
24 | 1fc3d392 | aurel32 | |
25 | 1fc3d392 | aurel32 | //#define DEBUG_G364
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26 | 1fc3d392 | aurel32 | |
27 | 0add30cf | aurel32 | #ifdef DEBUG_G364
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28 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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29 | 001faf32 | Blue Swirl | do { printf("g364: " fmt , ## __VA_ARGS__); } while (0) |
30 | 0add30cf | aurel32 | #else
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31 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
32 | 0add30cf | aurel32 | #endif
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33 | 001faf32 | Blue Swirl | #define BADF(fmt, ...) \
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34 | 001faf32 | Blue Swirl | do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0) |
35 | 0add30cf | aurel32 | |
36 | 1fc3d392 | aurel32 | typedef struct G364State { |
37 | 0add30cf | aurel32 | /* hardware */
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38 | 0add30cf | aurel32 | uint8_t *vram; |
39 | 0add30cf | aurel32 | ram_addr_t vram_offset; |
40 | 0add30cf | aurel32 | int vram_size;
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41 | 0add30cf | aurel32 | qemu_irq irq; |
42 | 0add30cf | aurel32 | /* registers */
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43 | 0add30cf | aurel32 | uint8_t color_palette[256][3]; |
44 | 0add30cf | aurel32 | uint8_t cursor_palette[3][3]; |
45 | 0add30cf | aurel32 | uint16_t cursor[512];
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46 | 0add30cf | aurel32 | uint32_t cursor_position; |
47 | 1fc3d392 | aurel32 | uint32_t ctla; |
48 | 0add30cf | aurel32 | uint32_t top_of_screen; |
49 | 0add30cf | aurel32 | uint32_t width, height; /* in pixels */
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50 | 1fc3d392 | aurel32 | /* display refresh support */
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51 | 1fc3d392 | aurel32 | DisplayState *ds; |
52 | 0add30cf | aurel32 | int depth;
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53 | 0add30cf | aurel32 | int blanked;
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54 | 1fc3d392 | aurel32 | } G364State; |
55 | 1fc3d392 | aurel32 | |
56 | 0add30cf | aurel32 | #define REG_ID 0x000000 |
57 | 0add30cf | aurel32 | #define REG_BOOT 0x080000 |
58 | 0add30cf | aurel32 | #define REG_DISPLAY 0x080118 |
59 | 0add30cf | aurel32 | #define REG_VDISPLAY 0x080150 |
60 | 0add30cf | aurel32 | #define REG_CTLA 0x080300 |
61 | 0add30cf | aurel32 | #define REG_TOP 0x080400 |
62 | 0add30cf | aurel32 | #define REG_CURS_PAL 0x080508 |
63 | 0add30cf | aurel32 | #define REG_CURS_POS 0x080638 |
64 | 0add30cf | aurel32 | #define REG_CLR_PAL 0x080800 |
65 | 0add30cf | aurel32 | #define REG_CURS_PAT 0x081000 |
66 | 0add30cf | aurel32 | #define REG_RESET 0x180000 |
67 | 0add30cf | aurel32 | |
68 | 0add30cf | aurel32 | #define CTLA_FORCE_BLANK 0x00000400 |
69 | 0add30cf | aurel32 | #define CTLA_NO_CURSOR 0x00800000 |
70 | 0add30cf | aurel32 | |
71 | 0add30cf | aurel32 | static inline int check_dirty(ram_addr_t page) |
72 | 0add30cf | aurel32 | { |
73 | 0add30cf | aurel32 | return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
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74 | 0add30cf | aurel32 | } |
75 | 0add30cf | aurel32 | |
76 | 0add30cf | aurel32 | static inline void reset_dirty(G364State *s, |
77 | 0add30cf | aurel32 | ram_addr_t page_min, ram_addr_t page_max) |
78 | 0add30cf | aurel32 | { |
79 | 0add30cf | aurel32 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
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80 | 0add30cf | aurel32 | VGA_DIRTY_FLAG); |
81 | 0add30cf | aurel32 | } |
82 | 0add30cf | aurel32 | |
83 | 0add30cf | aurel32 | static void g364fb_draw_graphic8(G364State *s) |
84 | 1fc3d392 | aurel32 | { |
85 | 0add30cf | aurel32 | int i, w;
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86 | 0add30cf | aurel32 | uint8_t *vram; |
87 | 0add30cf | aurel32 | uint8_t *data_display, *dd; |
88 | 0add30cf | aurel32 | ram_addr_t page, page_min, page_max; |
89 | 0add30cf | aurel32 | int x, y;
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90 | 0add30cf | aurel32 | int xmin, xmax;
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91 | 0add30cf | aurel32 | int ymin, ymax;
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92 | 0add30cf | aurel32 | int xcursor, ycursor;
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93 | 0add30cf | aurel32 | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); |
94 | 0add30cf | aurel32 | |
95 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
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96 | 1fc3d392 | aurel32 | case 8: |
97 | 0add30cf | aurel32 | rgb_to_pixel = rgb_to_pixel8; |
98 | 0add30cf | aurel32 | w = 1;
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99 | 1fc3d392 | aurel32 | break;
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100 | 1fc3d392 | aurel32 | case 15: |
101 | 0add30cf | aurel32 | rgb_to_pixel = rgb_to_pixel15; |
102 | 0add30cf | aurel32 | w = 2;
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103 | 1fc3d392 | aurel32 | break;
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104 | 1fc3d392 | aurel32 | case 16: |
105 | 0add30cf | aurel32 | rgb_to_pixel = rgb_to_pixel16; |
106 | 0add30cf | aurel32 | w = 2;
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107 | 1fc3d392 | aurel32 | break;
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108 | 1fc3d392 | aurel32 | case 32: |
109 | 0add30cf | aurel32 | rgb_to_pixel = rgb_to_pixel32; |
110 | 0add30cf | aurel32 | w = 4;
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111 | 1fc3d392 | aurel32 | break;
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112 | 1fc3d392 | aurel32 | default:
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113 | 0add30cf | aurel32 | BADF("unknown host depth %d\n", ds_get_bits_per_pixel(s->ds));
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114 | 1fc3d392 | aurel32 | return;
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115 | 1fc3d392 | aurel32 | } |
116 | 1fc3d392 | aurel32 | |
117 | 0add30cf | aurel32 | page = s->vram_offset; |
118 | 0add30cf | aurel32 | page_min = (ram_addr_t)-1;
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119 | 0add30cf | aurel32 | page_max = 0;
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120 | 0add30cf | aurel32 | |
121 | 0add30cf | aurel32 | x = y = 0;
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122 | 0add30cf | aurel32 | xmin = s->width; |
123 | 0add30cf | aurel32 | xmax = 0;
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124 | 0add30cf | aurel32 | ymin = s->height; |
125 | 0add30cf | aurel32 | ymax = 0;
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126 | 0add30cf | aurel32 | |
127 | 0add30cf | aurel32 | if (!(s->ctla & CTLA_NO_CURSOR)) {
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128 | 0add30cf | aurel32 | xcursor = s->cursor_position >> 12;
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129 | 0add30cf | aurel32 | ycursor = s->cursor_position & 0xfff;
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130 | 0add30cf | aurel32 | } else {
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131 | 0add30cf | aurel32 | xcursor = ycursor = -65;
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132 | 0add30cf | aurel32 | } |
133 | 0add30cf | aurel32 | |
134 | 0add30cf | aurel32 | vram = s->vram + s->top_of_screen; |
135 | 0add30cf | aurel32 | /* XXX: out of range in vram? */
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136 | 0add30cf | aurel32 | data_display = dd = ds_get_data(s->ds); |
137 | 0add30cf | aurel32 | while (y < s->height) {
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138 | 0add30cf | aurel32 | if (check_dirty(page)) {
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139 | 0add30cf | aurel32 | if (y < ymin)
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140 | 0add30cf | aurel32 | ymin = ymax = y; |
141 | 0add30cf | aurel32 | if (page_min == (ram_addr_t)-1) |
142 | 0add30cf | aurel32 | page_min = page; |
143 | 0add30cf | aurel32 | page_max = page; |
144 | 0add30cf | aurel32 | if (x < xmin)
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145 | 0add30cf | aurel32 | xmin = x; |
146 | 0add30cf | aurel32 | for (i = 0; i < TARGET_PAGE_SIZE; i++) { |
147 | 0add30cf | aurel32 | uint8_t index; |
148 | 0add30cf | aurel32 | unsigned int color; |
149 | 0add30cf | aurel32 | if (unlikely((y >= ycursor && y < ycursor + 64) && |
150 | 0add30cf | aurel32 | (x >= xcursor && x < xcursor + 64))) {
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151 | 0add30cf | aurel32 | /* pointer area */
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152 | 0add30cf | aurel32 | int xdiff = x - xcursor;
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153 | 0add30cf | aurel32 | uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; |
154 | 0add30cf | aurel32 | int op = (curs >> ((xdiff & 7) * 2)) & 3; |
155 | 0add30cf | aurel32 | if (likely(op == 0)) { |
156 | 0add30cf | aurel32 | /* transparent */
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157 | 0add30cf | aurel32 | index = *vram; |
158 | 0add30cf | aurel32 | color = (*rgb_to_pixel)( |
159 | 0add30cf | aurel32 | s->color_palette[index][0],
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160 | 0add30cf | aurel32 | s->color_palette[index][1],
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161 | 0add30cf | aurel32 | s->color_palette[index][2]);
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162 | 0add30cf | aurel32 | } else {
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163 | 0add30cf | aurel32 | /* get cursor color */
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164 | 0add30cf | aurel32 | index = op - 1;
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165 | 0add30cf | aurel32 | color = (*rgb_to_pixel)( |
166 | 0add30cf | aurel32 | s->cursor_palette[index][0],
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167 | 0add30cf | aurel32 | s->cursor_palette[index][1],
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168 | 0add30cf | aurel32 | s->cursor_palette[index][2]);
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169 | 0add30cf | aurel32 | } |
170 | 0add30cf | aurel32 | } else {
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171 | 0add30cf | aurel32 | /* normal area */
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172 | 0add30cf | aurel32 | index = *vram; |
173 | 0add30cf | aurel32 | color = (*rgb_to_pixel)( |
174 | 0add30cf | aurel32 | s->color_palette[index][0],
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175 | 0add30cf | aurel32 | s->color_palette[index][1],
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176 | 0add30cf | aurel32 | s->color_palette[index][2]);
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177 | 0add30cf | aurel32 | } |
178 | 0add30cf | aurel32 | memcpy(dd, &color, w); |
179 | 0add30cf | aurel32 | dd += w; |
180 | 0add30cf | aurel32 | x++; |
181 | 0add30cf | aurel32 | vram++; |
182 | 0add30cf | aurel32 | if (x == s->width) {
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183 | 0add30cf | aurel32 | xmax = s->width - 1;
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184 | 0add30cf | aurel32 | y++; |
185 | 0add30cf | aurel32 | if (y == s->height) {
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186 | 0add30cf | aurel32 | ymax = s->height - 1;
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187 | 0add30cf | aurel32 | goto done;
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188 | 0add30cf | aurel32 | } |
189 | 0add30cf | aurel32 | data_display = dd = data_display + ds_get_linesize(s->ds); |
190 | 0add30cf | aurel32 | xmin = 0;
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191 | 0add30cf | aurel32 | x = 0;
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192 | 0add30cf | aurel32 | } |
193 | 0add30cf | aurel32 | } |
194 | 0add30cf | aurel32 | if (x > xmax)
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195 | 0add30cf | aurel32 | xmax = x; |
196 | 0add30cf | aurel32 | if (y > ymax)
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197 | 0add30cf | aurel32 | ymax = y; |
198 | 0add30cf | aurel32 | } else {
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199 | 0add30cf | aurel32 | int dy;
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200 | 0add30cf | aurel32 | if (page_min != (ram_addr_t)-1) { |
201 | 0add30cf | aurel32 | reset_dirty(s, page_min, page_max); |
202 | 0add30cf | aurel32 | page_min = (ram_addr_t)-1;
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203 | 0add30cf | aurel32 | page_max = 0;
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204 | 0add30cf | aurel32 | dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
205 | 0add30cf | aurel32 | xmin = s->width; |
206 | 0add30cf | aurel32 | xmax = 0;
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207 | 0add30cf | aurel32 | ymin = s->height; |
208 | 0add30cf | aurel32 | ymax = 0;
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209 | 0add30cf | aurel32 | } |
210 | 0add30cf | aurel32 | x += TARGET_PAGE_SIZE; |
211 | 0add30cf | aurel32 | dy = x / s->width; |
212 | 0add30cf | aurel32 | x = x % s->width; |
213 | 0add30cf | aurel32 | y += dy; |
214 | 0add30cf | aurel32 | vram += TARGET_PAGE_SIZE; |
215 | 0add30cf | aurel32 | data_display += dy * ds_get_linesize(s->ds); |
216 | 0add30cf | aurel32 | dd = data_display + x * w; |
217 | 0add30cf | aurel32 | } |
218 | 0add30cf | aurel32 | page += TARGET_PAGE_SIZE; |
219 | 0add30cf | aurel32 | } |
220 | 0add30cf | aurel32 | |
221 | 0add30cf | aurel32 | done:
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222 | 0add30cf | aurel32 | if (page_min != (ram_addr_t)-1) { |
223 | 0add30cf | aurel32 | dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
224 | 0add30cf | aurel32 | reset_dirty(s, page_min, page_max); |
225 | 0add30cf | aurel32 | } |
226 | 1fc3d392 | aurel32 | } |
227 | 1fc3d392 | aurel32 | |
228 | 0add30cf | aurel32 | static void g364fb_draw_blank(G364State *s) |
229 | 1fc3d392 | aurel32 | { |
230 | 1fc3d392 | aurel32 | int i, w;
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231 | 1fc3d392 | aurel32 | uint8_t *d; |
232 | 1fc3d392 | aurel32 | |
233 | 0add30cf | aurel32 | if (s->blanked) {
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234 | 0add30cf | aurel32 | /* Screen is already blank. No need to redraw it */
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235 | 1fc3d392 | aurel32 | return;
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236 | 0add30cf | aurel32 | } |
237 | 1fc3d392 | aurel32 | |
238 | 0add30cf | aurel32 | w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); |
239 | 0e1f5a0c | aliguori | d = ds_get_data(s->ds); |
240 | 0add30cf | aurel32 | for (i = 0; i < s->height; i++) { |
241 | 1fc3d392 | aurel32 | memset(d, 0, w);
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242 | 0e1f5a0c | aliguori | d += ds_get_linesize(s->ds); |
243 | 1fc3d392 | aurel32 | } |
244 | 221bb2d5 | aurel32 | |
245 | 0add30cf | aurel32 | dpy_update(s->ds, 0, 0, s->width, s->height); |
246 | 0add30cf | aurel32 | s->blanked = 1;
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247 | 1fc3d392 | aurel32 | } |
248 | 1fc3d392 | aurel32 | |
249 | 1fc3d392 | aurel32 | static void g364fb_update_display(void *opaque) |
250 | 1fc3d392 | aurel32 | { |
251 | 1fc3d392 | aurel32 | G364State *s = opaque; |
252 | 1fc3d392 | aurel32 | |
253 | 0add30cf | aurel32 | if (s->width == 0 || s->height == 0) |
254 | 221bb2d5 | aurel32 | return;
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255 | 221bb2d5 | aurel32 | |
256 | 0add30cf | aurel32 | if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
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257 | 0add30cf | aurel32 | qemu_console_resize(s->ds, s->width, s->height); |
258 | 221bb2d5 | aurel32 | } |
259 | 0add30cf | aurel32 | |
260 | 0add30cf | aurel32 | if (s->ctla & CTLA_FORCE_BLANK) {
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261 | 0add30cf | aurel32 | g364fb_draw_blank(s); |
262 | 0add30cf | aurel32 | } else if (s->depth == 8) { |
263 | 0add30cf | aurel32 | g364fb_draw_graphic8(s); |
264 | 0add30cf | aurel32 | } else {
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265 | 0add30cf | aurel32 | BADF("unknown guest depth %d\n", s->depth);
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266 | 1fc3d392 | aurel32 | } |
267 | 0add30cf | aurel32 | |
268 | 0add30cf | aurel32 | qemu_irq_raise(s->irq); |
269 | 1fc3d392 | aurel32 | } |
270 | 1fc3d392 | aurel32 | |
271 | 0add30cf | aurel32 | static void inline g364fb_invalidate_display(void *opaque) |
272 | 1fc3d392 | aurel32 | { |
273 | 1fc3d392 | aurel32 | G364State *s = opaque; |
274 | 0add30cf | aurel32 | int i;
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275 | 0add30cf | aurel32 | |
276 | 0add30cf | aurel32 | s->blanked = 0;
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277 | 0add30cf | aurel32 | for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) { |
278 | 0add30cf | aurel32 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
279 | 0add30cf | aurel32 | } |
280 | 1fc3d392 | aurel32 | } |
281 | 1fc3d392 | aurel32 | |
282 | 1fc3d392 | aurel32 | static void g364fb_reset(void *opaque) |
283 | 1fc3d392 | aurel32 | { |
284 | 1fc3d392 | aurel32 | G364State *s = opaque; |
285 | 0add30cf | aurel32 | qemu_irq_lower(s->irq); |
286 | 0add30cf | aurel32 | |
287 | 0add30cf | aurel32 | memset(s->color_palette, 0, sizeof(s->color_palette)); |
288 | 0add30cf | aurel32 | memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); |
289 | 0add30cf | aurel32 | memset(s->cursor, 0, sizeof(s->cursor)); |
290 | 0add30cf | aurel32 | s->cursor_position = 0;
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291 | 0add30cf | aurel32 | s->ctla = 0;
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292 | 0add30cf | aurel32 | s->top_of_screen = 0;
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293 | 0add30cf | aurel32 | s->width = s->height = 0;
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294 | 0add30cf | aurel32 | memset(s->vram, 0, s->vram_size);
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295 | 0add30cf | aurel32 | g364fb_invalidate_display(opaque); |
296 | 1fc3d392 | aurel32 | } |
297 | 1fc3d392 | aurel32 | |
298 | 1fc3d392 | aurel32 | static void g364fb_screen_dump(void *opaque, const char *filename) |
299 | 1fc3d392 | aurel32 | { |
300 | 1fc3d392 | aurel32 | G364State *s = opaque; |
301 | 1fc3d392 | aurel32 | int y, x;
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302 | 1fc3d392 | aurel32 | uint8_t index; |
303 | 1fc3d392 | aurel32 | uint8_t *data_buffer; |
304 | 1fc3d392 | aurel32 | FILE *f; |
305 | 1fc3d392 | aurel32 | |
306 | 0add30cf | aurel32 | if (s->depth != 8) { |
307 | 0add30cf | aurel32 | BADF("unknown guest depth %d\n", s->depth);
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308 | 0add30cf | aurel32 | return;
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309 | 0add30cf | aurel32 | } |
310 | 0add30cf | aurel32 | |
311 | 1fc3d392 | aurel32 | f = fopen(filename, "wb");
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312 | 1fc3d392 | aurel32 | if (!f)
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313 | 1fc3d392 | aurel32 | return;
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314 | 1fc3d392 | aurel32 | |
315 | 0add30cf | aurel32 | if (s->ctla & CTLA_FORCE_BLANK) {
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316 | 0add30cf | aurel32 | /* blank screen */
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317 | 0add30cf | aurel32 | fprintf(f, "P4\n%d %d\n",
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318 | 0add30cf | aurel32 | s->width, s->height); |
319 | 0add30cf | aurel32 | for (y = 0; y < s->height; y++) |
320 | 0add30cf | aurel32 | for (x = 0; x < s->width; x++) |
321 | 0add30cf | aurel32 | fputc(0, f);
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322 | 0add30cf | aurel32 | } else {
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323 | 0add30cf | aurel32 | data_buffer = s->vram + s->top_of_screen; |
324 | 0add30cf | aurel32 | fprintf(f, "P6\n%d %d\n%d\n",
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325 | 0add30cf | aurel32 | s->width, s->height, 255);
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326 | 0add30cf | aurel32 | for (y = 0; y < s->height; y++) |
327 | 0add30cf | aurel32 | for (x = 0; x < s->width; x++, data_buffer++) { |
328 | 0add30cf | aurel32 | index = *data_buffer; |
329 | 0add30cf | aurel32 | fputc(s->color_palette[index][0], f);
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330 | 0add30cf | aurel32 | fputc(s->color_palette[index][1], f);
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331 | 0add30cf | aurel32 | fputc(s->color_palette[index][2], f);
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332 | 1fc3d392 | aurel32 | } |
333 | 0add30cf | aurel32 | } |
334 | 0add30cf | aurel32 | |
335 | 1fc3d392 | aurel32 | fclose(f); |
336 | 1fc3d392 | aurel32 | } |
337 | 1fc3d392 | aurel32 | |
338 | 1fc3d392 | aurel32 | /* called for accesses to io ports */
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339 | 0add30cf | aurel32 | static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr) |
340 | 1fc3d392 | aurel32 | { |
341 | 0add30cf | aurel32 | G364State *s = opaque; |
342 | 1fc3d392 | aurel32 | uint32_t val; |
343 | 1fc3d392 | aurel32 | |
344 | 0add30cf | aurel32 | if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
345 | 0add30cf | aurel32 | /* cursor pattern */
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346 | 0add30cf | aurel32 | int idx = (addr - REG_CURS_PAT) >> 3; |
347 | 0add30cf | aurel32 | val = s->cursor[idx]; |
348 | 0add30cf | aurel32 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
349 | 0add30cf | aurel32 | /* cursor palette */
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350 | 0add30cf | aurel32 | int idx = (addr - REG_CURS_PAL) >> 3; |
351 | 0add30cf | aurel32 | val = ((uint32_t)s->cursor_palette[idx][0] << 16); |
352 | 0add30cf | aurel32 | val |= ((uint32_t)s->cursor_palette[idx][1] << 8); |
353 | 0add30cf | aurel32 | val |= ((uint32_t)s->cursor_palette[idx][2] << 0); |
354 | 0add30cf | aurel32 | } else {
|
355 | 0add30cf | aurel32 | switch (addr) {
|
356 | 0add30cf | aurel32 | case REG_ID:
|
357 | 0add30cf | aurel32 | val = 0x10; /* Mips G364 */ |
358 | 0add30cf | aurel32 | break;
|
359 | 0add30cf | aurel32 | case REG_DISPLAY:
|
360 | 0add30cf | aurel32 | val = s->width / 4;
|
361 | 0add30cf | aurel32 | break;
|
362 | 0add30cf | aurel32 | case REG_VDISPLAY:
|
363 | 0add30cf | aurel32 | val = s->height * 2;
|
364 | 0add30cf | aurel32 | break;
|
365 | 0add30cf | aurel32 | case REG_CTLA:
|
366 | 0add30cf | aurel32 | val = s->ctla; |
367 | 0add30cf | aurel32 | break;
|
368 | 0add30cf | aurel32 | default:
|
369 | 0add30cf | aurel32 | { |
370 | 0add30cf | aurel32 | BADF("invalid read at [" TARGET_FMT_plx "]\n", addr); |
371 | 0add30cf | aurel32 | val = 0;
|
372 | 0add30cf | aurel32 | break;
|
373 | 0add30cf | aurel32 | } |
374 | 0add30cf | aurel32 | } |
375 | 1fc3d392 | aurel32 | } |
376 | 1fc3d392 | aurel32 | |
377 | 0add30cf | aurel32 | DPRINTF("read 0x%08x at [" TARGET_FMT_plx "]\n", val, addr); |
378 | 1fc3d392 | aurel32 | |
379 | 1fc3d392 | aurel32 | return val;
|
380 | 1fc3d392 | aurel32 | } |
381 | 1fc3d392 | aurel32 | |
382 | 1fc3d392 | aurel32 | static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr) |
383 | 1fc3d392 | aurel32 | { |
384 | 0add30cf | aurel32 | uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
385 | 0add30cf | aurel32 | if (addr & 0x2) |
386 | 0add30cf | aurel32 | return v >> 16; |
387 | 0add30cf | aurel32 | else
|
388 | 0add30cf | aurel32 | return v & 0xffff; |
389 | 1fc3d392 | aurel32 | } |
390 | 1fc3d392 | aurel32 | |
391 | 0add30cf | aurel32 | static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr) |
392 | 1fc3d392 | aurel32 | { |
393 | 0add30cf | aurel32 | uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
394 | 0add30cf | aurel32 | return (v >> (8 * (addr & 0x3))) & 0xff; |
395 | 1fc3d392 | aurel32 | } |
396 | 1fc3d392 | aurel32 | |
397 | 0add30cf | aurel32 | static void g364fb_update_depth(G364State *s) |
398 | 1fc3d392 | aurel32 | { |
399 | 0add30cf | aurel32 | const static int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; |
400 | 0add30cf | aurel32 | s->depth = depths[(s->ctla & 0x00700000) >> 20]; |
401 | 0add30cf | aurel32 | } |
402 | 1fc3d392 | aurel32 | |
403 | 0add30cf | aurel32 | static void g364_invalidate_cursor_position(G364State *s) |
404 | 0add30cf | aurel32 | { |
405 | 0add30cf | aurel32 | int ymin, ymax, start, end, i;
|
406 | 1fc3d392 | aurel32 | |
407 | 0add30cf | aurel32 | /* invalidate only near the cursor */
|
408 | 0add30cf | aurel32 | ymin = s->cursor_position & 0xfff;
|
409 | 0add30cf | aurel32 | ymax = MIN(s->height, ymin + 64);
|
410 | 0add30cf | aurel32 | start = ymin * ds_get_linesize(s->ds); |
411 | 0add30cf | aurel32 | end = (ymax + 1) * ds_get_linesize(s->ds);
|
412 | 1fc3d392 | aurel32 | |
413 | 0add30cf | aurel32 | for (i = start; i < end; i += TARGET_PAGE_SIZE) {
|
414 | 0add30cf | aurel32 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
415 | 0add30cf | aurel32 | } |
416 | 0add30cf | aurel32 | } |
417 | 0add30cf | aurel32 | |
418 | 0add30cf | aurel32 | static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
419 | 0add30cf | aurel32 | { |
420 | 0add30cf | aurel32 | G364State *s = opaque; |
421 | 0add30cf | aurel32 | |
422 | 0add30cf | aurel32 | DPRINTF("write 0x%08x at [" TARGET_FMT_plx "]\n", val, addr); |
423 | 0add30cf | aurel32 | |
424 | 0add30cf | aurel32 | if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { |
425 | 1fc3d392 | aurel32 | /* color palette */
|
426 | 0add30cf | aurel32 | int idx = (addr - REG_CLR_PAL) >> 3; |
427 | 0add30cf | aurel32 | s->color_palette[idx][0] = (val >> 16) & 0xff; |
428 | 0add30cf | aurel32 | s->color_palette[idx][1] = (val >> 8) & 0xff; |
429 | 0add30cf | aurel32 | s->color_palette[idx][2] = val & 0xff; |
430 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
431 | 0add30cf | aurel32 | } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
432 | 0add30cf | aurel32 | /* cursor pattern */
|
433 | 0add30cf | aurel32 | int idx = (addr - REG_CURS_PAT) >> 3; |
434 | 0add30cf | aurel32 | s->cursor[idx] = val; |
435 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
436 | 0add30cf | aurel32 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
437 | 0add30cf | aurel32 | /* cursor palette */
|
438 | 0add30cf | aurel32 | int idx = (addr - REG_CURS_PAL) >> 3; |
439 | 0add30cf | aurel32 | s->cursor_palette[idx][0] = (val >> 16) & 0xff; |
440 | 0add30cf | aurel32 | s->cursor_palette[idx][1] = (val >> 8) & 0xff; |
441 | 0add30cf | aurel32 | s->cursor_palette[idx][2] = val & 0xff; |
442 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
443 | 1fc3d392 | aurel32 | } else {
|
444 | 1fc3d392 | aurel32 | switch (addr) {
|
445 | 0add30cf | aurel32 | case REG_ID: /* Card identifier; read-only */ |
446 | 0add30cf | aurel32 | case REG_BOOT: /* Boot timing */ |
447 | 0add30cf | aurel32 | case 0x80108: /* Line timing: half sync */ |
448 | 0add30cf | aurel32 | case 0x80110: /* Line timing: back porch */ |
449 | 0add30cf | aurel32 | case 0x80120: /* Line timing: short display */ |
450 | 0add30cf | aurel32 | case 0x80128: /* Frame timing: broad pulse */ |
451 | 0add30cf | aurel32 | case 0x80130: /* Frame timing: v sync */ |
452 | 0add30cf | aurel32 | case 0x80138: /* Frame timing: v preequalise */ |
453 | 0add30cf | aurel32 | case 0x80140: /* Frame timing: v postequalise */ |
454 | 0add30cf | aurel32 | case 0x80148: /* Frame timing: v blank */ |
455 | 0add30cf | aurel32 | case 0x80158: /* Line timing: line time */ |
456 | 0add30cf | aurel32 | case 0x80160: /* Frame store: line start */ |
457 | 0add30cf | aurel32 | case 0x80168: /* vram cycle: mem init */ |
458 | 0add30cf | aurel32 | case 0x80170: /* vram cycle: transfer delay */ |
459 | 0add30cf | aurel32 | case 0x80200: /* vram cycle: mask register */ |
460 | 0add30cf | aurel32 | /* ignore */
|
461 | 0add30cf | aurel32 | break;
|
462 | 0add30cf | aurel32 | case REG_TOP:
|
463 | 0add30cf | aurel32 | s->top_of_screen = val; |
464 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
465 | 0add30cf | aurel32 | break;
|
466 | 0add30cf | aurel32 | case REG_DISPLAY:
|
467 | 0add30cf | aurel32 | s->width = val * 4;
|
468 | 1fc3d392 | aurel32 | break;
|
469 | 0add30cf | aurel32 | case REG_VDISPLAY:
|
470 | 0add30cf | aurel32 | s->height = val / 2;
|
471 | 1fc3d392 | aurel32 | break;
|
472 | 0add30cf | aurel32 | case REG_CTLA:
|
473 | 0add30cf | aurel32 | s->ctla = val; |
474 | 0add30cf | aurel32 | g364fb_update_depth(s); |
475 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
476 | 1fc3d392 | aurel32 | break;
|
477 | 0add30cf | aurel32 | case REG_CURS_POS:
|
478 | 0add30cf | aurel32 | g364_invalidate_cursor_position(s); |
479 | 0add30cf | aurel32 | s->cursor_position = val; |
480 | 0add30cf | aurel32 | g364_invalidate_cursor_position(s); |
481 | 0add30cf | aurel32 | break;
|
482 | 0add30cf | aurel32 | case REG_RESET:
|
483 | 0add30cf | aurel32 | g364fb_reset(s); |
484 | 1fc3d392 | aurel32 | break;
|
485 | 1fc3d392 | aurel32 | default:
|
486 | 0add30cf | aurel32 | BADF("invalid write of 0x%08x at [" TARGET_FMT_plx "]\n", val, addr); |
487 | 1fc3d392 | aurel32 | break;
|
488 | 1fc3d392 | aurel32 | } |
489 | 1fc3d392 | aurel32 | } |
490 | 0add30cf | aurel32 | qemu_irq_lower(s->irq); |
491 | 1fc3d392 | aurel32 | } |
492 | 1fc3d392 | aurel32 | |
493 | 1fc3d392 | aurel32 | static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
494 | 1fc3d392 | aurel32 | { |
495 | 0add30cf | aurel32 | uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
496 | 0add30cf | aurel32 | |
497 | 0add30cf | aurel32 | if (addr & 0x2) |
498 | 0add30cf | aurel32 | val = (val << 16) | (old_val & 0x0000ffff); |
499 | 0add30cf | aurel32 | else
|
500 | 0add30cf | aurel32 | val = val | (old_val & 0xffff0000);
|
501 | 0add30cf | aurel32 | g364fb_ctrl_writel(opaque, addr & ~0x3, val);
|
502 | 1fc3d392 | aurel32 | } |
503 | 1fc3d392 | aurel32 | |
504 | 0add30cf | aurel32 | static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
505 | 1fc3d392 | aurel32 | { |
506 | 0add30cf | aurel32 | uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
|
507 | 0add30cf | aurel32 | |
508 | 0add30cf | aurel32 | switch (addr & 3) { |
509 | 0add30cf | aurel32 | case 0: |
510 | 0add30cf | aurel32 | val = val | (old_val & 0xffffff00);
|
511 | 0add30cf | aurel32 | break;
|
512 | 0add30cf | aurel32 | case 1: |
513 | 0add30cf | aurel32 | val = (val << 8) | (old_val & 0xffff00ff); |
514 | 0add30cf | aurel32 | break;
|
515 | 0add30cf | aurel32 | case 2: |
516 | 0add30cf | aurel32 | val = (val << 16) | (old_val & 0xff00ffff); |
517 | 0add30cf | aurel32 | break;
|
518 | 0add30cf | aurel32 | case 3: |
519 | 0add30cf | aurel32 | val = (val << 24) | (old_val & 0x00ffffff); |
520 | 0add30cf | aurel32 | break;
|
521 | 0add30cf | aurel32 | } |
522 | 0add30cf | aurel32 | g364fb_ctrl_writel(opaque, addr & ~0x3, val);
|
523 | 1fc3d392 | aurel32 | } |
524 | 1fc3d392 | aurel32 | |
525 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = { |
526 | 1fc3d392 | aurel32 | g364fb_ctrl_readb, |
527 | 1fc3d392 | aurel32 | g364fb_ctrl_readw, |
528 | 1fc3d392 | aurel32 | g364fb_ctrl_readl, |
529 | 1fc3d392 | aurel32 | }; |
530 | 1fc3d392 | aurel32 | |
531 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = { |
532 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb, |
533 | 1fc3d392 | aurel32 | g364fb_ctrl_writew, |
534 | 1fc3d392 | aurel32 | g364fb_ctrl_writel, |
535 | 1fc3d392 | aurel32 | }; |
536 | 1fc3d392 | aurel32 | |
537 | 0add30cf | aurel32 | static int g364fb_load(QEMUFile *f, void *opaque, int version_id) |
538 | 1fc3d392 | aurel32 | { |
539 | 1fc3d392 | aurel32 | G364State *s = opaque; |
540 | 0add30cf | aurel32 | unsigned int i, vram_size; |
541 | 0add30cf | aurel32 | |
542 | 0add30cf | aurel32 | if (version_id != 1) |
543 | 0add30cf | aurel32 | return -EINVAL;
|
544 | 0add30cf | aurel32 | |
545 | 0add30cf | aurel32 | vram_size = qemu_get_be32(f); |
546 | 0add30cf | aurel32 | if (vram_size < s->vram_size)
|
547 | 0add30cf | aurel32 | return -EINVAL;
|
548 | 0add30cf | aurel32 | qemu_get_buffer(f, s->vram, s->vram_size); |
549 | 0add30cf | aurel32 | for (i = 0; i < 256; i++) |
550 | 0add30cf | aurel32 | qemu_get_buffer(f, s->color_palette[i], 3);
|
551 | 0add30cf | aurel32 | for (i = 0; i < 3; i++) |
552 | 0add30cf | aurel32 | qemu_get_buffer(f, s->cursor_palette[i], 3);
|
553 | 0add30cf | aurel32 | qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
|
554 | 0add30cf | aurel32 | s->cursor_position = qemu_get_be32(f); |
555 | 0add30cf | aurel32 | s->ctla = qemu_get_be32(f); |
556 | 0add30cf | aurel32 | s->top_of_screen = qemu_get_be32(f); |
557 | 0add30cf | aurel32 | s->width = qemu_get_be32(f); |
558 | 0add30cf | aurel32 | s->height = qemu_get_be32(f); |
559 | 0add30cf | aurel32 | |
560 | 0add30cf | aurel32 | /* force refresh */
|
561 | 0add30cf | aurel32 | g364fb_update_depth(s); |
562 | 0add30cf | aurel32 | g364fb_invalidate_display(s); |
563 | 1fc3d392 | aurel32 | |
564 | 0add30cf | aurel32 | return 0; |
565 | 1fc3d392 | aurel32 | } |
566 | 1fc3d392 | aurel32 | |
567 | 0add30cf | aurel32 | static void g364fb_save(QEMUFile *f, void *opaque) |
568 | 1fc3d392 | aurel32 | { |
569 | 1fc3d392 | aurel32 | G364State *s = opaque; |
570 | 0add30cf | aurel32 | int i;
|
571 | 0add30cf | aurel32 | |
572 | 0add30cf | aurel32 | qemu_put_be32(f, s->vram_size); |
573 | 0add30cf | aurel32 | qemu_put_buffer(f, s->vram, s->vram_size); |
574 | 0add30cf | aurel32 | for (i = 0; i < 256; i++) |
575 | 0add30cf | aurel32 | qemu_put_buffer(f, s->color_palette[i], 3);
|
576 | 0add30cf | aurel32 | for (i = 0; i < 3; i++) |
577 | 0add30cf | aurel32 | qemu_put_buffer(f, s->cursor_palette[i], 3);
|
578 | 0add30cf | aurel32 | qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
|
579 | 0add30cf | aurel32 | qemu_put_be32(f, s->cursor_position); |
580 | 0add30cf | aurel32 | qemu_put_be32(f, s->ctla); |
581 | 0add30cf | aurel32 | qemu_put_be32(f, s->top_of_screen); |
582 | 0add30cf | aurel32 | qemu_put_be32(f, s->width); |
583 | 0add30cf | aurel32 | qemu_put_be32(f, s->height); |
584 | 1fc3d392 | aurel32 | } |
585 | 1fc3d392 | aurel32 | |
586 | fbe1b595 | Paul Brook | int g364fb_mm_init(target_phys_addr_t vram_base,
|
587 | 0add30cf | aurel32 | target_phys_addr_t ctrl_base, int it_shift,
|
588 | 0add30cf | aurel32 | qemu_irq irq) |
589 | 1fc3d392 | aurel32 | { |
590 | 1fc3d392 | aurel32 | G364State *s; |
591 | 0add30cf | aurel32 | int io_ctrl;
|
592 | 1fc3d392 | aurel32 | |
593 | 1fc3d392 | aurel32 | s = qemu_mallocz(sizeof(G364State));
|
594 | 1fc3d392 | aurel32 | |
595 | fbe1b595 | Paul Brook | s->vram_size = 8 * 1024 * 1024; |
596 | fbe1b595 | Paul Brook | s->vram_offset = qemu_ram_alloc(s->vram_size); |
597 | b584726d | pbrook | s->vram = qemu_get_ram_ptr(s->vram_offset); |
598 | 0add30cf | aurel32 | s->irq = irq; |
599 | 1fc3d392 | aurel32 | |
600 | a08d4367 | Jan Kiszka | qemu_register_reset(g364fb_reset, s); |
601 | 0add30cf | aurel32 | register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s); |
602 | 1fc3d392 | aurel32 | g364fb_reset(s); |
603 | 1fc3d392 | aurel32 | |
604 | 3023f332 | aliguori | s->ds = graphic_console_init(g364fb_update_display, |
605 | 3023f332 | aliguori | g364fb_invalidate_display, |
606 | 3023f332 | aliguori | g364fb_screen_dump, NULL, s);
|
607 | 1fc3d392 | aurel32 | |
608 | 0add30cf | aurel32 | cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset); |
609 | 1fc3d392 | aurel32 | |
610 | 1eed09cb | Avi Kivity | io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s); |
611 | 0add30cf | aurel32 | cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
|
612 | 1fc3d392 | aurel32 | |
613 | 1fc3d392 | aurel32 | return 0; |
614 | 1fc3d392 | aurel32 | } |