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1 | 02eb84d0 | Michael S. Tsirkin | /*
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2 | 02eb84d0 | Michael S. Tsirkin | * MSI-X device support
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3 | 02eb84d0 | Michael S. Tsirkin | *
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4 | 02eb84d0 | Michael S. Tsirkin | * This module includes support for MSI-X in pci devices.
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5 | 02eb84d0 | Michael S. Tsirkin | *
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6 | 02eb84d0 | Michael S. Tsirkin | * Author: Michael S. Tsirkin <mst@redhat.com>
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7 | 02eb84d0 | Michael S. Tsirkin | *
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8 | 02eb84d0 | Michael S. Tsirkin | * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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9 | 02eb84d0 | Michael S. Tsirkin | *
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10 | 02eb84d0 | Michael S. Tsirkin | * This work is licensed under the terms of the GNU GPL, version 2. See
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11 | 02eb84d0 | Michael S. Tsirkin | * the COPYING file in the top-level directory.
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12 | 02eb84d0 | Michael S. Tsirkin | */
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13 | 02eb84d0 | Michael S. Tsirkin | |
14 | 02eb84d0 | Michael S. Tsirkin | #include "hw.h" |
15 | 02eb84d0 | Michael S. Tsirkin | #include "msix.h" |
16 | 02eb84d0 | Michael S. Tsirkin | #include "pci.h" |
17 | 02eb84d0 | Michael S. Tsirkin | |
18 | 02eb84d0 | Michael S. Tsirkin | /* Declaration from linux/pci_regs.h */
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19 | 02eb84d0 | Michael S. Tsirkin | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
20 | 02eb84d0 | Michael S. Tsirkin | #define PCI_MSIX_FLAGS 2 /* Table at lower 11 bits */ |
21 | 02eb84d0 | Michael S. Tsirkin | #define PCI_MSIX_FLAGS_QSIZE 0x7FF |
22 | 02eb84d0 | Michael S. Tsirkin | #define PCI_MSIX_FLAGS_ENABLE (1 << 15) |
23 | 02eb84d0 | Michael S. Tsirkin | #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
24 | 02eb84d0 | Michael S. Tsirkin | |
25 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X capability structure */
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26 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_TABLE_OFFSET 4 |
27 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_PBA_OFFSET 8 |
28 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_CAP_LENGTH 12 |
29 | 02eb84d0 | Michael S. Tsirkin | |
30 | 02eb84d0 | Michael S. Tsirkin | /* MSI enable bit is in byte 1 in FLAGS register */
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31 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) |
32 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) |
33 | 02eb84d0 | Michael S. Tsirkin | |
34 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X table format */
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35 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MSG_ADDR 0 |
36 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MSG_UPPER_ADDR 4 |
37 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MSG_DATA 8 |
38 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_VECTOR_CTRL 12 |
39 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENTRY_SIZE 16 |
40 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_VECTOR_MASK 0x1 |
41 | 02eb84d0 | Michael S. Tsirkin | |
42 | 02eb84d0 | Michael S. Tsirkin | /* How much space does an MSIX table need. */
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43 | 02eb84d0 | Michael S. Tsirkin | /* The spec requires giving the table structure
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44 | 02eb84d0 | Michael S. Tsirkin | * a 4K aligned region all by itself. Align it to
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45 | 02eb84d0 | Michael S. Tsirkin | * target pages so that drivers can do passthrough
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46 | 02eb84d0 | Michael S. Tsirkin | * on the rest of the region. */
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47 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_PAGE_SIZE TARGET_PAGE_ALIGN(0x1000) |
48 | 02eb84d0 | Michael S. Tsirkin | /* Reserve second half of the page for pending bits */
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49 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2) |
50 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MAX_ENTRIES 32 |
51 | 02eb84d0 | Michael S. Tsirkin | |
52 | 02eb84d0 | Michael S. Tsirkin | |
53 | 02eb84d0 | Michael S. Tsirkin | #ifdef MSIX_DEBUG
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54 | 02eb84d0 | Michael S. Tsirkin | #define DEBUG(fmt, ...) \
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55 | 02eb84d0 | Michael S. Tsirkin | do { \
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56 | 02eb84d0 | Michael S. Tsirkin | fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
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57 | 02eb84d0 | Michael S. Tsirkin | } while (0) |
58 | 02eb84d0 | Michael S. Tsirkin | #else
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59 | 02eb84d0 | Michael S. Tsirkin | #define DEBUG(fmt, ...) do { } while(0) |
60 | 02eb84d0 | Michael S. Tsirkin | #endif
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61 | 02eb84d0 | Michael S. Tsirkin | |
62 | 02eb84d0 | Michael S. Tsirkin | /* Flag for interrupt controller to declare MSI-X support */
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63 | 02eb84d0 | Michael S. Tsirkin | int msix_supported;
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64 | 02eb84d0 | Michael S. Tsirkin | |
65 | 02eb84d0 | Michael S. Tsirkin | /* Add MSI-X capability to the config space for the device. */
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66 | 02eb84d0 | Michael S. Tsirkin | /* Given a bar and its size, add MSI-X table on top of it
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67 | 02eb84d0 | Michael S. Tsirkin | * and fill MSI-X capability in the config space.
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68 | 02eb84d0 | Michael S. Tsirkin | * Original bar size must be a power of 2 or 0.
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69 | 02eb84d0 | Michael S. Tsirkin | * New bar size is returned. */
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70 | 02eb84d0 | Michael S. Tsirkin | static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, |
71 | 02eb84d0 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
72 | 02eb84d0 | Michael S. Tsirkin | { |
73 | 02eb84d0 | Michael S. Tsirkin | int config_offset;
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74 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config; |
75 | 02eb84d0 | Michael S. Tsirkin | uint32_t new_size; |
76 | 02eb84d0 | Michael S. Tsirkin | |
77 | 02eb84d0 | Michael S. Tsirkin | if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) |
78 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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79 | 02eb84d0 | Michael S. Tsirkin | if (bar_size > 0x80000000) |
80 | 02eb84d0 | Michael S. Tsirkin | return -ENOSPC;
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81 | 02eb84d0 | Michael S. Tsirkin | |
82 | 02eb84d0 | Michael S. Tsirkin | /* Add space for MSI-X structures */
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83 | 02eb84d0 | Michael S. Tsirkin | if (!bar_size)
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84 | 02eb84d0 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE; |
85 | 02eb84d0 | Michael S. Tsirkin | else if (bar_size < MSIX_PAGE_SIZE) { |
86 | 02eb84d0 | Michael S. Tsirkin | bar_size = MSIX_PAGE_SIZE; |
87 | 02eb84d0 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE * 2;
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88 | 02eb84d0 | Michael S. Tsirkin | } else
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89 | 02eb84d0 | Michael S. Tsirkin | new_size = bar_size * 2;
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90 | 02eb84d0 | Michael S. Tsirkin | |
91 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_bar_size = new_size; |
92 | 02eb84d0 | Michael S. Tsirkin | config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
93 | 02eb84d0 | Michael S. Tsirkin | if (config_offset < 0) |
94 | 02eb84d0 | Michael S. Tsirkin | return config_offset;
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95 | 02eb84d0 | Michael S. Tsirkin | config = pdev->config + config_offset; |
96 | 02eb84d0 | Michael S. Tsirkin | |
97 | 02eb84d0 | Michael S. Tsirkin | pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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98 | 02eb84d0 | Michael S. Tsirkin | /* Table on top of BAR */
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99 | 02eb84d0 | Michael S. Tsirkin | pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr); |
100 | 02eb84d0 | Michael S. Tsirkin | /* Pending bits on top of that */
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101 | 02eb84d0 | Michael S. Tsirkin | pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) | |
102 | 02eb84d0 | Michael S. Tsirkin | bar_nr); |
103 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_cap = config_offset; |
104 | 02eb84d0 | Michael S. Tsirkin | /* Make flags bit writeable. */
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105 | 02eb84d0 | Michael S. Tsirkin | pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK; |
106 | 02eb84d0 | Michael S. Tsirkin | return 0; |
107 | 02eb84d0 | Michael S. Tsirkin | } |
108 | 02eb84d0 | Michael S. Tsirkin | |
109 | 02eb84d0 | Michael S. Tsirkin | static void msix_free_irq_entries(PCIDevice *dev) |
110 | 02eb84d0 | Michael S. Tsirkin | { |
111 | 02eb84d0 | Michael S. Tsirkin | int vector;
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112 | 02eb84d0 | Michael S. Tsirkin | |
113 | 02eb84d0 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) |
114 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used[vector] = 0;
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115 | 02eb84d0 | Michael S. Tsirkin | } |
116 | 02eb84d0 | Michael S. Tsirkin | |
117 | 02eb84d0 | Michael S. Tsirkin | /* Handle MSI-X capability config write. */
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118 | 02eb84d0 | Michael S. Tsirkin | void msix_write_config(PCIDevice *dev, uint32_t addr,
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119 | 02eb84d0 | Michael S. Tsirkin | uint32_t val, int len)
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120 | 02eb84d0 | Michael S. Tsirkin | { |
121 | 02eb84d0 | Michael S. Tsirkin | unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
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122 | 02eb84d0 | Michael S. Tsirkin | if (addr + len <= enable_pos || addr > enable_pos)
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123 | 02eb84d0 | Michael S. Tsirkin | return;
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124 | 02eb84d0 | Michael S. Tsirkin | |
125 | 02eb84d0 | Michael S. Tsirkin | if (msix_enabled(dev))
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126 | 02eb84d0 | Michael S. Tsirkin | qemu_set_irq(dev->irq[0], 0); |
127 | 02eb84d0 | Michael S. Tsirkin | } |
128 | 02eb84d0 | Michael S. Tsirkin | |
129 | 02eb84d0 | Michael S. Tsirkin | static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) |
130 | 02eb84d0 | Michael S. Tsirkin | { |
131 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
132 | 02eb84d0 | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); |
133 | 02eb84d0 | Michael S. Tsirkin | void *page = dev->msix_table_page;
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134 | 02eb84d0 | Michael S. Tsirkin | uint32_t val = 0;
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135 | 02eb84d0 | Michael S. Tsirkin | |
136 | 02eb84d0 | Michael S. Tsirkin | memcpy(&val, (void *)((char *)page + offset), 4); |
137 | 02eb84d0 | Michael S. Tsirkin | |
138 | 02eb84d0 | Michael S. Tsirkin | return val;
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139 | 02eb84d0 | Michael S. Tsirkin | } |
140 | 02eb84d0 | Michael S. Tsirkin | |
141 | 02eb84d0 | Michael S. Tsirkin | static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr) |
142 | 02eb84d0 | Michael S. Tsirkin | { |
143 | 02eb84d0 | Michael S. Tsirkin | fprintf(stderr, "MSI-X: only dword read is allowed!\n");
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144 | 02eb84d0 | Michael S. Tsirkin | return 0; |
145 | 02eb84d0 | Michael S. Tsirkin | } |
146 | 02eb84d0 | Michael S. Tsirkin | |
147 | 02eb84d0 | Michael S. Tsirkin | static uint8_t msix_pending_mask(int vector) |
148 | 02eb84d0 | Michael S. Tsirkin | { |
149 | 02eb84d0 | Michael S. Tsirkin | return 1 << (vector % 8); |
150 | 02eb84d0 | Michael S. Tsirkin | } |
151 | 02eb84d0 | Michael S. Tsirkin | |
152 | 02eb84d0 | Michael S. Tsirkin | static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) |
153 | 02eb84d0 | Michael S. Tsirkin | { |
154 | 02eb84d0 | Michael S. Tsirkin | return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8; |
155 | 02eb84d0 | Michael S. Tsirkin | } |
156 | 02eb84d0 | Michael S. Tsirkin | |
157 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_pending(PCIDevice *dev, int vector) |
158 | 02eb84d0 | Michael S. Tsirkin | { |
159 | 02eb84d0 | Michael S. Tsirkin | return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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160 | 02eb84d0 | Michael S. Tsirkin | } |
161 | 02eb84d0 | Michael S. Tsirkin | |
162 | 02eb84d0 | Michael S. Tsirkin | static void msix_set_pending(PCIDevice *dev, int vector) |
163 | 02eb84d0 | Michael S. Tsirkin | { |
164 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) |= msix_pending_mask(vector); |
165 | 02eb84d0 | Michael S. Tsirkin | } |
166 | 02eb84d0 | Michael S. Tsirkin | |
167 | 02eb84d0 | Michael S. Tsirkin | static void msix_clr_pending(PCIDevice *dev, int vector) |
168 | 02eb84d0 | Michael S. Tsirkin | { |
169 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); |
170 | 02eb84d0 | Michael S. Tsirkin | } |
171 | 02eb84d0 | Michael S. Tsirkin | |
172 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_masked(PCIDevice *dev, int vector) |
173 | 02eb84d0 | Michael S. Tsirkin | { |
174 | 02eb84d0 | Michael S. Tsirkin | unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
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175 | 02eb84d0 | Michael S. Tsirkin | return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
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176 | 02eb84d0 | Michael S. Tsirkin | } |
177 | 02eb84d0 | Michael S. Tsirkin | |
178 | 02eb84d0 | Michael S. Tsirkin | static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, |
179 | 02eb84d0 | Michael S. Tsirkin | uint32_t val) |
180 | 02eb84d0 | Michael S. Tsirkin | { |
181 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
182 | 02eb84d0 | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); |
183 | 02eb84d0 | Michael S. Tsirkin | int vector = offset / MSIX_ENTRY_SIZE;
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184 | 02eb84d0 | Michael S. Tsirkin | memcpy(dev->msix_table_page + offset, &val, 4);
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185 | 02eb84d0 | Michael S. Tsirkin | if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
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186 | 02eb84d0 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
187 | 02eb84d0 | Michael S. Tsirkin | msix_notify(dev, vector); |
188 | 02eb84d0 | Michael S. Tsirkin | } |
189 | 02eb84d0 | Michael S. Tsirkin | } |
190 | 02eb84d0 | Michael S. Tsirkin | |
191 | 02eb84d0 | Michael S. Tsirkin | static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr, |
192 | 02eb84d0 | Michael S. Tsirkin | uint32_t val) |
193 | 02eb84d0 | Michael S. Tsirkin | { |
194 | 02eb84d0 | Michael S. Tsirkin | fprintf(stderr, "MSI-X: only dword write is allowed!\n");
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195 | 02eb84d0 | Michael S. Tsirkin | } |
196 | 02eb84d0 | Michael S. Tsirkin | |
197 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const msix_mmio_write[] = { |
198 | 02eb84d0 | Michael S. Tsirkin | msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel |
199 | 02eb84d0 | Michael S. Tsirkin | }; |
200 | 02eb84d0 | Michael S. Tsirkin | |
201 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const msix_mmio_read[] = { |
202 | 02eb84d0 | Michael S. Tsirkin | msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl |
203 | 02eb84d0 | Michael S. Tsirkin | }; |
204 | 02eb84d0 | Michael S. Tsirkin | |
205 | 02eb84d0 | Michael S. Tsirkin | /* Should be called from device's map method. */
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206 | 02eb84d0 | Michael S. Tsirkin | void msix_mmio_map(PCIDevice *d, int region_num, |
207 | 02eb84d0 | Michael S. Tsirkin | uint32_t addr, uint32_t size, int type)
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208 | 02eb84d0 | Michael S. Tsirkin | { |
209 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config = d->config + d->msix_cap; |
210 | 02eb84d0 | Michael S. Tsirkin | uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET); |
211 | 02eb84d0 | Michael S. Tsirkin | uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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212 | 02eb84d0 | Michael S. Tsirkin | /* TODO: for assigned devices, we'll want to make it possible to map
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213 | 02eb84d0 | Michael S. Tsirkin | * pending bits separately in case they are in a separate bar. */
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214 | 02eb84d0 | Michael S. Tsirkin | int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
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215 | 02eb84d0 | Michael S. Tsirkin | |
216 | 02eb84d0 | Michael S. Tsirkin | if (table_bir != region_num)
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217 | 02eb84d0 | Michael S. Tsirkin | return;
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218 | 02eb84d0 | Michael S. Tsirkin | if (size <= offset)
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219 | 02eb84d0 | Michael S. Tsirkin | return;
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220 | 02eb84d0 | Michael S. Tsirkin | cpu_register_physical_memory(addr + offset, size - offset, |
221 | 02eb84d0 | Michael S. Tsirkin | d->msix_mmio_index); |
222 | 02eb84d0 | Michael S. Tsirkin | } |
223 | 02eb84d0 | Michael S. Tsirkin | |
224 | 02eb84d0 | Michael S. Tsirkin | /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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225 | 02eb84d0 | Michael S. Tsirkin | * modified, it should be retrieved with msix_bar_size. */
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226 | 02eb84d0 | Michael S. Tsirkin | int msix_init(struct PCIDevice *dev, unsigned short nentries, |
227 | 02eb84d0 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
228 | 02eb84d0 | Michael S. Tsirkin | { |
229 | 02eb84d0 | Michael S. Tsirkin | int ret;
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230 | 02eb84d0 | Michael S. Tsirkin | /* Nothing to do if MSI is not supported by interrupt controller */
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231 | 02eb84d0 | Michael S. Tsirkin | if (!msix_supported)
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232 | 02eb84d0 | Michael S. Tsirkin | return -ENOTSUP;
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233 | 02eb84d0 | Michael S. Tsirkin | |
234 | 02eb84d0 | Michael S. Tsirkin | if (nentries > MSIX_MAX_ENTRIES)
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235 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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236 | 02eb84d0 | Michael S. Tsirkin | |
237 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES * |
238 | 02eb84d0 | Michael S. Tsirkin | sizeof *dev->msix_entry_used);
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239 | 02eb84d0 | Michael S. Tsirkin | |
240 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE); |
241 | 02eb84d0 | Michael S. Tsirkin | |
242 | 02eb84d0 | Michael S. Tsirkin | dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, |
243 | 02eb84d0 | Michael S. Tsirkin | msix_mmio_write, dev); |
244 | 02eb84d0 | Michael S. Tsirkin | if (dev->msix_mmio_index == -1) { |
245 | 02eb84d0 | Michael S. Tsirkin | ret = -EBUSY; |
246 | 02eb84d0 | Michael S. Tsirkin | goto err_index;
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247 | 02eb84d0 | Michael S. Tsirkin | } |
248 | 02eb84d0 | Michael S. Tsirkin | |
249 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = nentries; |
250 | 02eb84d0 | Michael S. Tsirkin | ret = msix_add_config(dev, nentries, bar_nr, bar_size); |
251 | 02eb84d0 | Michael S. Tsirkin | if (ret)
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252 | 02eb84d0 | Michael S. Tsirkin | goto err_config;
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253 | 02eb84d0 | Michael S. Tsirkin | |
254 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present |= QEMU_PCI_CAP_MSIX; |
255 | 02eb84d0 | Michael S. Tsirkin | return 0; |
256 | 02eb84d0 | Michael S. Tsirkin | |
257 | 02eb84d0 | Michael S. Tsirkin | err_config:
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258 | 3174ecd1 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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259 | 02eb84d0 | Michael S. Tsirkin | cpu_unregister_io_memory(dev->msix_mmio_index); |
260 | 02eb84d0 | Michael S. Tsirkin | err_index:
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261 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_table_page); |
262 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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263 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_entry_used); |
264 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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265 | 02eb84d0 | Michael S. Tsirkin | return ret;
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266 | 02eb84d0 | Michael S. Tsirkin | } |
267 | 02eb84d0 | Michael S. Tsirkin | |
268 | 02eb84d0 | Michael S. Tsirkin | /* Clean up resources for the device. */
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269 | 02eb84d0 | Michael S. Tsirkin | int msix_uninit(PCIDevice *dev)
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270 | 02eb84d0 | Michael S. Tsirkin | { |
271 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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272 | 02eb84d0 | Michael S. Tsirkin | return 0; |
273 | 02eb84d0 | Michael S. Tsirkin | pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
274 | 02eb84d0 | Michael S. Tsirkin | dev->msix_cap = 0;
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275 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
276 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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277 | 02eb84d0 | Michael S. Tsirkin | cpu_unregister_io_memory(dev->msix_mmio_index); |
278 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_table_page); |
279 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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280 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_entry_used); |
281 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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282 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present &= ~QEMU_PCI_CAP_MSIX; |
283 | 02eb84d0 | Michael S. Tsirkin | return 0; |
284 | 02eb84d0 | Michael S. Tsirkin | } |
285 | 02eb84d0 | Michael S. Tsirkin | |
286 | 02eb84d0 | Michael S. Tsirkin | void msix_save(PCIDevice *dev, QEMUFile *f)
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287 | 02eb84d0 | Michael S. Tsirkin | { |
288 | 9a3e12c8 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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289 | 9a3e12c8 | Michael S. Tsirkin | |
290 | 72755a70 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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291 | 9a3e12c8 | Michael S. Tsirkin | return;
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292 | 72755a70 | Michael S. Tsirkin | } |
293 | 9a3e12c8 | Michael S. Tsirkin | |
294 | 9a3e12c8 | Michael S. Tsirkin | qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE); |
295 | 9a3e12c8 | Michael S. Tsirkin | qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
296 | 02eb84d0 | Michael S. Tsirkin | } |
297 | 02eb84d0 | Michael S. Tsirkin | |
298 | 02eb84d0 | Michael S. Tsirkin | /* Should be called after restoring the config space. */
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299 | 02eb84d0 | Michael S. Tsirkin | void msix_load(PCIDevice *dev, QEMUFile *f)
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300 | 02eb84d0 | Michael S. Tsirkin | { |
301 | 02eb84d0 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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302 | 02eb84d0 | Michael S. Tsirkin | |
303 | 98846d73 | Blue Swirl | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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304 | 02eb84d0 | Michael S. Tsirkin | return;
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305 | 98846d73 | Blue Swirl | } |
306 | 02eb84d0 | Michael S. Tsirkin | |
307 | 4bfd1712 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
308 | 02eb84d0 | Michael S. Tsirkin | qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE); |
309 | 02eb84d0 | Michael S. Tsirkin | qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
310 | 02eb84d0 | Michael S. Tsirkin | } |
311 | 02eb84d0 | Michael S. Tsirkin | |
312 | 02eb84d0 | Michael S. Tsirkin | /* Does device support MSI-X? */
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313 | 02eb84d0 | Michael S. Tsirkin | int msix_present(PCIDevice *dev)
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314 | 02eb84d0 | Michael S. Tsirkin | { |
315 | 02eb84d0 | Michael S. Tsirkin | return dev->cap_present & QEMU_PCI_CAP_MSIX;
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316 | 02eb84d0 | Michael S. Tsirkin | } |
317 | 02eb84d0 | Michael S. Tsirkin | |
318 | 02eb84d0 | Michael S. Tsirkin | /* Is MSI-X enabled? */
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319 | 02eb84d0 | Michael S. Tsirkin | int msix_enabled(PCIDevice *dev)
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320 | 02eb84d0 | Michael S. Tsirkin | { |
321 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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322 | 02eb84d0 | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] & |
323 | 02eb84d0 | Michael S. Tsirkin | MSIX_ENABLE_MASK); |
324 | 02eb84d0 | Michael S. Tsirkin | } |
325 | 02eb84d0 | Michael S. Tsirkin | |
326 | 02eb84d0 | Michael S. Tsirkin | /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
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327 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size(PCIDevice *dev) |
328 | 02eb84d0 | Michael S. Tsirkin | { |
329 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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330 | 02eb84d0 | Michael S. Tsirkin | dev->msix_bar_size : 0;
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331 | 02eb84d0 | Michael S. Tsirkin | } |
332 | 02eb84d0 | Michael S. Tsirkin | |
333 | 02eb84d0 | Michael S. Tsirkin | /* Send an MSI-X message */
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334 | 02eb84d0 | Michael S. Tsirkin | void msix_notify(PCIDevice *dev, unsigned vector) |
335 | 02eb84d0 | Michael S. Tsirkin | { |
336 | 02eb84d0 | Michael S. Tsirkin | uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE; |
337 | 02eb84d0 | Michael S. Tsirkin | uint64_t address; |
338 | 02eb84d0 | Michael S. Tsirkin | uint32_t data; |
339 | 02eb84d0 | Michael S. Tsirkin | |
340 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
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341 | 02eb84d0 | Michael S. Tsirkin | return;
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342 | 02eb84d0 | Michael S. Tsirkin | if (msix_is_masked(dev, vector)) {
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343 | 02eb84d0 | Michael S. Tsirkin | msix_set_pending(dev, vector); |
344 | 02eb84d0 | Michael S. Tsirkin | return;
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345 | 02eb84d0 | Michael S. Tsirkin | } |
346 | 02eb84d0 | Michael S. Tsirkin | |
347 | 02eb84d0 | Michael S. Tsirkin | address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR); |
348 | 02eb84d0 | Michael S. Tsirkin | address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
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349 | 02eb84d0 | Michael S. Tsirkin | data = pci_get_long(table_entry + MSIX_MSG_DATA); |
350 | 02eb84d0 | Michael S. Tsirkin | stl_phys(address, data); |
351 | 02eb84d0 | Michael S. Tsirkin | } |
352 | 02eb84d0 | Michael S. Tsirkin | |
353 | 02eb84d0 | Michael S. Tsirkin | void msix_reset(PCIDevice *dev)
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354 | 02eb84d0 | Michael S. Tsirkin | { |
355 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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356 | 02eb84d0 | Michael S. Tsirkin | return;
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357 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
358 | 02eb84d0 | Michael S. Tsirkin | dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; |
359 | 02eb84d0 | Michael S. Tsirkin | memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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360 | 02eb84d0 | Michael S. Tsirkin | } |
361 | 02eb84d0 | Michael S. Tsirkin | |
362 | 02eb84d0 | Michael S. Tsirkin | /* PCI spec suggests that devices make it possible for software to configure
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363 | 02eb84d0 | Michael S. Tsirkin | * less vectors than supported by the device, but does not specify a standard
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364 | 02eb84d0 | Michael S. Tsirkin | * mechanism for devices to do so.
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365 | 02eb84d0 | Michael S. Tsirkin | *
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366 | 02eb84d0 | Michael S. Tsirkin | * We support this by asking devices to declare vectors software is going to
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367 | 02eb84d0 | Michael S. Tsirkin | * actually use, and checking this on the notification path. Devices that
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368 | 02eb84d0 | Michael S. Tsirkin | * don't want to follow the spec suggestion can declare all vectors as used. */
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369 | 02eb84d0 | Michael S. Tsirkin | |
370 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as used. */
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371 | 02eb84d0 | Michael S. Tsirkin | int msix_vector_use(PCIDevice *dev, unsigned vector) |
372 | 02eb84d0 | Michael S. Tsirkin | { |
373 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr)
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374 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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375 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used[vector]++; |
376 | 02eb84d0 | Michael S. Tsirkin | return 0; |
377 | 02eb84d0 | Michael S. Tsirkin | } |
378 | 02eb84d0 | Michael S. Tsirkin | |
379 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as unused. */
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380 | 02eb84d0 | Michael S. Tsirkin | void msix_vector_unuse(PCIDevice *dev, unsigned vector) |
381 | 02eb84d0 | Michael S. Tsirkin | { |
382 | 02eb84d0 | Michael S. Tsirkin | if (vector < dev->msix_entries_nr && dev->msix_entry_used[vector])
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383 | 02eb84d0 | Michael S. Tsirkin | --dev->msix_entry_used[vector]; |
384 | 02eb84d0 | Michael S. Tsirkin | } |