root / hw / ppc405_uc.c @ a8a358bf
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1 | 8ecc7913 | j_mayer | /*
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2 | 8ecc7913 | j_mayer | * QEMU PowerPC 405 embedded processors emulation
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3 | 5fafdf24 | ths | *
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4 | 8ecc7913 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | 8ecc7913 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8ecc7913 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 8ecc7913 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 8ecc7913 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8ecc7913 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 8ecc7913 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 8ecc7913 | j_mayer | *
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13 | 8ecc7913 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 8ecc7913 | j_mayer | * all copies or substantial portions of the Software.
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15 | 8ecc7913 | j_mayer | *
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16 | 8ecc7913 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8ecc7913 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8ecc7913 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8ecc7913 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8ecc7913 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8ecc7913 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8ecc7913 | j_mayer | * THE SOFTWARE.
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23 | 8ecc7913 | j_mayer | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 04f20795 | j_mayer | #include "ppc405.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "qemu-timer.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
31 | 8ecc7913 | j_mayer | |
32 | 8ecc7913 | j_mayer | #define DEBUG_OPBA
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33 | 8ecc7913 | j_mayer | #define DEBUG_SDRAM
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34 | 8ecc7913 | j_mayer | #define DEBUG_GPIO
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35 | 8ecc7913 | j_mayer | #define DEBUG_SERIAL
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36 | 8ecc7913 | j_mayer | #define DEBUG_OCM
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37 | 9c02f1a2 | j_mayer | //#define DEBUG_I2C
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38 | 9c02f1a2 | j_mayer | #define DEBUG_GPT
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39 | 9c02f1a2 | j_mayer | #define DEBUG_MAL
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40 | 8ecc7913 | j_mayer | #define DEBUG_CLOCKS
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41 | aae9366a | j_mayer | //#define DEBUG_CLOCKS_LL
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42 | 8ecc7913 | j_mayer | |
43 | b8d3f5d1 | j_mayer | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
44 | b8d3f5d1 | j_mayer | uint32_t flags) |
45 | 04f20795 | j_mayer | { |
46 | 04f20795 | j_mayer | ram_addr_t bdloc; |
47 | 04f20795 | j_mayer | int i, n;
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48 | 04f20795 | j_mayer | |
49 | 04f20795 | j_mayer | /* We put the bd structure at the top of memory */
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50 | be58fc7c | j_mayer | if (bd->bi_memsize >= 0x01000000UL) |
51 | be58fc7c | j_mayer | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
52 | be58fc7c | j_mayer | else
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53 | be58fc7c | j_mayer | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
54 | 5c130f65 | pbrook | stl_phys(bdloc + 0x00, bd->bi_memstart);
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55 | 5c130f65 | pbrook | stl_phys(bdloc + 0x04, bd->bi_memsize);
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56 | 5c130f65 | pbrook | stl_phys(bdloc + 0x08, bd->bi_flashstart);
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57 | 5c130f65 | pbrook | stl_phys(bdloc + 0x0C, bd->bi_flashsize);
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58 | 5c130f65 | pbrook | stl_phys(bdloc + 0x10, bd->bi_flashoffset);
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59 | 5c130f65 | pbrook | stl_phys(bdloc + 0x14, bd->bi_sramstart);
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60 | 5c130f65 | pbrook | stl_phys(bdloc + 0x18, bd->bi_sramsize);
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61 | 5c130f65 | pbrook | stl_phys(bdloc + 0x1C, bd->bi_bootflags);
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62 | 5c130f65 | pbrook | stl_phys(bdloc + 0x20, bd->bi_ipaddr);
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63 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
64 | 5c130f65 | pbrook | stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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65 | 5c130f65 | pbrook | stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
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66 | 5c130f65 | pbrook | stl_phys(bdloc + 0x2C, bd->bi_intfreq);
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67 | 5c130f65 | pbrook | stl_phys(bdloc + 0x30, bd->bi_busfreq);
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68 | 5c130f65 | pbrook | stl_phys(bdloc + 0x34, bd->bi_baudrate);
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69 | 04f20795 | j_mayer | for (i = 0; i < 4; i++) |
70 | 5c130f65 | pbrook | stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
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71 | 04f20795 | j_mayer | for (i = 0; i < 32; i++) |
72 | 5c130f65 | pbrook | stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
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73 | 5c130f65 | pbrook | stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
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74 | 5c130f65 | pbrook | stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
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75 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
76 | 5c130f65 | pbrook | stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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77 | 04f20795 | j_mayer | n = 0x6A;
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78 | b8d3f5d1 | j_mayer | if (flags & 0x00000001) { |
79 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
80 | 5c130f65 | pbrook | stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]); |
81 | 04f20795 | j_mayer | } |
82 | 5c130f65 | pbrook | stl_phys(bdloc + n, bd->bi_opbfreq); |
83 | 04f20795 | j_mayer | n += 4;
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84 | 04f20795 | j_mayer | for (i = 0; i < 2; i++) { |
85 | 5c130f65 | pbrook | stl_phys(bdloc + n, bd->bi_iic_fast[i]); |
86 | 04f20795 | j_mayer | n += 4;
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87 | 04f20795 | j_mayer | } |
88 | 04f20795 | j_mayer | |
89 | 04f20795 | j_mayer | return bdloc;
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90 | 04f20795 | j_mayer | } |
91 | 04f20795 | j_mayer | |
92 | 8ecc7913 | j_mayer | /*****************************************************************************/
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93 | 8ecc7913 | j_mayer | /* Shared peripherals */
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94 | 8ecc7913 | j_mayer | |
95 | 8ecc7913 | j_mayer | /*****************************************************************************/
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96 | 8ecc7913 | j_mayer | /* Peripheral local bus arbitrer */
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97 | 8ecc7913 | j_mayer | enum {
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98 | 8ecc7913 | j_mayer | PLB0_BESR = 0x084,
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99 | 8ecc7913 | j_mayer | PLB0_BEAR = 0x086,
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100 | 8ecc7913 | j_mayer | PLB0_ACR = 0x087,
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101 | 8ecc7913 | j_mayer | }; |
102 | 8ecc7913 | j_mayer | |
103 | 8ecc7913 | j_mayer | typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
104 | 8ecc7913 | j_mayer | struct ppc4xx_plb_t {
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105 | 8ecc7913 | j_mayer | uint32_t acr; |
106 | 8ecc7913 | j_mayer | uint32_t bear; |
107 | 8ecc7913 | j_mayer | uint32_t besr; |
108 | 8ecc7913 | j_mayer | }; |
109 | 8ecc7913 | j_mayer | |
110 | 8ecc7913 | j_mayer | static target_ulong dcr_read_plb (void *opaque, int dcrn) |
111 | 8ecc7913 | j_mayer | { |
112 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
113 | 8ecc7913 | j_mayer | target_ulong ret; |
114 | 8ecc7913 | j_mayer | |
115 | 8ecc7913 | j_mayer | plb = opaque; |
116 | 8ecc7913 | j_mayer | switch (dcrn) {
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117 | 8ecc7913 | j_mayer | case PLB0_ACR:
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118 | 8ecc7913 | j_mayer | ret = plb->acr; |
119 | 8ecc7913 | j_mayer | break;
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120 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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121 | 8ecc7913 | j_mayer | ret = plb->bear; |
122 | 8ecc7913 | j_mayer | break;
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123 | 8ecc7913 | j_mayer | case PLB0_BESR:
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124 | 8ecc7913 | j_mayer | ret = plb->besr; |
125 | 8ecc7913 | j_mayer | break;
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126 | 8ecc7913 | j_mayer | default:
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127 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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128 | 8ecc7913 | j_mayer | ret = 0;
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129 | 8ecc7913 | j_mayer | break;
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130 | 8ecc7913 | j_mayer | } |
131 | 8ecc7913 | j_mayer | |
132 | 8ecc7913 | j_mayer | return ret;
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133 | 8ecc7913 | j_mayer | } |
134 | 8ecc7913 | j_mayer | |
135 | 8ecc7913 | j_mayer | static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
136 | 8ecc7913 | j_mayer | { |
137 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
138 | 8ecc7913 | j_mayer | |
139 | 8ecc7913 | j_mayer | plb = opaque; |
140 | 8ecc7913 | j_mayer | switch (dcrn) {
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141 | 8ecc7913 | j_mayer | case PLB0_ACR:
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142 | 9c02f1a2 | j_mayer | /* We don't care about the actual parameters written as
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143 | 9c02f1a2 | j_mayer | * we don't manage any priorities on the bus
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144 | 9c02f1a2 | j_mayer | */
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145 | 9c02f1a2 | j_mayer | plb->acr = val & 0xF8000000;
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146 | 8ecc7913 | j_mayer | break;
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147 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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148 | 8ecc7913 | j_mayer | /* Read only */
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149 | 8ecc7913 | j_mayer | break;
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150 | 8ecc7913 | j_mayer | case PLB0_BESR:
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151 | 8ecc7913 | j_mayer | /* Write-clear */
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152 | 8ecc7913 | j_mayer | plb->besr &= ~val; |
153 | 8ecc7913 | j_mayer | break;
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154 | 8ecc7913 | j_mayer | } |
155 | 8ecc7913 | j_mayer | } |
156 | 8ecc7913 | j_mayer | |
157 | 8ecc7913 | j_mayer | static void ppc4xx_plb_reset (void *opaque) |
158 | 8ecc7913 | j_mayer | { |
159 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
160 | 8ecc7913 | j_mayer | |
161 | 8ecc7913 | j_mayer | plb = opaque; |
162 | 8ecc7913 | j_mayer | plb->acr = 0x00000000;
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163 | 8ecc7913 | j_mayer | plb->bear = 0x00000000;
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164 | 8ecc7913 | j_mayer | plb->besr = 0x00000000;
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165 | 8ecc7913 | j_mayer | } |
166 | 8ecc7913 | j_mayer | |
167 | 802670e6 | Blue Swirl | static void ppc4xx_plb_init(CPUState *env) |
168 | 8ecc7913 | j_mayer | { |
169 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
170 | 8ecc7913 | j_mayer | |
171 | 8ecc7913 | j_mayer | plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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172 | 487414f1 | aliguori | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
173 | 487414f1 | aliguori | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
174 | 487414f1 | aliguori | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
175 | 487414f1 | aliguori | ppc4xx_plb_reset(plb); |
176 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_plb_reset, plb); |
177 | 8ecc7913 | j_mayer | } |
178 | 8ecc7913 | j_mayer | |
179 | 8ecc7913 | j_mayer | /*****************************************************************************/
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180 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
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181 | 8ecc7913 | j_mayer | enum {
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182 | 8ecc7913 | j_mayer | POB0_BESR0 = 0x0A0,
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183 | 8ecc7913 | j_mayer | POB0_BESR1 = 0x0A2,
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184 | 8ecc7913 | j_mayer | POB0_BEAR = 0x0A4,
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185 | 8ecc7913 | j_mayer | }; |
186 | 8ecc7913 | j_mayer | |
187 | 8ecc7913 | j_mayer | typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
188 | 8ecc7913 | j_mayer | struct ppc4xx_pob_t {
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189 | 8ecc7913 | j_mayer | uint32_t bear; |
190 | 8ecc7913 | j_mayer | uint32_t besr[2];
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191 | 8ecc7913 | j_mayer | }; |
192 | 8ecc7913 | j_mayer | |
193 | 8ecc7913 | j_mayer | static target_ulong dcr_read_pob (void *opaque, int dcrn) |
194 | 8ecc7913 | j_mayer | { |
195 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
196 | 8ecc7913 | j_mayer | target_ulong ret; |
197 | 8ecc7913 | j_mayer | |
198 | 8ecc7913 | j_mayer | pob = opaque; |
199 | 8ecc7913 | j_mayer | switch (dcrn) {
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200 | 8ecc7913 | j_mayer | case POB0_BEAR:
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201 | 8ecc7913 | j_mayer | ret = pob->bear; |
202 | 8ecc7913 | j_mayer | break;
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203 | 8ecc7913 | j_mayer | case POB0_BESR0:
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204 | 8ecc7913 | j_mayer | case POB0_BESR1:
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205 | 8ecc7913 | j_mayer | ret = pob->besr[dcrn - POB0_BESR0]; |
206 | 8ecc7913 | j_mayer | break;
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207 | 8ecc7913 | j_mayer | default:
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208 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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209 | 8ecc7913 | j_mayer | ret = 0;
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210 | 8ecc7913 | j_mayer | break;
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211 | 8ecc7913 | j_mayer | } |
212 | 8ecc7913 | j_mayer | |
213 | 8ecc7913 | j_mayer | return ret;
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214 | 8ecc7913 | j_mayer | } |
215 | 8ecc7913 | j_mayer | |
216 | 8ecc7913 | j_mayer | static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
217 | 8ecc7913 | j_mayer | { |
218 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
219 | 8ecc7913 | j_mayer | |
220 | 8ecc7913 | j_mayer | pob = opaque; |
221 | 8ecc7913 | j_mayer | switch (dcrn) {
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222 | 8ecc7913 | j_mayer | case POB0_BEAR:
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223 | 8ecc7913 | j_mayer | /* Read only */
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224 | 8ecc7913 | j_mayer | break;
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225 | 8ecc7913 | j_mayer | case POB0_BESR0:
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226 | 8ecc7913 | j_mayer | case POB0_BESR1:
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227 | 8ecc7913 | j_mayer | /* Write-clear */
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228 | 8ecc7913 | j_mayer | pob->besr[dcrn - POB0_BESR0] &= ~val; |
229 | 8ecc7913 | j_mayer | break;
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230 | 8ecc7913 | j_mayer | } |
231 | 8ecc7913 | j_mayer | } |
232 | 8ecc7913 | j_mayer | |
233 | 8ecc7913 | j_mayer | static void ppc4xx_pob_reset (void *opaque) |
234 | 8ecc7913 | j_mayer | { |
235 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
236 | 8ecc7913 | j_mayer | |
237 | 8ecc7913 | j_mayer | pob = opaque; |
238 | 8ecc7913 | j_mayer | /* No error */
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239 | 8ecc7913 | j_mayer | pob->bear = 0x00000000;
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240 | 8ecc7913 | j_mayer | pob->besr[0] = 0x0000000; |
241 | 8ecc7913 | j_mayer | pob->besr[1] = 0x0000000; |
242 | 8ecc7913 | j_mayer | } |
243 | 8ecc7913 | j_mayer | |
244 | 802670e6 | Blue Swirl | static void ppc4xx_pob_init(CPUState *env) |
245 | 8ecc7913 | j_mayer | { |
246 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
247 | 8ecc7913 | j_mayer | |
248 | 8ecc7913 | j_mayer | pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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249 | 487414f1 | aliguori | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
250 | 487414f1 | aliguori | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
251 | 487414f1 | aliguori | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
252 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_pob_reset, pob); |
253 | 802670e6 | Blue Swirl | ppc4xx_pob_reset(pob); |
254 | 8ecc7913 | j_mayer | } |
255 | 8ecc7913 | j_mayer | |
256 | 8ecc7913 | j_mayer | /*****************************************************************************/
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257 | 8ecc7913 | j_mayer | /* OPB arbitrer */
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258 | 8ecc7913 | j_mayer | typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
259 | 8ecc7913 | j_mayer | struct ppc4xx_opba_t {
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260 | 8ecc7913 | j_mayer | uint8_t cr; |
261 | 8ecc7913 | j_mayer | uint8_t pr; |
262 | 8ecc7913 | j_mayer | }; |
263 | 8ecc7913 | j_mayer | |
264 | 8ecc7913 | j_mayer | static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
265 | 8ecc7913 | j_mayer | { |
266 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
267 | 8ecc7913 | j_mayer | uint32_t ret; |
268 | 8ecc7913 | j_mayer | |
269 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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270 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
271 | 8ecc7913 | j_mayer | #endif
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272 | 8ecc7913 | j_mayer | opba = opaque; |
273 | 802670e6 | Blue Swirl | switch (addr) {
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274 | 8ecc7913 | j_mayer | case 0x00: |
275 | 8ecc7913 | j_mayer | ret = opba->cr; |
276 | 8ecc7913 | j_mayer | break;
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277 | 8ecc7913 | j_mayer | case 0x01: |
278 | 8ecc7913 | j_mayer | ret = opba->pr; |
279 | 8ecc7913 | j_mayer | break;
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280 | 8ecc7913 | j_mayer | default:
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281 | 8ecc7913 | j_mayer | ret = 0x00;
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282 | 8ecc7913 | j_mayer | break;
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283 | 8ecc7913 | j_mayer | } |
284 | 8ecc7913 | j_mayer | |
285 | 8ecc7913 | j_mayer | return ret;
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286 | 8ecc7913 | j_mayer | } |
287 | 8ecc7913 | j_mayer | |
288 | 8ecc7913 | j_mayer | static void opba_writeb (void *opaque, |
289 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
290 | 8ecc7913 | j_mayer | { |
291 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
292 | 8ecc7913 | j_mayer | |
293 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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294 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
295 | 90e189ec | Blue Swirl | value); |
296 | 8ecc7913 | j_mayer | #endif
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297 | 8ecc7913 | j_mayer | opba = opaque; |
298 | 802670e6 | Blue Swirl | switch (addr) {
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299 | 8ecc7913 | j_mayer | case 0x00: |
300 | 8ecc7913 | j_mayer | opba->cr = value & 0xF8;
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301 | 8ecc7913 | j_mayer | break;
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302 | 8ecc7913 | j_mayer | case 0x01: |
303 | 8ecc7913 | j_mayer | opba->pr = value & 0xFF;
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304 | 8ecc7913 | j_mayer | break;
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305 | 8ecc7913 | j_mayer | default:
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306 | 8ecc7913 | j_mayer | break;
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307 | 8ecc7913 | j_mayer | } |
308 | 8ecc7913 | j_mayer | } |
309 | 8ecc7913 | j_mayer | |
310 | 8ecc7913 | j_mayer | static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
311 | 8ecc7913 | j_mayer | { |
312 | 8ecc7913 | j_mayer | uint32_t ret; |
313 | 8ecc7913 | j_mayer | |
314 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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315 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
316 | 8ecc7913 | j_mayer | #endif
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317 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 8;
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318 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1);
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319 | 8ecc7913 | j_mayer | |
320 | 8ecc7913 | j_mayer | return ret;
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321 | 8ecc7913 | j_mayer | } |
322 | 8ecc7913 | j_mayer | |
323 | 8ecc7913 | j_mayer | static void opba_writew (void *opaque, |
324 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
325 | 8ecc7913 | j_mayer | { |
326 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
327 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
328 | 90e189ec | Blue Swirl | value); |
329 | 8ecc7913 | j_mayer | #endif
|
330 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 8);
|
331 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value);
|
332 | 8ecc7913 | j_mayer | } |
333 | 8ecc7913 | j_mayer | |
334 | 8ecc7913 | j_mayer | static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
335 | 8ecc7913 | j_mayer | { |
336 | 8ecc7913 | j_mayer | uint32_t ret; |
337 | 8ecc7913 | j_mayer | |
338 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
339 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
340 | 8ecc7913 | j_mayer | #endif
|
341 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 24;
|
342 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1) << 16; |
343 | 8ecc7913 | j_mayer | |
344 | 8ecc7913 | j_mayer | return ret;
|
345 | 8ecc7913 | j_mayer | } |
346 | 8ecc7913 | j_mayer | |
347 | 8ecc7913 | j_mayer | static void opba_writel (void *opaque, |
348 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
349 | 8ecc7913 | j_mayer | { |
350 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
351 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
352 | 90e189ec | Blue Swirl | value); |
353 | 8ecc7913 | j_mayer | #endif
|
354 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 24);
|
355 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value >> 16); |
356 | 8ecc7913 | j_mayer | } |
357 | 8ecc7913 | j_mayer | |
358 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const opba_read[] = { |
359 | 8ecc7913 | j_mayer | &opba_readb, |
360 | 8ecc7913 | j_mayer | &opba_readw, |
361 | 8ecc7913 | j_mayer | &opba_readl, |
362 | 8ecc7913 | j_mayer | }; |
363 | 8ecc7913 | j_mayer | |
364 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const opba_write[] = { |
365 | 8ecc7913 | j_mayer | &opba_writeb, |
366 | 8ecc7913 | j_mayer | &opba_writew, |
367 | 8ecc7913 | j_mayer | &opba_writel, |
368 | 8ecc7913 | j_mayer | }; |
369 | 8ecc7913 | j_mayer | |
370 | 8ecc7913 | j_mayer | static void ppc4xx_opba_reset (void *opaque) |
371 | 8ecc7913 | j_mayer | { |
372 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
373 | 8ecc7913 | j_mayer | |
374 | 8ecc7913 | j_mayer | opba = opaque; |
375 | 8ecc7913 | j_mayer | opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
376 | 8ecc7913 | j_mayer | opba->pr = 0x11;
|
377 | 8ecc7913 | j_mayer | } |
378 | 8ecc7913 | j_mayer | |
379 | 802670e6 | Blue Swirl | static void ppc4xx_opba_init(target_phys_addr_t base) |
380 | 8ecc7913 | j_mayer | { |
381 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
382 | 802670e6 | Blue Swirl | int io;
|
383 | 8ecc7913 | j_mayer | |
384 | 8ecc7913 | j_mayer | opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
385 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
386 | 90e189ec | Blue Swirl | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
387 | 8ecc7913 | j_mayer | #endif
|
388 | 802670e6 | Blue Swirl | io = cpu_register_io_memory(opba_read, opba_write, opba); |
389 | 802670e6 | Blue Swirl | cpu_register_physical_memory(base, 0x002, io);
|
390 | 487414f1 | aliguori | ppc4xx_opba_reset(opba); |
391 | 802670e6 | Blue Swirl | qemu_register_reset(ppc4xx_opba_reset, opba); |
392 | 8ecc7913 | j_mayer | } |
393 | 8ecc7913 | j_mayer | |
394 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
395 | 8ecc7913 | j_mayer | /* Code decompression controller */
|
396 | 8ecc7913 | j_mayer | /* XXX: TODO */
|
397 | 8ecc7913 | j_mayer | |
398 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
399 | 8ecc7913 | j_mayer | /* Peripheral controller */
|
400 | 8ecc7913 | j_mayer | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
401 | 8ecc7913 | j_mayer | struct ppc4xx_ebc_t {
|
402 | 8ecc7913 | j_mayer | uint32_t addr; |
403 | 8ecc7913 | j_mayer | uint32_t bcr[8];
|
404 | 8ecc7913 | j_mayer | uint32_t bap[8];
|
405 | 8ecc7913 | j_mayer | uint32_t bear; |
406 | 8ecc7913 | j_mayer | uint32_t besr0; |
407 | 8ecc7913 | j_mayer | uint32_t besr1; |
408 | 8ecc7913 | j_mayer | uint32_t cfg; |
409 | 8ecc7913 | j_mayer | }; |
410 | 8ecc7913 | j_mayer | |
411 | 8ecc7913 | j_mayer | enum {
|
412 | 8ecc7913 | j_mayer | EBC0_CFGADDR = 0x012,
|
413 | 8ecc7913 | j_mayer | EBC0_CFGDATA = 0x013,
|
414 | 8ecc7913 | j_mayer | }; |
415 | 8ecc7913 | j_mayer | |
416 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
417 | 8ecc7913 | j_mayer | { |
418 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
419 | 8ecc7913 | j_mayer | target_ulong ret; |
420 | 8ecc7913 | j_mayer | |
421 | 8ecc7913 | j_mayer | ebc = opaque; |
422 | 8ecc7913 | j_mayer | switch (dcrn) {
|
423 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
424 | 8ecc7913 | j_mayer | ret = ebc->addr; |
425 | 8ecc7913 | j_mayer | break;
|
426 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
427 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
428 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
429 | 8ecc7913 | j_mayer | ret = ebc->bcr[0];
|
430 | 8ecc7913 | j_mayer | break;
|
431 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
432 | 8ecc7913 | j_mayer | ret = ebc->bcr[1];
|
433 | 8ecc7913 | j_mayer | break;
|
434 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
435 | 8ecc7913 | j_mayer | ret = ebc->bcr[2];
|
436 | 8ecc7913 | j_mayer | break;
|
437 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
438 | 8ecc7913 | j_mayer | ret = ebc->bcr[3];
|
439 | 8ecc7913 | j_mayer | break;
|
440 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
441 | 8ecc7913 | j_mayer | ret = ebc->bcr[4];
|
442 | 8ecc7913 | j_mayer | break;
|
443 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
444 | 8ecc7913 | j_mayer | ret = ebc->bcr[5];
|
445 | 8ecc7913 | j_mayer | break;
|
446 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
447 | 8ecc7913 | j_mayer | ret = ebc->bcr[6];
|
448 | 8ecc7913 | j_mayer | break;
|
449 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
450 | 8ecc7913 | j_mayer | ret = ebc->bcr[7];
|
451 | 8ecc7913 | j_mayer | break;
|
452 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
453 | 8ecc7913 | j_mayer | ret = ebc->bap[0];
|
454 | 8ecc7913 | j_mayer | break;
|
455 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
456 | 8ecc7913 | j_mayer | ret = ebc->bap[1];
|
457 | 8ecc7913 | j_mayer | break;
|
458 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
459 | 8ecc7913 | j_mayer | ret = ebc->bap[2];
|
460 | 8ecc7913 | j_mayer | break;
|
461 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
462 | 8ecc7913 | j_mayer | ret = ebc->bap[3];
|
463 | 8ecc7913 | j_mayer | break;
|
464 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
465 | 8ecc7913 | j_mayer | ret = ebc->bap[4];
|
466 | 8ecc7913 | j_mayer | break;
|
467 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
468 | 8ecc7913 | j_mayer | ret = ebc->bap[5];
|
469 | 8ecc7913 | j_mayer | break;
|
470 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
471 | 8ecc7913 | j_mayer | ret = ebc->bap[6];
|
472 | 8ecc7913 | j_mayer | break;
|
473 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
474 | 8ecc7913 | j_mayer | ret = ebc->bap[7];
|
475 | 8ecc7913 | j_mayer | break;
|
476 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
477 | 8ecc7913 | j_mayer | ret = ebc->bear; |
478 | 8ecc7913 | j_mayer | break;
|
479 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
480 | 8ecc7913 | j_mayer | ret = ebc->besr0; |
481 | 8ecc7913 | j_mayer | break;
|
482 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
483 | 8ecc7913 | j_mayer | ret = ebc->besr1; |
484 | 8ecc7913 | j_mayer | break;
|
485 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
486 | 8ecc7913 | j_mayer | ret = ebc->cfg; |
487 | 8ecc7913 | j_mayer | break;
|
488 | 8ecc7913 | j_mayer | default:
|
489 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
490 | 8ecc7913 | j_mayer | break;
|
491 | 8ecc7913 | j_mayer | } |
492 | 8ecc7913 | j_mayer | default:
|
493 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
494 | 8ecc7913 | j_mayer | break;
|
495 | 8ecc7913 | j_mayer | } |
496 | 8ecc7913 | j_mayer | |
497 | 8ecc7913 | j_mayer | return ret;
|
498 | 8ecc7913 | j_mayer | } |
499 | 8ecc7913 | j_mayer | |
500 | 8ecc7913 | j_mayer | static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
501 | 8ecc7913 | j_mayer | { |
502 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
503 | 8ecc7913 | j_mayer | |
504 | 8ecc7913 | j_mayer | ebc = opaque; |
505 | 8ecc7913 | j_mayer | switch (dcrn) {
|
506 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
507 | 8ecc7913 | j_mayer | ebc->addr = val; |
508 | 8ecc7913 | j_mayer | break;
|
509 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
510 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
511 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
512 | 8ecc7913 | j_mayer | break;
|
513 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
514 | 8ecc7913 | j_mayer | break;
|
515 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
516 | 8ecc7913 | j_mayer | break;
|
517 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
518 | 8ecc7913 | j_mayer | break;
|
519 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
520 | 8ecc7913 | j_mayer | break;
|
521 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
522 | 8ecc7913 | j_mayer | break;
|
523 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
524 | 8ecc7913 | j_mayer | break;
|
525 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
526 | 8ecc7913 | j_mayer | break;
|
527 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
528 | 8ecc7913 | j_mayer | break;
|
529 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
530 | 8ecc7913 | j_mayer | break;
|
531 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
532 | 8ecc7913 | j_mayer | break;
|
533 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
534 | 8ecc7913 | j_mayer | break;
|
535 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
536 | 8ecc7913 | j_mayer | break;
|
537 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
538 | 8ecc7913 | j_mayer | break;
|
539 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
540 | 8ecc7913 | j_mayer | break;
|
541 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
542 | 8ecc7913 | j_mayer | break;
|
543 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
544 | 8ecc7913 | j_mayer | break;
|
545 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
546 | 8ecc7913 | j_mayer | break;
|
547 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
548 | 8ecc7913 | j_mayer | break;
|
549 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
550 | 8ecc7913 | j_mayer | break;
|
551 | 8ecc7913 | j_mayer | default:
|
552 | 8ecc7913 | j_mayer | break;
|
553 | 8ecc7913 | j_mayer | } |
554 | 8ecc7913 | j_mayer | break;
|
555 | 8ecc7913 | j_mayer | default:
|
556 | 8ecc7913 | j_mayer | break;
|
557 | 8ecc7913 | j_mayer | } |
558 | 8ecc7913 | j_mayer | } |
559 | 8ecc7913 | j_mayer | |
560 | 8ecc7913 | j_mayer | static void ebc_reset (void *opaque) |
561 | 8ecc7913 | j_mayer | { |
562 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
563 | 8ecc7913 | j_mayer | int i;
|
564 | 8ecc7913 | j_mayer | |
565 | 8ecc7913 | j_mayer | ebc = opaque; |
566 | 8ecc7913 | j_mayer | ebc->addr = 0x00000000;
|
567 | 8ecc7913 | j_mayer | ebc->bap[0] = 0x7F8FFE80; |
568 | 8ecc7913 | j_mayer | ebc->bcr[0] = 0xFFE28000; |
569 | 8ecc7913 | j_mayer | for (i = 0; i < 8; i++) { |
570 | 8ecc7913 | j_mayer | ebc->bap[i] = 0x00000000;
|
571 | 8ecc7913 | j_mayer | ebc->bcr[i] = 0x00000000;
|
572 | 8ecc7913 | j_mayer | } |
573 | 8ecc7913 | j_mayer | ebc->besr0 = 0x00000000;
|
574 | 8ecc7913 | j_mayer | ebc->besr1 = 0x00000000;
|
575 | 9c02f1a2 | j_mayer | ebc->cfg = 0x80400000;
|
576 | 8ecc7913 | j_mayer | } |
577 | 8ecc7913 | j_mayer | |
578 | 802670e6 | Blue Swirl | static void ppc405_ebc_init(CPUState *env) |
579 | 8ecc7913 | j_mayer | { |
580 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
581 | 8ecc7913 | j_mayer | |
582 | 8ecc7913 | j_mayer | ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
583 | 487414f1 | aliguori | ebc_reset(ebc); |
584 | a08d4367 | Jan Kiszka | qemu_register_reset(&ebc_reset, ebc); |
585 | 487414f1 | aliguori | ppc_dcr_register(env, EBC0_CFGADDR, |
586 | 487414f1 | aliguori | ebc, &dcr_read_ebc, &dcr_write_ebc); |
587 | 487414f1 | aliguori | ppc_dcr_register(env, EBC0_CFGDATA, |
588 | 487414f1 | aliguori | ebc, &dcr_read_ebc, &dcr_write_ebc); |
589 | 8ecc7913 | j_mayer | } |
590 | 8ecc7913 | j_mayer | |
591 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
592 | 8ecc7913 | j_mayer | /* DMA controller */
|
593 | 8ecc7913 | j_mayer | enum {
|
594 | 8ecc7913 | j_mayer | DMA0_CR0 = 0x100,
|
595 | 8ecc7913 | j_mayer | DMA0_CT0 = 0x101,
|
596 | 8ecc7913 | j_mayer | DMA0_DA0 = 0x102,
|
597 | 8ecc7913 | j_mayer | DMA0_SA0 = 0x103,
|
598 | 8ecc7913 | j_mayer | DMA0_SG0 = 0x104,
|
599 | 8ecc7913 | j_mayer | DMA0_CR1 = 0x108,
|
600 | 8ecc7913 | j_mayer | DMA0_CT1 = 0x109,
|
601 | 8ecc7913 | j_mayer | DMA0_DA1 = 0x10A,
|
602 | 8ecc7913 | j_mayer | DMA0_SA1 = 0x10B,
|
603 | 8ecc7913 | j_mayer | DMA0_SG1 = 0x10C,
|
604 | 8ecc7913 | j_mayer | DMA0_CR2 = 0x110,
|
605 | 8ecc7913 | j_mayer | DMA0_CT2 = 0x111,
|
606 | 8ecc7913 | j_mayer | DMA0_DA2 = 0x112,
|
607 | 8ecc7913 | j_mayer | DMA0_SA2 = 0x113,
|
608 | 8ecc7913 | j_mayer | DMA0_SG2 = 0x114,
|
609 | 8ecc7913 | j_mayer | DMA0_CR3 = 0x118,
|
610 | 8ecc7913 | j_mayer | DMA0_CT3 = 0x119,
|
611 | 8ecc7913 | j_mayer | DMA0_DA3 = 0x11A,
|
612 | 8ecc7913 | j_mayer | DMA0_SA3 = 0x11B,
|
613 | 8ecc7913 | j_mayer | DMA0_SG3 = 0x11C,
|
614 | 8ecc7913 | j_mayer | DMA0_SR = 0x120,
|
615 | 8ecc7913 | j_mayer | DMA0_SGC = 0x123,
|
616 | 8ecc7913 | j_mayer | DMA0_SLP = 0x125,
|
617 | 8ecc7913 | j_mayer | DMA0_POL = 0x126,
|
618 | 8ecc7913 | j_mayer | }; |
619 | 8ecc7913 | j_mayer | |
620 | 8ecc7913 | j_mayer | typedef struct ppc405_dma_t ppc405_dma_t; |
621 | 8ecc7913 | j_mayer | struct ppc405_dma_t {
|
622 | 8ecc7913 | j_mayer | qemu_irq irqs[4];
|
623 | 8ecc7913 | j_mayer | uint32_t cr[4];
|
624 | 8ecc7913 | j_mayer | uint32_t ct[4];
|
625 | 8ecc7913 | j_mayer | uint32_t da[4];
|
626 | 8ecc7913 | j_mayer | uint32_t sa[4];
|
627 | 8ecc7913 | j_mayer | uint32_t sg[4];
|
628 | 8ecc7913 | j_mayer | uint32_t sr; |
629 | 8ecc7913 | j_mayer | uint32_t sgc; |
630 | 8ecc7913 | j_mayer | uint32_t slp; |
631 | 8ecc7913 | j_mayer | uint32_t pol; |
632 | 8ecc7913 | j_mayer | }; |
633 | 8ecc7913 | j_mayer | |
634 | 8ecc7913 | j_mayer | static target_ulong dcr_read_dma (void *opaque, int dcrn) |
635 | 8ecc7913 | j_mayer | { |
636 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
637 | 8ecc7913 | j_mayer | |
638 | 8ecc7913 | j_mayer | dma = opaque; |
639 | 8ecc7913 | j_mayer | |
640 | 8ecc7913 | j_mayer | return 0; |
641 | 8ecc7913 | j_mayer | } |
642 | 8ecc7913 | j_mayer | |
643 | 8ecc7913 | j_mayer | static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
644 | 8ecc7913 | j_mayer | { |
645 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
646 | 8ecc7913 | j_mayer | |
647 | 8ecc7913 | j_mayer | dma = opaque; |
648 | 8ecc7913 | j_mayer | } |
649 | 8ecc7913 | j_mayer | |
650 | 8ecc7913 | j_mayer | static void ppc405_dma_reset (void *opaque) |
651 | 8ecc7913 | j_mayer | { |
652 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
653 | 8ecc7913 | j_mayer | int i;
|
654 | 8ecc7913 | j_mayer | |
655 | 8ecc7913 | j_mayer | dma = opaque; |
656 | 8ecc7913 | j_mayer | for (i = 0; i < 4; i++) { |
657 | 8ecc7913 | j_mayer | dma->cr[i] = 0x00000000;
|
658 | 8ecc7913 | j_mayer | dma->ct[i] = 0x00000000;
|
659 | 8ecc7913 | j_mayer | dma->da[i] = 0x00000000;
|
660 | 8ecc7913 | j_mayer | dma->sa[i] = 0x00000000;
|
661 | 8ecc7913 | j_mayer | dma->sg[i] = 0x00000000;
|
662 | 8ecc7913 | j_mayer | } |
663 | 8ecc7913 | j_mayer | dma->sr = 0x00000000;
|
664 | 8ecc7913 | j_mayer | dma->sgc = 0x00000000;
|
665 | 8ecc7913 | j_mayer | dma->slp = 0x7C000000;
|
666 | 8ecc7913 | j_mayer | dma->pol = 0x00000000;
|
667 | 8ecc7913 | j_mayer | } |
668 | 8ecc7913 | j_mayer | |
669 | 802670e6 | Blue Swirl | static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) |
670 | 8ecc7913 | j_mayer | { |
671 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
672 | 8ecc7913 | j_mayer | |
673 | 8ecc7913 | j_mayer | dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
674 | 487414f1 | aliguori | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
675 | 487414f1 | aliguori | ppc405_dma_reset(dma); |
676 | a08d4367 | Jan Kiszka | qemu_register_reset(&ppc405_dma_reset, dma); |
677 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CR0, |
678 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
679 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CT0, |
680 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
681 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_DA0, |
682 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
683 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SA0, |
684 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
685 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SG0, |
686 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
687 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CR1, |
688 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
689 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CT1, |
690 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
691 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_DA1, |
692 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
693 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SA1, |
694 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
695 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SG1, |
696 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
697 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CR2, |
698 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
699 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CT2, |
700 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
701 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_DA2, |
702 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
703 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SA2, |
704 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
705 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SG2, |
706 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
707 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CR3, |
708 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
709 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_CT3, |
710 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
711 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_DA3, |
712 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
713 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SA3, |
714 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
715 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SG3, |
716 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
717 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SR, |
718 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
719 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SGC, |
720 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
721 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_SLP, |
722 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
723 | 487414f1 | aliguori | ppc_dcr_register(env, DMA0_POL, |
724 | 487414f1 | aliguori | dma, &dcr_read_dma, &dcr_write_dma); |
725 | 8ecc7913 | j_mayer | } |
726 | 8ecc7913 | j_mayer | |
727 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
728 | 8ecc7913 | j_mayer | /* GPIO */
|
729 | 8ecc7913 | j_mayer | typedef struct ppc405_gpio_t ppc405_gpio_t; |
730 | 8ecc7913 | j_mayer | struct ppc405_gpio_t {
|
731 | 8ecc7913 | j_mayer | uint32_t or; |
732 | 8ecc7913 | j_mayer | uint32_t tcr; |
733 | 8ecc7913 | j_mayer | uint32_t osrh; |
734 | 8ecc7913 | j_mayer | uint32_t osrl; |
735 | 8ecc7913 | j_mayer | uint32_t tsrh; |
736 | 8ecc7913 | j_mayer | uint32_t tsrl; |
737 | 8ecc7913 | j_mayer | uint32_t odr; |
738 | 8ecc7913 | j_mayer | uint32_t ir; |
739 | 8ecc7913 | j_mayer | uint32_t rr1; |
740 | 8ecc7913 | j_mayer | uint32_t isr1h; |
741 | 8ecc7913 | j_mayer | uint32_t isr1l; |
742 | 8ecc7913 | j_mayer | }; |
743 | 8ecc7913 | j_mayer | |
744 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
745 | 8ecc7913 | j_mayer | { |
746 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
747 | 8ecc7913 | j_mayer | |
748 | 8ecc7913 | j_mayer | gpio = opaque; |
749 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
750 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
751 | 8ecc7913 | j_mayer | #endif
|
752 | 8ecc7913 | j_mayer | |
753 | 8ecc7913 | j_mayer | return 0; |
754 | 8ecc7913 | j_mayer | } |
755 | 8ecc7913 | j_mayer | |
756 | 8ecc7913 | j_mayer | static void ppc405_gpio_writeb (void *opaque, |
757 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
758 | 8ecc7913 | j_mayer | { |
759 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
760 | 8ecc7913 | j_mayer | |
761 | 8ecc7913 | j_mayer | gpio = opaque; |
762 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
763 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
764 | 90e189ec | Blue Swirl | value); |
765 | 8ecc7913 | j_mayer | #endif
|
766 | 8ecc7913 | j_mayer | } |
767 | 8ecc7913 | j_mayer | |
768 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
769 | 8ecc7913 | j_mayer | { |
770 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
771 | 8ecc7913 | j_mayer | |
772 | 8ecc7913 | j_mayer | gpio = opaque; |
773 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
774 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
775 | 8ecc7913 | j_mayer | #endif
|
776 | 8ecc7913 | j_mayer | |
777 | 8ecc7913 | j_mayer | return 0; |
778 | 8ecc7913 | j_mayer | } |
779 | 8ecc7913 | j_mayer | |
780 | 8ecc7913 | j_mayer | static void ppc405_gpio_writew (void *opaque, |
781 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
782 | 8ecc7913 | j_mayer | { |
783 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
784 | 8ecc7913 | j_mayer | |
785 | 8ecc7913 | j_mayer | gpio = opaque; |
786 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
787 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
788 | 90e189ec | Blue Swirl | value); |
789 | 8ecc7913 | j_mayer | #endif
|
790 | 8ecc7913 | j_mayer | } |
791 | 8ecc7913 | j_mayer | |
792 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
793 | 8ecc7913 | j_mayer | { |
794 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
795 | 8ecc7913 | j_mayer | |
796 | 8ecc7913 | j_mayer | gpio = opaque; |
797 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
798 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
799 | 8ecc7913 | j_mayer | #endif
|
800 | 8ecc7913 | j_mayer | |
801 | 8ecc7913 | j_mayer | return 0; |
802 | 8ecc7913 | j_mayer | } |
803 | 8ecc7913 | j_mayer | |
804 | 8ecc7913 | j_mayer | static void ppc405_gpio_writel (void *opaque, |
805 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
806 | 8ecc7913 | j_mayer | { |
807 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
808 | 8ecc7913 | j_mayer | |
809 | 8ecc7913 | j_mayer | gpio = opaque; |
810 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
811 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
812 | 90e189ec | Blue Swirl | value); |
813 | 8ecc7913 | j_mayer | #endif
|
814 | 8ecc7913 | j_mayer | } |
815 | 8ecc7913 | j_mayer | |
816 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const ppc405_gpio_read[] = { |
817 | 8ecc7913 | j_mayer | &ppc405_gpio_readb, |
818 | 8ecc7913 | j_mayer | &ppc405_gpio_readw, |
819 | 8ecc7913 | j_mayer | &ppc405_gpio_readl, |
820 | 8ecc7913 | j_mayer | }; |
821 | 8ecc7913 | j_mayer | |
822 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const ppc405_gpio_write[] = { |
823 | 8ecc7913 | j_mayer | &ppc405_gpio_writeb, |
824 | 8ecc7913 | j_mayer | &ppc405_gpio_writew, |
825 | 8ecc7913 | j_mayer | &ppc405_gpio_writel, |
826 | 8ecc7913 | j_mayer | }; |
827 | 8ecc7913 | j_mayer | |
828 | 8ecc7913 | j_mayer | static void ppc405_gpio_reset (void *opaque) |
829 | 8ecc7913 | j_mayer | { |
830 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
831 | 8ecc7913 | j_mayer | |
832 | 8ecc7913 | j_mayer | gpio = opaque; |
833 | 8ecc7913 | j_mayer | } |
834 | 8ecc7913 | j_mayer | |
835 | 802670e6 | Blue Swirl | static void ppc405_gpio_init(target_phys_addr_t base) |
836 | 8ecc7913 | j_mayer | { |
837 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
838 | 802670e6 | Blue Swirl | int io;
|
839 | 8ecc7913 | j_mayer | |
840 | 8ecc7913 | j_mayer | gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
841 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
842 | 90e189ec | Blue Swirl | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
843 | 8ecc7913 | j_mayer | #endif
|
844 | 802670e6 | Blue Swirl | io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); |
845 | 802670e6 | Blue Swirl | cpu_register_physical_memory(base, 0x038, io);
|
846 | 802670e6 | Blue Swirl | ppc405_gpio_reset(gpio); |
847 | 802670e6 | Blue Swirl | qemu_register_reset(&ppc405_gpio_reset, gpio); |
848 | 8ecc7913 | j_mayer | } |
849 | 8ecc7913 | j_mayer | |
850 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
851 | 8ecc7913 | j_mayer | /* On Chip Memory */
|
852 | 8ecc7913 | j_mayer | enum {
|
853 | 8ecc7913 | j_mayer | OCM0_ISARC = 0x018,
|
854 | 8ecc7913 | j_mayer | OCM0_ISACNTL = 0x019,
|
855 | 8ecc7913 | j_mayer | OCM0_DSARC = 0x01A,
|
856 | 8ecc7913 | j_mayer | OCM0_DSACNTL = 0x01B,
|
857 | 8ecc7913 | j_mayer | }; |
858 | 8ecc7913 | j_mayer | |
859 | 8ecc7913 | j_mayer | typedef struct ppc405_ocm_t ppc405_ocm_t; |
860 | 8ecc7913 | j_mayer | struct ppc405_ocm_t {
|
861 | 8ecc7913 | j_mayer | target_ulong offset; |
862 | 8ecc7913 | j_mayer | uint32_t isarc; |
863 | 8ecc7913 | j_mayer | uint32_t isacntl; |
864 | 8ecc7913 | j_mayer | uint32_t dsarc; |
865 | 8ecc7913 | j_mayer | uint32_t dsacntl; |
866 | 8ecc7913 | j_mayer | }; |
867 | 8ecc7913 | j_mayer | |
868 | 8ecc7913 | j_mayer | static void ocm_update_mappings (ppc405_ocm_t *ocm, |
869 | 8ecc7913 | j_mayer | uint32_t isarc, uint32_t isacntl, |
870 | 8ecc7913 | j_mayer | uint32_t dsarc, uint32_t dsacntl) |
871 | 8ecc7913 | j_mayer | { |
872 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
873 | aae9366a | j_mayer | printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
874 | aae9366a | j_mayer | " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 |
875 | aae9366a | j_mayer | " (%08" PRIx32 " %08" PRIx32 ")\n", |
876 | 8ecc7913 | j_mayer | isarc, isacntl, dsarc, dsacntl, |
877 | 8ecc7913 | j_mayer | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
878 | 8ecc7913 | j_mayer | #endif
|
879 | 8ecc7913 | j_mayer | if (ocm->isarc != isarc ||
|
880 | 8ecc7913 | j_mayer | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
881 | 8ecc7913 | j_mayer | if (ocm->isacntl & 0x80000000) { |
882 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
883 | aae9366a | j_mayer | printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
884 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
885 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
886 | 8ecc7913 | j_mayer | } |
887 | 8ecc7913 | j_mayer | if (isacntl & 0x80000000) { |
888 | 8ecc7913 | j_mayer | /* Map new instruction memory region */
|
889 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
890 | aae9366a | j_mayer | printf("OCM map ISA %08" PRIx32 "\n", isarc); |
891 | 8ecc7913 | j_mayer | #endif
|
892 | 8ecc7913 | j_mayer | cpu_register_physical_memory(isarc, 0x04000000,
|
893 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
894 | 8ecc7913 | j_mayer | } |
895 | 8ecc7913 | j_mayer | } |
896 | 8ecc7913 | j_mayer | if (ocm->dsarc != dsarc ||
|
897 | 8ecc7913 | j_mayer | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
898 | 8ecc7913 | j_mayer | if (ocm->dsacntl & 0x80000000) { |
899 | 8ecc7913 | j_mayer | /* Beware not to unmap the region we just mapped */
|
900 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
901 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
902 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
903 | aae9366a | j_mayer | printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
904 | 8ecc7913 | j_mayer | #endif
|
905 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
906 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
907 | 8ecc7913 | j_mayer | } |
908 | 8ecc7913 | j_mayer | } |
909 | 8ecc7913 | j_mayer | if (dsacntl & 0x80000000) { |
910 | 8ecc7913 | j_mayer | /* Beware not to remap the region we just mapped */
|
911 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || dsarc != isarc) { |
912 | 8ecc7913 | j_mayer | /* Map new data memory region */
|
913 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
914 | aae9366a | j_mayer | printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
915 | 8ecc7913 | j_mayer | #endif
|
916 | 8ecc7913 | j_mayer | cpu_register_physical_memory(dsarc, 0x04000000,
|
917 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
918 | 8ecc7913 | j_mayer | } |
919 | 8ecc7913 | j_mayer | } |
920 | 8ecc7913 | j_mayer | } |
921 | 8ecc7913 | j_mayer | } |
922 | 8ecc7913 | j_mayer | |
923 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
924 | 8ecc7913 | j_mayer | { |
925 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
926 | 8ecc7913 | j_mayer | target_ulong ret; |
927 | 8ecc7913 | j_mayer | |
928 | 8ecc7913 | j_mayer | ocm = opaque; |
929 | 8ecc7913 | j_mayer | switch (dcrn) {
|
930 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
931 | 8ecc7913 | j_mayer | ret = ocm->isarc; |
932 | 8ecc7913 | j_mayer | break;
|
933 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
934 | 8ecc7913 | j_mayer | ret = ocm->isacntl; |
935 | 8ecc7913 | j_mayer | break;
|
936 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
937 | 8ecc7913 | j_mayer | ret = ocm->dsarc; |
938 | 8ecc7913 | j_mayer | break;
|
939 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
940 | 8ecc7913 | j_mayer | ret = ocm->dsacntl; |
941 | 8ecc7913 | j_mayer | break;
|
942 | 8ecc7913 | j_mayer | default:
|
943 | 8ecc7913 | j_mayer | ret = 0;
|
944 | 8ecc7913 | j_mayer | break;
|
945 | 8ecc7913 | j_mayer | } |
946 | 8ecc7913 | j_mayer | |
947 | 8ecc7913 | j_mayer | return ret;
|
948 | 8ecc7913 | j_mayer | } |
949 | 8ecc7913 | j_mayer | |
950 | 8ecc7913 | j_mayer | static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
951 | 8ecc7913 | j_mayer | { |
952 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
953 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
954 | 8ecc7913 | j_mayer | |
955 | 8ecc7913 | j_mayer | ocm = opaque; |
956 | 8ecc7913 | j_mayer | isarc = ocm->isarc; |
957 | 8ecc7913 | j_mayer | dsarc = ocm->dsarc; |
958 | 8ecc7913 | j_mayer | isacntl = ocm->isacntl; |
959 | 8ecc7913 | j_mayer | dsacntl = ocm->dsacntl; |
960 | 8ecc7913 | j_mayer | switch (dcrn) {
|
961 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
962 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
963 | 8ecc7913 | j_mayer | break;
|
964 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
965 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
966 | 8ecc7913 | j_mayer | break;
|
967 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
968 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
969 | 8ecc7913 | j_mayer | break;
|
970 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
971 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
972 | 8ecc7913 | j_mayer | break;
|
973 | 8ecc7913 | j_mayer | } |
974 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
975 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
976 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
977 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
978 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
979 | 8ecc7913 | j_mayer | } |
980 | 8ecc7913 | j_mayer | |
981 | 8ecc7913 | j_mayer | static void ocm_reset (void *opaque) |
982 | 8ecc7913 | j_mayer | { |
983 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
984 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
985 | 8ecc7913 | j_mayer | |
986 | 8ecc7913 | j_mayer | ocm = opaque; |
987 | 8ecc7913 | j_mayer | isarc = 0x00000000;
|
988 | 8ecc7913 | j_mayer | isacntl = 0x00000000;
|
989 | 8ecc7913 | j_mayer | dsarc = 0x00000000;
|
990 | 8ecc7913 | j_mayer | dsacntl = 0x00000000;
|
991 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
992 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
993 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
994 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
995 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
996 | 8ecc7913 | j_mayer | } |
997 | 8ecc7913 | j_mayer | |
998 | 802670e6 | Blue Swirl | static void ppc405_ocm_init(CPUState *env) |
999 | 8ecc7913 | j_mayer | { |
1000 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
1001 | 8ecc7913 | j_mayer | |
1002 | 8ecc7913 | j_mayer | ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
1003 | 5c130f65 | pbrook | ocm->offset = qemu_ram_alloc(4096);
|
1004 | 487414f1 | aliguori | ocm_reset(ocm); |
1005 | a08d4367 | Jan Kiszka | qemu_register_reset(&ocm_reset, ocm); |
1006 | 487414f1 | aliguori | ppc_dcr_register(env, OCM0_ISARC, |
1007 | 487414f1 | aliguori | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1008 | 487414f1 | aliguori | ppc_dcr_register(env, OCM0_ISACNTL, |
1009 | 487414f1 | aliguori | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1010 | 487414f1 | aliguori | ppc_dcr_register(env, OCM0_DSARC, |
1011 | 487414f1 | aliguori | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1012 | 487414f1 | aliguori | ppc_dcr_register(env, OCM0_DSACNTL, |
1013 | 487414f1 | aliguori | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1014 | 8ecc7913 | j_mayer | } |
1015 | 8ecc7913 | j_mayer | |
1016 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1017 | 8ecc7913 | j_mayer | /* I2C controller */
|
1018 | 8ecc7913 | j_mayer | typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
1019 | 8ecc7913 | j_mayer | struct ppc4xx_i2c_t {
|
1020 | 9c02f1a2 | j_mayer | qemu_irq irq; |
1021 | 8ecc7913 | j_mayer | uint8_t mdata; |
1022 | 8ecc7913 | j_mayer | uint8_t lmadr; |
1023 | 8ecc7913 | j_mayer | uint8_t hmadr; |
1024 | 8ecc7913 | j_mayer | uint8_t cntl; |
1025 | 8ecc7913 | j_mayer | uint8_t mdcntl; |
1026 | 8ecc7913 | j_mayer | uint8_t sts; |
1027 | 8ecc7913 | j_mayer | uint8_t extsts; |
1028 | 8ecc7913 | j_mayer | uint8_t sdata; |
1029 | 8ecc7913 | j_mayer | uint8_t lsadr; |
1030 | 8ecc7913 | j_mayer | uint8_t hsadr; |
1031 | 8ecc7913 | j_mayer | uint8_t clkdiv; |
1032 | 8ecc7913 | j_mayer | uint8_t intrmsk; |
1033 | 8ecc7913 | j_mayer | uint8_t xfrcnt; |
1034 | 8ecc7913 | j_mayer | uint8_t xtcntlss; |
1035 | 8ecc7913 | j_mayer | uint8_t directcntl; |
1036 | 8ecc7913 | j_mayer | }; |
1037 | 8ecc7913 | j_mayer | |
1038 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
1039 | 8ecc7913 | j_mayer | { |
1040 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1041 | 8ecc7913 | j_mayer | uint32_t ret; |
1042 | 8ecc7913 | j_mayer | |
1043 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1044 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1045 | 8ecc7913 | j_mayer | #endif
|
1046 | 8ecc7913 | j_mayer | i2c = opaque; |
1047 | 802670e6 | Blue Swirl | switch (addr) {
|
1048 | 8ecc7913 | j_mayer | case 0x00: |
1049 | 8ecc7913 | j_mayer | // i2c_readbyte(&i2c->mdata);
|
1050 | 8ecc7913 | j_mayer | ret = i2c->mdata; |
1051 | 8ecc7913 | j_mayer | break;
|
1052 | 8ecc7913 | j_mayer | case 0x02: |
1053 | 8ecc7913 | j_mayer | ret = i2c->sdata; |
1054 | 8ecc7913 | j_mayer | break;
|
1055 | 8ecc7913 | j_mayer | case 0x04: |
1056 | 8ecc7913 | j_mayer | ret = i2c->lmadr; |
1057 | 8ecc7913 | j_mayer | break;
|
1058 | 8ecc7913 | j_mayer | case 0x05: |
1059 | 8ecc7913 | j_mayer | ret = i2c->hmadr; |
1060 | 8ecc7913 | j_mayer | break;
|
1061 | 8ecc7913 | j_mayer | case 0x06: |
1062 | 8ecc7913 | j_mayer | ret = i2c->cntl; |
1063 | 8ecc7913 | j_mayer | break;
|
1064 | 8ecc7913 | j_mayer | case 0x07: |
1065 | 8ecc7913 | j_mayer | ret = i2c->mdcntl; |
1066 | 8ecc7913 | j_mayer | break;
|
1067 | 8ecc7913 | j_mayer | case 0x08: |
1068 | 8ecc7913 | j_mayer | ret = i2c->sts; |
1069 | 8ecc7913 | j_mayer | break;
|
1070 | 8ecc7913 | j_mayer | case 0x09: |
1071 | 8ecc7913 | j_mayer | ret = i2c->extsts; |
1072 | 8ecc7913 | j_mayer | break;
|
1073 | 8ecc7913 | j_mayer | case 0x0A: |
1074 | 8ecc7913 | j_mayer | ret = i2c->lsadr; |
1075 | 8ecc7913 | j_mayer | break;
|
1076 | 8ecc7913 | j_mayer | case 0x0B: |
1077 | 8ecc7913 | j_mayer | ret = i2c->hsadr; |
1078 | 8ecc7913 | j_mayer | break;
|
1079 | 8ecc7913 | j_mayer | case 0x0C: |
1080 | 8ecc7913 | j_mayer | ret = i2c->clkdiv; |
1081 | 8ecc7913 | j_mayer | break;
|
1082 | 8ecc7913 | j_mayer | case 0x0D: |
1083 | 8ecc7913 | j_mayer | ret = i2c->intrmsk; |
1084 | 8ecc7913 | j_mayer | break;
|
1085 | 8ecc7913 | j_mayer | case 0x0E: |
1086 | 8ecc7913 | j_mayer | ret = i2c->xfrcnt; |
1087 | 8ecc7913 | j_mayer | break;
|
1088 | 8ecc7913 | j_mayer | case 0x0F: |
1089 | 8ecc7913 | j_mayer | ret = i2c->xtcntlss; |
1090 | 8ecc7913 | j_mayer | break;
|
1091 | 8ecc7913 | j_mayer | case 0x10: |
1092 | 8ecc7913 | j_mayer | ret = i2c->directcntl; |
1093 | 8ecc7913 | j_mayer | break;
|
1094 | 8ecc7913 | j_mayer | default:
|
1095 | 8ecc7913 | j_mayer | ret = 0x00;
|
1096 | 8ecc7913 | j_mayer | break;
|
1097 | 8ecc7913 | j_mayer | } |
1098 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1099 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret); |
1100 | 8ecc7913 | j_mayer | #endif
|
1101 | 8ecc7913 | j_mayer | |
1102 | 8ecc7913 | j_mayer | return ret;
|
1103 | 8ecc7913 | j_mayer | } |
1104 | 8ecc7913 | j_mayer | |
1105 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writeb (void *opaque, |
1106 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1107 | 8ecc7913 | j_mayer | { |
1108 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1109 | 8ecc7913 | j_mayer | |
1110 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1111 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1112 | 90e189ec | Blue Swirl | value); |
1113 | 8ecc7913 | j_mayer | #endif
|
1114 | 8ecc7913 | j_mayer | i2c = opaque; |
1115 | 802670e6 | Blue Swirl | switch (addr) {
|
1116 | 8ecc7913 | j_mayer | case 0x00: |
1117 | 8ecc7913 | j_mayer | i2c->mdata = value; |
1118 | 8ecc7913 | j_mayer | // i2c_sendbyte(&i2c->mdata);
|
1119 | 8ecc7913 | j_mayer | break;
|
1120 | 8ecc7913 | j_mayer | case 0x02: |
1121 | 8ecc7913 | j_mayer | i2c->sdata = value; |
1122 | 8ecc7913 | j_mayer | break;
|
1123 | 8ecc7913 | j_mayer | case 0x04: |
1124 | 8ecc7913 | j_mayer | i2c->lmadr = value; |
1125 | 8ecc7913 | j_mayer | break;
|
1126 | 8ecc7913 | j_mayer | case 0x05: |
1127 | 8ecc7913 | j_mayer | i2c->hmadr = value; |
1128 | 8ecc7913 | j_mayer | break;
|
1129 | 8ecc7913 | j_mayer | case 0x06: |
1130 | 8ecc7913 | j_mayer | i2c->cntl = value; |
1131 | 8ecc7913 | j_mayer | break;
|
1132 | 8ecc7913 | j_mayer | case 0x07: |
1133 | 8ecc7913 | j_mayer | i2c->mdcntl = value & 0xDF;
|
1134 | 8ecc7913 | j_mayer | break;
|
1135 | 8ecc7913 | j_mayer | case 0x08: |
1136 | 8ecc7913 | j_mayer | i2c->sts &= ~(value & 0x0A);
|
1137 | 8ecc7913 | j_mayer | break;
|
1138 | 8ecc7913 | j_mayer | case 0x09: |
1139 | 8ecc7913 | j_mayer | i2c->extsts &= ~(value & 0x8F);
|
1140 | 8ecc7913 | j_mayer | break;
|
1141 | 8ecc7913 | j_mayer | case 0x0A: |
1142 | 8ecc7913 | j_mayer | i2c->lsadr = value; |
1143 | 8ecc7913 | j_mayer | break;
|
1144 | 8ecc7913 | j_mayer | case 0x0B: |
1145 | 8ecc7913 | j_mayer | i2c->hsadr = value; |
1146 | 8ecc7913 | j_mayer | break;
|
1147 | 8ecc7913 | j_mayer | case 0x0C: |
1148 | 8ecc7913 | j_mayer | i2c->clkdiv = value; |
1149 | 8ecc7913 | j_mayer | break;
|
1150 | 8ecc7913 | j_mayer | case 0x0D: |
1151 | 8ecc7913 | j_mayer | i2c->intrmsk = value; |
1152 | 8ecc7913 | j_mayer | break;
|
1153 | 8ecc7913 | j_mayer | case 0x0E: |
1154 | 8ecc7913 | j_mayer | i2c->xfrcnt = value & 0x77;
|
1155 | 8ecc7913 | j_mayer | break;
|
1156 | 8ecc7913 | j_mayer | case 0x0F: |
1157 | 8ecc7913 | j_mayer | i2c->xtcntlss = value; |
1158 | 8ecc7913 | j_mayer | break;
|
1159 | 8ecc7913 | j_mayer | case 0x10: |
1160 | 8ecc7913 | j_mayer | i2c->directcntl = value & 0x7;
|
1161 | 8ecc7913 | j_mayer | break;
|
1162 | 8ecc7913 | j_mayer | } |
1163 | 8ecc7913 | j_mayer | } |
1164 | 8ecc7913 | j_mayer | |
1165 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
1166 | 8ecc7913 | j_mayer | { |
1167 | 8ecc7913 | j_mayer | uint32_t ret; |
1168 | 8ecc7913 | j_mayer | |
1169 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1170 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1171 | 8ecc7913 | j_mayer | #endif
|
1172 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
1173 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
1174 | 8ecc7913 | j_mayer | |
1175 | 8ecc7913 | j_mayer | return ret;
|
1176 | 8ecc7913 | j_mayer | } |
1177 | 8ecc7913 | j_mayer | |
1178 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writew (void *opaque, |
1179 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1180 | 8ecc7913 | j_mayer | { |
1181 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1182 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1183 | 90e189ec | Blue Swirl | value); |
1184 | 8ecc7913 | j_mayer | #endif
|
1185 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
1186 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
1187 | 8ecc7913 | j_mayer | } |
1188 | 8ecc7913 | j_mayer | |
1189 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
1190 | 8ecc7913 | j_mayer | { |
1191 | 8ecc7913 | j_mayer | uint32_t ret; |
1192 | 8ecc7913 | j_mayer | |
1193 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1194 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1195 | 8ecc7913 | j_mayer | #endif
|
1196 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
1197 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
1198 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
1199 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
1200 | 8ecc7913 | j_mayer | |
1201 | 8ecc7913 | j_mayer | return ret;
|
1202 | 8ecc7913 | j_mayer | } |
1203 | 8ecc7913 | j_mayer | |
1204 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writel (void *opaque, |
1205 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1206 | 8ecc7913 | j_mayer | { |
1207 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1208 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1209 | 90e189ec | Blue Swirl | value); |
1210 | 8ecc7913 | j_mayer | #endif
|
1211 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
1212 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
1213 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
1214 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
1215 | 8ecc7913 | j_mayer | } |
1216 | 8ecc7913 | j_mayer | |
1217 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const i2c_read[] = { |
1218 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readb, |
1219 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readw, |
1220 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readl, |
1221 | 8ecc7913 | j_mayer | }; |
1222 | 8ecc7913 | j_mayer | |
1223 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const i2c_write[] = { |
1224 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writeb, |
1225 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writew, |
1226 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writel, |
1227 | 8ecc7913 | j_mayer | }; |
1228 | 8ecc7913 | j_mayer | |
1229 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_reset (void *opaque) |
1230 | 8ecc7913 | j_mayer | { |
1231 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1232 | 8ecc7913 | j_mayer | |
1233 | 8ecc7913 | j_mayer | i2c = opaque; |
1234 | 8ecc7913 | j_mayer | i2c->mdata = 0x00;
|
1235 | 8ecc7913 | j_mayer | i2c->sdata = 0x00;
|
1236 | 8ecc7913 | j_mayer | i2c->cntl = 0x00;
|
1237 | 8ecc7913 | j_mayer | i2c->mdcntl = 0x00;
|
1238 | 8ecc7913 | j_mayer | i2c->sts = 0x00;
|
1239 | 8ecc7913 | j_mayer | i2c->extsts = 0x00;
|
1240 | 8ecc7913 | j_mayer | i2c->clkdiv = 0x00;
|
1241 | 8ecc7913 | j_mayer | i2c->xfrcnt = 0x00;
|
1242 | 8ecc7913 | j_mayer | i2c->directcntl = 0x0F;
|
1243 | 8ecc7913 | j_mayer | } |
1244 | 8ecc7913 | j_mayer | |
1245 | 802670e6 | Blue Swirl | static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) |
1246 | 8ecc7913 | j_mayer | { |
1247 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1248 | 802670e6 | Blue Swirl | int io;
|
1249 | 8ecc7913 | j_mayer | |
1250 | 8ecc7913 | j_mayer | i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
1251 | 487414f1 | aliguori | i2c->irq = irq; |
1252 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1253 | 90e189ec | Blue Swirl | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1254 | 8ecc7913 | j_mayer | #endif
|
1255 | 802670e6 | Blue Swirl | io = cpu_register_io_memory(i2c_read, i2c_write, i2c); |
1256 | 802670e6 | Blue Swirl | cpu_register_physical_memory(base, 0x011, io);
|
1257 | 802670e6 | Blue Swirl | ppc4xx_i2c_reset(i2c); |
1258 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_i2c_reset, i2c); |
1259 | 8ecc7913 | j_mayer | } |
1260 | 8ecc7913 | j_mayer | |
1261 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1262 | 9c02f1a2 | j_mayer | /* General purpose timers */
|
1263 | 9c02f1a2 | j_mayer | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
1264 | 9c02f1a2 | j_mayer | struct ppc4xx_gpt_t {
|
1265 | 9c02f1a2 | j_mayer | int64_t tb_offset; |
1266 | 9c02f1a2 | j_mayer | uint32_t tb_freq; |
1267 | 9c02f1a2 | j_mayer | struct QEMUTimer *timer;
|
1268 | 9c02f1a2 | j_mayer | qemu_irq irqs[5];
|
1269 | 9c02f1a2 | j_mayer | uint32_t oe; |
1270 | 9c02f1a2 | j_mayer | uint32_t ol; |
1271 | 9c02f1a2 | j_mayer | uint32_t im; |
1272 | 9c02f1a2 | j_mayer | uint32_t is; |
1273 | 9c02f1a2 | j_mayer | uint32_t ie; |
1274 | 9c02f1a2 | j_mayer | uint32_t comp[5];
|
1275 | 9c02f1a2 | j_mayer | uint32_t mask[5];
|
1276 | 9c02f1a2 | j_mayer | }; |
1277 | 9c02f1a2 | j_mayer | |
1278 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
1279 | 9c02f1a2 | j_mayer | { |
1280 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1281 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1282 | 9c02f1a2 | j_mayer | #endif
|
1283 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1284 | 9c02f1a2 | j_mayer | return -1; |
1285 | 9c02f1a2 | j_mayer | } |
1286 | 9c02f1a2 | j_mayer | |
1287 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writeb (void *opaque, |
1288 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1289 | 9c02f1a2 | j_mayer | { |
1290 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1291 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1292 | 90e189ec | Blue Swirl | value); |
1293 | 9c02f1a2 | j_mayer | #endif
|
1294 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1295 | 9c02f1a2 | j_mayer | } |
1296 | 9c02f1a2 | j_mayer | |
1297 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
1298 | 9c02f1a2 | j_mayer | { |
1299 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1300 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1301 | 9c02f1a2 | j_mayer | #endif
|
1302 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1303 | 9c02f1a2 | j_mayer | return -1; |
1304 | 9c02f1a2 | j_mayer | } |
1305 | 9c02f1a2 | j_mayer | |
1306 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writew (void *opaque, |
1307 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1308 | 9c02f1a2 | j_mayer | { |
1309 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1310 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1311 | 90e189ec | Blue Swirl | value); |
1312 | 9c02f1a2 | j_mayer | #endif
|
1313 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1314 | 9c02f1a2 | j_mayer | } |
1315 | 9c02f1a2 | j_mayer | |
1316 | 9c02f1a2 | j_mayer | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
1317 | 9c02f1a2 | j_mayer | { |
1318 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1319 | 9c02f1a2 | j_mayer | return 0; |
1320 | 9c02f1a2 | j_mayer | } |
1321 | 9c02f1a2 | j_mayer | |
1322 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
1323 | 9c02f1a2 | j_mayer | { |
1324 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1325 | 9c02f1a2 | j_mayer | } |
1326 | 9c02f1a2 | j_mayer | |
1327 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
1328 | 9c02f1a2 | j_mayer | { |
1329 | 9c02f1a2 | j_mayer | uint32_t mask; |
1330 | 9c02f1a2 | j_mayer | int i;
|
1331 | 9c02f1a2 | j_mayer | |
1332 | 9c02f1a2 | j_mayer | mask = 0x80000000;
|
1333 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1334 | 9c02f1a2 | j_mayer | if (gpt->oe & mask) {
|
1335 | 9c02f1a2 | j_mayer | /* Output is enabled */
|
1336 | 9c02f1a2 | j_mayer | if (ppc4xx_gpt_compare(gpt, i)) {
|
1337 | 9c02f1a2 | j_mayer | /* Comparison is OK */
|
1338 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
1339 | 9c02f1a2 | j_mayer | } else {
|
1340 | 9c02f1a2 | j_mayer | /* Comparison is KO */
|
1341 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
1342 | 9c02f1a2 | j_mayer | } |
1343 | 9c02f1a2 | j_mayer | } |
1344 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
1345 | 9c02f1a2 | j_mayer | } |
1346 | 9c02f1a2 | j_mayer | } |
1347 | 9c02f1a2 | j_mayer | |
1348 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
1349 | 9c02f1a2 | j_mayer | { |
1350 | 9c02f1a2 | j_mayer | uint32_t mask; |
1351 | 9c02f1a2 | j_mayer | int i;
|
1352 | 9c02f1a2 | j_mayer | |
1353 | 9c02f1a2 | j_mayer | mask = 0x00008000;
|
1354 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1355 | 9c02f1a2 | j_mayer | if (gpt->is & gpt->im & mask)
|
1356 | 9c02f1a2 | j_mayer | qemu_irq_raise(gpt->irqs[i]); |
1357 | 9c02f1a2 | j_mayer | else
|
1358 | 9c02f1a2 | j_mayer | qemu_irq_lower(gpt->irqs[i]); |
1359 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
1360 | 9c02f1a2 | j_mayer | } |
1361 | 9c02f1a2 | j_mayer | } |
1362 | 9c02f1a2 | j_mayer | |
1363 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
1364 | 9c02f1a2 | j_mayer | { |
1365 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1366 | 9c02f1a2 | j_mayer | } |
1367 | 9c02f1a2 | j_mayer | |
1368 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
1369 | 9c02f1a2 | j_mayer | { |
1370 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1371 | 9c02f1a2 | j_mayer | uint32_t ret; |
1372 | 9c02f1a2 | j_mayer | int idx;
|
1373 | 9c02f1a2 | j_mayer | |
1374 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1375 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1376 | 9c02f1a2 | j_mayer | #endif
|
1377 | 9c02f1a2 | j_mayer | gpt = opaque; |
1378 | 802670e6 | Blue Swirl | switch (addr) {
|
1379 | 9c02f1a2 | j_mayer | case 0x00: |
1380 | 9c02f1a2 | j_mayer | /* Time base counter */
|
1381 | 9c02f1a2 | j_mayer | ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
1382 | 9c02f1a2 | j_mayer | gpt->tb_freq, ticks_per_sec); |
1383 | 9c02f1a2 | j_mayer | break;
|
1384 | 9c02f1a2 | j_mayer | case 0x10: |
1385 | 9c02f1a2 | j_mayer | /* Output enable */
|
1386 | 9c02f1a2 | j_mayer | ret = gpt->oe; |
1387 | 9c02f1a2 | j_mayer | break;
|
1388 | 9c02f1a2 | j_mayer | case 0x14: |
1389 | 9c02f1a2 | j_mayer | /* Output level */
|
1390 | 9c02f1a2 | j_mayer | ret = gpt->ol; |
1391 | 9c02f1a2 | j_mayer | break;
|
1392 | 9c02f1a2 | j_mayer | case 0x18: |
1393 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
1394 | 9c02f1a2 | j_mayer | ret = gpt->im; |
1395 | 9c02f1a2 | j_mayer | break;
|
1396 | 9c02f1a2 | j_mayer | case 0x1C: |
1397 | 9c02f1a2 | j_mayer | case 0x20: |
1398 | 9c02f1a2 | j_mayer | /* Interrupt status */
|
1399 | 9c02f1a2 | j_mayer | ret = gpt->is; |
1400 | 9c02f1a2 | j_mayer | break;
|
1401 | 9c02f1a2 | j_mayer | case 0x24: |
1402 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
1403 | 9c02f1a2 | j_mayer | ret = gpt->ie; |
1404 | 9c02f1a2 | j_mayer | break;
|
1405 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
1406 | 9c02f1a2 | j_mayer | /* Compare timer */
|
1407 | 802670e6 | Blue Swirl | idx = (addr - 0x80) >> 2; |
1408 | 9c02f1a2 | j_mayer | ret = gpt->comp[idx]; |
1409 | 9c02f1a2 | j_mayer | break;
|
1410 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
1411 | 9c02f1a2 | j_mayer | /* Compare mask */
|
1412 | 802670e6 | Blue Swirl | idx = (addr - 0xC0) >> 2; |
1413 | 9c02f1a2 | j_mayer | ret = gpt->mask[idx]; |
1414 | 9c02f1a2 | j_mayer | break;
|
1415 | 9c02f1a2 | j_mayer | default:
|
1416 | 9c02f1a2 | j_mayer | ret = -1;
|
1417 | 9c02f1a2 | j_mayer | break;
|
1418 | 9c02f1a2 | j_mayer | } |
1419 | 9c02f1a2 | j_mayer | |
1420 | 9c02f1a2 | j_mayer | return ret;
|
1421 | 9c02f1a2 | j_mayer | } |
1422 | 9c02f1a2 | j_mayer | |
1423 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writel (void *opaque, |
1424 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1425 | 9c02f1a2 | j_mayer | { |
1426 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1427 | 9c02f1a2 | j_mayer | int idx;
|
1428 | 9c02f1a2 | j_mayer | |
1429 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1430 | 90e189ec | Blue Swirl | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1431 | 90e189ec | Blue Swirl | value); |
1432 | 9c02f1a2 | j_mayer | #endif
|
1433 | 9c02f1a2 | j_mayer | gpt = opaque; |
1434 | 802670e6 | Blue Swirl | switch (addr) {
|
1435 | 9c02f1a2 | j_mayer | case 0x00: |
1436 | 9c02f1a2 | j_mayer | /* Time base counter */
|
1437 | 9c02f1a2 | j_mayer | gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
1438 | 9c02f1a2 | j_mayer | - qemu_get_clock(vm_clock); |
1439 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1440 | 9c02f1a2 | j_mayer | break;
|
1441 | 9c02f1a2 | j_mayer | case 0x10: |
1442 | 9c02f1a2 | j_mayer | /* Output enable */
|
1443 | 9c02f1a2 | j_mayer | gpt->oe = value & 0xF8000000;
|
1444 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1445 | 9c02f1a2 | j_mayer | break;
|
1446 | 9c02f1a2 | j_mayer | case 0x14: |
1447 | 9c02f1a2 | j_mayer | /* Output level */
|
1448 | 9c02f1a2 | j_mayer | gpt->ol = value & 0xF8000000;
|
1449 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1450 | 9c02f1a2 | j_mayer | break;
|
1451 | 9c02f1a2 | j_mayer | case 0x18: |
1452 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
1453 | 9c02f1a2 | j_mayer | gpt->im = value & 0x0000F800;
|
1454 | 9c02f1a2 | j_mayer | break;
|
1455 | 9c02f1a2 | j_mayer | case 0x1C: |
1456 | 9c02f1a2 | j_mayer | /* Interrupt status set */
|
1457 | 9c02f1a2 | j_mayer | gpt->is |= value & 0x0000F800;
|
1458 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1459 | 9c02f1a2 | j_mayer | break;
|
1460 | 9c02f1a2 | j_mayer | case 0x20: |
1461 | 9c02f1a2 | j_mayer | /* Interrupt status clear */
|
1462 | 9c02f1a2 | j_mayer | gpt->is &= ~(value & 0x0000F800);
|
1463 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1464 | 9c02f1a2 | j_mayer | break;
|
1465 | 9c02f1a2 | j_mayer | case 0x24: |
1466 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
1467 | 9c02f1a2 | j_mayer | gpt->ie = value & 0x0000F800;
|
1468 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1469 | 9c02f1a2 | j_mayer | break;
|
1470 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
1471 | 9c02f1a2 | j_mayer | /* Compare timer */
|
1472 | 802670e6 | Blue Swirl | idx = (addr - 0x80) >> 2; |
1473 | 9c02f1a2 | j_mayer | gpt->comp[idx] = value & 0xF8000000;
|
1474 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1475 | 9c02f1a2 | j_mayer | break;
|
1476 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
1477 | 9c02f1a2 | j_mayer | /* Compare mask */
|
1478 | 802670e6 | Blue Swirl | idx = (addr - 0xC0) >> 2; |
1479 | 9c02f1a2 | j_mayer | gpt->mask[idx] = value & 0xF8000000;
|
1480 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1481 | 9c02f1a2 | j_mayer | break;
|
1482 | 9c02f1a2 | j_mayer | } |
1483 | 9c02f1a2 | j_mayer | } |
1484 | 9c02f1a2 | j_mayer | |
1485 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const gpt_read[] = { |
1486 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readb, |
1487 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readw, |
1488 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readl, |
1489 | 9c02f1a2 | j_mayer | }; |
1490 | 9c02f1a2 | j_mayer | |
1491 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const gpt_write[] = { |
1492 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writeb, |
1493 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writew, |
1494 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writel, |
1495 | 9c02f1a2 | j_mayer | }; |
1496 | 9c02f1a2 | j_mayer | |
1497 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_cb (void *opaque) |
1498 | 9c02f1a2 | j_mayer | { |
1499 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1500 | 9c02f1a2 | j_mayer | |
1501 | 9c02f1a2 | j_mayer | gpt = opaque; |
1502 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1503 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1504 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1505 | 9c02f1a2 | j_mayer | } |
1506 | 9c02f1a2 | j_mayer | |
1507 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_reset (void *opaque) |
1508 | 9c02f1a2 | j_mayer | { |
1509 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1510 | 9c02f1a2 | j_mayer | int i;
|
1511 | 9c02f1a2 | j_mayer | |
1512 | 9c02f1a2 | j_mayer | gpt = opaque; |
1513 | 9c02f1a2 | j_mayer | qemu_del_timer(gpt->timer); |
1514 | 9c02f1a2 | j_mayer | gpt->oe = 0x00000000;
|
1515 | 9c02f1a2 | j_mayer | gpt->ol = 0x00000000;
|
1516 | 9c02f1a2 | j_mayer | gpt->im = 0x00000000;
|
1517 | 9c02f1a2 | j_mayer | gpt->is = 0x00000000;
|
1518 | 9c02f1a2 | j_mayer | gpt->ie = 0x00000000;
|
1519 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1520 | 9c02f1a2 | j_mayer | gpt->comp[i] = 0x00000000;
|
1521 | 9c02f1a2 | j_mayer | gpt->mask[i] = 0x00000000;
|
1522 | 9c02f1a2 | j_mayer | } |
1523 | 9c02f1a2 | j_mayer | } |
1524 | 9c02f1a2 | j_mayer | |
1525 | 802670e6 | Blue Swirl | static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) |
1526 | 9c02f1a2 | j_mayer | { |
1527 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1528 | 9c02f1a2 | j_mayer | int i;
|
1529 | 802670e6 | Blue Swirl | int io;
|
1530 | 9c02f1a2 | j_mayer | |
1531 | 9c02f1a2 | j_mayer | gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
1532 | 802670e6 | Blue Swirl | for (i = 0; i < 5; i++) { |
1533 | 487414f1 | aliguori | gpt->irqs[i] = irqs[i]; |
1534 | 802670e6 | Blue Swirl | } |
1535 | 487414f1 | aliguori | gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
1536 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1537 | 90e189ec | Blue Swirl | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1538 | 9c02f1a2 | j_mayer | #endif
|
1539 | 802670e6 | Blue Swirl | io = cpu_register_io_memory(gpt_read, gpt_write, gpt); |
1540 | 802670e6 | Blue Swirl | cpu_register_physical_memory(base, 0x0d4, io);
|
1541 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_gpt_reset, gpt); |
1542 | 802670e6 | Blue Swirl | ppc4xx_gpt_reset(gpt); |
1543 | 9c02f1a2 | j_mayer | } |
1544 | 9c02f1a2 | j_mayer | |
1545 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
1546 | 9c02f1a2 | j_mayer | /* MAL */
|
1547 | 9c02f1a2 | j_mayer | enum {
|
1548 | 9c02f1a2 | j_mayer | MAL0_CFG = 0x180,
|
1549 | 9c02f1a2 | j_mayer | MAL0_ESR = 0x181,
|
1550 | 9c02f1a2 | j_mayer | MAL0_IER = 0x182,
|
1551 | 9c02f1a2 | j_mayer | MAL0_TXCASR = 0x184,
|
1552 | 9c02f1a2 | j_mayer | MAL0_TXCARR = 0x185,
|
1553 | 9c02f1a2 | j_mayer | MAL0_TXEOBISR = 0x186,
|
1554 | 9c02f1a2 | j_mayer | MAL0_TXDEIR = 0x187,
|
1555 | 9c02f1a2 | j_mayer | MAL0_RXCASR = 0x190,
|
1556 | 9c02f1a2 | j_mayer | MAL0_RXCARR = 0x191,
|
1557 | 9c02f1a2 | j_mayer | MAL0_RXEOBISR = 0x192,
|
1558 | 9c02f1a2 | j_mayer | MAL0_RXDEIR = 0x193,
|
1559 | 9c02f1a2 | j_mayer | MAL0_TXCTP0R = 0x1A0,
|
1560 | 9c02f1a2 | j_mayer | MAL0_TXCTP1R = 0x1A1,
|
1561 | 9c02f1a2 | j_mayer | MAL0_TXCTP2R = 0x1A2,
|
1562 | 9c02f1a2 | j_mayer | MAL0_TXCTP3R = 0x1A3,
|
1563 | 9c02f1a2 | j_mayer | MAL0_RXCTP0R = 0x1C0,
|
1564 | 9c02f1a2 | j_mayer | MAL0_RXCTP1R = 0x1C1,
|
1565 | 9c02f1a2 | j_mayer | MAL0_RCBS0 = 0x1E0,
|
1566 | 9c02f1a2 | j_mayer | MAL0_RCBS1 = 0x1E1,
|
1567 | 9c02f1a2 | j_mayer | }; |
1568 | 9c02f1a2 | j_mayer | |
1569 | 9c02f1a2 | j_mayer | typedef struct ppc40x_mal_t ppc40x_mal_t; |
1570 | 9c02f1a2 | j_mayer | struct ppc40x_mal_t {
|
1571 | 9c02f1a2 | j_mayer | qemu_irq irqs[4];
|
1572 | 9c02f1a2 | j_mayer | uint32_t cfg; |
1573 | 9c02f1a2 | j_mayer | uint32_t esr; |
1574 | 9c02f1a2 | j_mayer | uint32_t ier; |
1575 | 9c02f1a2 | j_mayer | uint32_t txcasr; |
1576 | 9c02f1a2 | j_mayer | uint32_t txcarr; |
1577 | 9c02f1a2 | j_mayer | uint32_t txeobisr; |
1578 | 9c02f1a2 | j_mayer | uint32_t txdeir; |
1579 | 9c02f1a2 | j_mayer | uint32_t rxcasr; |
1580 | 9c02f1a2 | j_mayer | uint32_t rxcarr; |
1581 | 9c02f1a2 | j_mayer | uint32_t rxeobisr; |
1582 | 9c02f1a2 | j_mayer | uint32_t rxdeir; |
1583 | 9c02f1a2 | j_mayer | uint32_t txctpr[4];
|
1584 | 9c02f1a2 | j_mayer | uint32_t rxctpr[2];
|
1585 | 9c02f1a2 | j_mayer | uint32_t rcbs[2];
|
1586 | 9c02f1a2 | j_mayer | }; |
1587 | 9c02f1a2 | j_mayer | |
1588 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque); |
1589 | 9c02f1a2 | j_mayer | |
1590 | 9c02f1a2 | j_mayer | static target_ulong dcr_read_mal (void *opaque, int dcrn) |
1591 | 9c02f1a2 | j_mayer | { |
1592 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
1593 | 9c02f1a2 | j_mayer | target_ulong ret; |
1594 | 9c02f1a2 | j_mayer | |
1595 | 9c02f1a2 | j_mayer | mal = opaque; |
1596 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
1597 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
1598 | 9c02f1a2 | j_mayer | ret = mal->cfg; |
1599 | 9c02f1a2 | j_mayer | break;
|
1600 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
1601 | 9c02f1a2 | j_mayer | ret = mal->esr; |
1602 | 9c02f1a2 | j_mayer | break;
|
1603 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
1604 | 9c02f1a2 | j_mayer | ret = mal->ier; |
1605 | 9c02f1a2 | j_mayer | break;
|
1606 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
1607 | 9c02f1a2 | j_mayer | ret = mal->txcasr; |
1608 | 9c02f1a2 | j_mayer | break;
|
1609 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
1610 | 9c02f1a2 | j_mayer | ret = mal->txcarr; |
1611 | 9c02f1a2 | j_mayer | break;
|
1612 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
1613 | 9c02f1a2 | j_mayer | ret = mal->txeobisr; |
1614 | 9c02f1a2 | j_mayer | break;
|
1615 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
1616 | 9c02f1a2 | j_mayer | ret = mal->txdeir; |
1617 | 9c02f1a2 | j_mayer | break;
|
1618 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
1619 | 9c02f1a2 | j_mayer | ret = mal->rxcasr; |
1620 | 9c02f1a2 | j_mayer | break;
|
1621 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
1622 | 9c02f1a2 | j_mayer | ret = mal->rxcarr; |
1623 | 9c02f1a2 | j_mayer | break;
|
1624 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
1625 | 9c02f1a2 | j_mayer | ret = mal->rxeobisr; |
1626 | 9c02f1a2 | j_mayer | break;
|
1627 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
1628 | 9c02f1a2 | j_mayer | ret = mal->rxdeir; |
1629 | 9c02f1a2 | j_mayer | break;
|
1630 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
1631 | 9c02f1a2 | j_mayer | ret = mal->txctpr[0];
|
1632 | 9c02f1a2 | j_mayer | break;
|
1633 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
1634 | 9c02f1a2 | j_mayer | ret = mal->txctpr[1];
|
1635 | 9c02f1a2 | j_mayer | break;
|
1636 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
1637 | 9c02f1a2 | j_mayer | ret = mal->txctpr[2];
|
1638 | 9c02f1a2 | j_mayer | break;
|
1639 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
1640 | 9c02f1a2 | j_mayer | ret = mal->txctpr[3];
|
1641 | 9c02f1a2 | j_mayer | break;
|
1642 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
1643 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[0];
|
1644 | 9c02f1a2 | j_mayer | break;
|
1645 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
1646 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[1];
|
1647 | 9c02f1a2 | j_mayer | break;
|
1648 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
1649 | 9c02f1a2 | j_mayer | ret = mal->rcbs[0];
|
1650 | 9c02f1a2 | j_mayer | break;
|
1651 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
1652 | 9c02f1a2 | j_mayer | ret = mal->rcbs[1];
|
1653 | 9c02f1a2 | j_mayer | break;
|
1654 | 9c02f1a2 | j_mayer | default:
|
1655 | 9c02f1a2 | j_mayer | ret = 0;
|
1656 | 9c02f1a2 | j_mayer | break;
|
1657 | 9c02f1a2 | j_mayer | } |
1658 | 9c02f1a2 | j_mayer | |
1659 | 9c02f1a2 | j_mayer | return ret;
|
1660 | 9c02f1a2 | j_mayer | } |
1661 | 9c02f1a2 | j_mayer | |
1662 | 9c02f1a2 | j_mayer | static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
1663 | 9c02f1a2 | j_mayer | { |
1664 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
1665 | 9c02f1a2 | j_mayer | int idx;
|
1666 | 9c02f1a2 | j_mayer | |
1667 | 9c02f1a2 | j_mayer | mal = opaque; |
1668 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
1669 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
1670 | 9c02f1a2 | j_mayer | if (val & 0x80000000) |
1671 | 9c02f1a2 | j_mayer | ppc40x_mal_reset(mal); |
1672 | 9c02f1a2 | j_mayer | mal->cfg = val & 0x00FFC087;
|
1673 | 9c02f1a2 | j_mayer | break;
|
1674 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
1675 | 9c02f1a2 | j_mayer | /* Read/clear */
|
1676 | 9c02f1a2 | j_mayer | mal->esr &= ~val; |
1677 | 9c02f1a2 | j_mayer | break;
|
1678 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
1679 | 9c02f1a2 | j_mayer | mal->ier = val & 0x0000001F;
|
1680 | 9c02f1a2 | j_mayer | break;
|
1681 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
1682 | 9c02f1a2 | j_mayer | mal->txcasr = val & 0xF0000000;
|
1683 | 9c02f1a2 | j_mayer | break;
|
1684 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
1685 | 9c02f1a2 | j_mayer | mal->txcarr = val & 0xF0000000;
|
1686 | 9c02f1a2 | j_mayer | break;
|
1687 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
1688 | 9c02f1a2 | j_mayer | /* Read/clear */
|
1689 | 9c02f1a2 | j_mayer | mal->txeobisr &= ~val; |
1690 | 9c02f1a2 | j_mayer | break;
|
1691 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
1692 | 9c02f1a2 | j_mayer | /* Read/clear */
|
1693 | 9c02f1a2 | j_mayer | mal->txdeir &= ~val; |
1694 | 9c02f1a2 | j_mayer | break;
|
1695 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
1696 | 9c02f1a2 | j_mayer | mal->rxcasr = val & 0xC0000000;
|
1697 | 9c02f1a2 | j_mayer | break;
|
1698 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
1699 | 9c02f1a2 | j_mayer | mal->rxcarr = val & 0xC0000000;
|
1700 | 9c02f1a2 | j_mayer | break;
|
1701 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
1702 | 9c02f1a2 | j_mayer | /* Read/clear */
|
1703 | 9c02f1a2 | j_mayer | mal->rxeobisr &= ~val; |
1704 | 9c02f1a2 | j_mayer | break;
|
1705 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
1706 | 9c02f1a2 | j_mayer | /* Read/clear */
|
1707 | 9c02f1a2 | j_mayer | mal->rxdeir &= ~val; |
1708 | 9c02f1a2 | j_mayer | break;
|
1709 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
1710 | 9c02f1a2 | j_mayer | idx = 0;
|
1711 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
1712 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
1713 | 9c02f1a2 | j_mayer | idx = 1;
|
1714 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
1715 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
1716 | 9c02f1a2 | j_mayer | idx = 2;
|
1717 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
1718 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
1719 | 9c02f1a2 | j_mayer | idx = 3;
|
1720 | 9c02f1a2 | j_mayer | update_tx_ptr:
|
1721 | 9c02f1a2 | j_mayer | mal->txctpr[idx] = val; |
1722 | 9c02f1a2 | j_mayer | break;
|
1723 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
1724 | 9c02f1a2 | j_mayer | idx = 0;
|
1725 | 9c02f1a2 | j_mayer | goto update_rx_ptr;
|
1726 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
1727 | 9c02f1a2 | j_mayer | idx = 1;
|
1728 | 9c02f1a2 | j_mayer | update_rx_ptr:
|
1729 | 9c02f1a2 | j_mayer | mal->rxctpr[idx] = val; |
1730 | 9c02f1a2 | j_mayer | break;
|
1731 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
1732 | 9c02f1a2 | j_mayer | idx = 0;
|
1733 | 9c02f1a2 | j_mayer | goto update_rx_size;
|
1734 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
1735 | 9c02f1a2 | j_mayer | idx = 1;
|
1736 | 9c02f1a2 | j_mayer | update_rx_size:
|
1737 | 9c02f1a2 | j_mayer | mal->rcbs[idx] = val & 0x000000FF;
|
1738 | 9c02f1a2 | j_mayer | break;
|
1739 | 9c02f1a2 | j_mayer | } |
1740 | 9c02f1a2 | j_mayer | } |
1741 | 9c02f1a2 | j_mayer | |
1742 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque) |
1743 | 9c02f1a2 | j_mayer | { |
1744 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
1745 | 9c02f1a2 | j_mayer | |
1746 | 9c02f1a2 | j_mayer | mal = opaque; |
1747 | 9c02f1a2 | j_mayer | mal->cfg = 0x0007C000;
|
1748 | 9c02f1a2 | j_mayer | mal->esr = 0x00000000;
|
1749 | 9c02f1a2 | j_mayer | mal->ier = 0x00000000;
|
1750 | 9c02f1a2 | j_mayer | mal->rxcasr = 0x00000000;
|
1751 | 9c02f1a2 | j_mayer | mal->rxdeir = 0x00000000;
|
1752 | 9c02f1a2 | j_mayer | mal->rxeobisr = 0x00000000;
|
1753 | 9c02f1a2 | j_mayer | mal->txcasr = 0x00000000;
|
1754 | 9c02f1a2 | j_mayer | mal->txdeir = 0x00000000;
|
1755 | 9c02f1a2 | j_mayer | mal->txeobisr = 0x00000000;
|
1756 | 9c02f1a2 | j_mayer | } |
1757 | 9c02f1a2 | j_mayer | |
1758 | 802670e6 | Blue Swirl | static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) |
1759 | 9c02f1a2 | j_mayer | { |
1760 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
1761 | 9c02f1a2 | j_mayer | int i;
|
1762 | 9c02f1a2 | j_mayer | |
1763 | 9c02f1a2 | j_mayer | mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
1764 | 487414f1 | aliguori | for (i = 0; i < 4; i++) |
1765 | 487414f1 | aliguori | mal->irqs[i] = irqs[i]; |
1766 | 487414f1 | aliguori | ppc40x_mal_reset(mal); |
1767 | a08d4367 | Jan Kiszka | qemu_register_reset(&ppc40x_mal_reset, mal); |
1768 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_CFG, |
1769 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1770 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_ESR, |
1771 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1772 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_IER, |
1773 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1774 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCASR, |
1775 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1776 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCARR, |
1777 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1778 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXEOBISR, |
1779 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1780 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXDEIR, |
1781 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1782 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXCASR, |
1783 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1784 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXCARR, |
1785 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1786 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXEOBISR, |
1787 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1788 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXDEIR, |
1789 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1790 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCTP0R, |
1791 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1792 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCTP1R, |
1793 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1794 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCTP2R, |
1795 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1796 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_TXCTP3R, |
1797 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1798 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXCTP0R, |
1799 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1800 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RXCTP1R, |
1801 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1802 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RCBS0, |
1803 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1804 | 487414f1 | aliguori | ppc_dcr_register(env, MAL0_RCBS1, |
1805 | 487414f1 | aliguori | mal, &dcr_read_mal, &dcr_write_mal); |
1806 | 9c02f1a2 | j_mayer | } |
1807 | 9c02f1a2 | j_mayer | |
1808 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
1809 | 8ecc7913 | j_mayer | /* SPR */
|
1810 | 8ecc7913 | j_mayer | void ppc40x_core_reset (CPUState *env)
|
1811 | 8ecc7913 | j_mayer | { |
1812 | 8ecc7913 | j_mayer | target_ulong dbsr; |
1813 | 8ecc7913 | j_mayer | |
1814 | 8ecc7913 | j_mayer | printf("Reset PowerPC core\n");
|
1815 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1816 | ef397e88 | j_mayer | /* XXX: TOFIX */
|
1817 | ef397e88 | j_mayer | #if 0
|
1818 | 8ecc7913 | j_mayer | cpu_ppc_reset(env);
|
1819 | ef397e88 | j_mayer | #else
|
1820 | ef397e88 | j_mayer | qemu_system_reset_request(); |
1821 | ef397e88 | j_mayer | #endif
|
1822 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
1823 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
1824 | 8ecc7913 | j_mayer | dbsr |= 0x00000100;
|
1825 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
1826 | 8ecc7913 | j_mayer | } |
1827 | 8ecc7913 | j_mayer | |
1828 | 8ecc7913 | j_mayer | void ppc40x_chip_reset (CPUState *env)
|
1829 | 8ecc7913 | j_mayer | { |
1830 | 8ecc7913 | j_mayer | target_ulong dbsr; |
1831 | 8ecc7913 | j_mayer | |
1832 | 8ecc7913 | j_mayer | printf("Reset PowerPC chip\n");
|
1833 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1834 | ef397e88 | j_mayer | /* XXX: TOFIX */
|
1835 | ef397e88 | j_mayer | #if 0
|
1836 | 8ecc7913 | j_mayer | cpu_ppc_reset(env);
|
1837 | ef397e88 | j_mayer | #else
|
1838 | ef397e88 | j_mayer | qemu_system_reset_request(); |
1839 | ef397e88 | j_mayer | #endif
|
1840 | 8ecc7913 | j_mayer | /* XXX: TODO reset all internal peripherals */
|
1841 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
1842 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
1843 | 04f20795 | j_mayer | dbsr |= 0x00000200;
|
1844 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
1845 | 8ecc7913 | j_mayer | } |
1846 | 8ecc7913 | j_mayer | |
1847 | 8ecc7913 | j_mayer | void ppc40x_system_reset (CPUState *env)
|
1848 | 8ecc7913 | j_mayer | { |
1849 | 8ecc7913 | j_mayer | printf("Reset PowerPC system\n");
|
1850 | 8ecc7913 | j_mayer | qemu_system_reset_request(); |
1851 | 8ecc7913 | j_mayer | } |
1852 | 8ecc7913 | j_mayer | |
1853 | 8ecc7913 | j_mayer | void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
1854 | 8ecc7913 | j_mayer | { |
1855 | 8ecc7913 | j_mayer | switch ((val >> 28) & 0x3) { |
1856 | 8ecc7913 | j_mayer | case 0x0: |
1857 | 8ecc7913 | j_mayer | /* No action */
|
1858 | 8ecc7913 | j_mayer | break;
|
1859 | 8ecc7913 | j_mayer | case 0x1: |
1860 | 8ecc7913 | j_mayer | /* Core reset */
|
1861 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
1862 | 8ecc7913 | j_mayer | break;
|
1863 | 8ecc7913 | j_mayer | case 0x2: |
1864 | 8ecc7913 | j_mayer | /* Chip reset */
|
1865 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
1866 | 8ecc7913 | j_mayer | break;
|
1867 | 8ecc7913 | j_mayer | case 0x3: |
1868 | 8ecc7913 | j_mayer | /* System reset */
|
1869 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
1870 | 8ecc7913 | j_mayer | break;
|
1871 | 8ecc7913 | j_mayer | } |
1872 | 8ecc7913 | j_mayer | } |
1873 | 8ecc7913 | j_mayer | |
1874 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1875 | 8ecc7913 | j_mayer | /* PowerPC 405CR */
|
1876 | 8ecc7913 | j_mayer | enum {
|
1877 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PLLMR = 0x0B0,
|
1878 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR0 = 0x0B1,
|
1879 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR1 = 0x0B2,
|
1880 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PSR = 0x0B4,
|
1881 | 8ecc7913 | j_mayer | PPC405CR_CPC0_JTAGID = 0x0B5,
|
1882 | 8ecc7913 | j_mayer | PPC405CR_CPC0_ER = 0x0B9,
|
1883 | 8ecc7913 | j_mayer | PPC405CR_CPC0_FR = 0x0BA,
|
1884 | 8ecc7913 | j_mayer | PPC405CR_CPC0_SR = 0x0BB,
|
1885 | 8ecc7913 | j_mayer | }; |
1886 | 8ecc7913 | j_mayer | |
1887 | 04f20795 | j_mayer | enum {
|
1888 | 04f20795 | j_mayer | PPC405CR_CPU_CLK = 0,
|
1889 | 04f20795 | j_mayer | PPC405CR_TMR_CLK = 1,
|
1890 | 04f20795 | j_mayer | PPC405CR_PLB_CLK = 2,
|
1891 | 04f20795 | j_mayer | PPC405CR_SDRAM_CLK = 3,
|
1892 | 04f20795 | j_mayer | PPC405CR_OPB_CLK = 4,
|
1893 | 04f20795 | j_mayer | PPC405CR_EXT_CLK = 5,
|
1894 | 04f20795 | j_mayer | PPC405CR_UART_CLK = 6,
|
1895 | 04f20795 | j_mayer | PPC405CR_CLK_NB = 7,
|
1896 | 04f20795 | j_mayer | }; |
1897 | 04f20795 | j_mayer | |
1898 | 8ecc7913 | j_mayer | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
1899 | 8ecc7913 | j_mayer | struct ppc405cr_cpc_t {
|
1900 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
1901 | 8ecc7913 | j_mayer | uint32_t sysclk; |
1902 | 8ecc7913 | j_mayer | uint32_t psr; |
1903 | 8ecc7913 | j_mayer | uint32_t cr0; |
1904 | 8ecc7913 | j_mayer | uint32_t cr1; |
1905 | 8ecc7913 | j_mayer | uint32_t jtagid; |
1906 | 8ecc7913 | j_mayer | uint32_t pllmr; |
1907 | 8ecc7913 | j_mayer | uint32_t er; |
1908 | 8ecc7913 | j_mayer | uint32_t fr; |
1909 | 8ecc7913 | j_mayer | }; |
1910 | 8ecc7913 | j_mayer | |
1911 | 8ecc7913 | j_mayer | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
1912 | 8ecc7913 | j_mayer | { |
1913 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
1914 | 8ecc7913 | j_mayer | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
1915 | 8ecc7913 | j_mayer | int M, D0, D1, D2;
|
1916 | 8ecc7913 | j_mayer | |
1917 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
1918 | 8ecc7913 | j_mayer | if (cpc->pllmr & 0x80000000) { |
1919 | 8ecc7913 | j_mayer | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
1920 | 8ecc7913 | j_mayer | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
1921 | 8ecc7913 | j_mayer | M = D0 * D1 * D2; |
1922 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M; |
1923 | 8ecc7913 | j_mayer | if (VCO_out < 400000000 || VCO_out > 800000000) { |
1924 | 8ecc7913 | j_mayer | /* PLL cannot lock */
|
1925 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
1926 | 8ecc7913 | j_mayer | goto bypass_pll;
|
1927 | 8ecc7913 | j_mayer | } |
1928 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D2; |
1929 | 8ecc7913 | j_mayer | } else {
|
1930 | 8ecc7913 | j_mayer | /* Bypass PLL */
|
1931 | 8ecc7913 | j_mayer | bypass_pll:
|
1932 | 8ecc7913 | j_mayer | M = D0; |
1933 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk * M; |
1934 | 8ecc7913 | j_mayer | } |
1935 | 8ecc7913 | j_mayer | CPU_clk = PLL_out; |
1936 | 8ecc7913 | j_mayer | if (cpc->cr1 & 0x00800000) |
1937 | 8ecc7913 | j_mayer | TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
1938 | 8ecc7913 | j_mayer | else
|
1939 | 8ecc7913 | j_mayer | TMR_clk = CPU_clk; |
1940 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D0; |
1941 | 8ecc7913 | j_mayer | SDRAM_clk = PLB_clk; |
1942 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
1943 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D0; |
1944 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
1945 | 8ecc7913 | j_mayer | EXT_clk = PLB_clk / D0; |
1946 | 8ecc7913 | j_mayer | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
1947 | 8ecc7913 | j_mayer | UART_clk = CPU_clk / D0; |
1948 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
1949 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
1950 | 8ecc7913 | j_mayer | /* Setup time-base clock */
|
1951 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
1952 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
1953 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
1954 | 8ecc7913 | j_mayer | /* Setup SDRAM clock */
|
1955 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
1956 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
1957 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
1958 | 8ecc7913 | j_mayer | /* Setup external clock */
|
1959 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
1960 | 8ecc7913 | j_mayer | /* Setup UART clock */
|
1961 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
1962 | 8ecc7913 | j_mayer | } |
1963 | 8ecc7913 | j_mayer | |
1964 | 8ecc7913 | j_mayer | static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
1965 | 8ecc7913 | j_mayer | { |
1966 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
1967 | 8ecc7913 | j_mayer | target_ulong ret; |
1968 | 8ecc7913 | j_mayer | |
1969 | 8ecc7913 | j_mayer | cpc = opaque; |
1970 | 8ecc7913 | j_mayer | switch (dcrn) {
|
1971 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
1972 | 8ecc7913 | j_mayer | ret = cpc->pllmr; |
1973 | 8ecc7913 | j_mayer | break;
|
1974 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
1975 | 8ecc7913 | j_mayer | ret = cpc->cr0; |
1976 | 8ecc7913 | j_mayer | break;
|
1977 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
1978 | 8ecc7913 | j_mayer | ret = cpc->cr1; |
1979 | 8ecc7913 | j_mayer | break;
|
1980 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
1981 | 8ecc7913 | j_mayer | ret = cpc->psr; |
1982 | 8ecc7913 | j_mayer | break;
|
1983 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
1984 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
1985 | 8ecc7913 | j_mayer | break;
|
1986 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
1987 | 8ecc7913 | j_mayer | ret = cpc->er; |
1988 | 8ecc7913 | j_mayer | break;
|
1989 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
1990 | 8ecc7913 | j_mayer | ret = cpc->fr; |
1991 | 8ecc7913 | j_mayer | break;
|
1992 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
1993 | 8ecc7913 | j_mayer | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
1994 | 8ecc7913 | j_mayer | break;
|
1995 | 8ecc7913 | j_mayer | default:
|
1996 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
1997 | 8ecc7913 | j_mayer | ret = 0;
|
1998 | 8ecc7913 | j_mayer | break;
|
1999 | 8ecc7913 | j_mayer | } |
2000 | 8ecc7913 | j_mayer | |
2001 | 8ecc7913 | j_mayer | return ret;
|
2002 | 8ecc7913 | j_mayer | } |
2003 | 8ecc7913 | j_mayer | |
2004 | 8ecc7913 | j_mayer | static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2005 | 8ecc7913 | j_mayer | { |
2006 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2007 | 8ecc7913 | j_mayer | |
2008 | 8ecc7913 | j_mayer | cpc = opaque; |
2009 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2010 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
2011 | 8ecc7913 | j_mayer | cpc->pllmr = val & 0xFFF77C3F;
|
2012 | 8ecc7913 | j_mayer | break;
|
2013 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
2014 | 8ecc7913 | j_mayer | cpc->cr0 = val & 0x0FFFFFFE;
|
2015 | 8ecc7913 | j_mayer | break;
|
2016 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
2017 | 8ecc7913 | j_mayer | cpc->cr1 = val & 0x00800000;
|
2018 | 8ecc7913 | j_mayer | break;
|
2019 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
2020 | 8ecc7913 | j_mayer | /* Read-only */
|
2021 | 8ecc7913 | j_mayer | break;
|
2022 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
2023 | 8ecc7913 | j_mayer | /* Read-only */
|
2024 | 8ecc7913 | j_mayer | break;
|
2025 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
2026 | 8ecc7913 | j_mayer | cpc->er = val & 0xBFFC0000;
|
2027 | 8ecc7913 | j_mayer | break;
|
2028 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
2029 | 8ecc7913 | j_mayer | cpc->fr = val & 0xBFFC0000;
|
2030 | 8ecc7913 | j_mayer | break;
|
2031 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
2032 | 8ecc7913 | j_mayer | /* Read-only */
|
2033 | 8ecc7913 | j_mayer | break;
|
2034 | 8ecc7913 | j_mayer | } |
2035 | 8ecc7913 | j_mayer | } |
2036 | 8ecc7913 | j_mayer | |
2037 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_reset (void *opaque) |
2038 | 8ecc7913 | j_mayer | { |
2039 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2040 | 8ecc7913 | j_mayer | int D;
|
2041 | 8ecc7913 | j_mayer | |
2042 | 8ecc7913 | j_mayer | cpc = opaque; |
2043 | 8ecc7913 | j_mayer | /* Compute PLLMR value from PSR settings */
|
2044 | 8ecc7913 | j_mayer | cpc->pllmr = 0x80000000;
|
2045 | 8ecc7913 | j_mayer | /* PFWD */
|
2046 | 8ecc7913 | j_mayer | switch ((cpc->psr >> 30) & 3) { |
2047 | 8ecc7913 | j_mayer | case 0: |
2048 | 8ecc7913 | j_mayer | /* Bypass */
|
2049 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
2050 | 8ecc7913 | j_mayer | break;
|
2051 | 8ecc7913 | j_mayer | case 1: |
2052 | 8ecc7913 | j_mayer | /* Divide by 3 */
|
2053 | 8ecc7913 | j_mayer | cpc->pllmr |= 5 << 16; |
2054 | 8ecc7913 | j_mayer | break;
|
2055 | 8ecc7913 | j_mayer | case 2: |
2056 | 8ecc7913 | j_mayer | /* Divide by 4 */
|
2057 | 8ecc7913 | j_mayer | cpc->pllmr |= 4 << 16; |
2058 | 8ecc7913 | j_mayer | break;
|
2059 | 8ecc7913 | j_mayer | case 3: |
2060 | 8ecc7913 | j_mayer | /* Divide by 6 */
|
2061 | 8ecc7913 | j_mayer | cpc->pllmr |= 2 << 16; |
2062 | 8ecc7913 | j_mayer | break;
|
2063 | 8ecc7913 | j_mayer | } |
2064 | 8ecc7913 | j_mayer | /* PFBD */
|
2065 | 8ecc7913 | j_mayer | D = (cpc->psr >> 28) & 3; |
2066 | 8ecc7913 | j_mayer | cpc->pllmr |= (D + 1) << 20; |
2067 | 8ecc7913 | j_mayer | /* PT */
|
2068 | 8ecc7913 | j_mayer | D = (cpc->psr >> 25) & 7; |
2069 | 8ecc7913 | j_mayer | switch (D) {
|
2070 | 8ecc7913 | j_mayer | case 0x2: |
2071 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x13;
|
2072 | 8ecc7913 | j_mayer | break;
|
2073 | 8ecc7913 | j_mayer | case 0x4: |
2074 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x15;
|
2075 | 8ecc7913 | j_mayer | break;
|
2076 | 8ecc7913 | j_mayer | case 0x5: |
2077 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x16;
|
2078 | 8ecc7913 | j_mayer | break;
|
2079 | 8ecc7913 | j_mayer | default:
|
2080 | 8ecc7913 | j_mayer | break;
|
2081 | 8ecc7913 | j_mayer | } |
2082 | 8ecc7913 | j_mayer | /* PDC */
|
2083 | 8ecc7913 | j_mayer | D = (cpc->psr >> 23) & 3; |
2084 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 26;
|
2085 | 8ecc7913 | j_mayer | /* ODP */
|
2086 | 8ecc7913 | j_mayer | D = (cpc->psr >> 21) & 3; |
2087 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 10;
|
2088 | 8ecc7913 | j_mayer | /* EBPD */
|
2089 | 8ecc7913 | j_mayer | D = (cpc->psr >> 17) & 3; |
2090 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 24;
|
2091 | 8ecc7913 | j_mayer | cpc->cr0 = 0x0000003C;
|
2092 | 8ecc7913 | j_mayer | cpc->cr1 = 0x2B0D8800;
|
2093 | 8ecc7913 | j_mayer | cpc->er = 0x00000000;
|
2094 | 8ecc7913 | j_mayer | cpc->fr = 0x00000000;
|
2095 | 8ecc7913 | j_mayer | ppc405cr_clk_setup(cpc); |
2096 | 8ecc7913 | j_mayer | } |
2097 | 8ecc7913 | j_mayer | |
2098 | 8ecc7913 | j_mayer | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
2099 | 8ecc7913 | j_mayer | { |
2100 | 8ecc7913 | j_mayer | int D;
|
2101 | 8ecc7913 | j_mayer | |
2102 | 8ecc7913 | j_mayer | /* XXX: this should be read from IO pins */
|
2103 | 8ecc7913 | j_mayer | cpc->psr = 0x00000000; /* 8 bits ROM */ |
2104 | 8ecc7913 | j_mayer | /* PFWD */
|
2105 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
2106 | 8ecc7913 | j_mayer | cpc->psr |= D << 30;
|
2107 | 8ecc7913 | j_mayer | /* PFBD */
|
2108 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2109 | 8ecc7913 | j_mayer | cpc->psr |= D << 28;
|
2110 | 8ecc7913 | j_mayer | /* PDC */
|
2111 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2112 | 8ecc7913 | j_mayer | cpc->psr |= D << 23;
|
2113 | 8ecc7913 | j_mayer | /* PT */
|
2114 | 8ecc7913 | j_mayer | D = 0x5; /* M = 16 */ |
2115 | 8ecc7913 | j_mayer | cpc->psr |= D << 25;
|
2116 | 8ecc7913 | j_mayer | /* ODP */
|
2117 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2118 | 8ecc7913 | j_mayer | cpc->psr |= D << 21;
|
2119 | 8ecc7913 | j_mayer | /* EBDP */
|
2120 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
2121 | 8ecc7913 | j_mayer | cpc->psr |= D << 17;
|
2122 | 8ecc7913 | j_mayer | } |
2123 | 8ecc7913 | j_mayer | |
2124 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2125 | 8ecc7913 | j_mayer | uint32_t sysclk) |
2126 | 8ecc7913 | j_mayer | { |
2127 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2128 | 8ecc7913 | j_mayer | |
2129 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
2130 | 487414f1 | aliguori | memcpy(cpc->clk_setup, clk_setup, |
2131 | 487414f1 | aliguori | PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
2132 | 487414f1 | aliguori | cpc->sysclk = sysclk; |
2133 | 487414f1 | aliguori | cpc->jtagid = 0x42051049;
|
2134 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
2135 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2136 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
2137 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2138 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
2139 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2140 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
2141 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2142 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
2143 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2144 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
2145 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2146 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
2147 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2148 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
2149 | 487414f1 | aliguori | &dcr_read_crcpc, &dcr_write_crcpc); |
2150 | 487414f1 | aliguori | ppc405cr_clk_init(cpc); |
2151 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc405cr_cpc_reset, cpc); |
2152 | 487414f1 | aliguori | ppc405cr_cpc_reset(cpc); |
2153 | 8ecc7913 | j_mayer | } |
2154 | 8ecc7913 | j_mayer | |
2155 | 71db710f | blueswir1 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
2156 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[4],
|
2157 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
2158 | 5c130f65 | pbrook | int do_init)
|
2159 | 8ecc7913 | j_mayer | { |
2160 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2161 | 8ecc7913 | j_mayer | qemu_irq dma_irqs[4];
|
2162 | 8ecc7913 | j_mayer | CPUState *env; |
2163 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
2164 | 8ecc7913 | j_mayer | |
2165 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
2166 | 008ff9d7 | j_mayer | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
2167 | 04f20795 | j_mayer | &clk_setup[PPC405CR_TMR_CLK], sysclk); |
2168 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
2169 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
2170 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
2171 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
2172 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
2173 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
2174 | 802670e6 | Blue Swirl | ppc4xx_opba_init(0xef600600);
|
2175 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
2176 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2177 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
2178 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2179 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
2180 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2181 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2182 | 8ecc7913 | j_mayer | *picp = pic; |
2183 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
2184 | 80e8bd2b | aurel32 | ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
2185 | 8ecc7913 | j_mayer | /* External bus controller */
|
2186 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
2187 | 8ecc7913 | j_mayer | /* DMA controller */
|
2188 | 04f20795 | j_mayer | dma_irqs[0] = pic[26]; |
2189 | 04f20795 | j_mayer | dma_irqs[1] = pic[25]; |
2190 | 04f20795 | j_mayer | dma_irqs[2] = pic[24]; |
2191 | 04f20795 | j_mayer | dma_irqs[3] = pic[23]; |
2192 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
2193 | 8ecc7913 | j_mayer | /* Serial ports */
|
2194 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
2195 | 802670e6 | Blue Swirl | serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2196 | 802670e6 | Blue Swirl | serial_hds[0], 1); |
2197 | 8ecc7913 | j_mayer | } |
2198 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
2199 | 802670e6 | Blue Swirl | serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2200 | 802670e6 | Blue Swirl | serial_hds[1], 1); |
2201 | 8ecc7913 | j_mayer | } |
2202 | 8ecc7913 | j_mayer | /* IIC controller */
|
2203 | 802670e6 | Blue Swirl | ppc405_i2c_init(0xef600500, pic[2]); |
2204 | 8ecc7913 | j_mayer | /* GPIO */
|
2205 | 802670e6 | Blue Swirl | ppc405_gpio_init(0xef600700);
|
2206 | 8ecc7913 | j_mayer | /* CPU control */
|
2207 | 8ecc7913 | j_mayer | ppc405cr_cpc_init(env, clk_setup, sysclk); |
2208 | 8ecc7913 | j_mayer | |
2209 | 8ecc7913 | j_mayer | return env;
|
2210 | 8ecc7913 | j_mayer | } |
2211 | 8ecc7913 | j_mayer | |
2212 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
2213 | 8ecc7913 | j_mayer | /* PowerPC 405EP */
|
2214 | 8ecc7913 | j_mayer | /* CPU control */
|
2215 | 8ecc7913 | j_mayer | enum {
|
2216 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
2217 | 8ecc7913 | j_mayer | PPC405EP_CPC0_BOOT = 0x0F1,
|
2218 | 8ecc7913 | j_mayer | PPC405EP_CPC0_EPCTL = 0x0F3,
|
2219 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
2220 | 8ecc7913 | j_mayer | PPC405EP_CPC0_UCR = 0x0F5,
|
2221 | 8ecc7913 | j_mayer | PPC405EP_CPC0_SRR = 0x0F6,
|
2222 | 8ecc7913 | j_mayer | PPC405EP_CPC0_JTAGID = 0x0F7,
|
2223 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PCI = 0x0F9,
|
2224 | 9c02f1a2 | j_mayer | #if 0
|
2225 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_ER = xxx,
|
2226 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_FR = xxx,
|
2227 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_SR = xxx,
|
2228 | 9c02f1a2 | j_mayer | #endif
|
2229 | 8ecc7913 | j_mayer | }; |
2230 | 8ecc7913 | j_mayer | |
2231 | 04f20795 | j_mayer | enum {
|
2232 | 04f20795 | j_mayer | PPC405EP_CPU_CLK = 0,
|
2233 | 04f20795 | j_mayer | PPC405EP_PLB_CLK = 1,
|
2234 | 04f20795 | j_mayer | PPC405EP_OPB_CLK = 2,
|
2235 | 04f20795 | j_mayer | PPC405EP_EBC_CLK = 3,
|
2236 | 04f20795 | j_mayer | PPC405EP_MAL_CLK = 4,
|
2237 | 04f20795 | j_mayer | PPC405EP_PCI_CLK = 5,
|
2238 | 04f20795 | j_mayer | PPC405EP_UART0_CLK = 6,
|
2239 | 04f20795 | j_mayer | PPC405EP_UART1_CLK = 7,
|
2240 | 04f20795 | j_mayer | PPC405EP_CLK_NB = 8,
|
2241 | 04f20795 | j_mayer | }; |
2242 | 04f20795 | j_mayer | |
2243 | 8ecc7913 | j_mayer | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
2244 | 8ecc7913 | j_mayer | struct ppc405ep_cpc_t {
|
2245 | 8ecc7913 | j_mayer | uint32_t sysclk; |
2246 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
2247 | 8ecc7913 | j_mayer | uint32_t boot; |
2248 | 8ecc7913 | j_mayer | uint32_t epctl; |
2249 | 8ecc7913 | j_mayer | uint32_t pllmr[2];
|
2250 | 8ecc7913 | j_mayer | uint32_t ucr; |
2251 | 8ecc7913 | j_mayer | uint32_t srr; |
2252 | 8ecc7913 | j_mayer | uint32_t jtagid; |
2253 | 8ecc7913 | j_mayer | uint32_t pci; |
2254 | 9c02f1a2 | j_mayer | /* Clock and power management */
|
2255 | 9c02f1a2 | j_mayer | uint32_t er; |
2256 | 9c02f1a2 | j_mayer | uint32_t fr; |
2257 | 9c02f1a2 | j_mayer | uint32_t sr; |
2258 | 8ecc7913 | j_mayer | }; |
2259 | 8ecc7913 | j_mayer | |
2260 | 8ecc7913 | j_mayer | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
2261 | 8ecc7913 | j_mayer | { |
2262 | 8ecc7913 | j_mayer | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
2263 | 8ecc7913 | j_mayer | uint32_t UART0_clk, UART1_clk; |
2264 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
2265 | 8ecc7913 | j_mayer | int M, D;
|
2266 | 8ecc7913 | j_mayer | |
2267 | 8ecc7913 | j_mayer | VCO_out = 0;
|
2268 | 8ecc7913 | j_mayer | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
2269 | 8ecc7913 | j_mayer | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
2270 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2271 | aae9366a | j_mayer | printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); |
2272 | aae9366a | j_mayer | #endif
|
2273 | 8ecc7913 | j_mayer | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
2274 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2275 | aae9366a | j_mayer | printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); |
2276 | aae9366a | j_mayer | #endif
|
2277 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M * D; |
2278 | 8ecc7913 | j_mayer | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
2279 | 8ecc7913 | j_mayer | /* Error - unlock the PLL */
|
2280 | 8ecc7913 | j_mayer | printf("VCO out of range %" PRIu64 "\n", VCO_out); |
2281 | 8ecc7913 | j_mayer | #if 0
|
2282 | 8ecc7913 | j_mayer | cpc->pllmr[1] &= ~0x80000000;
|
2283 | 8ecc7913 | j_mayer | goto pll_bypass;
|
2284 | 8ecc7913 | j_mayer | #endif
|
2285 | 8ecc7913 | j_mayer | } |
2286 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D; |
2287 | 9c02f1a2 | j_mayer | /* Pretend the PLL is locked */
|
2288 | 9c02f1a2 | j_mayer | cpc->boot |= 0x00000001;
|
2289 | 8ecc7913 | j_mayer | } else {
|
2290 | 8ecc7913 | j_mayer | #if 0
|
2291 | 8ecc7913 | j_mayer | pll_bypass:
|
2292 | 8ecc7913 | j_mayer | #endif
|
2293 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk; |
2294 | 9c02f1a2 | j_mayer | if (cpc->pllmr[1] & 0x40000000) { |
2295 | 9c02f1a2 | j_mayer | /* Pretend the PLL is not locked */
|
2296 | 9c02f1a2 | j_mayer | cpc->boot &= ~0x00000001;
|
2297 | 9c02f1a2 | j_mayer | } |
2298 | 8ecc7913 | j_mayer | } |
2299 | 8ecc7913 | j_mayer | /* Now, compute all other clocks */
|
2300 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
2301 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2302 | aae9366a | j_mayer | printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); |
2303 | 8ecc7913 | j_mayer | #endif
|
2304 | 8ecc7913 | j_mayer | CPU_clk = PLL_out / D; |
2305 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
2306 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2307 | aae9366a | j_mayer | printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); |
2308 | 8ecc7913 | j_mayer | #endif
|
2309 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D; |
2310 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
2311 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2312 | aae9366a | j_mayer | printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); |
2313 | 8ecc7913 | j_mayer | #endif
|
2314 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D; |
2315 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
2316 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2317 | aae9366a | j_mayer | printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); |
2318 | 8ecc7913 | j_mayer | #endif
|
2319 | 8ecc7913 | j_mayer | EBC_clk = PLB_clk / D; |
2320 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
2321 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2322 | aae9366a | j_mayer | printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); |
2323 | 8ecc7913 | j_mayer | #endif
|
2324 | 8ecc7913 | j_mayer | MAL_clk = PLB_clk / D; |
2325 | 8ecc7913 | j_mayer | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
2326 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2327 | aae9366a | j_mayer | printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); |
2328 | 8ecc7913 | j_mayer | #endif
|
2329 | 8ecc7913 | j_mayer | PCI_clk = PLB_clk / D; |
2330 | 8ecc7913 | j_mayer | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
2331 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2332 | aae9366a | j_mayer | printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); |
2333 | 8ecc7913 | j_mayer | #endif
|
2334 | 8ecc7913 | j_mayer | UART0_clk = PLL_out / D; |
2335 | 8ecc7913 | j_mayer | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
2336 | aae9366a | j_mayer | #ifdef DEBUG_CLOCKS_LL
|
2337 | aae9366a | j_mayer | printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); |
2338 | 8ecc7913 | j_mayer | #endif
|
2339 | 8ecc7913 | j_mayer | UART1_clk = PLL_out / D; |
2340 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2341 | aae9366a | j_mayer | printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
2342 | 8ecc7913 | j_mayer | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
2343 | aae9366a | j_mayer | printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
2344 | aae9366a | j_mayer | " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 |
2345 | aae9366a | j_mayer | " UART1 %" PRIu32 "\n", |
2346 | 8ecc7913 | j_mayer | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
2347 | 8ecc7913 | j_mayer | UART0_clk, UART1_clk); |
2348 | 8ecc7913 | j_mayer | #endif
|
2349 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
2350 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
2351 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
2352 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
2353 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
2354 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
2355 | 8ecc7913 | j_mayer | /* Setup external clock */
|
2356 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
2357 | 8ecc7913 | j_mayer | /* Setup MAL clock */
|
2358 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
2359 | 8ecc7913 | j_mayer | /* Setup PCI clock */
|
2360 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
2361 | 8ecc7913 | j_mayer | /* Setup UART0 clock */
|
2362 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
2363 | 8ecc7913 | j_mayer | /* Setup UART1 clock */
|
2364 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
2365 | 8ecc7913 | j_mayer | } |
2366 | 8ecc7913 | j_mayer | |
2367 | 8ecc7913 | j_mayer | static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
2368 | 8ecc7913 | j_mayer | { |
2369 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2370 | 8ecc7913 | j_mayer | target_ulong ret; |
2371 | 8ecc7913 | j_mayer | |
2372 | 8ecc7913 | j_mayer | cpc = opaque; |
2373 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2374 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
2375 | 8ecc7913 | j_mayer | ret = cpc->boot; |
2376 | 8ecc7913 | j_mayer | break;
|
2377 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
2378 | 8ecc7913 | j_mayer | ret = cpc->epctl; |
2379 | 8ecc7913 | j_mayer | break;
|
2380 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
2381 | 8ecc7913 | j_mayer | ret = cpc->pllmr[0];
|
2382 | 8ecc7913 | j_mayer | break;
|
2383 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
2384 | 8ecc7913 | j_mayer | ret = cpc->pllmr[1];
|
2385 | 8ecc7913 | j_mayer | break;
|
2386 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
2387 | 8ecc7913 | j_mayer | ret = cpc->ucr; |
2388 | 8ecc7913 | j_mayer | break;
|
2389 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
2390 | 8ecc7913 | j_mayer | ret = cpc->srr; |
2391 | 8ecc7913 | j_mayer | break;
|
2392 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
2393 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
2394 | 8ecc7913 | j_mayer | break;
|
2395 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
2396 | 8ecc7913 | j_mayer | ret = cpc->pci; |
2397 | 8ecc7913 | j_mayer | break;
|
2398 | 8ecc7913 | j_mayer | default:
|
2399 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
2400 | 8ecc7913 | j_mayer | ret = 0;
|
2401 | 8ecc7913 | j_mayer | break;
|
2402 | 8ecc7913 | j_mayer | } |
2403 | 8ecc7913 | j_mayer | |
2404 | 8ecc7913 | j_mayer | return ret;
|
2405 | 8ecc7913 | j_mayer | } |
2406 | 8ecc7913 | j_mayer | |
2407 | 8ecc7913 | j_mayer | static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
2408 | 8ecc7913 | j_mayer | { |
2409 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2410 | 8ecc7913 | j_mayer | |
2411 | 8ecc7913 | j_mayer | cpc = opaque; |
2412 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2413 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
2414 | 8ecc7913 | j_mayer | /* Read-only register */
|
2415 | 8ecc7913 | j_mayer | break;
|
2416 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
2417 | 8ecc7913 | j_mayer | /* Don't care for now */
|
2418 | 8ecc7913 | j_mayer | cpc->epctl = val & 0xC00000F3;
|
2419 | 8ecc7913 | j_mayer | break;
|
2420 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
2421 | 8ecc7913 | j_mayer | cpc->pllmr[0] = val & 0x00633333; |
2422 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2423 | 8ecc7913 | j_mayer | break;
|
2424 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
2425 | 8ecc7913 | j_mayer | cpc->pllmr[1] = val & 0xC0F73FFF; |
2426 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2427 | 8ecc7913 | j_mayer | break;
|
2428 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
2429 | 8ecc7913 | j_mayer | /* UART control - don't care for now */
|
2430 | 8ecc7913 | j_mayer | cpc->ucr = val & 0x003F7F7F;
|
2431 | 8ecc7913 | j_mayer | break;
|
2432 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
2433 | 8ecc7913 | j_mayer | cpc->srr = val; |
2434 | 8ecc7913 | j_mayer | break;
|
2435 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
2436 | 8ecc7913 | j_mayer | /* Read-only */
|
2437 | 8ecc7913 | j_mayer | break;
|
2438 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
2439 | 8ecc7913 | j_mayer | cpc->pci = val; |
2440 | 8ecc7913 | j_mayer | break;
|
2441 | 8ecc7913 | j_mayer | } |
2442 | 8ecc7913 | j_mayer | } |
2443 | 8ecc7913 | j_mayer | |
2444 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_reset (void *opaque) |
2445 | 8ecc7913 | j_mayer | { |
2446 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc = opaque; |
2447 | 8ecc7913 | j_mayer | |
2448 | 8ecc7913 | j_mayer | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
2449 | 8ecc7913 | j_mayer | cpc->epctl = 0x00000000;
|
2450 | 8ecc7913 | j_mayer | cpc->pllmr[0] = 0x00011010; |
2451 | 8ecc7913 | j_mayer | cpc->pllmr[1] = 0x40000000; |
2452 | 8ecc7913 | j_mayer | cpc->ucr = 0x00000000;
|
2453 | 8ecc7913 | j_mayer | cpc->srr = 0x00040000;
|
2454 | 8ecc7913 | j_mayer | cpc->pci = 0x00000000;
|
2455 | 9c02f1a2 | j_mayer | cpc->er = 0x00000000;
|
2456 | 9c02f1a2 | j_mayer | cpc->fr = 0x00000000;
|
2457 | 9c02f1a2 | j_mayer | cpc->sr = 0x00000000;
|
2458 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2459 | 8ecc7913 | j_mayer | } |
2460 | 8ecc7913 | j_mayer | |
2461 | 8ecc7913 | j_mayer | /* XXX: sysclk should be between 25 and 100 MHz */
|
2462 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
2463 | 8ecc7913 | j_mayer | uint32_t sysclk) |
2464 | 8ecc7913 | j_mayer | { |
2465 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2466 | 8ecc7913 | j_mayer | |
2467 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
2468 | 487414f1 | aliguori | memcpy(cpc->clk_setup, clk_setup, |
2469 | 487414f1 | aliguori | PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
2470 | 487414f1 | aliguori | cpc->jtagid = 0x20267049;
|
2471 | 487414f1 | aliguori | cpc->sysclk = sysclk; |
2472 | 487414f1 | aliguori | ppc405ep_cpc_reset(cpc); |
2473 | a08d4367 | Jan Kiszka | qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
2474 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
2475 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2476 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
2477 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2478 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
2479 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2480 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
2481 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2482 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
2483 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2484 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
2485 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2486 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
2487 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2488 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
2489 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc); |
2490 | 9c02f1a2 | j_mayer | #if 0
|
2491 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
2492 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc);
|
2493 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
2494 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc);
|
2495 | 487414f1 | aliguori | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
2496 | 487414f1 | aliguori | &dcr_read_epcpc, &dcr_write_epcpc);
|
2497 | 9c02f1a2 | j_mayer | #endif
|
2498 | 8ecc7913 | j_mayer | } |
2499 | 8ecc7913 | j_mayer | |
2500 | 71db710f | blueswir1 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
2501 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[2],
|
2502 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
2503 | 5c130f65 | pbrook | int do_init)
|
2504 | 8ecc7913 | j_mayer | { |
2505 | 9c02f1a2 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2506 | 9c02f1a2 | j_mayer | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2507 | 8ecc7913 | j_mayer | CPUState *env; |
2508 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
2509 | 8ecc7913 | j_mayer | |
2510 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
2511 | 8ecc7913 | j_mayer | /* init CPUs */
|
2512 | 008ff9d7 | j_mayer | env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
2513 | 9c02f1a2 | j_mayer | &tlb_clk_setup, sysclk); |
2514 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
2515 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
2516 | 8ecc7913 | j_mayer | /* Internal devices init */
|
2517 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
2518 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
2519 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
2520 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
2521 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
2522 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
2523 | 802670e6 | Blue Swirl | ppc4xx_opba_init(0xef600600);
|
2524 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
2525 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2526 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
2527 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2528 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
2529 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2530 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2531 | 8ecc7913 | j_mayer | *picp = pic; |
2532 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
2533 | 923e5e33 | aurel32 | /* XXX 405EP has no ECC interrupt */
|
2534 | 80e8bd2b | aurel32 | ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
2535 | 8ecc7913 | j_mayer | /* External bus controller */
|
2536 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
2537 | 8ecc7913 | j_mayer | /* DMA controller */
|
2538 | 923e5e33 | aurel32 | dma_irqs[0] = pic[5]; |
2539 | 923e5e33 | aurel32 | dma_irqs[1] = pic[6]; |
2540 | 923e5e33 | aurel32 | dma_irqs[2] = pic[7]; |
2541 | 923e5e33 | aurel32 | dma_irqs[3] = pic[8]; |
2542 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
2543 | 8ecc7913 | j_mayer | /* IIC controller */
|
2544 | 802670e6 | Blue Swirl | ppc405_i2c_init(0xef600500, pic[2]); |
2545 | 8ecc7913 | j_mayer | /* GPIO */
|
2546 | 802670e6 | Blue Swirl | ppc405_gpio_init(0xef600700);
|
2547 | 8ecc7913 | j_mayer | /* Serial ports */
|
2548 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
2549 | 802670e6 | Blue Swirl | serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2550 | 802670e6 | Blue Swirl | serial_hds[0], 1); |
2551 | 8ecc7913 | j_mayer | } |
2552 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
2553 | 802670e6 | Blue Swirl | serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2554 | 802670e6 | Blue Swirl | serial_hds[1], 1); |
2555 | 8ecc7913 | j_mayer | } |
2556 | 8ecc7913 | j_mayer | /* OCM */
|
2557 | 5c130f65 | pbrook | ppc405_ocm_init(env); |
2558 | 9c02f1a2 | j_mayer | /* GPT */
|
2559 | 923e5e33 | aurel32 | gpt_irqs[0] = pic[19]; |
2560 | 923e5e33 | aurel32 | gpt_irqs[1] = pic[20]; |
2561 | 923e5e33 | aurel32 | gpt_irqs[2] = pic[21]; |
2562 | 923e5e33 | aurel32 | gpt_irqs[3] = pic[22]; |
2563 | 923e5e33 | aurel32 | gpt_irqs[4] = pic[23]; |
2564 | 802670e6 | Blue Swirl | ppc4xx_gpt_init(0xef600000, gpt_irqs);
|
2565 | 8ecc7913 | j_mayer | /* PCI */
|
2566 | 923e5e33 | aurel32 | /* Uses pic[3], pic[16], pic[18] */
|
2567 | 9c02f1a2 | j_mayer | /* MAL */
|
2568 | 923e5e33 | aurel32 | mal_irqs[0] = pic[11]; |
2569 | 923e5e33 | aurel32 | mal_irqs[1] = pic[12]; |
2570 | 923e5e33 | aurel32 | mal_irqs[2] = pic[13]; |
2571 | 923e5e33 | aurel32 | mal_irqs[3] = pic[14]; |
2572 | 9c02f1a2 | j_mayer | ppc405_mal_init(env, mal_irqs); |
2573 | 9c02f1a2 | j_mayer | /* Ethernet */
|
2574 | 923e5e33 | aurel32 | /* Uses pic[9], pic[15], pic[17] */
|
2575 | 8ecc7913 | j_mayer | /* CPU control */
|
2576 | 8ecc7913 | j_mayer | ppc405ep_cpc_init(env, clk_setup, sysclk); |
2577 | 8ecc7913 | j_mayer | |
2578 | 8ecc7913 | j_mayer | return env;
|
2579 | 8ecc7913 | j_mayer | } |