root / hw / slavio_timer.c @ a8a358bf
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | c70c59ee | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | c70c59ee | Blue Swirl | #include "sysbus.h" |
28 | e80cfcfc | bellard | |
29 | e80cfcfc | bellard | //#define DEBUG_TIMER
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30 | e80cfcfc | bellard | |
31 | 66321a11 | bellard | #ifdef DEBUG_TIMER
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32 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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33 | 001faf32 | Blue Swirl | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
34 | 66321a11 | bellard | #else
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35 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
36 | 66321a11 | bellard | #endif
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37 | 66321a11 | bellard | |
38 | e80cfcfc | bellard | /*
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39 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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40 | e80cfcfc | bellard | *
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41 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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42 | e80cfcfc | bellard | * produced as NCR89C105. See
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43 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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44 | 5fafdf24 | ths | *
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45 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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46 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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47 | e80cfcfc | bellard | *
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48 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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49 | ba3c64fb | bellard | * interrupt routing.
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50 | ba3c64fb | bellard | *
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51 | e80cfcfc | bellard | */
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52 | e80cfcfc | bellard | |
53 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
54 | 81732d19 | blueswir1 | |
55 | 7204ff9c | Blue Swirl | typedef struct CPUTimerState { |
56 | d7edfd27 | blueswir1 | qemu_irq irq; |
57 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
58 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
59 | 8d05ea8a | blueswir1 | uint64_t limit; |
60 | 115646b6 | blueswir1 | // processor only
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61 | 22548760 | blueswir1 | uint32_t running; |
62 | 7204ff9c | Blue Swirl | } CPUTimerState; |
63 | 7204ff9c | Blue Swirl | |
64 | 7204ff9c | Blue Swirl | typedef struct SLAVIO_TIMERState { |
65 | 7204ff9c | Blue Swirl | SysBusDevice busdev; |
66 | 7204ff9c | Blue Swirl | uint32_t num_cpus; |
67 | 7204ff9c | Blue Swirl | CPUTimerState cputimer[MAX_CPUS + 1];
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68 | 7204ff9c | Blue Swirl | uint32_t cputimer_mode; |
69 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
70 | e80cfcfc | bellard | |
71 | 7204ff9c | Blue Swirl | typedef struct TimerContext { |
72 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s; |
73 | 7204ff9c | Blue Swirl | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
74 | 7204ff9c | Blue Swirl | } TimerContext; |
75 | 7204ff9c | Blue Swirl | |
76 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
77 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
78 | e80cfcfc | bellard | |
79 | d2c38b24 | blueswir1 | #define TIMER_LIMIT 0 |
80 | d2c38b24 | blueswir1 | #define TIMER_COUNTER 1 |
81 | d2c38b24 | blueswir1 | #define TIMER_COUNTER_NORST 2 |
82 | d2c38b24 | blueswir1 | #define TIMER_STATUS 3 |
83 | d2c38b24 | blueswir1 | #define TIMER_MODE 4 |
84 | d2c38b24 | blueswir1 | |
85 | d2c38b24 | blueswir1 | #define TIMER_COUNT_MASK32 0xfffffe00 |
86 | d2c38b24 | blueswir1 | #define TIMER_LIMIT_MASK32 0x7fffffff |
87 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
88 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
89 | d2c38b24 | blueswir1 | #define TIMER_REACHED 0x80000000 |
90 | d2c38b24 | blueswir1 | #define TIMER_PERIOD 500ULL // 500ns |
91 | d2c38b24 | blueswir1 | #define LIMIT_TO_PERIODS(l) ((l) >> 9) |
92 | d2c38b24 | blueswir1 | #define PERIODS_TO_LIMIT(l) ((l) << 9) |
93 | d2c38b24 | blueswir1 | |
94 | 7204ff9c | Blue Swirl | static int slavio_timer_is_user(TimerContext *tc) |
95 | 115646b6 | blueswir1 | { |
96 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
97 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
98 | 7204ff9c | Blue Swirl | |
99 | 7204ff9c | Blue Swirl | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
100 | 115646b6 | blueswir1 | } |
101 | 115646b6 | blueswir1 | |
102 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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103 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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104 | 7204ff9c | Blue Swirl | static void slavio_timer_get_out(CPUTimerState *t) |
105 | e80cfcfc | bellard | { |
106 | bd7e2875 | blueswir1 | uint64_t count, limit; |
107 | e80cfcfc | bellard | |
108 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run system or processor counter */ |
109 | bd7e2875 | blueswir1 | limit = TIMER_MAX_COUNT32; |
110 | 7204ff9c | Blue Swirl | } else {
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111 | 7204ff9c | Blue Swirl | limit = t->limit; |
112 | 7204ff9c | Blue Swirl | } |
113 | 7204ff9c | Blue Swirl | if (t->timer) {
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114 | 7204ff9c | Blue Swirl | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
115 | 7204ff9c | Blue Swirl | } else {
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116 | 85e3023e | blueswir1 | count = 0;
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117 | 7204ff9c | Blue Swirl | } |
118 | 7204ff9c | Blue Swirl | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh, |
119 | 7204ff9c | Blue Swirl | t->count); |
120 | 7204ff9c | Blue Swirl | t->count = count & TIMER_COUNT_MASK32; |
121 | 7204ff9c | Blue Swirl | t->counthigh = count >> 32;
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122 | e80cfcfc | bellard | } |
123 | e80cfcfc | bellard | |
124 | e80cfcfc | bellard | // timer callback
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125 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
126 | e80cfcfc | bellard | { |
127 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
128 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
129 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
130 | 7204ff9c | Blue Swirl | |
131 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
132 | 7204ff9c | Blue Swirl | DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
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133 | 7204ff9c | Blue Swirl | t->reached = TIMER_REACHED; |
134 | 7204ff9c | Blue Swirl | if (!slavio_timer_is_user(tc)) {
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135 | 7204ff9c | Blue Swirl | qemu_irq_raise(t->irq); |
136 | 7204ff9c | Blue Swirl | } |
137 | e80cfcfc | bellard | } |
138 | e80cfcfc | bellard | |
139 | e80cfcfc | bellard | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
140 | e80cfcfc | bellard | { |
141 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
142 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
143 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
144 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
145 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
146 | e80cfcfc | bellard | |
147 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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148 | e80cfcfc | bellard | switch (saddr) {
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149 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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150 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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151 | f930d07e | blueswir1 | // part of counter (user mode)
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152 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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153 | 115646b6 | blueswir1 | // read user timer MSW
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154 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
155 | 7204ff9c | Blue Swirl | ret = t->counthigh | t->reached; |
156 | 115646b6 | blueswir1 | } else {
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157 | 115646b6 | blueswir1 | // read limit
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158 | f930d07e | blueswir1 | // clear irq
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159 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
160 | 7204ff9c | Blue Swirl | t->reached = 0;
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161 | 7204ff9c | Blue Swirl | ret = t->limit & TIMER_LIMIT_MASK32; |
162 | f930d07e | blueswir1 | } |
163 | 8d05ea8a | blueswir1 | break;
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164 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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165 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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166 | f930d07e | blueswir1 | // of counter (user mode)
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167 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
168 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) { // read user timer LSW |
169 | 7204ff9c | Blue Swirl | ret = t->count & TIMER_MAX_COUNT64; |
170 | 7204ff9c | Blue Swirl | } else { // read limit |
171 | 7204ff9c | Blue Swirl | ret = (t->count & TIMER_MAX_COUNT32) | |
172 | 7204ff9c | Blue Swirl | t->reached; |
173 | 7204ff9c | Blue Swirl | } |
174 | 8d05ea8a | blueswir1 | break;
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175 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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176 | 115646b6 | blueswir1 | // only available in processor counter/timer
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177 | f930d07e | blueswir1 | // read start/stop status
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178 | 7204ff9c | Blue Swirl | if (timer_index > 0) { |
179 | 7204ff9c | Blue Swirl | ret = t->running; |
180 | 7204ff9c | Blue Swirl | } else {
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181 | 7204ff9c | Blue Swirl | ret = 0;
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182 | 7204ff9c | Blue Swirl | } |
183 | 8d05ea8a | blueswir1 | break;
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184 | d2c38b24 | blueswir1 | case TIMER_MODE:
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185 | 115646b6 | blueswir1 | // only available in system counter
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186 | f930d07e | blueswir1 | // read user/system mode
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187 | 7204ff9c | Blue Swirl | ret = s->cputimer_mode; |
188 | 8d05ea8a | blueswir1 | break;
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189 | e80cfcfc | bellard | default:
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190 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
191 | 8d05ea8a | blueswir1 | ret = 0;
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192 | 8d05ea8a | blueswir1 | break;
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193 | e80cfcfc | bellard | } |
194 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
195 | 8d05ea8a | blueswir1 | |
196 | 8d05ea8a | blueswir1 | return ret;
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197 | e80cfcfc | bellard | } |
198 | e80cfcfc | bellard | |
199 | d2c38b24 | blueswir1 | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
200 | d2c38b24 | blueswir1 | uint32_t val) |
201 | e80cfcfc | bellard | { |
202 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
203 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
204 | e80cfcfc | bellard | uint32_t saddr; |
205 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
206 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
207 | e80cfcfc | bellard | |
208 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
209 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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210 | e80cfcfc | bellard | switch (saddr) {
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211 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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212 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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213 | e1cb9502 | blueswir1 | uint64_t count; |
214 | e1cb9502 | blueswir1 | |
215 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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216 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
217 | 7204ff9c | Blue Swirl | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
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218 | 7204ff9c | Blue Swirl | t->reached = 0;
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219 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh << 32) | t->count;
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220 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
221 | 7204ff9c | Blue Swirl | timer_index, count); |
222 | 7204ff9c | Blue Swirl | if (t->timer) {
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223 | 7204ff9c | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
224 | 7204ff9c | Blue Swirl | } |
225 | 115646b6 | blueswir1 | } else {
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226 | 115646b6 | blueswir1 | // set limit, reset counter
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227 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
228 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
229 | 7204ff9c | Blue Swirl | if (t->timer) {
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230 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run */ |
231 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, |
232 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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233 | 7204ff9c | Blue Swirl | } else {
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234 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
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235 | 7204ff9c | Blue Swirl | } |
236 | 85e3023e | blueswir1 | } |
237 | 81732d19 | blueswir1 | } |
238 | 115646b6 | blueswir1 | break;
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239 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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240 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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241 | e1cb9502 | blueswir1 | uint64_t count; |
242 | e1cb9502 | blueswir1 | |
243 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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244 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
245 | 7204ff9c | Blue Swirl | t->count = val & TIMER_MAX_COUNT64; |
246 | 7204ff9c | Blue Swirl | t->reached = 0;
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247 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh) << 32 | t->count;
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248 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
249 | 7204ff9c | Blue Swirl | timer_index, count); |
250 | 7204ff9c | Blue Swirl | if (t->timer) {
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251 | 7204ff9c | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
252 | 7204ff9c | Blue Swirl | } |
253 | 115646b6 | blueswir1 | } else
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254 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
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255 | 115646b6 | blueswir1 | break;
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256 | d2c38b24 | blueswir1 | case TIMER_COUNTER_NORST:
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257 | f930d07e | blueswir1 | // set limit without resetting counter
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258 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
259 | 7204ff9c | Blue Swirl | if (t->timer) {
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260 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run */ |
261 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, |
262 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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263 | 7204ff9c | Blue Swirl | } else {
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264 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
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265 | 7204ff9c | Blue Swirl | } |
266 | 85e3023e | blueswir1 | } |
267 | f930d07e | blueswir1 | break;
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268 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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269 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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270 | 115646b6 | blueswir1 | // start/stop user counter
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271 | 7204ff9c | Blue Swirl | if ((val & 1) && !t->running) { |
272 | 7204ff9c | Blue Swirl | DPRINTF("processor %d user timer started\n",
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273 | 7204ff9c | Blue Swirl | timer_index); |
274 | 7204ff9c | Blue Swirl | if (t->timer) {
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275 | 7204ff9c | Blue Swirl | ptimer_run(t->timer, 0);
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276 | 7204ff9c | Blue Swirl | } |
277 | 7204ff9c | Blue Swirl | t->running = 1;
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278 | 7204ff9c | Blue Swirl | } else if (!(val & 1) && t->running) { |
279 | 7204ff9c | Blue Swirl | DPRINTF("processor %d user timer stopped\n",
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280 | 7204ff9c | Blue Swirl | timer_index); |
281 | 7204ff9c | Blue Swirl | if (t->timer) {
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282 | 7204ff9c | Blue Swirl | ptimer_stop(t->timer); |
283 | 7204ff9c | Blue Swirl | } |
284 | 7204ff9c | Blue Swirl | t->running = 0;
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285 | f930d07e | blueswir1 | } |
286 | f930d07e | blueswir1 | } |
287 | f930d07e | blueswir1 | break;
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288 | d2c38b24 | blueswir1 | case TIMER_MODE:
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289 | 7204ff9c | Blue Swirl | if (timer_index == 0) { |
290 | 81732d19 | blueswir1 | unsigned int i; |
291 | 81732d19 | blueswir1 | |
292 | 7204ff9c | Blue Swirl | for (i = 0; i < s->num_cpus; i++) { |
293 | 67e42751 | blueswir1 | unsigned int processor = 1 << i; |
294 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer = &s->cputimer[i + 1];
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295 | 67e42751 | blueswir1 | |
296 | 67e42751 | blueswir1 | // check for a change in timer mode for this processor
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297 | 7204ff9c | Blue Swirl | if ((val & processor) != (s->cputimer_mode & processor)) {
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298 | 67e42751 | blueswir1 | if (val & processor) { // counter -> user timer |
299 | 7204ff9c | Blue Swirl | qemu_irq_lower(curr_timer->irq); |
300 | 67e42751 | blueswir1 | // counters are always running
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301 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
302 | 7204ff9c | Blue Swirl | curr_timer->running = 0;
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303 | 67e42751 | blueswir1 | // user timer limit is always the same
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304 | 7204ff9c | Blue Swirl | curr_timer->limit = TIMER_MAX_COUNT64; |
305 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
306 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(curr_timer->limit), |
307 | 77f193da | blueswir1 | 1);
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308 | 67e42751 | blueswir1 | // set this processors user timer bit in config
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309 | 67e42751 | blueswir1 | // register
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310 | 7204ff9c | Blue Swirl | s->cputimer_mode |= processor; |
311 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from counter to user "
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312 | 7204ff9c | Blue Swirl | "timer\n", timer_index);
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313 | 67e42751 | blueswir1 | } else { // user timer -> counter |
314 | 67e42751 | blueswir1 | // stop the user timer if it is running
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315 | 7204ff9c | Blue Swirl | if (curr_timer->running) {
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316 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
317 | 7204ff9c | Blue Swirl | } |
318 | 67e42751 | blueswir1 | // start the counter
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319 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
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320 | 7204ff9c | Blue Swirl | curr_timer->running = 1;
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321 | 67e42751 | blueswir1 | // clear this processors user timer bit in config
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322 | 67e42751 | blueswir1 | // register
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323 | 7204ff9c | Blue Swirl | s->cputimer_mode &= ~processor; |
324 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from user timer to "
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325 | 7204ff9c | Blue Swirl | "counter\n", timer_index);
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326 | 67e42751 | blueswir1 | } |
327 | 115646b6 | blueswir1 | } |
328 | 81732d19 | blueswir1 | } |
329 | 7204ff9c | Blue Swirl | } else {
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330 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
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331 | 7204ff9c | Blue Swirl | } |
332 | f930d07e | blueswir1 | break;
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333 | e80cfcfc | bellard | default:
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334 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
335 | f930d07e | blueswir1 | break;
|
336 | e80cfcfc | bellard | } |
337 | e80cfcfc | bellard | } |
338 | e80cfcfc | bellard | |
339 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = { |
340 | 7c560456 | blueswir1 | NULL,
|
341 | 7c560456 | blueswir1 | NULL,
|
342 | e80cfcfc | bellard | slavio_timer_mem_readl, |
343 | e80cfcfc | bellard | }; |
344 | e80cfcfc | bellard | |
345 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = { |
346 | 7c560456 | blueswir1 | NULL,
|
347 | 7c560456 | blueswir1 | NULL,
|
348 | e80cfcfc | bellard | slavio_timer_mem_writel, |
349 | e80cfcfc | bellard | }; |
350 | e80cfcfc | bellard | |
351 | e80cfcfc | bellard | static void slavio_timer_save(QEMUFile *f, void *opaque) |
352 | e80cfcfc | bellard | { |
353 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
354 | 7204ff9c | Blue Swirl | unsigned int i; |
355 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer; |
356 | 7204ff9c | Blue Swirl | |
357 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
358 | 7204ff9c | Blue Swirl | curr_timer = &s->cputimer[i]; |
359 | 7204ff9c | Blue Swirl | qemu_put_be64s(f, &curr_timer->limit); |
360 | 7204ff9c | Blue Swirl | qemu_put_be32s(f, &curr_timer->count); |
361 | 7204ff9c | Blue Swirl | qemu_put_be32s(f, &curr_timer->counthigh); |
362 | 7204ff9c | Blue Swirl | qemu_put_be32s(f, &curr_timer->reached); |
363 | 7204ff9c | Blue Swirl | qemu_put_be32s(f, &curr_timer->running); |
364 | 7204ff9c | Blue Swirl | if (curr_timer->timer) {
|
365 | 7204ff9c | Blue Swirl | qemu_put_ptimer(f, curr_timer->timer); |
366 | 7204ff9c | Blue Swirl | } |
367 | 7204ff9c | Blue Swirl | } |
368 | e80cfcfc | bellard | } |
369 | e80cfcfc | bellard | |
370 | e80cfcfc | bellard | static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id) |
371 | e80cfcfc | bellard | { |
372 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
373 | 7204ff9c | Blue Swirl | unsigned int i; |
374 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer; |
375 | 3b46e624 | ths | |
376 | 85e3023e | blueswir1 | if (version_id != 3) |
377 | e80cfcfc | bellard | return -EINVAL;
|
378 | e80cfcfc | bellard | |
379 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
380 | 7204ff9c | Blue Swirl | curr_timer = &s->cputimer[i]; |
381 | 7204ff9c | Blue Swirl | qemu_get_be64s(f, &curr_timer->limit); |
382 | 7204ff9c | Blue Swirl | qemu_get_be32s(f, &curr_timer->count); |
383 | 7204ff9c | Blue Swirl | qemu_get_be32s(f, &curr_timer->counthigh); |
384 | 7204ff9c | Blue Swirl | qemu_get_be32s(f, &curr_timer->reached); |
385 | 7204ff9c | Blue Swirl | qemu_get_be32s(f, &curr_timer->running); |
386 | 7204ff9c | Blue Swirl | if (curr_timer->timer) {
|
387 | 7204ff9c | Blue Swirl | qemu_get_ptimer(f, curr_timer->timer); |
388 | 7204ff9c | Blue Swirl | } |
389 | 7204ff9c | Blue Swirl | } |
390 | 8d05ea8a | blueswir1 | |
391 | e80cfcfc | bellard | return 0; |
392 | e80cfcfc | bellard | } |
393 | e80cfcfc | bellard | |
394 | e80cfcfc | bellard | static void slavio_timer_reset(void *opaque) |
395 | e80cfcfc | bellard | { |
396 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
397 | 7204ff9c | Blue Swirl | unsigned int i; |
398 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer; |
399 | 7204ff9c | Blue Swirl | |
400 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
401 | 7204ff9c | Blue Swirl | curr_timer = &s->cputimer[i]; |
402 | 7204ff9c | Blue Swirl | curr_timer->limit = 0;
|
403 | 7204ff9c | Blue Swirl | curr_timer->count = 0;
|
404 | 7204ff9c | Blue Swirl | curr_timer->reached = 0;
|
405 | 7204ff9c | Blue Swirl | if (i < s->num_cpus) {
|
406 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
407 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
|
408 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
|
409 | 7204ff9c | Blue Swirl | } |
410 | 7204ff9c | Blue Swirl | curr_timer->running = 1;
|
411 | 85e3023e | blueswir1 | } |
412 | 7204ff9c | Blue Swirl | s->cputimer_mode = 0;
|
413 | e80cfcfc | bellard | } |
414 | e80cfcfc | bellard | |
415 | c70c59ee | Blue Swirl | static void slavio_timer_init1(SysBusDevice *dev) |
416 | c70c59ee | Blue Swirl | { |
417 | c70c59ee | Blue Swirl | int io;
|
418 | c70c59ee | Blue Swirl | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); |
419 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
420 | 7204ff9c | Blue Swirl | unsigned int i; |
421 | 7204ff9c | Blue Swirl | TimerContext *tc; |
422 | e80cfcfc | bellard | |
423 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
424 | 7204ff9c | Blue Swirl | tc = qemu_mallocz(sizeof(TimerContext));
|
425 | 7204ff9c | Blue Swirl | tc->s = s; |
426 | 7204ff9c | Blue Swirl | tc->timer_index = i; |
427 | c70c59ee | Blue Swirl | |
428 | 7204ff9c | Blue Swirl | bh = qemu_bh_new(slavio_timer_irq, tc); |
429 | 7204ff9c | Blue Swirl | s->cputimer[i].timer = ptimer_init(bh); |
430 | 7204ff9c | Blue Swirl | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
431 | e80cfcfc | bellard | |
432 | 7204ff9c | Blue Swirl | io = cpu_register_io_memory(slavio_timer_mem_read, |
433 | 7204ff9c | Blue Swirl | slavio_timer_mem_write, tc); |
434 | 7204ff9c | Blue Swirl | if (i == 0) { |
435 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); |
436 | 7204ff9c | Blue Swirl | } else {
|
437 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); |
438 | 7204ff9c | Blue Swirl | } |
439 | 7204ff9c | Blue Swirl | |
440 | 7204ff9c | Blue Swirl | sysbus_init_irq(dev, &s->cputimer[i].irq); |
441 | c70c59ee | Blue Swirl | } |
442 | c70c59ee | Blue Swirl | |
443 | c70c59ee | Blue Swirl | register_savevm("slavio_timer", -1, 3, slavio_timer_save, |
444 | d2c38b24 | blueswir1 | slavio_timer_load, s); |
445 | a08d4367 | Jan Kiszka | qemu_register_reset(slavio_timer_reset, s); |
446 | e80cfcfc | bellard | slavio_timer_reset(s); |
447 | 81732d19 | blueswir1 | } |
448 | 81732d19 | blueswir1 | |
449 | c70c59ee | Blue Swirl | static SysBusDeviceInfo slavio_timer_info = {
|
450 | c70c59ee | Blue Swirl | .init = slavio_timer_init1, |
451 | c70c59ee | Blue Swirl | .qdev.name = "slavio_timer",
|
452 | c70c59ee | Blue Swirl | .qdev.size = sizeof(SLAVIO_TIMERState),
|
453 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
454 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
455 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
456 | c70c59ee | Blue Swirl | } |
457 | c70c59ee | Blue Swirl | }; |
458 | c70c59ee | Blue Swirl | |
459 | c70c59ee | Blue Swirl | static void slavio_timer_register_devices(void) |
460 | c70c59ee | Blue Swirl | { |
461 | c70c59ee | Blue Swirl | sysbus_register_withprop(&slavio_timer_info); |
462 | c70c59ee | Blue Swirl | } |
463 | c70c59ee | Blue Swirl | |
464 | c70c59ee | Blue Swirl | device_init(slavio_timer_register_devices) |