root / hw / sun4m.c @ a8a358bf
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 9d07d757 | Paul Brook | #include "sysbus.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 8b17de88 | blueswir1 | #include "scsi.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | 4b48bf05 | Blue Swirl | #include "qdev-addr.h" |
40 | d2c63fc1 | blueswir1 | |
41 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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42 | 420557e8 | bellard | |
43 | 36cd9210 | blueswir1 | /*
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44 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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45 | 36cd9210 | blueswir1 | *
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46 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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47 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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48 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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49 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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50 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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51 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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52 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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53 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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54 | 36cd9210 | blueswir1 | * SPARCstation 4
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55 | 36cd9210 | blueswir1 | *
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56 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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57 | 7d85892b | blueswir1 | *
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58 | 7d85892b | blueswir1 | * SPARCcenter 2000
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59 | 7d85892b | blueswir1 | * SPARCserver 1000
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60 | 7d85892b | blueswir1 | *
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61 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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62 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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63 | ee76f82e | blueswir1 | * SPARCstation SLC
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64 | ee76f82e | blueswir1 | * SPARCstation IPC
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65 | ee76f82e | blueswir1 | * SPARCstation ELC
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66 | ee76f82e | blueswir1 | * SPARCstation IPX
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67 | ee76f82e | blueswir1 | *
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68 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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69 | 36cd9210 | blueswir1 | */
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70 | 36cd9210 | blueswir1 | |
71 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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72 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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73 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
74 | b3a23197 | blueswir1 | #else
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75 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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76 | b3a23197 | blueswir1 | #endif
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77 | b3a23197 | blueswir1 | |
78 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
79 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
80 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
81 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
82 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
83 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
84 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
85 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
86 | b8174937 | bellard | |
87 | ba3c64fb | bellard | #define MAX_CPUS 16 |
88 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
89 | 420557e8 | bellard | |
90 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
91 | b4ed08e0 | blueswir1 | |
92 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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93 | 5dcb6b91 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
94 | 5dcb6b91 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
95 | 5dcb6b91 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
96 | 4c2485de | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
97 | 0019ad53 | blueswir1 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
98 | 7eb0c8e8 | blueswir1 | target_phys_addr_t ecc_base; |
99 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
100 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
101 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
102 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
103 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
104 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
105 | 36cd9210 | blueswir1 | }; |
106 | 36cd9210 | blueswir1 | |
107 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
108 | 7d85892b | blueswir1 | |
109 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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110 | 7d85892b | blueswir1 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
111 | 7d85892b | blueswir1 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
112 | 7d85892b | blueswir1 | target_phys_addr_t serial_base; |
113 | 7d85892b | blueswir1 | target_phys_addr_t espdma_base, esp_base; |
114 | 7d85892b | blueswir1 | target_phys_addr_t ledma_base, le_base; |
115 | 7d85892b | blueswir1 | target_phys_addr_t tcx_base; |
116 | 7d85892b | blueswir1 | target_phys_addr_t sbi_base; |
117 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
118 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
119 | 7d85892b | blueswir1 | uint32_t iounit_version; |
120 | 7d85892b | blueswir1 | uint64_t max_mem; |
121 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
122 | 7d85892b | blueswir1 | }; |
123 | 7d85892b | blueswir1 | |
124 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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125 | 8137cde8 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
126 | 8137cde8 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
127 | 8137cde8 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
128 | 8137cde8 | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
129 | 1572a18c | blueswir1 | target_phys_addr_t tcx_base, aux1_base; |
130 | 8137cde8 | blueswir1 | uint8_t nvram_machine_id; |
131 | 8137cde8 | blueswir1 | uint16_t machine_id; |
132 | 8137cde8 | blueswir1 | uint32_t iommu_version; |
133 | 8137cde8 | blueswir1 | uint64_t max_mem; |
134 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
135 | 8137cde8 | blueswir1 | }; |
136 | 8137cde8 | blueswir1 | |
137 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
138 | 6f7e9aec | bellard | { |
139 | 6f7e9aec | bellard | return 0; |
140 | 6f7e9aec | bellard | } |
141 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
142 | 6f7e9aec | bellard | { |
143 | 6f7e9aec | bellard | return 0; |
144 | 6f7e9aec | bellard | } |
145 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
146 | 6f7e9aec | bellard | { |
147 | 6f7e9aec | bellard | return 0; |
148 | 6f7e9aec | bellard | } |
149 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
150 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
151 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
152 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
153 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
154 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
155 | 6f7e9aec | bellard | void *opaque)
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156 | 6f7e9aec | bellard | { |
157 | 6f7e9aec | bellard | } |
158 | 6f7e9aec | bellard | |
159 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
160 | 81864572 | blueswir1 | { |
161 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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162 | 81864572 | blueswir1 | return 0; |
163 | 81864572 | blueswir1 | } |
164 | 81864572 | blueswir1 | |
165 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
166 | 6ef05b95 | blueswir1 | const char *boot_devices, ram_addr_t RAM_size, |
167 | f930d07e | blueswir1 | uint32_t kernel_size, |
168 | f930d07e | blueswir1 | int width, int height, int depth, |
169 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
170 | e80cfcfc | bellard | { |
171 | d2c63fc1 | blueswir1 | unsigned int i; |
172 | 66508601 | blueswir1 | uint32_t start, end; |
173 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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174 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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175 | d2c63fc1 | blueswir1 | |
176 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
177 | e80cfcfc | bellard | |
178 | 513f789f | blueswir1 | start = 0;
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179 | b6f479d3 | bellard | |
180 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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181 | 66508601 | blueswir1 | // Variable partition
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182 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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183 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
184 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
185 | 66508601 | blueswir1 | |
186 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
187 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
188 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
189 | d2c63fc1 | blueswir1 | |
190 | d2c63fc1 | blueswir1 | // End marker
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191 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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192 | 66508601 | blueswir1 | |
193 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
194 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
195 | 66508601 | blueswir1 | |
196 | 66508601 | blueswir1 | // free partition
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197 | 66508601 | blueswir1 | start = end; |
198 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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199 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
200 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
201 | 66508601 | blueswir1 | |
202 | 66508601 | blueswir1 | end = 0x1fd0;
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203 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
204 | d2c63fc1 | blueswir1 | |
205 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
206 | 905fdcb5 | blueswir1 | nvram_machine_id); |
207 | d2c63fc1 | blueswir1 | |
208 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
209 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
210 | e80cfcfc | bellard | } |
211 | e80cfcfc | bellard | |
212 | d453c2c3 | Blue Swirl | static DeviceState *slavio_intctl;
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213 | e80cfcfc | bellard | |
214 | 376253ec | aliguori | void pic_info(Monitor *mon)
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215 | e80cfcfc | bellard | { |
216 | 7d85892b | blueswir1 | if (slavio_intctl)
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217 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
218 | e80cfcfc | bellard | } |
219 | e80cfcfc | bellard | |
220 | 376253ec | aliguori | void irq_info(Monitor *mon)
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221 | e80cfcfc | bellard | { |
222 | 7d85892b | blueswir1 | if (slavio_intctl)
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223 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
224 | e80cfcfc | bellard | } |
225 | e80cfcfc | bellard | |
226 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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227 | 327ac2e7 | blueswir1 | { |
228 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
229 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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230 | 327ac2e7 | blueswir1 | unsigned int i; |
231 | 327ac2e7 | blueswir1 | |
232 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
233 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
234 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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235 | 327ac2e7 | blueswir1 | |
236 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
237 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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238 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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239 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
240 | f32d7ec5 | blueswir1 | } |
241 | 327ac2e7 | blueswir1 | break;
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242 | 327ac2e7 | blueswir1 | } |
243 | 327ac2e7 | blueswir1 | } |
244 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
245 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
246 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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247 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
248 | 327ac2e7 | blueswir1 | } |
249 | 327ac2e7 | blueswir1 | } |
250 | 327ac2e7 | blueswir1 | |
251 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
252 | b3a23197 | blueswir1 | { |
253 | b3a23197 | blueswir1 | CPUState *env = opaque; |
254 | b3a23197 | blueswir1 | |
255 | b3a23197 | blueswir1 | if (level) {
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256 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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257 | b3a23197 | blueswir1 | env->halted = 0;
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258 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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259 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
260 | b3a23197 | blueswir1 | } else {
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261 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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262 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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263 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
264 | b3a23197 | blueswir1 | } |
265 | b3a23197 | blueswir1 | } |
266 | b3a23197 | blueswir1 | |
267 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
268 | b3a23197 | blueswir1 | { |
269 | b3a23197 | blueswir1 | } |
270 | b3a23197 | blueswir1 | |
271 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
272 | c68ea704 | bellard | { |
273 | c68ea704 | bellard | CPUState *env = opaque; |
274 | 3d29fbef | blueswir1 | |
275 | 3d29fbef | blueswir1 | cpu_reset(env); |
276 | 3d29fbef | blueswir1 | env->halted = 0;
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277 | 3d29fbef | blueswir1 | } |
278 | 3d29fbef | blueswir1 | |
279 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
280 | 3d29fbef | blueswir1 | { |
281 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
282 | 3d29fbef | blueswir1 | |
283 | c68ea704 | bellard | cpu_reset(env); |
284 | 3d29fbef | blueswir1 | env->halted = 1;
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285 | c68ea704 | bellard | } |
286 | c68ea704 | bellard | |
287 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
288 | 6d0c293d | blueswir1 | { |
289 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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290 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
291 | 6d0c293d | blueswir1 | } |
292 | 6d0c293d | blueswir1 | |
293 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
294 | 293f78bc | blueswir1 | const char *initrd_filename, |
295 | 293f78bc | blueswir1 | ram_addr_t RAM_size) |
296 | 3ebf5aaf | blueswir1 | { |
297 | 3ebf5aaf | blueswir1 | int linux_boot;
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298 | 3ebf5aaf | blueswir1 | unsigned int i; |
299 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
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300 | 3ebf5aaf | blueswir1 | |
301 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
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302 | 3ebf5aaf | blueswir1 | |
303 | 3ebf5aaf | blueswir1 | kernel_size = 0;
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304 | 3ebf5aaf | blueswir1 | if (linux_boot) {
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305 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
306 | 3ebf5aaf | blueswir1 | NULL);
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307 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
308 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
309 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
310 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
311 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
312 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
313 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
314 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
315 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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316 | 3ebf5aaf | blueswir1 | kernel_filename); |
317 | 3ebf5aaf | blueswir1 | exit(1);
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318 | 3ebf5aaf | blueswir1 | } |
319 | 3ebf5aaf | blueswir1 | |
320 | 3ebf5aaf | blueswir1 | /* load initrd */
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321 | 3ebf5aaf | blueswir1 | initrd_size = 0;
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322 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
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323 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
324 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
325 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
326 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
327 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
328 | 3ebf5aaf | blueswir1 | initrd_filename); |
329 | 3ebf5aaf | blueswir1 | exit(1);
|
330 | 3ebf5aaf | blueswir1 | } |
331 | 3ebf5aaf | blueswir1 | } |
332 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
333 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
334 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
335 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
336 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
337 | 3ebf5aaf | blueswir1 | break;
|
338 | 3ebf5aaf | blueswir1 | } |
339 | 3ebf5aaf | blueswir1 | } |
340 | 3ebf5aaf | blueswir1 | } |
341 | 3ebf5aaf | blueswir1 | } |
342 | 3ebf5aaf | blueswir1 | return kernel_size;
|
343 | 3ebf5aaf | blueswir1 | } |
344 | 3ebf5aaf | blueswir1 | |
345 | 4b48bf05 | Blue Swirl | static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
346 | 4b48bf05 | Blue Swirl | { |
347 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
348 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
349 | 4b48bf05 | Blue Swirl | |
350 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "iommu"); |
351 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
352 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
353 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
354 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
355 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
356 | 4b48bf05 | Blue Swirl | |
357 | 4b48bf05 | Blue Swirl | return s;
|
358 | 4b48bf05 | Blue Swirl | } |
359 | 4b48bf05 | Blue Swirl | |
360 | 74ff8d90 | Blue Swirl | static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
361 | 74ff8d90 | Blue Swirl | void *iommu, qemu_irq *dev_irq)
|
362 | 74ff8d90 | Blue Swirl | { |
363 | 74ff8d90 | Blue Swirl | DeviceState *dev; |
364 | 74ff8d90 | Blue Swirl | SysBusDevice *s; |
365 | 74ff8d90 | Blue Swirl | |
366 | 74ff8d90 | Blue Swirl | dev = qdev_create(NULL, "sparc32_dma"); |
367 | 74ff8d90 | Blue Swirl | qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
368 | 74ff8d90 | Blue Swirl | qdev_init(dev); |
369 | 74ff8d90 | Blue Swirl | s = sysbus_from_qdev(dev); |
370 | 74ff8d90 | Blue Swirl | sysbus_connect_irq(s, 0, parent_irq);
|
371 | 74ff8d90 | Blue Swirl | *dev_irq = qdev_get_gpio_in(dev, 0);
|
372 | 74ff8d90 | Blue Swirl | sysbus_mmio_map(s, 0, daddr);
|
373 | 74ff8d90 | Blue Swirl | |
374 | 74ff8d90 | Blue Swirl | return s;
|
375 | 74ff8d90 | Blue Swirl | } |
376 | 74ff8d90 | Blue Swirl | |
377 | 9d07d757 | Paul Brook | static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
378 | 74ff8d90 | Blue Swirl | void *dma_opaque, qemu_irq irq)
|
379 | 9d07d757 | Paul Brook | { |
380 | 9d07d757 | Paul Brook | DeviceState *dev; |
381 | 9d07d757 | Paul Brook | SysBusDevice *s; |
382 | 74ff8d90 | Blue Swirl | qemu_irq reset; |
383 | 9d07d757 | Paul Brook | |
384 | 9d07d757 | Paul Brook | qemu_check_nic_model(&nd_table[0], "lance"); |
385 | 9d07d757 | Paul Brook | |
386 | 9d07d757 | Paul Brook | dev = qdev_create(NULL, "lance"); |
387 | ee6847d1 | Gerd Hoffmann | dev->nd = nd; |
388 | daa65491 | Blue Swirl | qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
389 | 9d07d757 | Paul Brook | qdev_init(dev); |
390 | 9d07d757 | Paul Brook | s = sysbus_from_qdev(dev); |
391 | 9d07d757 | Paul Brook | sysbus_mmio_map(s, 0, leaddr);
|
392 | 9d07d757 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
393 | 74ff8d90 | Blue Swirl | reset = qdev_get_gpio_in(dev, 0);
|
394 | 74ff8d90 | Blue Swirl | qdev_connect_gpio_out(dma_opaque, 0, reset);
|
395 | 9d07d757 | Paul Brook | } |
396 | 9d07d757 | Paul Brook | |
397 | 4b48bf05 | Blue Swirl | static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
|
398 | 4b48bf05 | Blue Swirl | target_phys_addr_t addrg, |
399 | 462eda24 | Blue Swirl | qemu_irq **parent_irq) |
400 | 4b48bf05 | Blue Swirl | { |
401 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
402 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
403 | 4b48bf05 | Blue Swirl | unsigned int i, j; |
404 | 4b48bf05 | Blue Swirl | |
405 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_intctl"); |
406 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
407 | 4b48bf05 | Blue Swirl | |
408 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
409 | 4b48bf05 | Blue Swirl | |
410 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
411 | 4b48bf05 | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
412 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
413 | 4b48bf05 | Blue Swirl | } |
414 | 4b48bf05 | Blue Swirl | } |
415 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addrg);
|
416 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
417 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
418 | 4b48bf05 | Blue Swirl | } |
419 | 4b48bf05 | Blue Swirl | |
420 | 4b48bf05 | Blue Swirl | return dev;
|
421 | 4b48bf05 | Blue Swirl | } |
422 | 4b48bf05 | Blue Swirl | |
423 | 4b48bf05 | Blue Swirl | #define SYS_TIMER_OFFSET 0x10000ULL |
424 | 4b48bf05 | Blue Swirl | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
425 | 4b48bf05 | Blue Swirl | |
426 | 4b48bf05 | Blue Swirl | static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
427 | 4b48bf05 | Blue Swirl | qemu_irq *cpu_irqs, unsigned int num_cpus) |
428 | 4b48bf05 | Blue Swirl | { |
429 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
430 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
431 | 4b48bf05 | Blue Swirl | unsigned int i; |
432 | 4b48bf05 | Blue Swirl | |
433 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
434 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
435 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
436 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
437 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, master_irq);
|
438 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
439 | 4b48bf05 | Blue Swirl | |
440 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
441 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
|
442 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
443 | 4b48bf05 | Blue Swirl | } |
444 | 4b48bf05 | Blue Swirl | } |
445 | 4b48bf05 | Blue Swirl | |
446 | 4b48bf05 | Blue Swirl | #define MISC_LEDS 0x01600000 |
447 | 4b48bf05 | Blue Swirl | #define MISC_CFG 0x01800000 |
448 | 4b48bf05 | Blue Swirl | #define MISC_DIAG 0x01a00000 |
449 | 4b48bf05 | Blue Swirl | #define MISC_MDM 0x01b00000 |
450 | 4b48bf05 | Blue Swirl | #define MISC_SYS 0x01f00000 |
451 | 4b48bf05 | Blue Swirl | |
452 | b2b6f6ec | Blue Swirl | static void slavio_misc_init(target_phys_addr_t base, |
453 | b2b6f6ec | Blue Swirl | target_phys_addr_t aux1_base, |
454 | b2b6f6ec | Blue Swirl | target_phys_addr_t aux2_base, qemu_irq irq, |
455 | b2b6f6ec | Blue Swirl | qemu_irq fdc_tc) |
456 | 4b48bf05 | Blue Swirl | { |
457 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
458 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
459 | 4b48bf05 | Blue Swirl | |
460 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
461 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
462 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
463 | 4b48bf05 | Blue Swirl | if (base) {
|
464 | 4b48bf05 | Blue Swirl | /* 8 bit registers */
|
465 | 4b48bf05 | Blue Swirl | /* Slavio control */
|
466 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
467 | 4b48bf05 | Blue Swirl | /* Diagnostics */
|
468 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
469 | 4b48bf05 | Blue Swirl | /* Modem control */
|
470 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
471 | 4b48bf05 | Blue Swirl | /* 16 bit registers */
|
472 | 4b48bf05 | Blue Swirl | /* ss600mp diag LEDs */
|
473 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
474 | 4b48bf05 | Blue Swirl | /* 32 bit registers */
|
475 | 4b48bf05 | Blue Swirl | /* System control */
|
476 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
477 | 4b48bf05 | Blue Swirl | } |
478 | 4b48bf05 | Blue Swirl | if (aux1_base) {
|
479 | 4b48bf05 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
480 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
481 | 4b48bf05 | Blue Swirl | } |
482 | 4b48bf05 | Blue Swirl | if (aux2_base) {
|
483 | 4b48bf05 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
484 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
485 | 4b48bf05 | Blue Swirl | } |
486 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
487 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
488 | d9c32310 | Blue Swirl | qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
489 | 4b48bf05 | Blue Swirl | } |
490 | 4b48bf05 | Blue Swirl | |
491 | 4b48bf05 | Blue Swirl | static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
492 | 4b48bf05 | Blue Swirl | { |
493 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
494 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
495 | 4b48bf05 | Blue Swirl | |
496 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "eccmemctl"); |
497 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
498 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
499 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
500 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
501 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base);
|
502 | 4b48bf05 | Blue Swirl | if (version == 0) { // SS-600MP only |
503 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x1000); |
504 | 4b48bf05 | Blue Swirl | } |
505 | 4b48bf05 | Blue Swirl | } |
506 | 4b48bf05 | Blue Swirl | |
507 | 4b48bf05 | Blue Swirl | static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
508 | 4b48bf05 | Blue Swirl | { |
509 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
510 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
511 | 4b48bf05 | Blue Swirl | |
512 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
513 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
514 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
515 | 4b48bf05 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
516 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
517 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
518 | 4b48bf05 | Blue Swirl | } |
519 | 4b48bf05 | Blue Swirl | |
520 | 4b48bf05 | Blue Swirl | static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
521 | 4b48bf05 | Blue Swirl | int height, int depth) |
522 | 4b48bf05 | Blue Swirl | { |
523 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
524 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
525 | 4b48bf05 | Blue Swirl | |
526 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "SUNW,tcx"); |
527 | 4b48bf05 | Blue Swirl | qdev_prop_set_taddr(dev, "addr", addr);
|
528 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
529 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "width", width);
|
530 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "height", height);
|
531 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "depth", depth);
|
532 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
533 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
534 | 4b48bf05 | Blue Swirl | /* 8-bit plane */
|
535 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
536 | 4b48bf05 | Blue Swirl | /* DAC */
|
537 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
538 | 4b48bf05 | Blue Swirl | /* TEC (dummy) */
|
539 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
540 | 4b48bf05 | Blue Swirl | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
541 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
542 | 4b48bf05 | Blue Swirl | if (depth == 24) { |
543 | 4b48bf05 | Blue Swirl | /* 24-bit plane */
|
544 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
545 | 4b48bf05 | Blue Swirl | /* Control plane */
|
546 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
547 | 4b48bf05 | Blue Swirl | } else {
|
548 | 4b48bf05 | Blue Swirl | /* THC 8 bit (dummy) */
|
549 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
550 | 4b48bf05 | Blue Swirl | } |
551 | 4b48bf05 | Blue Swirl | } |
552 | 4b48bf05 | Blue Swirl | |
553 | 325f2747 | Blue Swirl | /* NCR89C100/MACIO Internal ID register */
|
554 | 325f2747 | Blue Swirl | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
555 | 325f2747 | Blue Swirl | |
556 | 325f2747 | Blue Swirl | static void idreg_init(target_phys_addr_t addr) |
557 | 325f2747 | Blue Swirl | { |
558 | 325f2747 | Blue Swirl | DeviceState *dev; |
559 | 325f2747 | Blue Swirl | SysBusDevice *s; |
560 | 325f2747 | Blue Swirl | |
561 | 325f2747 | Blue Swirl | dev = qdev_create(NULL, "macio_idreg"); |
562 | 325f2747 | Blue Swirl | qdev_init(dev); |
563 | 325f2747 | Blue Swirl | s = sysbus_from_qdev(dev); |
564 | 325f2747 | Blue Swirl | |
565 | 325f2747 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
566 | 325f2747 | Blue Swirl | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
567 | 325f2747 | Blue Swirl | } |
568 | 325f2747 | Blue Swirl | |
569 | 325f2747 | Blue Swirl | static void idreg_init1(SysBusDevice *dev) |
570 | 325f2747 | Blue Swirl | { |
571 | 325f2747 | Blue Swirl | ram_addr_t idreg_offset; |
572 | 325f2747 | Blue Swirl | |
573 | 325f2747 | Blue Swirl | idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
|
574 | 325f2747 | Blue Swirl | sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
575 | 325f2747 | Blue Swirl | } |
576 | 325f2747 | Blue Swirl | |
577 | 325f2747 | Blue Swirl | static SysBusDeviceInfo idreg_info = {
|
578 | 325f2747 | Blue Swirl | .init = idreg_init1, |
579 | 325f2747 | Blue Swirl | .qdev.name = "macio_idreg",
|
580 | 325f2747 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
581 | 325f2747 | Blue Swirl | }; |
582 | 325f2747 | Blue Swirl | |
583 | 325f2747 | Blue Swirl | static void idreg_register_devices(void) |
584 | 325f2747 | Blue Swirl | { |
585 | 325f2747 | Blue Swirl | sysbus_register_withprop(&idreg_info); |
586 | 325f2747 | Blue Swirl | } |
587 | 325f2747 | Blue Swirl | |
588 | 325f2747 | Blue Swirl | device_init(idreg_register_devices); |
589 | 325f2747 | Blue Swirl | |
590 | f48f6569 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
591 | f48f6569 | Blue Swirl | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
592 | f48f6569 | Blue Swirl | { |
593 | f48f6569 | Blue Swirl | DeviceState *dev; |
594 | f48f6569 | Blue Swirl | SysBusDevice *s; |
595 | f48f6569 | Blue Swirl | char *filename;
|
596 | f48f6569 | Blue Swirl | int ret;
|
597 | f48f6569 | Blue Swirl | |
598 | f48f6569 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
599 | f48f6569 | Blue Swirl | qdev_init(dev); |
600 | f48f6569 | Blue Swirl | s = sysbus_from_qdev(dev); |
601 | f48f6569 | Blue Swirl | |
602 | f48f6569 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
603 | f48f6569 | Blue Swirl | |
604 | f48f6569 | Blue Swirl | /* load boot prom */
|
605 | f48f6569 | Blue Swirl | if (bios_name == NULL) { |
606 | f48f6569 | Blue Swirl | bios_name = PROM_FILENAME; |
607 | f48f6569 | Blue Swirl | } |
608 | f48f6569 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
609 | f48f6569 | Blue Swirl | if (filename) {
|
610 | f48f6569 | Blue Swirl | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); |
611 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
612 | f48f6569 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
613 | f48f6569 | Blue Swirl | } |
614 | f48f6569 | Blue Swirl | qemu_free(filename); |
615 | f48f6569 | Blue Swirl | } else {
|
616 | f48f6569 | Blue Swirl | ret = -1;
|
617 | f48f6569 | Blue Swirl | } |
618 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
619 | f48f6569 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
620 | f48f6569 | Blue Swirl | exit(1);
|
621 | f48f6569 | Blue Swirl | } |
622 | f48f6569 | Blue Swirl | } |
623 | f48f6569 | Blue Swirl | |
624 | f48f6569 | Blue Swirl | static void prom_init1(SysBusDevice *dev) |
625 | f48f6569 | Blue Swirl | { |
626 | f48f6569 | Blue Swirl | ram_addr_t prom_offset; |
627 | f48f6569 | Blue Swirl | |
628 | f48f6569 | Blue Swirl | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
629 | f48f6569 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
630 | f48f6569 | Blue Swirl | } |
631 | f48f6569 | Blue Swirl | |
632 | f48f6569 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
633 | f48f6569 | Blue Swirl | .init = prom_init1, |
634 | f48f6569 | Blue Swirl | .qdev.name = "openprom",
|
635 | f48f6569 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
636 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
637 | ee6847d1 | Gerd Hoffmann | {/* end of property list */}
|
638 | f48f6569 | Blue Swirl | } |
639 | f48f6569 | Blue Swirl | }; |
640 | f48f6569 | Blue Swirl | |
641 | f48f6569 | Blue Swirl | static void prom_register_devices(void) |
642 | f48f6569 | Blue Swirl | { |
643 | f48f6569 | Blue Swirl | sysbus_register_withprop(&prom_info); |
644 | f48f6569 | Blue Swirl | } |
645 | f48f6569 | Blue Swirl | |
646 | f48f6569 | Blue Swirl | device_init(prom_register_devices); |
647 | f48f6569 | Blue Swirl | |
648 | ee6847d1 | Gerd Hoffmann | typedef struct RamDevice |
649 | ee6847d1 | Gerd Hoffmann | { |
650 | ee6847d1 | Gerd Hoffmann | SysBusDevice busdev; |
651 | 04843626 | Blue Swirl | uint64_t size; |
652 | ee6847d1 | Gerd Hoffmann | } RamDevice; |
653 | ee6847d1 | Gerd Hoffmann | |
654 | a350db85 | Blue Swirl | /* System RAM */
|
655 | a350db85 | Blue Swirl | static void ram_init1(SysBusDevice *dev) |
656 | a350db85 | Blue Swirl | { |
657 | a350db85 | Blue Swirl | ram_addr_t RAM_size, ram_offset; |
658 | ee6847d1 | Gerd Hoffmann | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
659 | a350db85 | Blue Swirl | |
660 | ee6847d1 | Gerd Hoffmann | RAM_size = d->size; |
661 | a350db85 | Blue Swirl | |
662 | a350db85 | Blue Swirl | ram_offset = qemu_ram_alloc(RAM_size); |
663 | a350db85 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
664 | a350db85 | Blue Swirl | } |
665 | a350db85 | Blue Swirl | |
666 | a350db85 | Blue Swirl | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
667 | a350db85 | Blue Swirl | uint64_t max_mem) |
668 | a350db85 | Blue Swirl | { |
669 | a350db85 | Blue Swirl | DeviceState *dev; |
670 | a350db85 | Blue Swirl | SysBusDevice *s; |
671 | ee6847d1 | Gerd Hoffmann | RamDevice *d; |
672 | a350db85 | Blue Swirl | |
673 | a350db85 | Blue Swirl | /* allocate RAM */
|
674 | a350db85 | Blue Swirl | if ((uint64_t)RAM_size > max_mem) {
|
675 | a350db85 | Blue Swirl | fprintf(stderr, |
676 | a350db85 | Blue Swirl | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
677 | a350db85 | Blue Swirl | (unsigned int)(RAM_size / (1024 * 1024)), |
678 | a350db85 | Blue Swirl | (unsigned int)(max_mem / (1024 * 1024))); |
679 | a350db85 | Blue Swirl | exit(1);
|
680 | a350db85 | Blue Swirl | } |
681 | a350db85 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
682 | a350db85 | Blue Swirl | s = sysbus_from_qdev(dev); |
683 | a350db85 | Blue Swirl | |
684 | ee6847d1 | Gerd Hoffmann | d = FROM_SYSBUS(RamDevice, s); |
685 | ee6847d1 | Gerd Hoffmann | d->size = RAM_size; |
686 | f6e097e7 | Blue Swirl | qdev_init(dev); |
687 | ee6847d1 | Gerd Hoffmann | |
688 | a350db85 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
689 | a350db85 | Blue Swirl | } |
690 | a350db85 | Blue Swirl | |
691 | a350db85 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
692 | a350db85 | Blue Swirl | .init = ram_init1, |
693 | a350db85 | Blue Swirl | .qdev.name = "memory",
|
694 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(RamDevice),
|
695 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
696 | c885159a | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
697 | c885159a | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
698 | a350db85 | Blue Swirl | } |
699 | a350db85 | Blue Swirl | }; |
700 | a350db85 | Blue Swirl | |
701 | a350db85 | Blue Swirl | static void ram_register_devices(void) |
702 | a350db85 | Blue Swirl | { |
703 | a350db85 | Blue Swirl | sysbus_register_withprop(&ram_info); |
704 | a350db85 | Blue Swirl | } |
705 | a350db85 | Blue Swirl | |
706 | a350db85 | Blue Swirl | device_init(ram_register_devices); |
707 | a350db85 | Blue Swirl | |
708 | 666713c0 | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, |
709 | 666713c0 | Blue Swirl | uint64_t prom_addr, qemu_irq **cpu_irqs) |
710 | 666713c0 | Blue Swirl | { |
711 | 666713c0 | Blue Swirl | CPUState *env; |
712 | 666713c0 | Blue Swirl | |
713 | 666713c0 | Blue Swirl | env = cpu_init(cpu_model); |
714 | 666713c0 | Blue Swirl | if (!env) {
|
715 | 666713c0 | Blue Swirl | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
716 | 666713c0 | Blue Swirl | exit(1);
|
717 | 666713c0 | Blue Swirl | } |
718 | 666713c0 | Blue Swirl | |
719 | 666713c0 | Blue Swirl | cpu_sparc_set_id(env, id); |
720 | 666713c0 | Blue Swirl | if (id == 0) { |
721 | 666713c0 | Blue Swirl | qemu_register_reset(main_cpu_reset, env); |
722 | 666713c0 | Blue Swirl | } else {
|
723 | 666713c0 | Blue Swirl | qemu_register_reset(secondary_cpu_reset, env); |
724 | 666713c0 | Blue Swirl | env->halted = 1;
|
725 | 666713c0 | Blue Swirl | } |
726 | 666713c0 | Blue Swirl | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
727 | 666713c0 | Blue Swirl | env->prom_addr = prom_addr; |
728 | 666713c0 | Blue Swirl | |
729 | 666713c0 | Blue Swirl | return env;
|
730 | 666713c0 | Blue Swirl | } |
731 | 666713c0 | Blue Swirl | |
732 | 8137cde8 | blueswir1 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
733 | 3ebf5aaf | blueswir1 | const char *boot_device, |
734 | 3023f332 | aliguori | const char *kernel_filename, |
735 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
736 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
737 | 420557e8 | bellard | { |
738 | 666713c0 | Blue Swirl | CPUState *envs[MAX_CPUS]; |
739 | 713c45fa | bellard | unsigned int i; |
740 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
741 | a1961a4b | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
742 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
743 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
744 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
745 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
746 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
747 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
748 | 3cce6243 | blueswir1 | void *fw_cfg;
|
749 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
750 | 420557e8 | bellard | |
751 | ba3c64fb | bellard | /* init CPUs */
|
752 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
753 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
754 | b3a23197 | blueswir1 | |
755 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
756 | 666713c0 | Blue Swirl | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
757 | ba3c64fb | bellard | } |
758 | b3a23197 | blueswir1 | |
759 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
760 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
761 | b3a23197 | blueswir1 | |
762 | 3ebf5aaf | blueswir1 | |
763 | 3ebf5aaf | blueswir1 | /* set up devices */
|
764 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
765 | a350db85 | Blue Swirl | |
766 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
767 | f48f6569 | Blue Swirl | |
768 | d453c2c3 | Blue Swirl | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
769 | d453c2c3 | Blue Swirl | hwdef->intctl_base + 0x10000ULL,
|
770 | 462eda24 | Blue Swirl | cpu_irqs); |
771 | a1961a4b | Blue Swirl | |
772 | a1961a4b | Blue Swirl | for (i = 0; i < 32; i++) { |
773 | d453c2c3 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
774 | a1961a4b | Blue Swirl | } |
775 | a1961a4b | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
776 | d453c2c3 | Blue Swirl | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
777 | a1961a4b | Blue Swirl | } |
778 | b3a23197 | blueswir1 | |
779 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
780 | 325f2747 | Blue Swirl | idreg_init(hwdef->idreg_base); |
781 | 4c2485de | blueswir1 | } |
782 | 4c2485de | blueswir1 | |
783 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
784 | c533e0b3 | Blue Swirl | slavio_irq[30]);
|
785 | ff403da6 | blueswir1 | |
786 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
787 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
788 | 2d069bab | blueswir1 | |
789 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
790 | 74ff8d90 | Blue Swirl | slavio_irq[16], iommu, &ledma_irq);
|
791 | ba3c64fb | bellard | |
792 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
793 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
794 | eee0b836 | blueswir1 | exit (1);
|
795 | eee0b836 | blueswir1 | } |
796 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
797 | dc828ca1 | pbrook | graphic_depth); |
798 | dbe06e18 | blueswir1 | |
799 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
800 | dbe06e18 | blueswir1 | |
801 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
802 | 81732d19 | blueswir1 | |
803 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
804 | 81732d19 | blueswir1 | |
805 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
806 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
807 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
808 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
809 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
810 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
811 | 741402f9 | blueswir1 | |
812 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
813 | b2b6f6ec | Blue Swirl | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
814 | b2b6f6ec | Blue Swirl | slavio_irq[30], fdc_tc);
|
815 | b2b6f6ec | Blue Swirl | |
816 | 2582cfa0 | Blue Swirl | if (hwdef->apc_base) {
|
817 | 2582cfa0 | Blue Swirl | apc_init(hwdef->apc_base, cpu_halt[0]);
|
818 | 2582cfa0 | Blue Swirl | } |
819 | 2be17ebd | blueswir1 | |
820 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
821 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
822 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
823 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_FLOPPY, 0, 0); |
824 | 751c6a17 | Gerd Hoffmann | if (dinfo)
|
825 | 751c6a17 | Gerd Hoffmann | fd[0] = dinfo->bdrv;
|
826 | 2d069bab | blueswir1 | |
827 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
828 | 2582cfa0 | Blue Swirl | &fdc_tc); |
829 | e4bcb14c | ths | } |
830 | e4bcb14c | ths | |
831 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
832 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
833 | e4bcb14c | ths | exit(1);
|
834 | e4bcb14c | ths | } |
835 | e4bcb14c | ths | |
836 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
837 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
838 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
839 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
840 | 74ff8d90 | Blue Swirl | |
841 | f1587550 | ths | |
842 | fa28ec52 | Blue Swirl | if (hwdef->cs_base) {
|
843 | fa28ec52 | Blue Swirl | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
844 | c533e0b3 | Blue Swirl | slavio_irq[5]);
|
845 | fa28ec52 | Blue Swirl | } |
846 | b3ceef24 | blueswir1 | |
847 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
848 | 293f78bc | blueswir1 | RAM_size); |
849 | 36cd9210 | blueswir1 | |
850 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
851 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
852 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
853 | 905fdcb5 | blueswir1 | "Sun4m");
|
854 | 7eb0c8e8 | blueswir1 | |
855 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
856 | c533e0b3 | Blue Swirl | ecc_init(hwdef->ecc_base, slavio_irq[28],
|
857 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
858 | 3cce6243 | blueswir1 | |
859 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
860 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
861 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
862 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
863 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
864 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
865 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
866 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
867 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
868 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
869 | 513f789f | blueswir1 | } else {
|
870 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
871 | 513f789f | blueswir1 | } |
872 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
873 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
874 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
875 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
876 | 36cd9210 | blueswir1 | } |
877 | 36cd9210 | blueswir1 | |
878 | 905fdcb5 | blueswir1 | enum {
|
879 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
880 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
881 | 905fdcb5 | blueswir1 | vger_id, |
882 | 905fdcb5 | blueswir1 | lx_id, |
883 | 905fdcb5 | blueswir1 | ss4_id, |
884 | 905fdcb5 | blueswir1 | scls_id, |
885 | 905fdcb5 | blueswir1 | sbook_id, |
886 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
887 | 905fdcb5 | blueswir1 | ss20_id, |
888 | 905fdcb5 | blueswir1 | ss600mp_id, |
889 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
890 | 905fdcb5 | blueswir1 | ss2000_id, |
891 | 905fdcb5 | blueswir1 | }; |
892 | 905fdcb5 | blueswir1 | |
893 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
894 | 36cd9210 | blueswir1 | /* SS-5 */
|
895 | 36cd9210 | blueswir1 | { |
896 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
897 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
898 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
899 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
900 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
901 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
902 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
903 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
904 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
905 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
906 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
907 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
908 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
909 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
910 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
911 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
912 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
913 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
914 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
915 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
916 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
917 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
918 | e0353fe2 | blueswir1 | }, |
919 | e0353fe2 | blueswir1 | /* SS-10 */
|
920 | e0353fe2 | blueswir1 | { |
921 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
922 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
923 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
924 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
925 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
926 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
927 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
928 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
929 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
930 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
931 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
932 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
933 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
934 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
935 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
936 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
937 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
938 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
939 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
940 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
941 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
942 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
943 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
944 | 36cd9210 | blueswir1 | }, |
945 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
946 | 6a3b9cc9 | blueswir1 | { |
947 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
948 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
949 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
950 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
951 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
952 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
953 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
954 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
955 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
956 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
957 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
958 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
959 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
960 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
961 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
962 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
963 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
964 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
965 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
966 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
967 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
968 | 6a3b9cc9 | blueswir1 | }, |
969 | ae40972f | blueswir1 | /* SS-20 */
|
970 | ae40972f | blueswir1 | { |
971 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
972 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
973 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
974 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
975 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
976 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
977 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
978 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
979 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
980 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
981 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
982 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
983 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
984 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
985 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
986 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
987 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
988 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
989 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
990 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
991 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
992 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
993 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
994 | ae40972f | blueswir1 | }, |
995 | a526a31c | blueswir1 | /* Voyager */
|
996 | a526a31c | blueswir1 | { |
997 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
998 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
999 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1000 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1001 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1002 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1003 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1004 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1005 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1006 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1007 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1008 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1009 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1010 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
1011 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1012 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1013 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1014 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1015 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1016 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1017 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1018 | a526a31c | blueswir1 | }, |
1019 | a526a31c | blueswir1 | /* LX */
|
1020 | a526a31c | blueswir1 | { |
1021 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1022 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1023 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1024 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1025 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1026 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1027 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1028 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1029 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1030 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1031 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1032 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1033 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1034 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1035 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1036 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1037 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1038 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1039 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1040 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1041 | a526a31c | blueswir1 | }, |
1042 | a526a31c | blueswir1 | /* SS-4 */
|
1043 | a526a31c | blueswir1 | { |
1044 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1045 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1046 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1047 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1048 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1049 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1050 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1051 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1052 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1053 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1054 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1055 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1056 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1057 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1058 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1059 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1060 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1061 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1062 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1063 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1064 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1065 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1066 | a526a31c | blueswir1 | }, |
1067 | a526a31c | blueswir1 | /* SPARCClassic */
|
1068 | a526a31c | blueswir1 | { |
1069 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1070 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1071 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1072 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1073 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1074 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1075 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1076 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1077 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1078 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1079 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1080 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1081 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1082 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1083 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1084 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1085 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1086 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1087 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1088 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1089 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1090 | a526a31c | blueswir1 | }, |
1091 | a526a31c | blueswir1 | /* SPARCbook */
|
1092 | a526a31c | blueswir1 | { |
1093 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1094 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1095 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1096 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1097 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1098 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1099 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1100 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1101 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1102 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1103 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1104 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1105 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1106 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1107 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1108 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1109 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1110 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1111 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1112 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1113 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1114 | a526a31c | blueswir1 | }, |
1115 | 36cd9210 | blueswir1 | }; |
1116 | 36cd9210 | blueswir1 | |
1117 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1118 | fbe1b595 | Paul Brook | static void ss5_init(ram_addr_t RAM_size, |
1119 | 3023f332 | aliguori | const char *boot_device, |
1120 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1121 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1122 | 36cd9210 | blueswir1 | { |
1123 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1124 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1125 | 420557e8 | bellard | } |
1126 | c0e564d5 | bellard | |
1127 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1128 | fbe1b595 | Paul Brook | static void ss10_init(ram_addr_t RAM_size, |
1129 | 3023f332 | aliguori | const char *boot_device, |
1130 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1131 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1132 | e0353fe2 | blueswir1 | { |
1133 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1134 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1135 | e0353fe2 | blueswir1 | } |
1136 | e0353fe2 | blueswir1 | |
1137 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1138 | fbe1b595 | Paul Brook | static void ss600mp_init(ram_addr_t RAM_size, |
1139 | 3023f332 | aliguori | const char *boot_device, |
1140 | 77f193da | blueswir1 | const char *kernel_filename, |
1141 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1142 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1143 | 6a3b9cc9 | blueswir1 | { |
1144 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1145 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1146 | 6a3b9cc9 | blueswir1 | } |
1147 | 6a3b9cc9 | blueswir1 | |
1148 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1149 | fbe1b595 | Paul Brook | static void ss20_init(ram_addr_t RAM_size, |
1150 | 3023f332 | aliguori | const char *boot_device, |
1151 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1152 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1153 | ae40972f | blueswir1 | { |
1154 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1155 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1156 | ee76f82e | blueswir1 | } |
1157 | ee76f82e | blueswir1 | |
1158 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1159 | fbe1b595 | Paul Brook | static void vger_init(ram_addr_t RAM_size, |
1160 | 3023f332 | aliguori | const char *boot_device, |
1161 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1162 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1163 | a526a31c | blueswir1 | { |
1164 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1165 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1166 | a526a31c | blueswir1 | } |
1167 | a526a31c | blueswir1 | |
1168 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1169 | fbe1b595 | Paul Brook | static void ss_lx_init(ram_addr_t RAM_size, |
1170 | 3023f332 | aliguori | const char *boot_device, |
1171 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1172 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1173 | a526a31c | blueswir1 | { |
1174 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1175 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1176 | a526a31c | blueswir1 | } |
1177 | a526a31c | blueswir1 | |
1178 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1179 | fbe1b595 | Paul Brook | static void ss4_init(ram_addr_t RAM_size, |
1180 | 3023f332 | aliguori | const char *boot_device, |
1181 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1182 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1183 | a526a31c | blueswir1 | { |
1184 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1185 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1186 | a526a31c | blueswir1 | } |
1187 | a526a31c | blueswir1 | |
1188 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1189 | fbe1b595 | Paul Brook | static void scls_init(ram_addr_t RAM_size, |
1190 | 3023f332 | aliguori | const char *boot_device, |
1191 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1192 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1193 | a526a31c | blueswir1 | { |
1194 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1195 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1196 | a526a31c | blueswir1 | } |
1197 | a526a31c | blueswir1 | |
1198 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1199 | fbe1b595 | Paul Brook | static void sbook_init(ram_addr_t RAM_size, |
1200 | 3023f332 | aliguori | const char *boot_device, |
1201 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1202 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1203 | a526a31c | blueswir1 | { |
1204 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1205 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1206 | a526a31c | blueswir1 | } |
1207 | a526a31c | blueswir1 | |
1208 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss5_machine = {
|
1209 | 66de733b | blueswir1 | .name = "SS-5",
|
1210 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1211 | 66de733b | blueswir1 | .init = ss5_init, |
1212 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1213 | 0c257437 | Anthony Liguori | .is_default = 1,
|
1214 | c0e564d5 | bellard | }; |
1215 | e0353fe2 | blueswir1 | |
1216 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss10_machine = {
|
1217 | 66de733b | blueswir1 | .name = "SS-10",
|
1218 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1219 | 66de733b | blueswir1 | .init = ss10_init, |
1220 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1221 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1222 | e0353fe2 | blueswir1 | }; |
1223 | 6a3b9cc9 | blueswir1 | |
1224 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss600mp_machine = {
|
1225 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1226 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1227 | 66de733b | blueswir1 | .init = ss600mp_init, |
1228 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1229 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1230 | 6a3b9cc9 | blueswir1 | }; |
1231 | ae40972f | blueswir1 | |
1232 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss20_machine = {
|
1233 | 66de733b | blueswir1 | .name = "SS-20",
|
1234 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1235 | 66de733b | blueswir1 | .init = ss20_init, |
1236 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1237 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1238 | ae40972f | blueswir1 | }; |
1239 | ae40972f | blueswir1 | |
1240 | f80f9ec9 | Anthony Liguori | static QEMUMachine voyager_machine = {
|
1241 | 66de733b | blueswir1 | .name = "Voyager",
|
1242 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1243 | 66de733b | blueswir1 | .init = vger_init, |
1244 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1245 | a526a31c | blueswir1 | }; |
1246 | a526a31c | blueswir1 | |
1247 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss_lx_machine = {
|
1248 | 66de733b | blueswir1 | .name = "LX",
|
1249 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1250 | 66de733b | blueswir1 | .init = ss_lx_init, |
1251 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1252 | a526a31c | blueswir1 | }; |
1253 | a526a31c | blueswir1 | |
1254 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss4_machine = {
|
1255 | 66de733b | blueswir1 | .name = "SS-4",
|
1256 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1257 | 66de733b | blueswir1 | .init = ss4_init, |
1258 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1259 | a526a31c | blueswir1 | }; |
1260 | a526a31c | blueswir1 | |
1261 | f80f9ec9 | Anthony Liguori | static QEMUMachine scls_machine = {
|
1262 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1263 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1264 | 66de733b | blueswir1 | .init = scls_init, |
1265 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1266 | a526a31c | blueswir1 | }; |
1267 | a526a31c | blueswir1 | |
1268 | f80f9ec9 | Anthony Liguori | static QEMUMachine sbook_machine = {
|
1269 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1270 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1271 | 66de733b | blueswir1 | .init = sbook_init, |
1272 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1273 | a526a31c | blueswir1 | }; |
1274 | a526a31c | blueswir1 | |
1275 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1276 | 7d85892b | blueswir1 | /* SS-1000 */
|
1277 | 7d85892b | blueswir1 | { |
1278 | 7d85892b | blueswir1 | .iounit_bases = { |
1279 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1280 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1281 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1282 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1283 | 7d85892b | blueswir1 | -1,
|
1284 | 7d85892b | blueswir1 | }, |
1285 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1286 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1287 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1288 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1289 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1290 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1291 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1292 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1293 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1294 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1295 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1296 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1297 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1298 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1299 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1300 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1301 | 7d85892b | blueswir1 | }, |
1302 | 7d85892b | blueswir1 | /* SS-2000 */
|
1303 | 7d85892b | blueswir1 | { |
1304 | 7d85892b | blueswir1 | .iounit_bases = { |
1305 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1306 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1307 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1308 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1309 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1310 | 7d85892b | blueswir1 | }, |
1311 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1312 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1313 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1314 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1315 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1316 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1317 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1318 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1319 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1320 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1321 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1322 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1323 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1324 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1325 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1326 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1327 | 7d85892b | blueswir1 | }, |
1328 | 7d85892b | blueswir1 | }; |
1329 | 7d85892b | blueswir1 | |
1330 | 4b48bf05 | Blue Swirl | static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1331 | 4b48bf05 | Blue Swirl | { |
1332 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1333 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1334 | 4b48bf05 | Blue Swirl | unsigned int i; |
1335 | 4b48bf05 | Blue Swirl | |
1336 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sbi"); |
1337 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
1338 | 4b48bf05 | Blue Swirl | |
1339 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1340 | 4b48bf05 | Blue Swirl | |
1341 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1342 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, *parent_irq[i]); |
1343 | 4b48bf05 | Blue Swirl | } |
1344 | 4b48bf05 | Blue Swirl | |
1345 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1346 | 4b48bf05 | Blue Swirl | |
1347 | 4b48bf05 | Blue Swirl | return dev;
|
1348 | 4b48bf05 | Blue Swirl | } |
1349 | 4b48bf05 | Blue Swirl | |
1350 | 6ef05b95 | blueswir1 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1351 | 7d85892b | blueswir1 | const char *boot_device, |
1352 | 3023f332 | aliguori | const char *kernel_filename, |
1353 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1354 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1355 | 7d85892b | blueswir1 | { |
1356 | 666713c0 | Blue Swirl | CPUState *envs[MAX_CPUS]; |
1357 | 7d85892b | blueswir1 | unsigned int i; |
1358 | 7fc06735 | Blue Swirl | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1359 | 7fc06735 | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1360 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
1361 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1362 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1363 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1364 | 7fc06735 | Blue Swirl | DeviceState *dev; |
1365 | 7d85892b | blueswir1 | |
1366 | 7d85892b | blueswir1 | /* init CPUs */
|
1367 | 7d85892b | blueswir1 | if (!cpu_model)
|
1368 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1369 | 7d85892b | blueswir1 | |
1370 | 666713c0 | Blue Swirl | for(i = 0; i < smp_cpus; i++) { |
1371 | 666713c0 | Blue Swirl | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1372 | 7d85892b | blueswir1 | } |
1373 | 7d85892b | blueswir1 | |
1374 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1375 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1376 | 7d85892b | blueswir1 | |
1377 | 7d85892b | blueswir1 | /* set up devices */
|
1378 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1379 | a350db85 | Blue Swirl | |
1380 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1381 | f48f6569 | Blue Swirl | |
1382 | 7fc06735 | Blue Swirl | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1383 | 7fc06735 | Blue Swirl | |
1384 | 7fc06735 | Blue Swirl | for (i = 0; i < 32; i++) { |
1385 | 7fc06735 | Blue Swirl | sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1386 | 7fc06735 | Blue Swirl | } |
1387 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1388 | 7fc06735 | Blue Swirl | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1389 | 7fc06735 | Blue Swirl | } |
1390 | 7d85892b | blueswir1 | |
1391 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1392 | 7d85892b | blueswir1 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1393 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1394 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1395 | c533e0b3 | Blue Swirl | sbi_irq[0]);
|
1396 | 7d85892b | blueswir1 | |
1397 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1398 | 74ff8d90 | Blue Swirl | iounits[0], &espdma_irq);
|
1399 | 7d85892b | blueswir1 | |
1400 | c533e0b3 | Blue Swirl | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1401 | 74ff8d90 | Blue Swirl | iounits[0], &ledma_irq);
|
1402 | 7d85892b | blueswir1 | |
1403 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1404 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1405 | 7d85892b | blueswir1 | exit (1);
|
1406 | 7d85892b | blueswir1 | } |
1407 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1408 | dc828ca1 | pbrook | graphic_depth); |
1409 | 7d85892b | blueswir1 | |
1410 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1411 | 7d85892b | blueswir1 | |
1412 | d95d8f1c | Blue Swirl | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1413 | 7d85892b | blueswir1 | |
1414 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1415 | 7d85892b | blueswir1 | |
1416 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1417 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1418 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1419 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1420 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1421 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1422 | 7d85892b | blueswir1 | |
1423 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1424 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1425 | 7d85892b | blueswir1 | exit(1);
|
1426 | 7d85892b | blueswir1 | } |
1427 | 7d85892b | blueswir1 | |
1428 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1429 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1430 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1431 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1432 | 7d85892b | blueswir1 | |
1433 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1434 | 293f78bc | blueswir1 | RAM_size); |
1435 | 7d85892b | blueswir1 | |
1436 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1437 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1438 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1439 | 905fdcb5 | blueswir1 | "Sun4d");
|
1440 | 3cce6243 | blueswir1 | |
1441 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1442 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1443 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1444 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1445 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1446 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1447 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1448 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1449 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1450 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1451 | 513f789f | blueswir1 | } else {
|
1452 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1453 | 513f789f | blueswir1 | } |
1454 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1455 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1456 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1457 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1458 | 7d85892b | blueswir1 | } |
1459 | 7d85892b | blueswir1 | |
1460 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1461 | fbe1b595 | Paul Brook | static void ss1000_init(ram_addr_t RAM_size, |
1462 | 3023f332 | aliguori | const char *boot_device, |
1463 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1464 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1465 | 7d85892b | blueswir1 | { |
1466 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1467 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1468 | 7d85892b | blueswir1 | } |
1469 | 7d85892b | blueswir1 | |
1470 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1471 | fbe1b595 | Paul Brook | static void ss2000_init(ram_addr_t RAM_size, |
1472 | 3023f332 | aliguori | const char *boot_device, |
1473 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1474 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1475 | 7d85892b | blueswir1 | { |
1476 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1477 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1478 | 7d85892b | blueswir1 | } |
1479 | 7d85892b | blueswir1 | |
1480 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss1000_machine = {
|
1481 | 66de733b | blueswir1 | .name = "SS-1000",
|
1482 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1483 | 66de733b | blueswir1 | .init = ss1000_init, |
1484 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1485 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1486 | 7d85892b | blueswir1 | }; |
1487 | 7d85892b | blueswir1 | |
1488 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2000_machine = {
|
1489 | 66de733b | blueswir1 | .name = "SS-2000",
|
1490 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1491 | 66de733b | blueswir1 | .init = ss2000_init, |
1492 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1493 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1494 | 7d85892b | blueswir1 | }; |
1495 | 8137cde8 | blueswir1 | |
1496 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1497 | 8137cde8 | blueswir1 | /* SS-2 */
|
1498 | 8137cde8 | blueswir1 | { |
1499 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1500 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1501 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1502 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1503 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1504 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1505 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1506 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1507 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1508 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1509 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1510 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1511 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1512 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1513 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1514 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1515 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1516 | 8137cde8 | blueswir1 | }, |
1517 | 8137cde8 | blueswir1 | }; |
1518 | 8137cde8 | blueswir1 | |
1519 | 4b48bf05 | Blue Swirl | static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1520 | 4b48bf05 | Blue Swirl | qemu_irq *parent_irq) |
1521 | 4b48bf05 | Blue Swirl | { |
1522 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1523 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1524 | 4b48bf05 | Blue Swirl | unsigned int i; |
1525 | 4b48bf05 | Blue Swirl | |
1526 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sun4c_intctl"); |
1527 | 4b48bf05 | Blue Swirl | qdev_init(dev); |
1528 | 4b48bf05 | Blue Swirl | |
1529 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1530 | 4b48bf05 | Blue Swirl | |
1531 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
1532 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, parent_irq[i]); |
1533 | 4b48bf05 | Blue Swirl | } |
1534 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1535 | 4b48bf05 | Blue Swirl | |
1536 | 4b48bf05 | Blue Swirl | return dev;
|
1537 | 4b48bf05 | Blue Swirl | } |
1538 | 4b48bf05 | Blue Swirl | |
1539 | 8137cde8 | blueswir1 | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1540 | 8137cde8 | blueswir1 | const char *boot_device, |
1541 | 3023f332 | aliguori | const char *kernel_filename, |
1542 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1543 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1544 | 8137cde8 | blueswir1 | { |
1545 | 8137cde8 | blueswir1 | CPUState *env; |
1546 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
1547 | e32cba29 | Blue Swirl | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1548 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1549 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
1550 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1551 | 8137cde8 | blueswir1 | BlockDriverState *fd[MAX_FD]; |
1552 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1553 | e32cba29 | Blue Swirl | DeviceState *dev; |
1554 | e32cba29 | Blue Swirl | unsigned int i; |
1555 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
1556 | 8137cde8 | blueswir1 | |
1557 | 8137cde8 | blueswir1 | /* init CPU */
|
1558 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1559 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1560 | 8137cde8 | blueswir1 | |
1561 | 666713c0 | Blue Swirl | env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1562 | 8137cde8 | blueswir1 | |
1563 | 8137cde8 | blueswir1 | /* set up devices */
|
1564 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1565 | a350db85 | Blue Swirl | |
1566 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1567 | f48f6569 | Blue Swirl | |
1568 | e32cba29 | Blue Swirl | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1569 | e32cba29 | Blue Swirl | |
1570 | e32cba29 | Blue Swirl | for (i = 0; i < 8; i++) { |
1571 | e32cba29 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1572 | e32cba29 | Blue Swirl | } |
1573 | 8137cde8 | blueswir1 | |
1574 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1575 | c533e0b3 | Blue Swirl | slavio_irq[1]);
|
1576 | 8137cde8 | blueswir1 | |
1577 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1578 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
1579 | 8137cde8 | blueswir1 | |
1580 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1581 | 74ff8d90 | Blue Swirl | slavio_irq[3], iommu, &ledma_irq);
|
1582 | 8137cde8 | blueswir1 | |
1583 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1584 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1585 | 8137cde8 | blueswir1 | exit (1);
|
1586 | 8137cde8 | blueswir1 | } |
1587 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1588 | dc828ca1 | pbrook | graphic_depth); |
1589 | 8137cde8 | blueswir1 | |
1590 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1591 | 8137cde8 | blueswir1 | |
1592 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1593 | 8137cde8 | blueswir1 | |
1594 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1595 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1596 | 8137cde8 | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1597 | 8137cde8 | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1598 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[1],
|
1599 | c533e0b3 | Blue Swirl | slavio_irq[1], serial_hds[0], serial_hds[1], |
1600 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1601 | 8137cde8 | blueswir1 | |
1602 | b2b6f6ec | Blue Swirl | slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1603 | 8137cde8 | blueswir1 | |
1604 | 8137cde8 | blueswir1 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1605 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1606 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1607 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_FLOPPY, 0, 0); |
1608 | 751c6a17 | Gerd Hoffmann | if (dinfo)
|
1609 | 751c6a17 | Gerd Hoffmann | fd[0] = dinfo->bdrv;
|
1610 | 8137cde8 | blueswir1 | |
1611 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1612 | 2582cfa0 | Blue Swirl | &fdc_tc); |
1613 | 8137cde8 | blueswir1 | } |
1614 | 8137cde8 | blueswir1 | |
1615 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1616 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1617 | 8137cde8 | blueswir1 | exit(1);
|
1618 | 8137cde8 | blueswir1 | } |
1619 | 8137cde8 | blueswir1 | |
1620 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1621 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1622 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1623 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1624 | 8137cde8 | blueswir1 | |
1625 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1626 | 8137cde8 | blueswir1 | RAM_size); |
1627 | 8137cde8 | blueswir1 | |
1628 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1629 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1630 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1631 | 8137cde8 | blueswir1 | "Sun4c");
|
1632 | 8137cde8 | blueswir1 | |
1633 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1634 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1635 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1636 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1637 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1638 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1639 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1640 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1641 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1642 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1643 | 513f789f | blueswir1 | } else {
|
1644 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1645 | 513f789f | blueswir1 | } |
1646 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1647 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1648 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1649 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1650 | 8137cde8 | blueswir1 | } |
1651 | 8137cde8 | blueswir1 | |
1652 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1653 | fbe1b595 | Paul Brook | static void ss2_init(ram_addr_t RAM_size, |
1654 | 3023f332 | aliguori | const char *boot_device, |
1655 | 8137cde8 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1656 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1657 | 8137cde8 | blueswir1 | { |
1658 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1659 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1660 | 8137cde8 | blueswir1 | } |
1661 | 8137cde8 | blueswir1 | |
1662 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2_machine = {
|
1663 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1664 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1665 | 8137cde8 | blueswir1 | .init = ss2_init, |
1666 | 8137cde8 | blueswir1 | .use_scsi = 1,
|
1667 | 8137cde8 | blueswir1 | }; |
1668 | f80f9ec9 | Anthony Liguori | |
1669 | f80f9ec9 | Anthony Liguori | static void ss2_machine_init(void) |
1670 | f80f9ec9 | Anthony Liguori | { |
1671 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss5_machine); |
1672 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss10_machine); |
1673 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss600mp_machine); |
1674 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss20_machine); |
1675 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&voyager_machine); |
1676 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss_lx_machine); |
1677 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss4_machine); |
1678 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&scls_machine); |
1679 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sbook_machine); |
1680 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss1000_machine); |
1681 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2000_machine); |
1682 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2_machine); |
1683 | f80f9ec9 | Anthony Liguori | } |
1684 | f80f9ec9 | Anthony Liguori | |
1685 | f80f9ec9 | Anthony Liguori | machine_init(ss2_machine_init); |