root / hw / timer / m48t59.c @ a8aec295
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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
25 | 0d09e41a | Paolo Bonzini | #include "hw/timer/m48t59.h" |
26 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
27 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
28 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
29 | 0d09e41a | Paolo Bonzini | #include "hw/isa/isa.h" |
30 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
31 | a541f297 | bellard | |
32 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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33 | a541f297 | bellard | |
34 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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35 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
36 | a541f297 | bellard | #else
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37 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
38 | a541f297 | bellard | #endif
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39 | a541f297 | bellard | |
40 | 819385c5 | bellard | /*
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41 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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42 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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43 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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44 | 819385c5 | bellard | */
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45 | 930f3fe1 | Blue Swirl | |
46 | 930f3fe1 | Blue Swirl | /*
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47 | 930f3fe1 | Blue Swirl | * Chipset docs:
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48 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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49 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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50 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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51 | 930f3fe1 | Blue Swirl | */
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52 | 930f3fe1 | Blue Swirl | |
53 | 43a34704 | Blue Swirl | struct M48t59State {
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54 | a541f297 | bellard | /* Hardware parameters */
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55 | d537cf6c | pbrook | qemu_irq IRQ; |
56 | 5a31cd68 | Avi Kivity | MemoryRegion iomem; |
57 | a541f297 | bellard | uint32_t io_base; |
58 | ee6847d1 | Gerd Hoffmann | uint32_t size; |
59 | a541f297 | bellard | /* RTC management */
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60 | a541f297 | bellard | time_t time_offset; |
61 | a541f297 | bellard | time_t stop_time; |
62 | a541f297 | bellard | /* Alarm & watchdog */
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63 | f6503059 | balrog | struct tm alarm;
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64 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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65 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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66 | a541f297 | bellard | /* NVRAM storage */
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67 | a541f297 | bellard | uint8_t *buffer; |
68 | 42c812b9 | Blue Swirl | /* Model parameters */
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69 | 7bc3018b | Paolo Bonzini | uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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70 | 42c812b9 | Blue Swirl | /* NVRAM storage */
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71 | 42c812b9 | Blue Swirl | uint16_t addr; |
72 | 42c812b9 | Blue Swirl | uint8_t lock; |
73 | c5df018e | bellard | }; |
74 | a541f297 | bellard | |
75 | a2772c70 | Andreas Färber | #define TYPE_ISA_M48T59 "m48t59_isa" |
76 | a2772c70 | Andreas Färber | #define ISA_M48T59(obj) \
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77 | a2772c70 | Andreas Färber | OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) |
78 | a2772c70 | Andreas Färber | |
79 | f80237d4 | Blue Swirl | typedef struct M48t59ISAState { |
80 | a2772c70 | Andreas Färber | ISADevice parent_obj; |
81 | a2772c70 | Andreas Färber | |
82 | 43a34704 | Blue Swirl | M48t59State state; |
83 | 9936d6e4 | Richard Henderson | MemoryRegion io; |
84 | f80237d4 | Blue Swirl | } M48t59ISAState; |
85 | f80237d4 | Blue Swirl | |
86 | f80237d4 | Blue Swirl | typedef struct M48t59SysBusState { |
87 | f80237d4 | Blue Swirl | SysBusDevice busdev; |
88 | 43a34704 | Blue Swirl | M48t59State state; |
89 | 087bd055 | Alexander Graf | MemoryRegion io; |
90 | f80237d4 | Blue Swirl | } M48t59SysBusState; |
91 | f80237d4 | Blue Swirl | |
92 | a541f297 | bellard | /* Fake timer functions */
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93 | a541f297 | bellard | |
94 | a541f297 | bellard | /* Alarm management */
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95 | a541f297 | bellard | static void alarm_cb (void *opaque) |
96 | a541f297 | bellard | { |
97 | f6503059 | balrog | struct tm tm;
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98 | a541f297 | bellard | uint64_t next_time; |
99 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
100 | a541f297 | bellard | |
101 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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102 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
103 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
104 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
105 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
106 | f6503059 | balrog | /* Repeat once a month */
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107 | f6503059 | balrog | qemu_get_timedate(&tm, NVRAM->time_offset); |
108 | f6503059 | balrog | tm.tm_mon++; |
109 | f6503059 | balrog | if (tm.tm_mon == 13) { |
110 | f6503059 | balrog | tm.tm_mon = 1;
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111 | f6503059 | balrog | tm.tm_year++; |
112 | f6503059 | balrog | } |
113 | f6503059 | balrog | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
114 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
115 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
116 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
117 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
118 | f6503059 | balrog | /* Repeat once a day */
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119 | f6503059 | balrog | next_time = 24 * 60 * 60; |
120 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
121 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
122 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
123 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
124 | f6503059 | balrog | /* Repeat once an hour */
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125 | f6503059 | balrog | next_time = 60 * 60; |
126 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
127 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
128 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
129 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
130 | f6503059 | balrog | /* Repeat once a minute */
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131 | f6503059 | balrog | next_time = 60;
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132 | a541f297 | bellard | } else {
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133 | f6503059 | balrog | /* Repeat once a second */
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134 | f6503059 | balrog | next_time = 1;
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135 | a541f297 | bellard | } |
136 | 1d849502 | Paolo Bonzini | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
137 | f6503059 | balrog | next_time * 1000);
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138 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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139 | a541f297 | bellard | } |
140 | a541f297 | bellard | |
141 | 43a34704 | Blue Swirl | static void set_alarm(M48t59State *NVRAM) |
142 | f6503059 | balrog | { |
143 | f6503059 | balrog | int diff;
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144 | f6503059 | balrog | if (NVRAM->alrm_timer != NULL) { |
145 | f6503059 | balrog | qemu_del_timer(NVRAM->alrm_timer); |
146 | f6503059 | balrog | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
147 | f6503059 | balrog | if (diff > 0) |
148 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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149 | f6503059 | balrog | } |
150 | f6503059 | balrog | } |
151 | a541f297 | bellard | |
152 | f6503059 | balrog | /* RTC management helpers */
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153 | 43a34704 | Blue Swirl | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
154 | a541f297 | bellard | { |
155 | f6503059 | balrog | qemu_get_timedate(tm, NVRAM->time_offset); |
156 | a541f297 | bellard | } |
157 | a541f297 | bellard | |
158 | 43a34704 | Blue Swirl | static void set_time(M48t59State *NVRAM, struct tm *tm) |
159 | a541f297 | bellard | { |
160 | f6503059 | balrog | NVRAM->time_offset = qemu_timedate_diff(tm); |
161 | f6503059 | balrog | set_alarm(NVRAM); |
162 | a541f297 | bellard | } |
163 | a541f297 | bellard | |
164 | a541f297 | bellard | /* Watchdog management */
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165 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
166 | a541f297 | bellard | { |
167 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
168 | a541f297 | bellard | |
169 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
170 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
171 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
172 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
173 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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174 | d7d02e3c | bellard | qemu_system_reset_request(); |
175 | a541f297 | bellard | } else {
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176 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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177 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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178 | a541f297 | bellard | } |
179 | a541f297 | bellard | } |
180 | a541f297 | bellard | |
181 | 43a34704 | Blue Swirl | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
182 | a541f297 | bellard | { |
183 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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184 | a541f297 | bellard | |
185 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
186 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
187 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
188 | 868d585a | j_mayer | if (value != 0) { |
189 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
190 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
191 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
192 | 868d585a | j_mayer | } |
193 | a541f297 | bellard | } |
194 | a541f297 | bellard | } |
195 | a541f297 | bellard | |
196 | a541f297 | bellard | /* Direct access to NVRAM */
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197 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
198 | a541f297 | bellard | { |
199 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
200 | a541f297 | bellard | struct tm tm;
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201 | a541f297 | bellard | int tmp;
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202 | a541f297 | bellard | |
203 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
204 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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205 | 4aed2c33 | blueswir1 | |
206 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
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207 | 7bc3018b | Paolo Bonzini | if ((NVRAM->model == 2 && addr < 0x7f8) || |
208 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 8 && addr < 0x1ff8) || |
209 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 59 && addr < 0x1ff0)) { |
210 | 819385c5 | bellard | goto do_write;
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211 | 7bc3018b | Paolo Bonzini | } |
212 | 4aed2c33 | blueswir1 | |
213 | 4aed2c33 | blueswir1 | /* TOD access */
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214 | 819385c5 | bellard | switch (addr) {
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215 | a541f297 | bellard | case 0x1FF0: |
216 | a541f297 | bellard | /* flags register : read-only */
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217 | a541f297 | bellard | break;
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218 | a541f297 | bellard | case 0x1FF1: |
219 | a541f297 | bellard | /* unused */
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220 | a541f297 | bellard | break;
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221 | a541f297 | bellard | case 0x1FF2: |
222 | a541f297 | bellard | /* alarm seconds */
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223 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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224 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
225 | f6503059 | balrog | NVRAM->alarm.tm_sec = tmp; |
226 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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227 | f6503059 | balrog | set_alarm(NVRAM); |
228 | 819385c5 | bellard | } |
229 | a541f297 | bellard | break;
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230 | a541f297 | bellard | case 0x1FF3: |
231 | a541f297 | bellard | /* alarm minutes */
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232 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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233 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
234 | f6503059 | balrog | NVRAM->alarm.tm_min = tmp; |
235 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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236 | f6503059 | balrog | set_alarm(NVRAM); |
237 | 819385c5 | bellard | } |
238 | a541f297 | bellard | break;
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239 | a541f297 | bellard | case 0x1FF4: |
240 | a541f297 | bellard | /* alarm hours */
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241 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x3F);
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242 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
243 | f6503059 | balrog | NVRAM->alarm.tm_hour = tmp; |
244 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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245 | f6503059 | balrog | set_alarm(NVRAM); |
246 | 819385c5 | bellard | } |
247 | a541f297 | bellard | break;
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248 | a541f297 | bellard | case 0x1FF5: |
249 | a541f297 | bellard | /* alarm date */
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250 | 02f5da11 | Artyom Tarasenko | tmp = from_bcd(val & 0x3F);
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251 | 819385c5 | bellard | if (tmp != 0) { |
252 | f6503059 | balrog | NVRAM->alarm.tm_mday = tmp; |
253 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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254 | f6503059 | balrog | set_alarm(NVRAM); |
255 | 819385c5 | bellard | } |
256 | a541f297 | bellard | break;
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257 | a541f297 | bellard | case 0x1FF6: |
258 | a541f297 | bellard | /* interrupts */
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259 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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260 | a541f297 | bellard | break;
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261 | a541f297 | bellard | case 0x1FF7: |
262 | a541f297 | bellard | /* watchdog */
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263 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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264 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
265 | a541f297 | bellard | break;
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266 | a541f297 | bellard | case 0x1FF8: |
267 | 4aed2c33 | blueswir1 | case 0x07F8: |
268 | a541f297 | bellard | /* control */
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269 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
270 | a541f297 | bellard | break;
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271 | a541f297 | bellard | case 0x1FF9: |
272 | 4aed2c33 | blueswir1 | case 0x07F9: |
273 | a541f297 | bellard | /* seconds (BCD) */
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274 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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275 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
276 | a541f297 | bellard | get_time(NVRAM, &tm); |
277 | a541f297 | bellard | tm.tm_sec = tmp; |
278 | a541f297 | bellard | set_time(NVRAM, &tm); |
279 | a541f297 | bellard | } |
280 | f6503059 | balrog | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
281 | a541f297 | bellard | if (val & 0x80) { |
282 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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283 | a541f297 | bellard | } else {
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284 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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285 | a541f297 | bellard | NVRAM->stop_time = 0;
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286 | a541f297 | bellard | } |
287 | a541f297 | bellard | } |
288 | f6503059 | balrog | NVRAM->buffer[addr] = val & 0x80;
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289 | a541f297 | bellard | break;
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290 | a541f297 | bellard | case 0x1FFA: |
291 | 4aed2c33 | blueswir1 | case 0x07FA: |
292 | a541f297 | bellard | /* minutes (BCD) */
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293 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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294 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
295 | a541f297 | bellard | get_time(NVRAM, &tm); |
296 | a541f297 | bellard | tm.tm_min = tmp; |
297 | a541f297 | bellard | set_time(NVRAM, &tm); |
298 | a541f297 | bellard | } |
299 | a541f297 | bellard | break;
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300 | a541f297 | bellard | case 0x1FFB: |
301 | 4aed2c33 | blueswir1 | case 0x07FB: |
302 | a541f297 | bellard | /* hours (BCD) */
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303 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x3F);
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304 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
305 | a541f297 | bellard | get_time(NVRAM, &tm); |
306 | a541f297 | bellard | tm.tm_hour = tmp; |
307 | a541f297 | bellard | set_time(NVRAM, &tm); |
308 | a541f297 | bellard | } |
309 | a541f297 | bellard | break;
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310 | a541f297 | bellard | case 0x1FFC: |
311 | 4aed2c33 | blueswir1 | case 0x07FC: |
312 | a541f297 | bellard | /* day of the week / century */
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313 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x07);
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314 | a541f297 | bellard | get_time(NVRAM, &tm); |
315 | a541f297 | bellard | tm.tm_wday = tmp; |
316 | a541f297 | bellard | set_time(NVRAM, &tm); |
317 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
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318 | a541f297 | bellard | break;
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319 | a541f297 | bellard | case 0x1FFD: |
320 | 4aed2c33 | blueswir1 | case 0x07FD: |
321 | 02f5da11 | Artyom Tarasenko | /* date (BCD) */
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322 | 02f5da11 | Artyom Tarasenko | tmp = from_bcd(val & 0x3F);
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323 | a541f297 | bellard | if (tmp != 0) { |
324 | a541f297 | bellard | get_time(NVRAM, &tm); |
325 | a541f297 | bellard | tm.tm_mday = tmp; |
326 | a541f297 | bellard | set_time(NVRAM, &tm); |
327 | a541f297 | bellard | } |
328 | a541f297 | bellard | break;
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329 | a541f297 | bellard | case 0x1FFE: |
330 | 4aed2c33 | blueswir1 | case 0x07FE: |
331 | a541f297 | bellard | /* month */
|
332 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x1F);
|
333 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
334 | a541f297 | bellard | get_time(NVRAM, &tm); |
335 | a541f297 | bellard | tm.tm_mon = tmp - 1;
|
336 | a541f297 | bellard | set_time(NVRAM, &tm); |
337 | a541f297 | bellard | } |
338 | a541f297 | bellard | break;
|
339 | a541f297 | bellard | case 0x1FFF: |
340 | 4aed2c33 | blueswir1 | case 0x07FF: |
341 | a541f297 | bellard | /* year */
|
342 | abd0c6bd | Paul Brook | tmp = from_bcd(val); |
343 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
344 | a541f297 | bellard | get_time(NVRAM, &tm); |
345 | 7bc3018b | Paolo Bonzini | if (NVRAM->model == 8) { |
346 | abd0c6bd | Paul Brook | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
347 | 7bc3018b | Paolo Bonzini | } else {
|
348 | abd0c6bd | Paul Brook | tm.tm_year = from_bcd(val); |
349 | 7bc3018b | Paolo Bonzini | } |
350 | a541f297 | bellard | set_time(NVRAM, &tm); |
351 | a541f297 | bellard | } |
352 | a541f297 | bellard | break;
|
353 | a541f297 | bellard | default:
|
354 | 13ab5daa | bellard | /* Check lock registers state */
|
355 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
356 | 13ab5daa | bellard | break;
|
357 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
358 | 13ab5daa | bellard | break;
|
359 | 819385c5 | bellard | do_write:
|
360 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
361 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
362 | a541f297 | bellard | } |
363 | a541f297 | bellard | break;
|
364 | a541f297 | bellard | } |
365 | a541f297 | bellard | } |
366 | a541f297 | bellard | |
367 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
368 | a541f297 | bellard | { |
369 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
370 | a541f297 | bellard | struct tm tm;
|
371 | a541f297 | bellard | uint32_t retval = 0xFF;
|
372 | a541f297 | bellard | |
373 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
374 | 7bc3018b | Paolo Bonzini | if ((NVRAM->model == 2 && addr < 0x078f) || |
375 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 8 && addr < 0x1ff8) || |
376 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 59 && addr < 0x1ff0)) { |
377 | 819385c5 | bellard | goto do_read;
|
378 | 7bc3018b | Paolo Bonzini | } |
379 | 4aed2c33 | blueswir1 | |
380 | 4aed2c33 | blueswir1 | /* TOD access */
|
381 | 819385c5 | bellard | switch (addr) {
|
382 | a541f297 | bellard | case 0x1FF0: |
383 | a541f297 | bellard | /* flags register */
|
384 | a541f297 | bellard | goto do_read;
|
385 | a541f297 | bellard | case 0x1FF1: |
386 | a541f297 | bellard | /* unused */
|
387 | a541f297 | bellard | retval = 0;
|
388 | a541f297 | bellard | break;
|
389 | a541f297 | bellard | case 0x1FF2: |
390 | a541f297 | bellard | /* alarm seconds */
|
391 | a541f297 | bellard | goto do_read;
|
392 | a541f297 | bellard | case 0x1FF3: |
393 | a541f297 | bellard | /* alarm minutes */
|
394 | a541f297 | bellard | goto do_read;
|
395 | a541f297 | bellard | case 0x1FF4: |
396 | a541f297 | bellard | /* alarm hours */
|
397 | a541f297 | bellard | goto do_read;
|
398 | a541f297 | bellard | case 0x1FF5: |
399 | a541f297 | bellard | /* alarm date */
|
400 | a541f297 | bellard | goto do_read;
|
401 | a541f297 | bellard | case 0x1FF6: |
402 | a541f297 | bellard | /* interrupts */
|
403 | a541f297 | bellard | goto do_read;
|
404 | a541f297 | bellard | case 0x1FF7: |
405 | a541f297 | bellard | /* A read resets the watchdog */
|
406 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
407 | a541f297 | bellard | goto do_read;
|
408 | a541f297 | bellard | case 0x1FF8: |
409 | 4aed2c33 | blueswir1 | case 0x07F8: |
410 | a541f297 | bellard | /* control */
|
411 | a541f297 | bellard | goto do_read;
|
412 | a541f297 | bellard | case 0x1FF9: |
413 | 4aed2c33 | blueswir1 | case 0x07F9: |
414 | a541f297 | bellard | /* seconds (BCD) */
|
415 | a541f297 | bellard | get_time(NVRAM, &tm); |
416 | abd0c6bd | Paul Brook | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
417 | a541f297 | bellard | break;
|
418 | a541f297 | bellard | case 0x1FFA: |
419 | 4aed2c33 | blueswir1 | case 0x07FA: |
420 | a541f297 | bellard | /* minutes (BCD) */
|
421 | a541f297 | bellard | get_time(NVRAM, &tm); |
422 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_min); |
423 | a541f297 | bellard | break;
|
424 | a541f297 | bellard | case 0x1FFB: |
425 | 4aed2c33 | blueswir1 | case 0x07FB: |
426 | a541f297 | bellard | /* hours (BCD) */
|
427 | a541f297 | bellard | get_time(NVRAM, &tm); |
428 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_hour); |
429 | a541f297 | bellard | break;
|
430 | a541f297 | bellard | case 0x1FFC: |
431 | 4aed2c33 | blueswir1 | case 0x07FC: |
432 | a541f297 | bellard | /* day of the week / century */
|
433 | a541f297 | bellard | get_time(NVRAM, &tm); |
434 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
435 | a541f297 | bellard | break;
|
436 | a541f297 | bellard | case 0x1FFD: |
437 | 4aed2c33 | blueswir1 | case 0x07FD: |
438 | a541f297 | bellard | /* date */
|
439 | a541f297 | bellard | get_time(NVRAM, &tm); |
440 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_mday); |
441 | a541f297 | bellard | break;
|
442 | a541f297 | bellard | case 0x1FFE: |
443 | 4aed2c33 | blueswir1 | case 0x07FE: |
444 | a541f297 | bellard | /* month */
|
445 | a541f297 | bellard | get_time(NVRAM, &tm); |
446 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_mon + 1);
|
447 | a541f297 | bellard | break;
|
448 | a541f297 | bellard | case 0x1FFF: |
449 | 4aed2c33 | blueswir1 | case 0x07FF: |
450 | a541f297 | bellard | /* year */
|
451 | a541f297 | bellard | get_time(NVRAM, &tm); |
452 | 7bc3018b | Paolo Bonzini | if (NVRAM->model == 8) { |
453 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
454 | 7bc3018b | Paolo Bonzini | } else {
|
455 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_year); |
456 | 7bc3018b | Paolo Bonzini | } |
457 | a541f297 | bellard | break;
|
458 | a541f297 | bellard | default:
|
459 | 13ab5daa | bellard | /* Check lock registers state */
|
460 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
461 | 13ab5daa | bellard | break;
|
462 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
463 | 13ab5daa | bellard | break;
|
464 | 819385c5 | bellard | do_read:
|
465 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
466 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
467 | a541f297 | bellard | } |
468 | a541f297 | bellard | break;
|
469 | a541f297 | bellard | } |
470 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
471 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
472 | a541f297 | bellard | |
473 | a541f297 | bellard | return retval;
|
474 | a541f297 | bellard | } |
475 | a541f297 | bellard | |
476 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
477 | 13ab5daa | bellard | { |
478 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
479 | 897b4c6c | j_mayer | |
480 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
481 | 13ab5daa | bellard | } |
482 | 13ab5daa | bellard | |
483 | a541f297 | bellard | /* IO access to NVRAM */
|
484 | 087bd055 | Alexander Graf | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
485 | 087bd055 | Alexander Graf | unsigned size)
|
486 | a541f297 | bellard | { |
487 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
488 | a541f297 | bellard | |
489 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
490 | a541f297 | bellard | switch (addr) {
|
491 | a541f297 | bellard | case 0: |
492 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
493 | a541f297 | bellard | NVRAM->addr |= val; |
494 | a541f297 | bellard | break;
|
495 | a541f297 | bellard | case 1: |
496 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
497 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
498 | a541f297 | bellard | break;
|
499 | a541f297 | bellard | case 3: |
500 | b1f88301 | Blue Swirl | m48t59_write(NVRAM, NVRAM->addr, val); |
501 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
502 | a541f297 | bellard | break;
|
503 | a541f297 | bellard | default:
|
504 | a541f297 | bellard | break;
|
505 | a541f297 | bellard | } |
506 | a541f297 | bellard | } |
507 | a541f297 | bellard | |
508 | 087bd055 | Alexander Graf | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
509 | a541f297 | bellard | { |
510 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
511 | 13ab5daa | bellard | uint32_t retval; |
512 | a541f297 | bellard | |
513 | 13ab5daa | bellard | switch (addr) {
|
514 | 13ab5daa | bellard | case 3: |
515 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
516 | 13ab5daa | bellard | break;
|
517 | 13ab5daa | bellard | default:
|
518 | 13ab5daa | bellard | retval = -1;
|
519 | 13ab5daa | bellard | break;
|
520 | 13ab5daa | bellard | } |
521 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
522 | a541f297 | bellard | |
523 | 13ab5daa | bellard | return retval;
|
524 | a541f297 | bellard | } |
525 | a541f297 | bellard | |
526 | a8170e5e | Avi Kivity | static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
527 | e1bb04f7 | bellard | { |
528 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
529 | 3b46e624 | ths | |
530 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
531 | e1bb04f7 | bellard | } |
532 | e1bb04f7 | bellard | |
533 | a8170e5e | Avi Kivity | static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
534 | e1bb04f7 | bellard | { |
535 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
536 | 3b46e624 | ths | |
537 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
538 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
539 | e1bb04f7 | bellard | } |
540 | e1bb04f7 | bellard | |
541 | a8170e5e | Avi Kivity | static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
542 | e1bb04f7 | bellard | { |
543 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
544 | 3b46e624 | ths | |
545 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
546 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
547 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
548 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
549 | e1bb04f7 | bellard | } |
550 | e1bb04f7 | bellard | |
551 | a8170e5e | Avi Kivity | static uint32_t nvram_readb (void *opaque, hwaddr addr) |
552 | e1bb04f7 | bellard | { |
553 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
554 | 819385c5 | bellard | uint32_t retval; |
555 | 3b46e624 | ths | |
556 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
557 | e1bb04f7 | bellard | return retval;
|
558 | e1bb04f7 | bellard | } |
559 | e1bb04f7 | bellard | |
560 | a8170e5e | Avi Kivity | static uint32_t nvram_readw (void *opaque, hwaddr addr) |
561 | e1bb04f7 | bellard | { |
562 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
563 | 819385c5 | bellard | uint32_t retval; |
564 | 3b46e624 | ths | |
565 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
566 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
567 | e1bb04f7 | bellard | return retval;
|
568 | e1bb04f7 | bellard | } |
569 | e1bb04f7 | bellard | |
570 | a8170e5e | Avi Kivity | static uint32_t nvram_readl (void *opaque, hwaddr addr) |
571 | e1bb04f7 | bellard | { |
572 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
573 | 819385c5 | bellard | uint32_t retval; |
574 | e1bb04f7 | bellard | |
575 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
576 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
577 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
578 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
579 | e1bb04f7 | bellard | return retval;
|
580 | e1bb04f7 | bellard | } |
581 | e1bb04f7 | bellard | |
582 | 5a31cd68 | Avi Kivity | static const MemoryRegionOps nvram_ops = { |
583 | 5a31cd68 | Avi Kivity | .old_mmio = { |
584 | 5a31cd68 | Avi Kivity | .read = { nvram_readb, nvram_readw, nvram_readl, }, |
585 | 5a31cd68 | Avi Kivity | .write = { nvram_writeb, nvram_writew, nvram_writel, }, |
586 | 5a31cd68 | Avi Kivity | }, |
587 | 5a31cd68 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
588 | e1bb04f7 | bellard | }; |
589 | 819385c5 | bellard | |
590 | fd484ae4 | Juan Quintela | static const VMStateDescription vmstate_m48t59 = { |
591 | fd484ae4 | Juan Quintela | .name = "m48t59",
|
592 | fd484ae4 | Juan Quintela | .version_id = 1,
|
593 | fd484ae4 | Juan Quintela | .minimum_version_id = 1,
|
594 | fd484ae4 | Juan Quintela | .minimum_version_id_old = 1,
|
595 | fd484ae4 | Juan Quintela | .fields = (VMStateField[]) { |
596 | fd484ae4 | Juan Quintela | VMSTATE_UINT8(lock, M48t59State), |
597 | fd484ae4 | Juan Quintela | VMSTATE_UINT16(addr, M48t59State), |
598 | fd484ae4 | Juan Quintela | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
599 | fd484ae4 | Juan Quintela | VMSTATE_END_OF_LIST() |
600 | fd484ae4 | Juan Quintela | } |
601 | fd484ae4 | Juan Quintela | }; |
602 | 3ccacc4a | blueswir1 | |
603 | 43a34704 | Blue Swirl | static void m48t59_reset_common(M48t59State *NVRAM) |
604 | 3ccacc4a | blueswir1 | { |
605 | 6e6b7363 | blueswir1 | NVRAM->addr = 0;
|
606 | 6e6b7363 | blueswir1 | NVRAM->lock = 0;
|
607 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
608 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
609 | 3ccacc4a | blueswir1 | |
610 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
611 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
612 | 3ccacc4a | blueswir1 | } |
613 | 3ccacc4a | blueswir1 | |
614 | 285e468d | Blue Swirl | static void m48t59_reset_isa(DeviceState *d) |
615 | 285e468d | Blue Swirl | { |
616 | a2772c70 | Andreas Färber | M48t59ISAState *isa = ISA_M48T59(d); |
617 | 43a34704 | Blue Swirl | M48t59State *NVRAM = &isa->state; |
618 | 285e468d | Blue Swirl | |
619 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
620 | 285e468d | Blue Swirl | } |
621 | 285e468d | Blue Swirl | |
622 | 285e468d | Blue Swirl | static void m48t59_reset_sysbus(DeviceState *d) |
623 | 285e468d | Blue Swirl | { |
624 | 285e468d | Blue Swirl | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
625 | 43a34704 | Blue Swirl | M48t59State *NVRAM = &sys->state; |
626 | 285e468d | Blue Swirl | |
627 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
628 | 285e468d | Blue Swirl | } |
629 | 285e468d | Blue Swirl | |
630 | 9936d6e4 | Richard Henderson | static const MemoryRegionOps m48t59_io_ops = { |
631 | 087bd055 | Alexander Graf | .read = NVRAM_readb, |
632 | 087bd055 | Alexander Graf | .write = NVRAM_writeb, |
633 | 087bd055 | Alexander Graf | .impl = { |
634 | 087bd055 | Alexander Graf | .min_access_size = 1,
|
635 | 087bd055 | Alexander Graf | .max_access_size = 1,
|
636 | 087bd055 | Alexander Graf | }, |
637 | 087bd055 | Alexander Graf | .endianness = DEVICE_LITTLE_ENDIAN, |
638 | 9936d6e4 | Richard Henderson | }; |
639 | 9936d6e4 | Richard Henderson | |
640 | a541f297 | bellard | /* Initialisation routine */
|
641 | a8170e5e | Avi Kivity | M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
642 | 7bc3018b | Paolo Bonzini | uint32_t io_base, uint16_t size, int model)
|
643 | a541f297 | bellard | { |
644 | d27cf0ae | Blue Swirl | DeviceState *dev; |
645 | d27cf0ae | Blue Swirl | SysBusDevice *s; |
646 | f80237d4 | Blue Swirl | M48t59SysBusState *d; |
647 | 51f9b84e | Hervé Poussineau | M48t59State *state; |
648 | d27cf0ae | Blue Swirl | |
649 | d27cf0ae | Blue Swirl | dev = qdev_create(NULL, "m48t59"); |
650 | 7bc3018b | Paolo Bonzini | qdev_prop_set_uint32(dev, "model", model);
|
651 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "size", size);
|
652 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "io_base", io_base);
|
653 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
654 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
655 | 51f9b84e | Hervé Poussineau | d = FROM_SYSBUS(M48t59SysBusState, s); |
656 | 51f9b84e | Hervé Poussineau | state = &d->state; |
657 | d27cf0ae | Blue Swirl | sysbus_connect_irq(s, 0, IRQ);
|
658 | 087bd055 | Alexander Graf | memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); |
659 | 819385c5 | bellard | if (io_base != 0) { |
660 | 087bd055 | Alexander Graf | memory_region_add_subregion(get_system_io(), io_base, &d->io); |
661 | 819385c5 | bellard | } |
662 | e1bb04f7 | bellard | if (mem_base != 0) { |
663 | d27cf0ae | Blue Swirl | sysbus_mmio_map(s, 0, mem_base);
|
664 | e1bb04f7 | bellard | } |
665 | d27cf0ae | Blue Swirl | |
666 | 51f9b84e | Hervé Poussineau | return state;
|
667 | d27cf0ae | Blue Swirl | } |
668 | d27cf0ae | Blue Swirl | |
669 | 48a18b3c | Hervé Poussineau | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
670 | 7bc3018b | Paolo Bonzini | int model)
|
671 | d27cf0ae | Blue Swirl | { |
672 | f80237d4 | Blue Swirl | M48t59ISAState *d; |
673 | a2772c70 | Andreas Färber | ISADevice *isadev; |
674 | a2772c70 | Andreas Färber | DeviceState *dev; |
675 | 43a34704 | Blue Swirl | M48t59State *s; |
676 | f80237d4 | Blue Swirl | |
677 | a2772c70 | Andreas Färber | isadev = isa_create(bus, TYPE_ISA_M48T59); |
678 | a2772c70 | Andreas Färber | dev = DEVICE(isadev); |
679 | a2772c70 | Andreas Färber | qdev_prop_set_uint32(dev, "model", model);
|
680 | a2772c70 | Andreas Färber | qdev_prop_set_uint32(dev, "size", size);
|
681 | a2772c70 | Andreas Färber | qdev_prop_set_uint32(dev, "io_base", io_base);
|
682 | a2772c70 | Andreas Färber | qdev_init_nofail(dev); |
683 | a2772c70 | Andreas Färber | d = ISA_M48T59(isadev); |
684 | f80237d4 | Blue Swirl | s = &d->state; |
685 | d27cf0ae | Blue Swirl | |
686 | 9936d6e4 | Richard Henderson | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
687 | f80237d4 | Blue Swirl | if (io_base != 0) { |
688 | a2772c70 | Andreas Färber | isa_register_ioport(isadev, &d->io, io_base); |
689 | f80237d4 | Blue Swirl | } |
690 | d27cf0ae | Blue Swirl | |
691 | f80237d4 | Blue Swirl | return s;
|
692 | f80237d4 | Blue Swirl | } |
693 | d27cf0ae | Blue Swirl | |
694 | db895a1e | Andreas Färber | static void m48t59_realize_common(M48t59State *s, Error **errp) |
695 | f80237d4 | Blue Swirl | { |
696 | 7267c094 | Anthony Liguori | s->buffer = g_malloc0(s->size); |
697 | 7bc3018b | Paolo Bonzini | if (s->model == 59) { |
698 | 1d849502 | Paolo Bonzini | s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
699 | 74475455 | Paolo Bonzini | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
700 | 819385c5 | bellard | } |
701 | f6503059 | balrog | qemu_get_timedate(&s->alarm, 0);
|
702 | 13ab5daa | bellard | |
703 | fd484ae4 | Juan Quintela | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
704 | f80237d4 | Blue Swirl | } |
705 | f80237d4 | Blue Swirl | |
706 | db895a1e | Andreas Färber | static void m48t59_isa_realize(DeviceState *dev, Error **errp) |
707 | f80237d4 | Blue Swirl | { |
708 | db895a1e | Andreas Färber | ISADevice *isadev = ISA_DEVICE(dev); |
709 | a2772c70 | Andreas Färber | M48t59ISAState *d = ISA_M48T59(dev); |
710 | 43a34704 | Blue Swirl | M48t59State *s = &d->state; |
711 | f80237d4 | Blue Swirl | |
712 | db895a1e | Andreas Färber | isa_init_irq(isadev, &s->IRQ, 8);
|
713 | db895a1e | Andreas Färber | m48t59_realize_common(s, errp); |
714 | d27cf0ae | Blue Swirl | } |
715 | 3ccacc4a | blueswir1 | |
716 | f80237d4 | Blue Swirl | static int m48t59_init1(SysBusDevice *dev) |
717 | f80237d4 | Blue Swirl | { |
718 | f80237d4 | Blue Swirl | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
719 | 43a34704 | Blue Swirl | M48t59State *s = &d->state; |
720 | db895a1e | Andreas Färber | Error *err = NULL;
|
721 | f80237d4 | Blue Swirl | |
722 | f80237d4 | Blue Swirl | sysbus_init_irq(dev, &s->IRQ); |
723 | f80237d4 | Blue Swirl | |
724 | 5a31cd68 | Avi Kivity | memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
|
725 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
726 | db895a1e | Andreas Färber | m48t59_realize_common(s, &err); |
727 | db895a1e | Andreas Färber | if (err != NULL) { |
728 | db895a1e | Andreas Färber | error_free(err); |
729 | db895a1e | Andreas Färber | return -1; |
730 | db895a1e | Andreas Färber | } |
731 | f80237d4 | Blue Swirl | |
732 | f80237d4 | Blue Swirl | return 0; |
733 | f80237d4 | Blue Swirl | } |
734 | f80237d4 | Blue Swirl | |
735 | 39bffca2 | Anthony Liguori | static Property m48t59_isa_properties[] = {
|
736 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
737 | 7bc3018b | Paolo Bonzini | DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
738 | 39bffca2 | Anthony Liguori | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
739 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
740 | 39bffca2 | Anthony Liguori | }; |
741 | 39bffca2 | Anthony Liguori | |
742 | a2772c70 | Andreas Färber | static void m48t59_isa_class_init(ObjectClass *klass, void *data) |
743 | 8f04ee08 | Anthony Liguori | { |
744 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
745 | db895a1e | Andreas Färber | |
746 | db895a1e | Andreas Färber | dc->realize = m48t59_isa_realize; |
747 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
748 | 39bffca2 | Anthony Liguori | dc->reset = m48t59_reset_isa; |
749 | 39bffca2 | Anthony Liguori | dc->props = m48t59_isa_properties; |
750 | 8f04ee08 | Anthony Liguori | } |
751 | 8f04ee08 | Anthony Liguori | |
752 | 8c43a6f0 | Andreas Färber | static const TypeInfo m48t59_isa_info = { |
753 | a2772c70 | Andreas Färber | .name = TYPE_ISA_M48T59, |
754 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
755 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(M48t59ISAState),
|
756 | a2772c70 | Andreas Färber | .class_init = m48t59_isa_class_init, |
757 | f80237d4 | Blue Swirl | }; |
758 | f80237d4 | Blue Swirl | |
759 | 999e12bb | Anthony Liguori | static Property m48t59_properties[] = {
|
760 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
761 | 7bc3018b | Paolo Bonzini | DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
762 | 999e12bb | Anthony Liguori | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
763 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
764 | 999e12bb | Anthony Liguori | }; |
765 | 999e12bb | Anthony Liguori | |
766 | 999e12bb | Anthony Liguori | static void m48t59_class_init(ObjectClass *klass, void *data) |
767 | 999e12bb | Anthony Liguori | { |
768 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
769 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
770 | 999e12bb | Anthony Liguori | |
771 | 999e12bb | Anthony Liguori | k->init = m48t59_init1; |
772 | 39bffca2 | Anthony Liguori | dc->reset = m48t59_reset_sysbus; |
773 | 39bffca2 | Anthony Liguori | dc->props = m48t59_properties; |
774 | 999e12bb | Anthony Liguori | } |
775 | 999e12bb | Anthony Liguori | |
776 | 8c43a6f0 | Andreas Färber | static const TypeInfo m48t59_info = { |
777 | 39bffca2 | Anthony Liguori | .name = "m48t59",
|
778 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
779 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(M48t59SysBusState),
|
780 | 39bffca2 | Anthony Liguori | .class_init = m48t59_class_init, |
781 | ee6847d1 | Gerd Hoffmann | }; |
782 | ee6847d1 | Gerd Hoffmann | |
783 | 83f7d43a | Andreas Färber | static void m48t59_register_types(void) |
784 | d27cf0ae | Blue Swirl | { |
785 | 39bffca2 | Anthony Liguori | type_register_static(&m48t59_info); |
786 | 39bffca2 | Anthony Liguori | type_register_static(&m48t59_isa_info); |
787 | a541f297 | bellard | } |
788 | d27cf0ae | Blue Swirl | |
789 | 83f7d43a | Andreas Färber | type_init(m48t59_register_types) |