root / target-sh4 / op_helper.c @ a8aec295
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h> |
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#include <stdlib.h> |
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#include "cpu.h" |
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#include "helper.h" |
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#ifndef CONFIG_USER_ONLY
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#include "exec/softmmu_exec.h" |
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#define MMUSUFFIX _mmu
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#define SHIFT 0 |
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#include "exec/softmmu_template.h" |
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#define SHIFT 1 |
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#include "exec/softmmu_template.h" |
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#define SHIFT 2 |
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#include "exec/softmmu_template.h" |
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#define SHIFT 3 |
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#include "exec/softmmu_template.h" |
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|
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void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx, |
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uintptr_t retaddr) |
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{
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int ret;
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ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx); |
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if (ret) {
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/* now we have a real cpu fault */
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if (retaddr) {
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cpu_restore_state(env, retaddr); |
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} |
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cpu_loop_exit(env); |
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} |
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} |
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|
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#endif
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|
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void helper_ldtlb(CPUSH4State *env)
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{
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#ifdef CONFIG_USER_ONLY
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/* XXXXX */
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cpu_abort(env, "Unhandled ldtlb");
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#else
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cpu_load_tlb(env); |
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#endif
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} |
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|
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static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, |
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uintptr_t retaddr) |
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{
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env->exception_index = index; |
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if (retaddr) {
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cpu_restore_state(env, retaddr); |
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} |
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cpu_loop_exit(env); |
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} |
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|
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void helper_raise_illegal_instruction(CPUSH4State *env)
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{
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raise_exception(env, 0x180, 0); |
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} |
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|
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void helper_raise_slot_illegal_instruction(CPUSH4State *env)
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{
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raise_exception(env, 0x1a0, 0); |
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} |
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void helper_raise_fpu_disable(CPUSH4State *env)
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{
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raise_exception(env, 0x800, 0); |
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} |
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|
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void helper_raise_slot_fpu_disable(CPUSH4State *env)
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{
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raise_exception(env, 0x820, 0); |
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} |
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|
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void helper_debug(CPUSH4State *env)
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{
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raise_exception(env, EXCP_DEBUG, 0);
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} |
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|
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void helper_sleep(CPUSH4State *env)
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{
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CPUState *cs = CPU(sh_env_get_cpu(env)); |
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cs->halted = 1;
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env->in_sleep = 1;
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raise_exception(env, EXCP_HLT, 0);
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} |
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void helper_trapa(CPUSH4State *env, uint32_t tra)
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{
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env->tra = tra << 2;
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raise_exception(env, 0x160, 0); |
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} |
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void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
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{
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if (cpu_sh4_is_cached (env, address))
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{
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memory_content *r = malloc (sizeof(memory_content));
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r->address = address; |
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r->value = value; |
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r->next = NULL;
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*(env->movcal_backup_tail) = r; |
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env->movcal_backup_tail = &(r->next); |
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} |
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} |
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void helper_discard_movcal_backup(CPUSH4State *env)
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{
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memory_content *current = env->movcal_backup; |
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while(current)
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{
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memory_content *next = current->next; |
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free (current); |
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env->movcal_backup = current = next; |
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if (current == NULL) |
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env->movcal_backup_tail = &(env->movcal_backup); |
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} |
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} |
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void helper_ocbi(CPUSH4State *env, uint32_t address)
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{
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memory_content **current = &(env->movcal_backup); |
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while (*current)
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{
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uint32_t a = (*current)->address; |
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if ((a & ~0x1F) == (address & ~0x1F)) |
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{
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memory_content *next = (*current)->next; |
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cpu_stl_data(env, a, (*current)->value); |
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if (next == NULL) |
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{
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env->movcal_backup_tail = current; |
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} |
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free (*current); |
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*current = next; |
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break;
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} |
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} |
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} |
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#define T (env->sr & SR_T)
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#define Q (env->sr & SR_Q ? 1 : 0) |
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#define M (env->sr & SR_M ? 1 : 0) |
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#define SETT env->sr |= SR_T
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#define CLRT env->sr &= ~SR_T
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#define SETQ env->sr |= SR_Q
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#define CLRQ env->sr &= ~SR_Q
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#define SETM env->sr |= SR_M
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#define CLRM env->sr &= ~SR_M
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uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1) |
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{
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uint32_t tmp0, tmp2; |
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uint8_t old_q, tmp1 = 0xff;
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//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
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old_q = Q; |
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if ((0x80000000 & arg1) != 0) |
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SETQ; |
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else
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CLRQ; |
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tmp2 = arg0; |
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arg1 <<= 1;
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arg1 |= T; |
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switch (old_q) {
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case 0: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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case 1: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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} |
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if (Q == M)
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SETT; |
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else
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CLRT; |
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//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
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return arg1;
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} |
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void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
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{
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < 0) |
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env->mach |= 0xffff0000;
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else
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env->mach &= 0x00007fff;
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} |
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} |
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|
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void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
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{
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < -0x80000000) { |
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env->mach = 1;
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env->macl = 0x80000000;
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} else if (res > 0x000000007fffffff) { |
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env->mach = 1;
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env->macl = 0x7fffffff;
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} |
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} |
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} |
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|
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static inline void set_t(CPUSH4State *env) |
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{
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env->sr |= SR_T; |
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} |
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|
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static inline void clr_t(CPUSH4State *env) |
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{
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env->sr &= ~SR_T; |
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} |
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|
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void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
|
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{
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env->fpscr = val & FPSCR_MASK; |
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if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
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set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
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} else {
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
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} |
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set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
|
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} |
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|
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static void update_fpscr(CPUSH4State *env, uintptr_t retaddr) |
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{
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int xcpt, cause, enable;
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|
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xcpt = get_float_exception_flags(&env->fp_status); |
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|
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/* Clear the flag entries */
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env->fpscr &= ~FPSCR_FLAG_MASK; |
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|
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if (unlikely(xcpt)) {
|
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if (xcpt & float_flag_invalid) {
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env->fpscr |= FPSCR_FLAG_V; |
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} |
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if (xcpt & float_flag_divbyzero) {
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env->fpscr |= FPSCR_FLAG_Z; |
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} |
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if (xcpt & float_flag_overflow) {
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env->fpscr |= FPSCR_FLAG_O; |
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} |
| 362 |
if (xcpt & float_flag_underflow) {
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env->fpscr |= FPSCR_FLAG_U; |
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} |
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if (xcpt & float_flag_inexact) {
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env->fpscr |= FPSCR_FLAG_I; |
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} |
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|
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/* Accumulate in cause entries */
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env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK) |
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<< (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); |
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|
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/* Generate an exception if enabled */
|
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cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; |
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enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; |
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if (cause & enable) {
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raise_exception(env, 0x120, retaddr);
|
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} |
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} |
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} |
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|
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float32 helper_fabs_FT(float32 t0) |
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{
|
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return float32_abs(t0);
|
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} |
| 386 |
|
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float64 helper_fabs_DT(float64 t0) |
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{
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return float64_abs(t0);
|
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} |
| 391 |
|
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float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) |
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{
|
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set_float_exception_flags(0, &env->fp_status);
|
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t0 = float32_add(t0, t1, &env->fp_status); |
| 396 |
update_fpscr(env, GETPC()); |
| 397 |
return t0;
|
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} |
| 399 |
|
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float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 401 |
{
|
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set_float_exception_flags(0, &env->fp_status);
|
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t0 = float64_add(t0, t1, &env->fp_status); |
| 404 |
update_fpscr(env, GETPC()); |
| 405 |
return t0;
|
| 406 |
} |
| 407 |
|
| 408 |
void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
|
| 409 |
{
|
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int relation;
|
| 411 |
|
| 412 |
set_float_exception_flags(0, &env->fp_status);
|
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relation = float32_compare(t0, t1, &env->fp_status); |
| 414 |
if (unlikely(relation == float_relation_unordered)) {
|
| 415 |
update_fpscr(env, GETPC()); |
| 416 |
} else if (relation == float_relation_equal) { |
| 417 |
set_t(env); |
| 418 |
} else {
|
| 419 |
clr_t(env); |
| 420 |
} |
| 421 |
} |
| 422 |
|
| 423 |
void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
|
| 424 |
{
|
| 425 |
int relation;
|
| 426 |
|
| 427 |
set_float_exception_flags(0, &env->fp_status);
|
| 428 |
relation = float64_compare(t0, t1, &env->fp_status); |
| 429 |
if (unlikely(relation == float_relation_unordered)) {
|
| 430 |
update_fpscr(env, GETPC()); |
| 431 |
} else if (relation == float_relation_equal) { |
| 432 |
set_t(env); |
| 433 |
} else {
|
| 434 |
clr_t(env); |
| 435 |
} |
| 436 |
} |
| 437 |
|
| 438 |
void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
|
| 439 |
{
|
| 440 |
int relation;
|
| 441 |
|
| 442 |
set_float_exception_flags(0, &env->fp_status);
|
| 443 |
relation = float32_compare(t0, t1, &env->fp_status); |
| 444 |
if (unlikely(relation == float_relation_unordered)) {
|
| 445 |
update_fpscr(env, GETPC()); |
| 446 |
} else if (relation == float_relation_greater) { |
| 447 |
set_t(env); |
| 448 |
} else {
|
| 449 |
clr_t(env); |
| 450 |
} |
| 451 |
} |
| 452 |
|
| 453 |
void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
|
| 454 |
{
|
| 455 |
int relation;
|
| 456 |
|
| 457 |
set_float_exception_flags(0, &env->fp_status);
|
| 458 |
relation = float64_compare(t0, t1, &env->fp_status); |
| 459 |
if (unlikely(relation == float_relation_unordered)) {
|
| 460 |
update_fpscr(env, GETPC()); |
| 461 |
} else if (relation == float_relation_greater) { |
| 462 |
set_t(env); |
| 463 |
} else {
|
| 464 |
clr_t(env); |
| 465 |
} |
| 466 |
} |
| 467 |
|
| 468 |
float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) |
| 469 |
{
|
| 470 |
float64 ret; |
| 471 |
set_float_exception_flags(0, &env->fp_status);
|
| 472 |
ret = float32_to_float64(t0, &env->fp_status); |
| 473 |
update_fpscr(env, GETPC()); |
| 474 |
return ret;
|
| 475 |
} |
| 476 |
|
| 477 |
float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0) |
| 478 |
{
|
| 479 |
float32 ret; |
| 480 |
set_float_exception_flags(0, &env->fp_status);
|
| 481 |
ret = float64_to_float32(t0, &env->fp_status); |
| 482 |
update_fpscr(env, GETPC()); |
| 483 |
return ret;
|
| 484 |
} |
| 485 |
|
| 486 |
float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 487 |
{
|
| 488 |
set_float_exception_flags(0, &env->fp_status);
|
| 489 |
t0 = float32_div(t0, t1, &env->fp_status); |
| 490 |
update_fpscr(env, GETPC()); |
| 491 |
return t0;
|
| 492 |
} |
| 493 |
|
| 494 |
float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 495 |
{
|
| 496 |
set_float_exception_flags(0, &env->fp_status);
|
| 497 |
t0 = float64_div(t0, t1, &env->fp_status); |
| 498 |
update_fpscr(env, GETPC()); |
| 499 |
return t0;
|
| 500 |
} |
| 501 |
|
| 502 |
float32 helper_float_FT(CPUSH4State *env, uint32_t t0) |
| 503 |
{
|
| 504 |
float32 ret; |
| 505 |
set_float_exception_flags(0, &env->fp_status);
|
| 506 |
ret = int32_to_float32(t0, &env->fp_status); |
| 507 |
update_fpscr(env, GETPC()); |
| 508 |
return ret;
|
| 509 |
} |
| 510 |
|
| 511 |
float64 helper_float_DT(CPUSH4State *env, uint32_t t0) |
| 512 |
{
|
| 513 |
float64 ret; |
| 514 |
set_float_exception_flags(0, &env->fp_status);
|
| 515 |
ret = int32_to_float64(t0, &env->fp_status); |
| 516 |
update_fpscr(env, GETPC()); |
| 517 |
return ret;
|
| 518 |
} |
| 519 |
|
| 520 |
float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2) |
| 521 |
{
|
| 522 |
set_float_exception_flags(0, &env->fp_status);
|
| 523 |
t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
|
| 524 |
update_fpscr(env, GETPC()); |
| 525 |
return t0;
|
| 526 |
} |
| 527 |
|
| 528 |
float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 529 |
{
|
| 530 |
set_float_exception_flags(0, &env->fp_status);
|
| 531 |
t0 = float32_mul(t0, t1, &env->fp_status); |
| 532 |
update_fpscr(env, GETPC()); |
| 533 |
return t0;
|
| 534 |
} |
| 535 |
|
| 536 |
float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 537 |
{
|
| 538 |
set_float_exception_flags(0, &env->fp_status);
|
| 539 |
t0 = float64_mul(t0, t1, &env->fp_status); |
| 540 |
update_fpscr(env, GETPC()); |
| 541 |
return t0;
|
| 542 |
} |
| 543 |
|
| 544 |
float32 helper_fneg_T(float32 t0) |
| 545 |
{
|
| 546 |
return float32_chs(t0);
|
| 547 |
} |
| 548 |
|
| 549 |
float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0) |
| 550 |
{
|
| 551 |
set_float_exception_flags(0, &env->fp_status);
|
| 552 |
t0 = float32_sqrt(t0, &env->fp_status); |
| 553 |
update_fpscr(env, GETPC()); |
| 554 |
return t0;
|
| 555 |
} |
| 556 |
|
| 557 |
float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0) |
| 558 |
{
|
| 559 |
set_float_exception_flags(0, &env->fp_status);
|
| 560 |
t0 = float64_sqrt(t0, &env->fp_status); |
| 561 |
update_fpscr(env, GETPC()); |
| 562 |
return t0;
|
| 563 |
} |
| 564 |
|
| 565 |
float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1) |
| 566 |
{
|
| 567 |
set_float_exception_flags(0, &env->fp_status);
|
| 568 |
t0 = float32_sub(t0, t1, &env->fp_status); |
| 569 |
update_fpscr(env, GETPC()); |
| 570 |
return t0;
|
| 571 |
} |
| 572 |
|
| 573 |
float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1) |
| 574 |
{
|
| 575 |
set_float_exception_flags(0, &env->fp_status);
|
| 576 |
t0 = float64_sub(t0, t1, &env->fp_status); |
| 577 |
update_fpscr(env, GETPC()); |
| 578 |
return t0;
|
| 579 |
} |
| 580 |
|
| 581 |
uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0) |
| 582 |
{
|
| 583 |
uint32_t ret; |
| 584 |
set_float_exception_flags(0, &env->fp_status);
|
| 585 |
ret = float32_to_int32_round_to_zero(t0, &env->fp_status); |
| 586 |
update_fpscr(env, GETPC()); |
| 587 |
return ret;
|
| 588 |
} |
| 589 |
|
| 590 |
uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0) |
| 591 |
{
|
| 592 |
uint32_t ret; |
| 593 |
set_float_exception_flags(0, &env->fp_status);
|
| 594 |
ret = float64_to_int32_round_to_zero(t0, &env->fp_status); |
| 595 |
update_fpscr(env, GETPC()); |
| 596 |
return ret;
|
| 597 |
} |
| 598 |
|
| 599 |
void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
|
| 600 |
{
|
| 601 |
int bank, i;
|
| 602 |
float32 r, p; |
| 603 |
|
| 604 |
bank = (env->sr & FPSCR_FR) ? 16 : 0; |
| 605 |
r = float32_zero; |
| 606 |
set_float_exception_flags(0, &env->fp_status);
|
| 607 |
|
| 608 |
for (i = 0 ; i < 4 ; i++) { |
| 609 |
p = float32_mul(env->fregs[bank + m + i], |
| 610 |
env->fregs[bank + n + i], |
| 611 |
&env->fp_status); |
| 612 |
r = float32_add(r, p, &env->fp_status); |
| 613 |
} |
| 614 |
update_fpscr(env, GETPC()); |
| 615 |
|
| 616 |
env->fregs[bank + n + 3] = r;
|
| 617 |
} |
| 618 |
|
| 619 |
void helper_ftrv(CPUSH4State *env, uint32_t n)
|
| 620 |
{
|
| 621 |
int bank_matrix, bank_vector;
|
| 622 |
int i, j;
|
| 623 |
float32 r[4];
|
| 624 |
float32 p; |
| 625 |
|
| 626 |
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; |
| 627 |
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0; |
| 628 |
set_float_exception_flags(0, &env->fp_status);
|
| 629 |
for (i = 0 ; i < 4 ; i++) { |
| 630 |
r[i] = float32_zero; |
| 631 |
for (j = 0 ; j < 4 ; j++) { |
| 632 |
p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
|
| 633 |
env->fregs[bank_vector + j], |
| 634 |
&env->fp_status); |
| 635 |
r[i] = float32_add(r[i], p, &env->fp_status); |
| 636 |
} |
| 637 |
} |
| 638 |
update_fpscr(env, GETPC()); |
| 639 |
|
| 640 |
for (i = 0 ; i < 4 ; i++) { |
| 641 |
env->fregs[bank_vector + i] = r[i]; |
| 642 |
} |
| 643 |
} |