root / hw / pxa2xx_dma.c @ a8b7063b
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 DMA controller.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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7 | c1713132 | balrog | *
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8 | c1713132 | balrog | * This code is licenced under the GPL.
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9 | c1713132 | balrog | */
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10 | c1713132 | balrog | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | c1713132 | balrog | |
14 | bc24a225 | Paul Brook | typedef struct { |
15 | c1713132 | balrog | target_phys_addr_t descr; |
16 | c1713132 | balrog | target_phys_addr_t src; |
17 | c1713132 | balrog | target_phys_addr_t dest; |
18 | c1713132 | balrog | uint32_t cmd; |
19 | c1713132 | balrog | uint32_t state; |
20 | c1713132 | balrog | int request;
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21 | bc24a225 | Paul Brook | } PXA2xxDMAChannel; |
22 | c1713132 | balrog | |
23 | c1713132 | balrog | /* Allow the DMA to be used as a PIC. */
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24 | c1713132 | balrog | typedef void (*pxa2xx_dma_handler_t)(void *opaque, int irq, int level); |
25 | c1713132 | balrog | |
26 | bc24a225 | Paul Brook | struct PXA2xxDMAState {
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27 | c1713132 | balrog | pxa2xx_dma_handler_t handler; |
28 | c1713132 | balrog | qemu_irq irq; |
29 | c1713132 | balrog | |
30 | c1713132 | balrog | uint32_t stopintr; |
31 | c1713132 | balrog | uint32_t eorintr; |
32 | c1713132 | balrog | uint32_t rasintr; |
33 | c1713132 | balrog | uint32_t startintr; |
34 | c1713132 | balrog | uint32_t endintr; |
35 | c1713132 | balrog | |
36 | c1713132 | balrog | uint32_t align; |
37 | c1713132 | balrog | uint32_t pio; |
38 | c1713132 | balrog | |
39 | c1713132 | balrog | int channels;
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40 | bc24a225 | Paul Brook | PXA2xxDMAChannel *chan; |
41 | c1713132 | balrog | |
42 | c1713132 | balrog | uint8_t *req; |
43 | c1713132 | balrog | |
44 | c1713132 | balrog | /* Flag to avoid recursive DMA invocations. */
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45 | c1713132 | balrog | int running;
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46 | c1713132 | balrog | }; |
47 | c1713132 | balrog | |
48 | c1713132 | balrog | #define PXA255_DMA_NUM_CHANNELS 16 |
49 | c1713132 | balrog | #define PXA27X_DMA_NUM_CHANNELS 32 |
50 | c1713132 | balrog | |
51 | c1713132 | balrog | #define PXA2XX_DMA_NUM_REQUESTS 75 |
52 | c1713132 | balrog | |
53 | c1713132 | balrog | #define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ |
54 | c1713132 | balrog | #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ |
55 | c1713132 | balrog | #define DALGN 0x00a0 /* DMA Alignment register */ |
56 | c1713132 | balrog | #define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ |
57 | c1713132 | balrog | #define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ |
58 | c1713132 | balrog | #define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ |
59 | c1713132 | balrog | #define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ |
60 | c1713132 | balrog | #define DINT 0x00f0 /* DMA Interrupt register */ |
61 | c1713132 | balrog | #define DRCMR0 0x0100 /* Request to Channel Map register 0 */ |
62 | c1713132 | balrog | #define DRCMR63 0x01fc /* Request to Channel Map register 63 */ |
63 | c1713132 | balrog | #define D_CH0 0x0200 /* Channel 0 Descriptor start */ |
64 | c1713132 | balrog | #define DRCMR64 0x1100 /* Request to Channel Map register 64 */ |
65 | c1713132 | balrog | #define DRCMR74 0x1128 /* Request to Channel Map register 74 */ |
66 | c1713132 | balrog | |
67 | c1713132 | balrog | /* Per-channel register */
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68 | c1713132 | balrog | #define DDADR 0x00 |
69 | c1713132 | balrog | #define DSADR 0x01 |
70 | c1713132 | balrog | #define DTADR 0x02 |
71 | c1713132 | balrog | #define DCMD 0x03 |
72 | c1713132 | balrog | |
73 | c1713132 | balrog | /* Bit-field masks */
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74 | c1713132 | balrog | #define DRCMR_CHLNUM 0x1f |
75 | c1713132 | balrog | #define DRCMR_MAPVLD (1 << 7) |
76 | c1713132 | balrog | #define DDADR_STOP (1 << 0) |
77 | c1713132 | balrog | #define DDADR_BREN (1 << 1) |
78 | c1713132 | balrog | #define DCMD_LEN 0x1fff |
79 | c1713132 | balrog | #define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) |
80 | c1713132 | balrog | #define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) |
81 | c1713132 | balrog | #define DCMD_FLYBYT (1 << 19) |
82 | c1713132 | balrog | #define DCMD_FLYBYS (1 << 20) |
83 | c1713132 | balrog | #define DCMD_ENDIRQEN (1 << 21) |
84 | c1713132 | balrog | #define DCMD_STARTIRQEN (1 << 22) |
85 | c1713132 | balrog | #define DCMD_CMPEN (1 << 25) |
86 | c1713132 | balrog | #define DCMD_FLOWTRG (1 << 28) |
87 | c1713132 | balrog | #define DCMD_FLOWSRC (1 << 29) |
88 | c1713132 | balrog | #define DCMD_INCTRGADDR (1 << 30) |
89 | c1713132 | balrog | #define DCMD_INCSRCADDR (1 << 31) |
90 | c1713132 | balrog | #define DCSR_BUSERRINTR (1 << 0) |
91 | c1713132 | balrog | #define DCSR_STARTINTR (1 << 1) |
92 | c1713132 | balrog | #define DCSR_ENDINTR (1 << 2) |
93 | c1713132 | balrog | #define DCSR_STOPINTR (1 << 3) |
94 | c1713132 | balrog | #define DCSR_RASINTR (1 << 4) |
95 | c1713132 | balrog | #define DCSR_REQPEND (1 << 8) |
96 | c1713132 | balrog | #define DCSR_EORINT (1 << 9) |
97 | c1713132 | balrog | #define DCSR_CMPST (1 << 10) |
98 | c1713132 | balrog | #define DCSR_MASKRUN (1 << 22) |
99 | c1713132 | balrog | #define DCSR_RASIRQEN (1 << 23) |
100 | c1713132 | balrog | #define DCSR_CLRCMPST (1 << 24) |
101 | c1713132 | balrog | #define DCSR_SETCMPST (1 << 25) |
102 | c1713132 | balrog | #define DCSR_EORSTOPEN (1 << 26) |
103 | c1713132 | balrog | #define DCSR_EORJMPEN (1 << 27) |
104 | c1713132 | balrog | #define DCSR_EORIRQEN (1 << 28) |
105 | c1713132 | balrog | #define DCSR_STOPIRQEN (1 << 29) |
106 | c1713132 | balrog | #define DCSR_NODESCFETCH (1 << 30) |
107 | c1713132 | balrog | #define DCSR_RUN (1 << 31) |
108 | c1713132 | balrog | |
109 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch) |
110 | c1713132 | balrog | { |
111 | c1713132 | balrog | if (ch >= 0) { |
112 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
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113 | c1713132 | balrog | (s->chan[ch].state & DCSR_STOPINTR)) |
114 | c1713132 | balrog | s->stopintr |= 1 << ch;
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115 | c1713132 | balrog | else
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116 | c1713132 | balrog | s->stopintr &= ~(1 << ch);
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117 | c1713132 | balrog | |
118 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_EORIRQEN) &&
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119 | c1713132 | balrog | (s->chan[ch].state & DCSR_EORINT)) |
120 | c1713132 | balrog | s->eorintr |= 1 << ch;
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121 | c1713132 | balrog | else
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122 | c1713132 | balrog | s->eorintr &= ~(1 << ch);
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123 | c1713132 | balrog | |
124 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_RASIRQEN) &&
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125 | c1713132 | balrog | (s->chan[ch].state & DCSR_RASINTR)) |
126 | c1713132 | balrog | s->rasintr |= 1 << ch;
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127 | c1713132 | balrog | else
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128 | c1713132 | balrog | s->rasintr &= ~(1 << ch);
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129 | c1713132 | balrog | |
130 | c1713132 | balrog | if (s->chan[ch].state & DCSR_STARTINTR)
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131 | c1713132 | balrog | s->startintr |= 1 << ch;
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132 | c1713132 | balrog | else
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133 | c1713132 | balrog | s->startintr &= ~(1 << ch);
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134 | c1713132 | balrog | |
135 | c1713132 | balrog | if (s->chan[ch].state & DCSR_ENDINTR)
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136 | c1713132 | balrog | s->endintr |= 1 << ch;
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137 | c1713132 | balrog | else
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138 | c1713132 | balrog | s->endintr &= ~(1 << ch);
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139 | c1713132 | balrog | } |
140 | c1713132 | balrog | |
141 | c1713132 | balrog | if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
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142 | c1713132 | balrog | qemu_irq_raise(s->irq); |
143 | c1713132 | balrog | else
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144 | c1713132 | balrog | qemu_irq_lower(s->irq); |
145 | c1713132 | balrog | } |
146 | c1713132 | balrog | |
147 | c1713132 | balrog | static inline void pxa2xx_dma_descriptor_fetch( |
148 | bc24a225 | Paul Brook | PXA2xxDMAState *s, int ch)
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149 | c1713132 | balrog | { |
150 | c1713132 | balrog | uint32_t desc[4];
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151 | c1713132 | balrog | target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
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152 | c1713132 | balrog | if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
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153 | c1713132 | balrog | daddr += 32;
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154 | c1713132 | balrog | |
155 | c1713132 | balrog | cpu_physical_memory_read(daddr, (uint8_t *) desc, 16);
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156 | c1713132 | balrog | s->chan[ch].descr = desc[DDADR]; |
157 | c1713132 | balrog | s->chan[ch].src = desc[DSADR]; |
158 | c1713132 | balrog | s->chan[ch].dest = desc[DTADR]; |
159 | c1713132 | balrog | s->chan[ch].cmd = desc[DCMD]; |
160 | c1713132 | balrog | |
161 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_FLOWSRC)
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162 | c1713132 | balrog | s->chan[ch].src &= ~3;
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163 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_FLOWTRG)
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164 | c1713132 | balrog | s->chan[ch].dest &= ~3;
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165 | c1713132 | balrog | |
166 | c1713132 | balrog | if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
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167 | c1713132 | balrog | printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
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168 | c1713132 | balrog | |
169 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_STARTIRQEN)
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170 | c1713132 | balrog | s->chan[ch].state |= DCSR_STARTINTR; |
171 | c1713132 | balrog | } |
172 | c1713132 | balrog | |
173 | bc24a225 | Paul Brook | static void pxa2xx_dma_run(PXA2xxDMAState *s) |
174 | c1713132 | balrog | { |
175 | c1713132 | balrog | int c, srcinc, destinc;
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176 | c1713132 | balrog | uint32_t n, size; |
177 | c1713132 | balrog | uint32_t width; |
178 | c1713132 | balrog | uint32_t length; |
179 | b55266b5 | blueswir1 | uint8_t buffer[32];
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180 | bc24a225 | Paul Brook | PXA2xxDMAChannel *ch; |
181 | c1713132 | balrog | |
182 | c1713132 | balrog | if (s->running ++)
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183 | c1713132 | balrog | return;
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184 | c1713132 | balrog | |
185 | c1713132 | balrog | while (s->running) {
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186 | c1713132 | balrog | s->running = 1;
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187 | c1713132 | balrog | for (c = 0; c < s->channels; c ++) { |
188 | c1713132 | balrog | ch = &s->chan[c]; |
189 | c1713132 | balrog | |
190 | c1713132 | balrog | while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
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191 | c1713132 | balrog | /* Test for pending requests */
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192 | c1713132 | balrog | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
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193 | c1713132 | balrog | break;
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194 | c1713132 | balrog | |
195 | c1713132 | balrog | length = ch->cmd & DCMD_LEN; |
196 | c1713132 | balrog | size = DCMD_SIZE(ch->cmd); |
197 | c1713132 | balrog | width = DCMD_WIDTH(ch->cmd); |
198 | c1713132 | balrog | |
199 | c1713132 | balrog | srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
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200 | c1713132 | balrog | destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
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201 | c1713132 | balrog | |
202 | c1713132 | balrog | while (length) {
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203 | c1713132 | balrog | size = MIN(length, size); |
204 | c1713132 | balrog | |
205 | c1713132 | balrog | for (n = 0; n < size; n += width) { |
206 | c1713132 | balrog | cpu_physical_memory_read(ch->src, buffer + n, width); |
207 | c1713132 | balrog | ch->src += srcinc; |
208 | c1713132 | balrog | } |
209 | c1713132 | balrog | |
210 | c1713132 | balrog | for (n = 0; n < size; n += width) { |
211 | c1713132 | balrog | cpu_physical_memory_write(ch->dest, buffer + n, width); |
212 | c1713132 | balrog | ch->dest += destinc; |
213 | c1713132 | balrog | } |
214 | c1713132 | balrog | |
215 | c1713132 | balrog | length -= size; |
216 | c1713132 | balrog | |
217 | c1713132 | balrog | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
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218 | c1713132 | balrog | !ch->request) { |
219 | c1713132 | balrog | ch->state |= DCSR_EORINT; |
220 | c1713132 | balrog | if (ch->state & DCSR_EORSTOPEN)
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221 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
222 | c1713132 | balrog | if ((ch->state & DCSR_EORJMPEN) &&
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223 | c1713132 | balrog | !(ch->state & DCSR_NODESCFETCH)) |
224 | c1713132 | balrog | pxa2xx_dma_descriptor_fetch(s, c); |
225 | c1713132 | balrog | break;
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226 | c1713132 | balrog | } |
227 | c1713132 | balrog | } |
228 | c1713132 | balrog | |
229 | c1713132 | balrog | ch->cmd = (ch->cmd & ~DCMD_LEN) | length; |
230 | c1713132 | balrog | |
231 | c1713132 | balrog | /* Is the transfer complete now? */
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232 | c1713132 | balrog | if (!length) {
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233 | c1713132 | balrog | if (ch->cmd & DCMD_ENDIRQEN)
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234 | c1713132 | balrog | ch->state |= DCSR_ENDINTR; |
235 | c1713132 | balrog | |
236 | c1713132 | balrog | if ((ch->state & DCSR_NODESCFETCH) ||
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237 | c1713132 | balrog | (ch->descr & DDADR_STOP) || |
238 | c1713132 | balrog | (ch->state & DCSR_EORSTOPEN)) { |
239 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
240 | c1713132 | balrog | ch->state &= ~DCSR_RUN; |
241 | c1713132 | balrog | |
242 | c1713132 | balrog | break;
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243 | c1713132 | balrog | } |
244 | c1713132 | balrog | |
245 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
246 | c1713132 | balrog | break;
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247 | c1713132 | balrog | } |
248 | c1713132 | balrog | } |
249 | c1713132 | balrog | } |
250 | c1713132 | balrog | |
251 | c1713132 | balrog | s->running --; |
252 | c1713132 | balrog | } |
253 | c1713132 | balrog | } |
254 | c1713132 | balrog | |
255 | c1713132 | balrog | static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) |
256 | c1713132 | balrog | { |
257 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
258 | c1713132 | balrog | unsigned int channel; |
259 | c1713132 | balrog | |
260 | c1713132 | balrog | switch (offset) {
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261 | c1713132 | balrog | case DRCMR64 ... DRCMR74:
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262 | c1713132 | balrog | offset -= DRCMR64 - DRCMR0 - (64 << 2); |
263 | c1713132 | balrog | /* Fall through */
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264 | c1713132 | balrog | case DRCMR0 ... DRCMR63:
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265 | c1713132 | balrog | channel = (offset - DRCMR0) >> 2;
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266 | c1713132 | balrog | return s->req[channel];
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267 | c1713132 | balrog | |
268 | c1713132 | balrog | case DRQSR0:
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269 | c1713132 | balrog | case DRQSR1:
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270 | c1713132 | balrog | case DRQSR2:
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271 | c1713132 | balrog | return 0; |
272 | c1713132 | balrog | |
273 | c1713132 | balrog | case DCSR0 ... DCSR31:
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274 | c1713132 | balrog | channel = offset >> 2;
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275 | c1713132 | balrog | if (s->chan[channel].request)
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276 | c1713132 | balrog | return s->chan[channel].state | DCSR_REQPEND;
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277 | c1713132 | balrog | return s->chan[channel].state;
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278 | c1713132 | balrog | |
279 | c1713132 | balrog | case DINT:
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280 | c1713132 | balrog | return s->stopintr | s->eorintr | s->rasintr |
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281 | c1713132 | balrog | s->startintr | s->endintr; |
282 | c1713132 | balrog | |
283 | c1713132 | balrog | case DALGN:
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284 | c1713132 | balrog | return s->align;
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285 | c1713132 | balrog | |
286 | c1713132 | balrog | case DPCSR:
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287 | c1713132 | balrog | return s->pio;
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288 | c1713132 | balrog | } |
289 | c1713132 | balrog | |
290 | c1713132 | balrog | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
291 | c1713132 | balrog | channel = (offset - D_CH0) >> 4;
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292 | c1713132 | balrog | switch ((offset & 0x0f) >> 2) { |
293 | c1713132 | balrog | case DDADR:
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294 | c1713132 | balrog | return s->chan[channel].descr;
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295 | c1713132 | balrog | case DSADR:
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296 | c1713132 | balrog | return s->chan[channel].src;
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297 | c1713132 | balrog | case DTADR:
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298 | c1713132 | balrog | return s->chan[channel].dest;
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299 | c1713132 | balrog | case DCMD:
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300 | c1713132 | balrog | return s->chan[channel].cmd;
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301 | c1713132 | balrog | } |
302 | c1713132 | balrog | } |
303 | c1713132 | balrog | |
304 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset); |
305 | c1713132 | balrog | return 7; |
306 | c1713132 | balrog | } |
307 | c1713132 | balrog | |
308 | c1713132 | balrog | static void pxa2xx_dma_write(void *opaque, |
309 | c1713132 | balrog | target_phys_addr_t offset, uint32_t value) |
310 | c1713132 | balrog | { |
311 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
312 | c1713132 | balrog | unsigned int channel; |
313 | c1713132 | balrog | |
314 | c1713132 | balrog | switch (offset) {
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315 | c1713132 | balrog | case DRCMR64 ... DRCMR74:
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316 | c1713132 | balrog | offset -= DRCMR64 - DRCMR0 - (64 << 2); |
317 | c1713132 | balrog | /* Fall through */
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318 | c1713132 | balrog | case DRCMR0 ... DRCMR63:
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319 | c1713132 | balrog | channel = (offset - DRCMR0) >> 2;
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320 | c1713132 | balrog | |
321 | c1713132 | balrog | if (value & DRCMR_MAPVLD)
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322 | c1713132 | balrog | if ((value & DRCMR_CHLNUM) > s->channels)
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323 | 2ac71179 | Paul Brook | hw_error("%s: Bad DMA channel %i\n",
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324 | 2ac71179 | Paul Brook | __FUNCTION__, value & DRCMR_CHLNUM); |
325 | c1713132 | balrog | |
326 | c1713132 | balrog | s->req[channel] = value; |
327 | c1713132 | balrog | break;
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328 | c1713132 | balrog | |
329 | c1713132 | balrog | case DRQSR0:
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330 | c1713132 | balrog | case DRQSR1:
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331 | c1713132 | balrog | case DRQSR2:
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332 | c1713132 | balrog | /* Nothing to do */
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333 | c1713132 | balrog | break;
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334 | c1713132 | balrog | |
335 | c1713132 | balrog | case DCSR0 ... DCSR31:
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336 | c1713132 | balrog | channel = offset >> 2;
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337 | c1713132 | balrog | s->chan[channel].state &= 0x0000071f & ~(value &
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338 | c1713132 | balrog | (DCSR_EORINT | DCSR_ENDINTR | |
339 | c1713132 | balrog | DCSR_STARTINTR | DCSR_BUSERRINTR)); |
340 | c1713132 | balrog | s->chan[channel].state |= value & 0xfc800000;
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341 | c1713132 | balrog | |
342 | c1713132 | balrog | if (s->chan[channel].state & DCSR_STOPIRQEN)
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343 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
344 | c1713132 | balrog | |
345 | c1713132 | balrog | if (value & DCSR_NODESCFETCH) {
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346 | c1713132 | balrog | /* No-descriptor-fetch mode */
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347 | e1dad5a6 | balrog | if (value & DCSR_RUN) {
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348 | e1dad5a6 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
349 | c1713132 | balrog | pxa2xx_dma_run(s); |
350 | e1dad5a6 | balrog | } |
351 | c1713132 | balrog | } else {
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352 | c1713132 | balrog | /* Descriptor-fetch mode */
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353 | c1713132 | balrog | if (value & DCSR_RUN) {
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354 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
355 | c1713132 | balrog | pxa2xx_dma_descriptor_fetch(s, channel); |
356 | c1713132 | balrog | pxa2xx_dma_run(s); |
357 | c1713132 | balrog | } |
358 | c1713132 | balrog | } |
359 | c1713132 | balrog | |
360 | c1713132 | balrog | /* Shouldn't matter as our DMA is synchronous. */
|
361 | c1713132 | balrog | if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
|
362 | c1713132 | balrog | s->chan[channel].state |= DCSR_STOPINTR; |
363 | c1713132 | balrog | |
364 | c1713132 | balrog | if (value & DCSR_CLRCMPST)
|
365 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_CMPST; |
366 | c1713132 | balrog | if (value & DCSR_SETCMPST)
|
367 | c1713132 | balrog | s->chan[channel].state |= DCSR_CMPST; |
368 | c1713132 | balrog | |
369 | c1713132 | balrog | pxa2xx_dma_update(s, channel); |
370 | c1713132 | balrog | break;
|
371 | c1713132 | balrog | |
372 | c1713132 | balrog | case DALGN:
|
373 | c1713132 | balrog | s->align = value; |
374 | c1713132 | balrog | break;
|
375 | c1713132 | balrog | |
376 | c1713132 | balrog | case DPCSR:
|
377 | c1713132 | balrog | s->pio = value & 0x80000001;
|
378 | c1713132 | balrog | break;
|
379 | c1713132 | balrog | |
380 | c1713132 | balrog | default:
|
381 | c1713132 | balrog | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
382 | c1713132 | balrog | channel = (offset - D_CH0) >> 4;
|
383 | c1713132 | balrog | switch ((offset & 0x0f) >> 2) { |
384 | c1713132 | balrog | case DDADR:
|
385 | c1713132 | balrog | s->chan[channel].descr = value; |
386 | c1713132 | balrog | break;
|
387 | c1713132 | balrog | case DSADR:
|
388 | c1713132 | balrog | s->chan[channel].src = value; |
389 | c1713132 | balrog | break;
|
390 | c1713132 | balrog | case DTADR:
|
391 | c1713132 | balrog | s->chan[channel].dest = value; |
392 | c1713132 | balrog | break;
|
393 | c1713132 | balrog | case DCMD:
|
394 | c1713132 | balrog | s->chan[channel].cmd = value; |
395 | c1713132 | balrog | break;
|
396 | c1713132 | balrog | default:
|
397 | c1713132 | balrog | goto fail;
|
398 | c1713132 | balrog | } |
399 | c1713132 | balrog | |
400 | c1713132 | balrog | break;
|
401 | c1713132 | balrog | } |
402 | c1713132 | balrog | fail:
|
403 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset); |
404 | c1713132 | balrog | } |
405 | c1713132 | balrog | } |
406 | c1713132 | balrog | |
407 | c1713132 | balrog | static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset) |
408 | c1713132 | balrog | { |
409 | 2ac71179 | Paul Brook | hw_error("%s: Bad access width\n", __FUNCTION__);
|
410 | c1713132 | balrog | return 5; |
411 | c1713132 | balrog | } |
412 | c1713132 | balrog | |
413 | c1713132 | balrog | static void pxa2xx_dma_writebad(void *opaque, |
414 | c1713132 | balrog | target_phys_addr_t offset, uint32_t value) |
415 | c1713132 | balrog | { |
416 | 2ac71179 | Paul Brook | hw_error("%s: Bad access width\n", __FUNCTION__);
|
417 | c1713132 | balrog | } |
418 | c1713132 | balrog | |
419 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = {
|
420 | c1713132 | balrog | pxa2xx_dma_readbad, |
421 | c1713132 | balrog | pxa2xx_dma_readbad, |
422 | c1713132 | balrog | pxa2xx_dma_read |
423 | c1713132 | balrog | }; |
424 | c1713132 | balrog | |
425 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_dma_writefn[] = {
|
426 | c1713132 | balrog | pxa2xx_dma_writebad, |
427 | c1713132 | balrog | pxa2xx_dma_writebad, |
428 | c1713132 | balrog | pxa2xx_dma_write |
429 | c1713132 | balrog | }; |
430 | c1713132 | balrog | |
431 | aa941b94 | balrog | static void pxa2xx_dma_save(QEMUFile *f, void *opaque) |
432 | aa941b94 | balrog | { |
433 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
434 | aa941b94 | balrog | int i;
|
435 | aa941b94 | balrog | |
436 | aa941b94 | balrog | qemu_put_be32(f, s->channels); |
437 | aa941b94 | balrog | |
438 | aa941b94 | balrog | qemu_put_be32s(f, &s->stopintr); |
439 | aa941b94 | balrog | qemu_put_be32s(f, &s->eorintr); |
440 | aa941b94 | balrog | qemu_put_be32s(f, &s->rasintr); |
441 | aa941b94 | balrog | qemu_put_be32s(f, &s->startintr); |
442 | aa941b94 | balrog | qemu_put_be32s(f, &s->endintr); |
443 | aa941b94 | balrog | qemu_put_be32s(f, &s->align); |
444 | aa941b94 | balrog | qemu_put_be32s(f, &s->pio); |
445 | aa941b94 | balrog | |
446 | aa941b94 | balrog | qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
447 | aa941b94 | balrog | for (i = 0; i < s->channels; i ++) { |
448 | aa941b94 | balrog | qemu_put_betl(f, s->chan[i].descr); |
449 | aa941b94 | balrog | qemu_put_betl(f, s->chan[i].src); |
450 | aa941b94 | balrog | qemu_put_betl(f, s->chan[i].dest); |
451 | aa941b94 | balrog | qemu_put_be32s(f, &s->chan[i].cmd); |
452 | aa941b94 | balrog | qemu_put_be32s(f, &s->chan[i].state); |
453 | aa941b94 | balrog | qemu_put_be32(f, s->chan[i].request); |
454 | aa941b94 | balrog | }; |
455 | aa941b94 | balrog | } |
456 | aa941b94 | balrog | |
457 | aa941b94 | balrog | static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) |
458 | aa941b94 | balrog | { |
459 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
460 | aa941b94 | balrog | int i;
|
461 | aa941b94 | balrog | |
462 | aa941b94 | balrog | if (qemu_get_be32(f) != s->channels)
|
463 | aa941b94 | balrog | return -EINVAL;
|
464 | aa941b94 | balrog | |
465 | aa941b94 | balrog | qemu_get_be32s(f, &s->stopintr); |
466 | aa941b94 | balrog | qemu_get_be32s(f, &s->eorintr); |
467 | aa941b94 | balrog | qemu_get_be32s(f, &s->rasintr); |
468 | aa941b94 | balrog | qemu_get_be32s(f, &s->startintr); |
469 | aa941b94 | balrog | qemu_get_be32s(f, &s->endintr); |
470 | aa941b94 | balrog | qemu_get_be32s(f, &s->align); |
471 | aa941b94 | balrog | qemu_get_be32s(f, &s->pio); |
472 | aa941b94 | balrog | |
473 | aa941b94 | balrog | qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
474 | aa941b94 | balrog | for (i = 0; i < s->channels; i ++) { |
475 | aa941b94 | balrog | s->chan[i].descr = qemu_get_betl(f); |
476 | aa941b94 | balrog | s->chan[i].src = qemu_get_betl(f); |
477 | aa941b94 | balrog | s->chan[i].dest = qemu_get_betl(f); |
478 | aa941b94 | balrog | qemu_get_be32s(f, &s->chan[i].cmd); |
479 | aa941b94 | balrog | qemu_get_be32s(f, &s->chan[i].state); |
480 | aa941b94 | balrog | s->chan[i].request = qemu_get_be32(f); |
481 | aa941b94 | balrog | }; |
482 | aa941b94 | balrog | |
483 | aa941b94 | balrog | return 0; |
484 | aa941b94 | balrog | } |
485 | aa941b94 | balrog | |
486 | bc24a225 | Paul Brook | static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
|
487 | c1713132 | balrog | qemu_irq irq, int channels)
|
488 | c1713132 | balrog | { |
489 | c1713132 | balrog | int i, iomemtype;
|
490 | bc24a225 | Paul Brook | PXA2xxDMAState *s; |
491 | bc24a225 | Paul Brook | s = (PXA2xxDMAState *) |
492 | bc24a225 | Paul Brook | qemu_mallocz(sizeof(PXA2xxDMAState));
|
493 | c1713132 | balrog | |
494 | c1713132 | balrog | s->channels = channels; |
495 | bc24a225 | Paul Brook | s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels);
|
496 | c1713132 | balrog | s->irq = irq; |
497 | c1713132 | balrog | s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request; |
498 | 3f582262 | balrog | s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
|
499 | c1713132 | balrog | |
500 | bc24a225 | Paul Brook | memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels); |
501 | c1713132 | balrog | for (i = 0; i < s->channels; i ++) |
502 | c1713132 | balrog | s->chan[i].state = DCSR_STOPINTR; |
503 | c1713132 | balrog | |
504 | 3f582262 | balrog | memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
505 | c1713132 | balrog | |
506 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn,
|
507 | 3f582262 | balrog | pxa2xx_dma_writefn, s); |
508 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00010000, iomemtype);
|
509 | c1713132 | balrog | |
510 | aa941b94 | balrog | register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); |
511 | aa941b94 | balrog | |
512 | c1713132 | balrog | return s;
|
513 | c1713132 | balrog | } |
514 | c1713132 | balrog | |
515 | bc24a225 | Paul Brook | PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
516 | c1713132 | balrog | qemu_irq irq) |
517 | c1713132 | balrog | { |
518 | c1713132 | balrog | return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS);
|
519 | c1713132 | balrog | } |
520 | c1713132 | balrog | |
521 | bc24a225 | Paul Brook | PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
522 | c1713132 | balrog | qemu_irq irq) |
523 | c1713132 | balrog | { |
524 | c1713132 | balrog | return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS);
|
525 | c1713132 | balrog | } |
526 | c1713132 | balrog | |
527 | bc24a225 | Paul Brook | void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on) |
528 | c1713132 | balrog | { |
529 | c1713132 | balrog | int ch;
|
530 | c1713132 | balrog | if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) |
531 | 2ac71179 | Paul Brook | hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
|
532 | c1713132 | balrog | |
533 | c1713132 | balrog | if (!(s->req[req_num] & DRCMR_MAPVLD))
|
534 | c1713132 | balrog | return;
|
535 | c1713132 | balrog | ch = s->req[req_num] & DRCMR_CHLNUM; |
536 | c1713132 | balrog | |
537 | c1713132 | balrog | if (!s->chan[ch].request && on)
|
538 | c1713132 | balrog | s->chan[ch].state |= DCSR_RASINTR; |
539 | c1713132 | balrog | else
|
540 | c1713132 | balrog | s->chan[ch].state &= ~DCSR_RASINTR; |
541 | c1713132 | balrog | if (s->chan[ch].request && !on)
|
542 | c1713132 | balrog | s->chan[ch].state |= DCSR_EORINT; |
543 | c1713132 | balrog | |
544 | c1713132 | balrog | s->chan[ch].request = on; |
545 | c1713132 | balrog | if (on) {
|
546 | c1713132 | balrog | pxa2xx_dma_run(s); |
547 | c1713132 | balrog | pxa2xx_dma_update(s, ch); |
548 | c1713132 | balrog | } |
549 | c1713132 | balrog | } |