root / hw / ppc_prep.c @ a8c490cd
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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | a541f297 | bellard | *
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4 | a541f297 | bellard | * Copyright (c) 2003-2004 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 9a64fbe4 | bellard | #include "vl.h" |
25 | a541f297 | bellard | #include "m48t59.h" |
26 | 9a64fbe4 | bellard | |
27 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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28 | a541f297 | bellard | //#define DEBUG_PPC_IO
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29 | 9a64fbe4 | bellard | |
30 | 9a64fbe4 | bellard | extern int loglevel; |
31 | 9a64fbe4 | bellard | extern FILE *logfile;
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32 | 9a64fbe4 | bellard | |
33 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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34 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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35 | 9a64fbe4 | bellard | #endif
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36 | 9a64fbe4 | bellard | |
37 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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38 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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39 | 9a64fbe4 | bellard | do { \
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40 | 9a64fbe4 | bellard | if (loglevel > 0) { \ |
41 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
42 | 9a64fbe4 | bellard | } else { \
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43 | 9a64fbe4 | bellard | printf("%s : " fmt, __func__ , ##args); \ |
44 | 9a64fbe4 | bellard | } \ |
45 | 9a64fbe4 | bellard | } while (0) |
46 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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47 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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48 | 9a64fbe4 | bellard | do { \
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49 | 9a64fbe4 | bellard | if (loglevel > 0) { \ |
50 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
51 | 9a64fbe4 | bellard | } \ |
52 | 9a64fbe4 | bellard | } while (0) |
53 | 9a64fbe4 | bellard | #else
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54 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
55 | 9a64fbe4 | bellard | #endif
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56 | 9a64fbe4 | bellard | |
57 | a541f297 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
58 | a541f297 | bellard | |
59 | a541f297 | bellard | #define KERNEL_LOAD_ADDR 0x00000000 |
60 | a541f297 | bellard | #define KERNEL_STACK_ADDR 0x00400000 |
61 | a541f297 | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
62 | a541f297 | bellard | |
63 | a541f297 | bellard | int load_kernel(const char *filename, uint8_t *addr, |
64 | a541f297 | bellard | uint8_t *real_addr) |
65 | a541f297 | bellard | { |
66 | a541f297 | bellard | int fd, size;
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67 | a541f297 | bellard | int setup_sects;
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68 | a541f297 | bellard | |
69 | a541f297 | bellard | fd = open(filename, O_RDONLY); |
70 | a541f297 | bellard | if (fd < 0) |
71 | a541f297 | bellard | return -1; |
72 | a541f297 | bellard | |
73 | a541f297 | bellard | /* load 16 bit code */
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74 | a541f297 | bellard | if (read(fd, real_addr, 512) != 512) |
75 | a541f297 | bellard | goto fail;
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76 | a541f297 | bellard | setup_sects = real_addr[0x1F1];
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77 | a541f297 | bellard | if (!setup_sects)
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78 | a541f297 | bellard | setup_sects = 4;
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79 | a541f297 | bellard | if (read(fd, real_addr + 512, setup_sects * 512) != |
80 | a541f297 | bellard | setup_sects * 512)
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81 | a541f297 | bellard | goto fail;
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82 | a541f297 | bellard | |
83 | a541f297 | bellard | /* load 32 bit code */
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84 | a541f297 | bellard | size = read(fd, addr, 16 * 1024 * 1024); |
85 | a541f297 | bellard | if (size < 0) |
86 | a541f297 | bellard | goto fail;
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87 | a541f297 | bellard | close(fd); |
88 | a541f297 | bellard | return size;
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89 | a541f297 | bellard | fail:
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90 | a541f297 | bellard | close(fd); |
91 | a541f297 | bellard | return -1; |
92 | a541f297 | bellard | } |
93 | a541f297 | bellard | |
94 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
95 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
96 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
97 | a541f297 | bellard | |
98 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
99 | a541f297 | bellard | |
100 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
101 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
102 | 9a64fbe4 | bellard | |
103 | 9a64fbe4 | bellard | /* IO ports emulation */
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104 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
105 | 9a64fbe4 | bellard | |
106 | 2e12669a | bellard | static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value) |
107 | 9a64fbe4 | bellard | { |
108 | 9a64fbe4 | bellard | /* Don't polute serial port output */
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109 | a541f297 | bellard | #if 0
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110 | 9a64fbe4 | bellard | if ((addr < 0x800003F0 || addr > 0x80000400) &&
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111 | 9a64fbe4 | bellard | (addr < 0x80000074 || addr > 0x80000077) &&
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112 | 9a64fbe4 | bellard | (addr < 0x80000020 || addr > 0x80000021) &&
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113 | 9a64fbe4 | bellard | (addr < 0x800000a0 || addr > 0x800000a1) &&
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114 | 9a64fbe4 | bellard | (addr < 0x800001f0 || addr > 0x800001f7) &&
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115 | a541f297 | bellard | (addr < 0x80000170 || addr > 0x80000177))
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116 | a541f297 | bellard | #endif
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117 | a541f297 | bellard | { |
118 | 9a64fbe4 | bellard | PPC_IO_DPRINTF("0x%08x => 0x%02x\n", addr - PPC_IO_BASE, value);
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119 | 9a64fbe4 | bellard | } |
120 | 9a64fbe4 | bellard | cpu_outb(NULL, addr - PPC_IO_BASE, value);
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121 | 9a64fbe4 | bellard | } |
122 | 9a64fbe4 | bellard | |
123 | 2e12669a | bellard | static uint32_t PPC_io_readb (target_phys_addr_t addr)
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124 | 9a64fbe4 | bellard | { |
125 | 9a64fbe4 | bellard | uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
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126 | 9a64fbe4 | bellard | |
127 | a541f297 | bellard | #if 0
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128 | 9a64fbe4 | bellard | if ((addr < 0x800003F0 || addr > 0x80000400) &&
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129 | 9a64fbe4 | bellard | (addr < 0x80000074 || addr > 0x80000077) &&
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130 | 9a64fbe4 | bellard | (addr < 0x80000020 || addr > 0x80000021) &&
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131 | 9a64fbe4 | bellard | (addr < 0x800000a0 || addr > 0x800000a1) &&
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132 | 9a64fbe4 | bellard | (addr < 0x800001f0 || addr > 0x800001f7) &&
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133 | 9a64fbe4 | bellard | (addr < 0x80000170 || addr > 0x80000177) &&
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134 | a541f297 | bellard | (addr < 0x8000060 || addr > 0x8000064))
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135 | a541f297 | bellard | #endif
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136 | a541f297 | bellard | { |
137 | a541f297 | bellard | PPC_IO_DPRINTF("0x%08x <= 0x%02x\n", addr - PPC_IO_BASE, ret);
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138 | 9a64fbe4 | bellard | } |
139 | 9a64fbe4 | bellard | return ret;
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140 | 9a64fbe4 | bellard | } |
141 | 9a64fbe4 | bellard | |
142 | 2e12669a | bellard | static void PPC_io_writew (target_phys_addr_t addr, uint32_t value) |
143 | 9a64fbe4 | bellard | { |
144 | 9a64fbe4 | bellard | if ((addr < 0x800001f0 || addr > 0x800001f7) && |
145 | 9a64fbe4 | bellard | (addr < 0x80000170 || addr > 0x80000177)) { |
146 | 9a64fbe4 | bellard | PPC_IO_DPRINTF("0x%08x => 0x%04x\n", addr - PPC_IO_BASE, value);
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147 | 9a64fbe4 | bellard | } |
148 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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149 | f658b4db | bellard | value = bswap16(value); |
150 | f658b4db | bellard | #endif
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151 | 9a64fbe4 | bellard | cpu_outw(NULL, addr - PPC_IO_BASE, value);
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152 | 9a64fbe4 | bellard | } |
153 | 9a64fbe4 | bellard | |
154 | 2e12669a | bellard | static uint32_t PPC_io_readw (target_phys_addr_t addr)
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155 | 9a64fbe4 | bellard | { |
156 | 9a64fbe4 | bellard | uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
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157 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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158 | f658b4db | bellard | ret = bswap16(ret); |
159 | f658b4db | bellard | #endif
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160 | 9a64fbe4 | bellard | if ((addr < 0x800001f0 || addr > 0x800001f7) && |
161 | 9a64fbe4 | bellard | (addr < 0x80000170 || addr > 0x80000177)) { |
162 | 9a64fbe4 | bellard | PPC_IO_DPRINTF("0x%08x <= 0x%04x\n", addr - PPC_IO_BASE, ret);
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163 | 9a64fbe4 | bellard | } |
164 | 9a64fbe4 | bellard | return ret;
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165 | 9a64fbe4 | bellard | } |
166 | 9a64fbe4 | bellard | |
167 | 2e12669a | bellard | static void PPC_io_writel (target_phys_addr_t addr, uint32_t value) |
168 | 9a64fbe4 | bellard | { |
169 | 9a64fbe4 | bellard | PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
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170 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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171 | f658b4db | bellard | value = bswap32(value); |
172 | f658b4db | bellard | #endif
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173 | 9a64fbe4 | bellard | cpu_outl(NULL, addr - PPC_IO_BASE, value);
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174 | 9a64fbe4 | bellard | } |
175 | 9a64fbe4 | bellard | |
176 | 2e12669a | bellard | static uint32_t PPC_io_readl (target_phys_addr_t addr)
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177 | 9a64fbe4 | bellard | { |
178 | 9a64fbe4 | bellard | uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
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179 | 9a64fbe4 | bellard | |
180 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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181 | f658b4db | bellard | ret = bswap32(ret); |
182 | f658b4db | bellard | #endif
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183 | 9a64fbe4 | bellard | PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, ret);
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184 | 9a64fbe4 | bellard | return ret;
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185 | 9a64fbe4 | bellard | } |
186 | 9a64fbe4 | bellard | |
187 | 9a64fbe4 | bellard | static CPUWriteMemoryFunc *PPC_io_write[] = {
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188 | 9a64fbe4 | bellard | &PPC_io_writeb, |
189 | 9a64fbe4 | bellard | &PPC_io_writew, |
190 | 9a64fbe4 | bellard | &PPC_io_writel, |
191 | 9a64fbe4 | bellard | }; |
192 | 9a64fbe4 | bellard | |
193 | 9a64fbe4 | bellard | static CPUReadMemoryFunc *PPC_io_read[] = {
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194 | 9a64fbe4 | bellard | &PPC_io_readb, |
195 | 9a64fbe4 | bellard | &PPC_io_readw, |
196 | 9a64fbe4 | bellard | &PPC_io_readl, |
197 | 9a64fbe4 | bellard | }; |
198 | 9a64fbe4 | bellard | |
199 | 9a64fbe4 | bellard | /* Read-only register (?) */
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200 | 2e12669a | bellard | static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value) |
201 | 9a64fbe4 | bellard | { |
202 | a541f297 | bellard | // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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203 | 9a64fbe4 | bellard | } |
204 | 9a64fbe4 | bellard | |
205 | 2e12669a | bellard | static uint32_t _PPC_ioB_read (target_phys_addr_t addr)
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206 | 9a64fbe4 | bellard | { |
207 | 9a64fbe4 | bellard | uint32_t retval = 0;
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208 | 9a64fbe4 | bellard | |
209 | 9a64fbe4 | bellard | if (addr == 0xBFFFFFF0) |
210 | 9a64fbe4 | bellard | retval = pic_intack_read(NULL);
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211 | a541f297 | bellard | // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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212 | 9a64fbe4 | bellard | |
213 | 9a64fbe4 | bellard | return retval;
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214 | 9a64fbe4 | bellard | } |
215 | 9a64fbe4 | bellard | |
216 | 9a64fbe4 | bellard | static CPUWriteMemoryFunc *PPC_ioB_write[] = {
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217 | 9a64fbe4 | bellard | &_PPC_ioB_write, |
218 | 9a64fbe4 | bellard | &_PPC_ioB_write, |
219 | 9a64fbe4 | bellard | &_PPC_ioB_write, |
220 | 9a64fbe4 | bellard | }; |
221 | 9a64fbe4 | bellard | |
222 | 9a64fbe4 | bellard | static CPUReadMemoryFunc *PPC_ioB_read[] = {
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223 | 9a64fbe4 | bellard | &_PPC_ioB_read, |
224 | 9a64fbe4 | bellard | &_PPC_ioB_read, |
225 | 9a64fbe4 | bellard | &_PPC_ioB_read, |
226 | 9a64fbe4 | bellard | }; |
227 | 9a64fbe4 | bellard | |
228 | 9a64fbe4 | bellard | #if 0
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229 | 9a64fbe4 | bellard | static CPUWriteMemoryFunc *PPC_io3_write[] = {
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230 | 9a64fbe4 | bellard | &PPC_io3_writeb,
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231 | 9a64fbe4 | bellard | &PPC_io3_writew,
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232 | 9a64fbe4 | bellard | &PPC_io3_writel,
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233 | 9a64fbe4 | bellard | };
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234 | 9a64fbe4 | bellard | |
235 | 9a64fbe4 | bellard | static CPUReadMemoryFunc *PPC_io3_read[] = {
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236 | 9a64fbe4 | bellard | &PPC_io3_readb,
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237 | 9a64fbe4 | bellard | &PPC_io3_readw,
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238 | 9a64fbe4 | bellard | &PPC_io3_readl,
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239 | 9a64fbe4 | bellard | };
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240 | 9a64fbe4 | bellard | #endif
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241 | 9a64fbe4 | bellard | |
242 | 9a64fbe4 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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243 | 9a64fbe4 | bellard | static uint8_t PREP_fake_io[2]; |
244 | 9a64fbe4 | bellard | static uint8_t NVRAM_lock;
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245 | 9a64fbe4 | bellard | |
246 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
247 | 9a64fbe4 | bellard | { |
248 | a541f297 | bellard | PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
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249 | 9a64fbe4 | bellard | PREP_fake_io[addr - 0x0398] = val;
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250 | 9a64fbe4 | bellard | } |
251 | 9a64fbe4 | bellard | |
252 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
253 | 9a64fbe4 | bellard | { |
254 | a541f297 | bellard | PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, PREP_fake_io[addr - 0x0398]); |
255 | 9a64fbe4 | bellard | return PREP_fake_io[addr - 0x0398]; |
256 | 9a64fbe4 | bellard | } |
257 | 9a64fbe4 | bellard | |
258 | 9a64fbe4 | bellard | static uint8_t syscontrol;
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259 | 9a64fbe4 | bellard | |
260 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
261 | 9a64fbe4 | bellard | { |
262 | a541f297 | bellard | PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
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263 | 9a64fbe4 | bellard | switch (addr) {
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264 | 9a64fbe4 | bellard | case 0x0092: |
265 | 9a64fbe4 | bellard | /* Special port 92 */
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266 | 9a64fbe4 | bellard | /* Check soft reset asked */
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267 | 9a64fbe4 | bellard | if (val & 0x80) { |
268 | 9a64fbe4 | bellard | printf("Soft reset asked... Stop emulation\n");
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269 | 9a64fbe4 | bellard | abort(); |
270 | 9a64fbe4 | bellard | } |
271 | 9a64fbe4 | bellard | /* Check LE mode */
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272 | 9a64fbe4 | bellard | if (val & 0x40) { |
273 | 9a64fbe4 | bellard | printf("Little Endian mode isn't supported (yet ?)\n");
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274 | 9a64fbe4 | bellard | abort(); |
275 | 9a64fbe4 | bellard | } |
276 | 9a64fbe4 | bellard | break;
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277 | 9a64fbe4 | bellard | case 0x0808: |
278 | 9a64fbe4 | bellard | /* Hardfile light register: don't care */
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279 | 9a64fbe4 | bellard | break;
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280 | 9a64fbe4 | bellard | case 0x0810: |
281 | 9a64fbe4 | bellard | /* Password protect 1 register */
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282 | 9a64fbe4 | bellard | NVRAM_lock ^= 0x01;
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283 | 9a64fbe4 | bellard | break;
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284 | 9a64fbe4 | bellard | case 0x0812: |
285 | 9a64fbe4 | bellard | /* Password protect 2 register */
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286 | 9a64fbe4 | bellard | NVRAM_lock ^= 0x02;
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287 | 9a64fbe4 | bellard | break;
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288 | 9a64fbe4 | bellard | case 0x0814: |
289 | 9a64fbe4 | bellard | /* L2 invalidate register: don't care */
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290 | 9a64fbe4 | bellard | break;
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291 | 9a64fbe4 | bellard | case 0x081C: |
292 | 9a64fbe4 | bellard | /* system control register */
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293 | 9a64fbe4 | bellard | syscontrol = val; |
294 | 9a64fbe4 | bellard | break;
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295 | 9a64fbe4 | bellard | case 0x0850: |
296 | 9a64fbe4 | bellard | /* I/O map type register */
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297 | 9a64fbe4 | bellard | if (val & 0x80) { |
298 | 9a64fbe4 | bellard | printf("No support for non-continuous I/O map mode\n");
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299 | 9a64fbe4 | bellard | abort(); |
300 | 9a64fbe4 | bellard | } |
301 | 9a64fbe4 | bellard | break;
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302 | 9a64fbe4 | bellard | default:
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303 | 9a64fbe4 | bellard | break;
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304 | 9a64fbe4 | bellard | } |
305 | 9a64fbe4 | bellard | } |
306 | 9a64fbe4 | bellard | |
307 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
308 | 9a64fbe4 | bellard | { |
309 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
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310 | 9a64fbe4 | bellard | |
311 | 9a64fbe4 | bellard | switch (addr) {
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312 | 9a64fbe4 | bellard | case 0x0092: |
313 | 9a64fbe4 | bellard | /* Special port 92 */
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314 | 9a64fbe4 | bellard | retval = 0x40;
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315 | 9a64fbe4 | bellard | break;
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316 | 9a64fbe4 | bellard | case 0x080C: |
317 | 9a64fbe4 | bellard | /* Equipment present register:
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318 | 9a64fbe4 | bellard | * no L2 cache
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319 | 9a64fbe4 | bellard | * no upgrade processor
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320 | 9a64fbe4 | bellard | * no cards in PCI slots
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321 | 9a64fbe4 | bellard | * SCSI fuse is bad
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322 | 9a64fbe4 | bellard | */
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323 | 9a64fbe4 | bellard | retval = 0xFC;
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324 | 9a64fbe4 | bellard | break;
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325 | 9a64fbe4 | bellard | case 0x0818: |
326 | 9a64fbe4 | bellard | /* Keylock */
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327 | 9a64fbe4 | bellard | retval = 0x00;
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328 | 9a64fbe4 | bellard | break;
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329 | 9a64fbe4 | bellard | case 0x081C: |
330 | 9a64fbe4 | bellard | /* system control register
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331 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
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332 | 9a64fbe4 | bellard | */
|
333 | 9a64fbe4 | bellard | retval = syscontrol; |
334 | 9a64fbe4 | bellard | break;
|
335 | 9a64fbe4 | bellard | case 0x0823: |
336 | 9a64fbe4 | bellard | /* */
|
337 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
338 | 9a64fbe4 | bellard | break;
|
339 | 9a64fbe4 | bellard | case 0x0850: |
340 | 9a64fbe4 | bellard | /* I/O map type register */
|
341 | 9a64fbe4 | bellard | retval = 0x00;
|
342 | 9a64fbe4 | bellard | break;
|
343 | 9a64fbe4 | bellard | default:
|
344 | 9a64fbe4 | bellard | break;
|
345 | 9a64fbe4 | bellard | } |
346 | a541f297 | bellard | PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, retval);
|
347 | 9a64fbe4 | bellard | |
348 | 9a64fbe4 | bellard | return retval;
|
349 | 9a64fbe4 | bellard | } |
350 | 9a64fbe4 | bellard | |
351 | a541f297 | bellard | #define NVRAM_SIZE 0x2000 |
352 | a541f297 | bellard | #define NVRAM_END 0x1FF0 |
353 | a541f297 | bellard | #define NVRAM_OSAREA_SIZE 512 |
354 | a541f297 | bellard | #define NVRAM_CONFSIZE 1024 |
355 | 9a64fbe4 | bellard | |
356 | c5df018e | bellard | static inline void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value) |
357 | a541f297 | bellard | { |
358 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
359 | c5df018e | bellard | m48t59_write(nvram, value); |
360 | a541f297 | bellard | } |
361 | a541f297 | bellard | |
362 | c5df018e | bellard | static inline uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
363 | a541f297 | bellard | { |
364 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
365 | c5df018e | bellard | return m48t59_read(nvram);
|
366 | a541f297 | bellard | } |
367 | a541f297 | bellard | |
368 | c5df018e | bellard | static inline void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value) |
369 | a541f297 | bellard | { |
370 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
371 | c5df018e | bellard | m48t59_write(nvram, value >> 8);
|
372 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 1);
|
373 | c5df018e | bellard | m48t59_write(nvram, value & 0xFF);
|
374 | a541f297 | bellard | } |
375 | 9a64fbe4 | bellard | |
376 | c5df018e | bellard | static inline uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
377 | 9a64fbe4 | bellard | { |
378 | a541f297 | bellard | uint16_t tmp; |
379 | a541f297 | bellard | |
380 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
381 | c5df018e | bellard | tmp = m48t59_read(nvram) << 8;
|
382 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 1);
|
383 | c5df018e | bellard | tmp |= m48t59_read(nvram); |
384 | a541f297 | bellard | |
385 | a541f297 | bellard | return tmp;
|
386 | 9a64fbe4 | bellard | } |
387 | 9a64fbe4 | bellard | |
388 | c5df018e | bellard | static inline void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, |
389 | a541f297 | bellard | uint32_t value) |
390 | 9a64fbe4 | bellard | { |
391 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
392 | c5df018e | bellard | m48t59_write(nvram, value >> 24);
|
393 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 1);
|
394 | c5df018e | bellard | m48t59_write(nvram, (value >> 16) & 0xFF); |
395 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 2);
|
396 | c5df018e | bellard | m48t59_write(nvram, (value >> 8) & 0xFF); |
397 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 3);
|
398 | c5df018e | bellard | m48t59_write(nvram, value & 0xFF);
|
399 | a541f297 | bellard | } |
400 | 9a64fbe4 | bellard | |
401 | c5df018e | bellard | static inline uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
402 | a541f297 | bellard | { |
403 | a541f297 | bellard | uint32_t tmp; |
404 | a541f297 | bellard | |
405 | c5df018e | bellard | m48t59_set_addr(nvram, addr); |
406 | c5df018e | bellard | tmp = m48t59_read(nvram) << 24;
|
407 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 1);
|
408 | c5df018e | bellard | tmp |= m48t59_read(nvram) << 16;
|
409 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 2);
|
410 | c5df018e | bellard | tmp |= m48t59_read(nvram) << 8;
|
411 | c5df018e | bellard | m48t59_set_addr(nvram, addr + 3);
|
412 | c5df018e | bellard | tmp |= m48t59_read(nvram); |
413 | a541f297 | bellard | |
414 | a541f297 | bellard | return tmp;
|
415 | 9a64fbe4 | bellard | } |
416 | 9a64fbe4 | bellard | |
417 | a541f297 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
418 | 9a64fbe4 | bellard | { |
419 | a541f297 | bellard | uint16_t tmp; |
420 | a541f297 | bellard | uint16_t pd, pd1, pd2; |
421 | a541f297 | bellard | |
422 | a541f297 | bellard | tmp = prev >> 8;
|
423 | a541f297 | bellard | pd = prev ^ value; |
424 | a541f297 | bellard | pd1 = pd & 0x000F;
|
425 | a541f297 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
426 | a541f297 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
427 | a541f297 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
428 | a541f297 | bellard | |
429 | a541f297 | bellard | return tmp;
|
430 | a541f297 | bellard | } |
431 | a541f297 | bellard | |
432 | c5df018e | bellard | static void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr, |
433 | a541f297 | bellard | uint32_t start, uint32_t count) |
434 | a541f297 | bellard | { |
435 | a541f297 | bellard | uint32_t i; |
436 | a541f297 | bellard | uint16_t crc = 0xFFFF;
|
437 | a541f297 | bellard | int odd = 0; |
438 | a541f297 | bellard | |
439 | a541f297 | bellard | if (count & 1) |
440 | a541f297 | bellard | odd = 1;
|
441 | a541f297 | bellard | count &= ~1;
|
442 | a541f297 | bellard | for (i = 0; i != count; i++) { |
443 | c5df018e | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
444 | a541f297 | bellard | } |
445 | a541f297 | bellard | if (odd) {
|
446 | c5df018e | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
447 | a541f297 | bellard | } |
448 | c5df018e | bellard | NVRAM_set_word(nvram, addr, crc); |
449 | a541f297 | bellard | } |
450 | a541f297 | bellard | |
451 | a541f297 | bellard | static void prep_NVRAM_init (void) |
452 | a541f297 | bellard | { |
453 | c5df018e | bellard | m48t59_t *nvram; |
454 | a541f297 | bellard | |
455 | c5df018e | bellard | nvram = m48t59_init(8, 0x0074, NVRAM_SIZE); |
456 | 9a64fbe4 | bellard | /* NVRAM header */
|
457 | 9a64fbe4 | bellard | /* 0x00: NVRAM size in kB */
|
458 | c5df018e | bellard | NVRAM_set_word(nvram, 0x00, NVRAM_SIZE >> 10); |
459 | 9a64fbe4 | bellard | /* 0x02: NVRAM version */
|
460 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x02, 0x01); |
461 | 9a64fbe4 | bellard | /* 0x03: NVRAM revision */
|
462 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x03, 0x01); |
463 | 9a64fbe4 | bellard | /* 0x08: last OS */
|
464 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x08, 0x00); /* Unknown */ |
465 | 9a64fbe4 | bellard | /* 0x09: endian */
|
466 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x09, 'B'); /* Big-endian */ |
467 | a541f297 | bellard | /* 0x0A: OSArea usage */
|
468 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x0A, 0x00); /* Empty */ |
469 | 9a64fbe4 | bellard | /* 0x0B: PM mode */
|
470 | c5df018e | bellard | NVRAM_set_byte(nvram, 0x0B, 0x00); /* Normal */ |
471 | 9a64fbe4 | bellard | /* Restart block description record */
|
472 | 9a64fbe4 | bellard | /* 0x0C: restart block version */
|
473 | c5df018e | bellard | NVRAM_set_word(nvram, 0x0C, 0x01); |
474 | 9a64fbe4 | bellard | /* 0x0E: restart block revision */
|
475 | c5df018e | bellard | NVRAM_set_word(nvram, 0x0E, 0x01); |
476 | 9a64fbe4 | bellard | /* 0x20: restart address */
|
477 | c5df018e | bellard | NVRAM_set_lword(nvram, 0x20, 0x00); |
478 | 9a64fbe4 | bellard | /* 0x24: save area address */
|
479 | c5df018e | bellard | NVRAM_set_lword(nvram, 0x24, 0x00); |
480 | 9a64fbe4 | bellard | /* 0x28: save area length */
|
481 | c5df018e | bellard | NVRAM_set_lword(nvram, 0x28, 0x00); |
482 | a541f297 | bellard | /* 0x1C: checksum of restart block */
|
483 | c5df018e | bellard | NVRAM_set_crc(nvram, 0x1C, 0x0C, 32); |
484 | a541f297 | bellard | |
485 | 9a64fbe4 | bellard | /* Security section */
|
486 | 9a64fbe4 | bellard | /* Set all to zero */
|
487 | 9a64fbe4 | bellard | /* 0xC4: pointer to global environment area */
|
488 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xC4, 0x0100); |
489 | 9a64fbe4 | bellard | /* 0xC8: size of global environment area */
|
490 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xC8,
|
491 | a541f297 | bellard | NVRAM_END - NVRAM_OSAREA_SIZE - NVRAM_CONFSIZE - 0x0100);
|
492 | 9a64fbe4 | bellard | /* 0xD4: pointer to configuration area */
|
493 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xD4, NVRAM_END - NVRAM_CONFSIZE);
|
494 | 9a64fbe4 | bellard | /* 0xD8: size of configuration area */
|
495 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xD8, NVRAM_CONFSIZE);
|
496 | 9a64fbe4 | bellard | /* 0xE8: pointer to OS specific area */
|
497 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xE8,
|
498 | a541f297 | bellard | NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE); |
499 | 9a64fbe4 | bellard | /* 0xD8: size of OS specific area */
|
500 | c5df018e | bellard | NVRAM_set_lword(nvram, 0xEC, NVRAM_OSAREA_SIZE);
|
501 | 9a64fbe4 | bellard | |
502 | a541f297 | bellard | /* Configuration area */
|
503 | a541f297 | bellard | /* RTC init */
|
504 | c5df018e | bellard | // NVRAM_set_lword(nvram, 0x1FFC, 0x50);
|
505 | 9a64fbe4 | bellard | |
506 | a541f297 | bellard | /* 0x04: checksum 0 => OS area */
|
507 | c5df018e | bellard | NVRAM_set_crc(nvram, 0x04, 0x00, |
508 | a541f297 | bellard | NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE); |
509 | a541f297 | bellard | /* 0x06: checksum of config area */
|
510 | c5df018e | bellard | NVRAM_set_crc(nvram, 0x06, NVRAM_END - NVRAM_CONFSIZE, NVRAM_CONFSIZE);
|
511 | 9a64fbe4 | bellard | } |
512 | 9a64fbe4 | bellard | |
513 | 9a64fbe4 | bellard | int load_initrd (const char *filename, uint8_t *addr) |
514 | 9a64fbe4 | bellard | { |
515 | 9a64fbe4 | bellard | int fd, size;
|
516 | 9a64fbe4 | bellard | |
517 | 9a64fbe4 | bellard | printf("Load initrd\n");
|
518 | 9a64fbe4 | bellard | fd = open(filename, O_RDONLY); |
519 | 9a64fbe4 | bellard | if (fd < 0) |
520 | 9a64fbe4 | bellard | return -1; |
521 | 9a64fbe4 | bellard | size = read(fd, addr, 16 * 1024 * 1024); |
522 | 9a64fbe4 | bellard | if (size < 0) |
523 | 9a64fbe4 | bellard | goto fail;
|
524 | 9a64fbe4 | bellard | close(fd); |
525 | 9a64fbe4 | bellard | printf("Load initrd: %d\n", size);
|
526 | 9a64fbe4 | bellard | return size;
|
527 | 9a64fbe4 | bellard | fail:
|
528 | 9a64fbe4 | bellard | close(fd); |
529 | 9a64fbe4 | bellard | printf("Load initrd failed\n");
|
530 | 9a64fbe4 | bellard | return -1; |
531 | 9a64fbe4 | bellard | } |
532 | 9a64fbe4 | bellard | |
533 | 9a64fbe4 | bellard | /* Quick hack for PPC memory infos... */
|
534 | 9a64fbe4 | bellard | static void put_long (void *addr, uint32_t l) |
535 | 9a64fbe4 | bellard | { |
536 | 9a64fbe4 | bellard | char *pos = addr;
|
537 | 9a64fbe4 | bellard | pos[0] = (l >> 24) & 0xFF; |
538 | 9a64fbe4 | bellard | pos[1] = (l >> 16) & 0xFF; |
539 | 9a64fbe4 | bellard | pos[2] = (l >> 8) & 0xFF; |
540 | 9a64fbe4 | bellard | pos[3] = l & 0xFF; |
541 | 9a64fbe4 | bellard | } |
542 | 9a64fbe4 | bellard | |
543 | 9a64fbe4 | bellard | /* bootloader infos are in the form:
|
544 | 9a64fbe4 | bellard | * uint32_t TAG
|
545 | 9a64fbe4 | bellard | * uint32_t TAG_size (from TAG to next TAG).
|
546 | a541f297 | bellard | * data
|
547 | 9a64fbe4 | bellard | * ....
|
548 | 9a64fbe4 | bellard | */
|
549 | 9a64fbe4 | bellard | #if !defined (USE_OPEN_FIRMWARE)
|
550 | 9a64fbe4 | bellard | static void *set_bootinfo_tag (void *addr, uint32_t tag, uint32_t size, |
551 | 9a64fbe4 | bellard | void *data)
|
552 | 9a64fbe4 | bellard | { |
553 | 9a64fbe4 | bellard | char *pos = addr;
|
554 | 9a64fbe4 | bellard | |
555 | 9a64fbe4 | bellard | put_long(pos, tag); |
556 | 9a64fbe4 | bellard | pos += 4;
|
557 | 9a64fbe4 | bellard | put_long(pos, size + 8);
|
558 | 9a64fbe4 | bellard | pos += 4;
|
559 | 9a64fbe4 | bellard | memcpy(pos, data, size); |
560 | 9a64fbe4 | bellard | pos += size; |
561 | 9a64fbe4 | bellard | |
562 | 9a64fbe4 | bellard | return pos;
|
563 | 9a64fbe4 | bellard | } |
564 | 9a64fbe4 | bellard | #endif
|
565 | 9a64fbe4 | bellard | |
566 | 9a64fbe4 | bellard | typedef struct boot_dev_t { |
567 | 9a64fbe4 | bellard | const unsigned char *name; |
568 | 9a64fbe4 | bellard | int major;
|
569 | 9a64fbe4 | bellard | int minor;
|
570 | 9a64fbe4 | bellard | } boot_dev_t; |
571 | 9a64fbe4 | bellard | |
572 | 9a64fbe4 | bellard | static boot_dev_t boot_devs[] =
|
573 | 9a64fbe4 | bellard | { |
574 | 9a64fbe4 | bellard | { "/dev/fd0", 2, 0, }, |
575 | 9a64fbe4 | bellard | { "/dev/fd1", 2, 1, }, |
576 | a541f297 | bellard | { "/dev/hda", 3, 1, }, |
577 | 9a64fbe4 | bellard | // { "/dev/ide/host0/bus0/target0/lun0/part1", 3, 1, },
|
578 | a541f297 | bellard | // { "/dev/hdc", 22, 0, },
|
579 | a541f297 | bellard | { "/dev/hdc", 22, 1, }, |
580 | 9a64fbe4 | bellard | { "/dev/ram0 init=/linuxrc", 1, 0, }, |
581 | 9a64fbe4 | bellard | }; |
582 | 9a64fbe4 | bellard | |
583 | 9a64fbe4 | bellard | /* BATU:
|
584 | 9a64fbe4 | bellard | * BEPI : bloc virtual address
|
585 | 9a64fbe4 | bellard | * BL : area size bits (128 kB is 0, 256 1, 512 3, ...
|
586 | 9a64fbe4 | bellard | * Vs/Vp
|
587 | 9a64fbe4 | bellard | * BATL:
|
588 | 9a64fbe4 | bellard | * BPRN : bloc real address align on 4MB boundary
|
589 | 9a64fbe4 | bellard | * WIMG : cache access mode : not used
|
590 | 9a64fbe4 | bellard | * PP : protection bits
|
591 | 9a64fbe4 | bellard | */
|
592 | 9a64fbe4 | bellard | static void setup_BAT (CPUPPCState *env, int BAT, |
593 | 9a64fbe4 | bellard | uint32_t virtual, uint32_t physical, |
594 | 9a64fbe4 | bellard | uint32_t size, int Vs, int Vp, int PP) |
595 | 9a64fbe4 | bellard | { |
596 | 9a64fbe4 | bellard | uint32_t sz_bits, tmp_sz, align, tmp; |
597 | 9a64fbe4 | bellard | |
598 | 9a64fbe4 | bellard | sz_bits = 0;
|
599 | 9a64fbe4 | bellard | align = 131072;
|
600 | 9a64fbe4 | bellard | for (tmp_sz = size / 131072; tmp_sz != 1; tmp_sz = tmp_sz >> 1) { |
601 | 9a64fbe4 | bellard | sz_bits = (sz_bits << 1) + 1; |
602 | 9a64fbe4 | bellard | align = align << 1;
|
603 | 9a64fbe4 | bellard | } |
604 | 9a64fbe4 | bellard | tmp = virtual & ~(align - 1); /* Align virtual area start */ |
605 | 9a64fbe4 | bellard | tmp |= sz_bits << 2; /* Fix BAT size */ |
606 | 9a64fbe4 | bellard | tmp |= Vs << 1; /* Supervisor access */ |
607 | 9a64fbe4 | bellard | tmp |= Vp; /* User access */
|
608 | 9a64fbe4 | bellard | env->DBAT[0][BAT] = tmp;
|
609 | 9a64fbe4 | bellard | env->IBAT[0][BAT] = tmp;
|
610 | 9a64fbe4 | bellard | tmp = physical & ~(align - 1); /* Align physical area start */ |
611 | 9a64fbe4 | bellard | tmp |= 0; /* Don't care about WIMG */ |
612 | 9a64fbe4 | bellard | tmp |= PP; /* Protection */
|
613 | 9a64fbe4 | bellard | env->DBAT[1][BAT] = tmp;
|
614 | 9a64fbe4 | bellard | env->IBAT[1][BAT] = tmp;
|
615 | 9a64fbe4 | bellard | printf("Set BATU0 to 0x%08x BATL0 to 0x%08x\n",
|
616 | 9a64fbe4 | bellard | env->DBAT[0][BAT], env->DBAT[1][BAT]); |
617 | 9a64fbe4 | bellard | } |
618 | 9a64fbe4 | bellard | |
619 | 9a64fbe4 | bellard | static void VGA_printf (uint8_t *s) |
620 | 9a64fbe4 | bellard | { |
621 | 9a64fbe4 | bellard | uint16_t *arg_ptr; |
622 | 9a64fbe4 | bellard | unsigned int format_width, i; |
623 | 9a64fbe4 | bellard | int in_format;
|
624 | 9a64fbe4 | bellard | uint16_t arg, digit, nibble; |
625 | 9a64fbe4 | bellard | uint8_t c; |
626 | 9a64fbe4 | bellard | |
627 | a541f297 | bellard | arg_ptr = (uint16_t *)((void *)&s);
|
628 | 9a64fbe4 | bellard | in_format = 0;
|
629 | 9a64fbe4 | bellard | format_width = 0;
|
630 | 9a64fbe4 | bellard | while ((c = *s) != '\0') { |
631 | 9a64fbe4 | bellard | if (c == '%') { |
632 | 9a64fbe4 | bellard | in_format = 1;
|
633 | 9a64fbe4 | bellard | format_width = 0;
|
634 | 9a64fbe4 | bellard | } else if (in_format) { |
635 | 9a64fbe4 | bellard | if ((c >= '0') && (c <= '9')) { |
636 | 9a64fbe4 | bellard | format_width = (format_width * 10) + (c - '0'); |
637 | 9a64fbe4 | bellard | } else if (c == 'x') { |
638 | 9a64fbe4 | bellard | arg_ptr++; // increment to next arg
|
639 | 9a64fbe4 | bellard | arg = *arg_ptr; |
640 | 9a64fbe4 | bellard | if (format_width == 0) |
641 | 9a64fbe4 | bellard | format_width = 4;
|
642 | 9a64fbe4 | bellard | digit = format_width - 1;
|
643 | 9a64fbe4 | bellard | for (i = 0; i < format_width; i++) { |
644 | 9a64fbe4 | bellard | nibble = (arg >> (4 * digit)) & 0x000f; |
645 | 9a64fbe4 | bellard | if (nibble <= 9) |
646 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0'); |
647 | 9a64fbe4 | bellard | else
|
648 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A'); |
649 | 9a64fbe4 | bellard | digit--; |
650 | 9a64fbe4 | bellard | } |
651 | 9a64fbe4 | bellard | in_format = 0;
|
652 | 9a64fbe4 | bellard | } |
653 | 9a64fbe4 | bellard | //else if (c == 'd') {
|
654 | 9a64fbe4 | bellard | // in_format = 0;
|
655 | 9a64fbe4 | bellard | // }
|
656 | 9a64fbe4 | bellard | } else {
|
657 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x500, c);
|
658 | 9a64fbe4 | bellard | } |
659 | 9a64fbe4 | bellard | s++; |
660 | 9a64fbe4 | bellard | } |
661 | 9a64fbe4 | bellard | } |
662 | 9a64fbe4 | bellard | |
663 | 9a64fbe4 | bellard | static void VGA_init (void) |
664 | 9a64fbe4 | bellard | { |
665 | 9a64fbe4 | bellard | /* Basic VGA init, inspired by plex86 VGAbios */
|
666 | 9a64fbe4 | bellard | printf("Init VGA...\n");
|
667 | a541f297 | bellard | #if 1 |
668 | 9a64fbe4 | bellard | /* switch to color mode and enable CPU access 480 lines */
|
669 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3); |
670 | 9a64fbe4 | bellard | /* more than 64k 3C4/04 */
|
671 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04); |
672 | 2e12669a | bellard | PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02); |
673 | a541f297 | bellard | #endif
|
674 | 9a64fbe4 | bellard | VGA_printf("PPC VGA BIOS...\n");
|
675 | 9a64fbe4 | bellard | } |
676 | 9a64fbe4 | bellard | |
677 | a541f297 | bellard | extern CPUPPCState *global_env;
|
678 | a541f297 | bellard | |
679 | 7fd7b91f | bellard | static uint32_t get_le32 (void *addr) |
680 | 7fd7b91f | bellard | { |
681 | 7fd7b91f | bellard | return le32_to_cpu(*((uint32_t *)addr));
|
682 | 7fd7b91f | bellard | } |
683 | 7fd7b91f | bellard | |
684 | a541f297 | bellard | void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size, |
685 | 9a64fbe4 | bellard | uint32_t kernel_addr, uint32_t kernel_size, |
686 | a541f297 | bellard | uint32_t stack_addr, int boot_device,
|
687 | a541f297 | bellard | const unsigned char *initrd_file) |
688 | 9a64fbe4 | bellard | { |
689 | a541f297 | bellard | CPUPPCState *env = global_env; |
690 | 7fd7b91f | bellard | uint8_t *p; |
691 | 9a64fbe4 | bellard | #if !defined (USE_OPEN_FIRMWARE)
|
692 | 9a64fbe4 | bellard | char *tmp;
|
693 | 9a64fbe4 | bellard | uint32_t tmpi[2];
|
694 | 9a64fbe4 | bellard | #endif
|
695 | a541f297 | bellard | |
696 | a541f297 | bellard | printf("RAM size: %u 0x%08x (%u)\n", mem_size, mem_size, mem_size >> 20); |
697 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
|
698 | 9a64fbe4 | bellard | setup_memory(env, mem_size); |
699 | 9a64fbe4 | bellard | #endif
|
700 | 9a64fbe4 | bellard | |
701 | 9a64fbe4 | bellard | /* Fake bootloader */
|
702 | a541f297 | bellard | { |
703 | a541f297 | bellard | #if 1 |
704 | 7fd7b91f | bellard | uint32_t offset = get_le32(phys_ram_base + kernel_addr); |
705 | a541f297 | bellard | #else
|
706 | a541f297 | bellard | uint32_t offset = 12;
|
707 | a541f297 | bellard | #endif
|
708 | a541f297 | bellard | env->nip = kernel_addr + offset; |
709 | a541f297 | bellard | printf("Start address: 0x%08x\n", env->nip);
|
710 | a541f297 | bellard | } |
711 | 9a64fbe4 | bellard | /* Set up msr according to PREP specification */
|
712 | 9a64fbe4 | bellard | msr_ee = 0;
|
713 | 9a64fbe4 | bellard | msr_fp = 1;
|
714 | 9a64fbe4 | bellard | msr_pr = 0; /* Start in supervisor mode */ |
715 | 9a64fbe4 | bellard | msr_me = 1;
|
716 | 9a64fbe4 | bellard | msr_fe0 = msr_fe1 = 0;
|
717 | 9a64fbe4 | bellard | msr_ip = 0;
|
718 | 9a64fbe4 | bellard | msr_ir = msr_dr = 1;
|
719 | 9a64fbe4 | bellard | // msr_sf = 0;
|
720 | 9a64fbe4 | bellard | msr_le = msr_ile = 0;
|
721 | 9a64fbe4 | bellard | env->gpr[1] = stack_addr; /* Let's have a stack */ |
722 | 9a64fbe4 | bellard | env->gpr[2] = 0; |
723 | 9a64fbe4 | bellard | env->gpr[8] = kernel_addr;
|
724 | 9a64fbe4 | bellard | /* There is a bug in 2.4 kernels:
|
725 | 9a64fbe4 | bellard | * if a decrementer exception is pending when it enables msr_ee,
|
726 | 9a64fbe4 | bellard | * it's not ready to handle it...
|
727 | 9a64fbe4 | bellard | */
|
728 | 9a64fbe4 | bellard | env->decr = 0xFFFFFFFF;
|
729 | 7fd7b91f | bellard | p = phys_ram_base + kernel_addr; |
730 | 9a64fbe4 | bellard | #if !defined (USE_OPEN_FIRMWARE)
|
731 | 9a64fbe4 | bellard | /* Let's register the whole memory available only in supervisor mode */
|
732 | 9a64fbe4 | bellard | setup_BAT(env, 0, 0x00000000, 0x00000000, mem_size, 1, 0, 2); |
733 | 9a64fbe4 | bellard | /* Avoid open firmware init call (to get a console)
|
734 | 9a64fbe4 | bellard | * This will make the kernel think we are a PREP machine...
|
735 | 9a64fbe4 | bellard | */
|
736 | 9a64fbe4 | bellard | put_long(p, 0xdeadc0de);
|
737 | 9a64fbe4 | bellard | /* Build a real stack room */
|
738 | 7fd7b91f | bellard | p = phys_ram_base + stack_addr; |
739 | 9a64fbe4 | bellard | put_long(p, stack_addr); |
740 | 9a64fbe4 | bellard | p -= 32;
|
741 | 9a64fbe4 | bellard | env->gpr[1] -= 32; |
742 | 9a64fbe4 | bellard | /* Pretend there are no residual data */
|
743 | 9a64fbe4 | bellard | env->gpr[3] = 0; |
744 | a541f297 | bellard | if (initrd_file != NULL) { |
745 | 9a64fbe4 | bellard | int size;
|
746 | a541f297 | bellard | env->gpr[4] = (kernel_addr + kernel_size + 4095) & ~4095; |
747 | a541f297 | bellard | size = load_initrd(initrd_file, |
748 | 7fd7b91f | bellard | phys_ram_base + env->gpr[4]);
|
749 | 9a64fbe4 | bellard | if (size < 0) { |
750 | 9a64fbe4 | bellard | /* No initrd */
|
751 | 9a64fbe4 | bellard | env->gpr[4] = env->gpr[5] = 0; |
752 | 9a64fbe4 | bellard | } else {
|
753 | 9a64fbe4 | bellard | env->gpr[5] = size;
|
754 | 9a64fbe4 | bellard | boot_device = 'e';
|
755 | 9a64fbe4 | bellard | } |
756 | a541f297 | bellard | printf("Initrd loaded at 0x%08x (%d) (0x%08x 0x%08x)\n",
|
757 | a541f297 | bellard | env->gpr[4], env->gpr[5], kernel_addr, kernel_size); |
758 | a541f297 | bellard | } else {
|
759 | a541f297 | bellard | env->gpr[4] = env->gpr[5] = 0; |
760 | 9a64fbe4 | bellard | } |
761 | 9a64fbe4 | bellard | /* We have to put bootinfos after the BSS
|
762 | 9a64fbe4 | bellard | * The BSS starts after the kernel end.
|
763 | 9a64fbe4 | bellard | */
|
764 | 9a64fbe4 | bellard | #if 0
|
765 | 7fd7b91f | bellard | p = phys_ram_base + kernel_addr +
|
766 | 7fd7b91f | bellard | kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1);
|
767 | 9a64fbe4 | bellard | #else
|
768 | 7fd7b91f | bellard | p = phys_ram_base + kernel_addr + 0x400000;
|
769 | 9a64fbe4 | bellard | #endif
|
770 | 9a64fbe4 | bellard | if (loglevel > 0) { |
771 | 9a64fbe4 | bellard | fprintf(logfile, "bootinfos: %p 0x%08x\n",
|
772 | 7fd7b91f | bellard | p, (int)(p - phys_ram_base));
|
773 | 9a64fbe4 | bellard | } else {
|
774 | 9a64fbe4 | bellard | printf("bootinfos: %p 0x%08x\n",
|
775 | 7fd7b91f | bellard | p, (int)(p - phys_ram_base));
|
776 | 9a64fbe4 | bellard | } |
777 | 9a64fbe4 | bellard | /* Command line: let's put it after bootinfos */
|
778 | 9a64fbe4 | bellard | #if 0
|
779 | 9a64fbe4 | bellard | sprintf(p + 0x1000, "console=ttyS0,9600 root=%02x%02x mem=%dM",
|
780 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].major,
|
781 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].minor,
|
782 | a541f297 | bellard | mem_size >> 20);
|
783 | 9a64fbe4 | bellard | #else
|
784 | a541f297 | bellard | sprintf(p + 0x1000, "console=ttyS0,9600 console=tty0 root=%s mem=%dM", |
785 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].name,
|
786 | a541f297 | bellard | mem_size >> 20);
|
787 | 9a64fbe4 | bellard | #endif
|
788 | 7fd7b91f | bellard | env->gpr[6] = p + 0x1000 - phys_ram_base; |
789 | 9a64fbe4 | bellard | env->gpr[7] = env->gpr[6] + strlen(p + 0x1000); |
790 | 9a64fbe4 | bellard | if (loglevel > 0) { |
791 | 9a64fbe4 | bellard | fprintf(logfile, "cmdline: %p 0x%08x [%s]\n",
|
792 | 9a64fbe4 | bellard | p + 0x1000, env->gpr[6], p + 0x1000); |
793 | 9a64fbe4 | bellard | } else {
|
794 | 9a64fbe4 | bellard | printf("cmdline: %p 0x%08x [%s]\n",
|
795 | 9a64fbe4 | bellard | p + 0x1000, env->gpr[6], p + 0x1000); |
796 | 9a64fbe4 | bellard | } |
797 | 9a64fbe4 | bellard | /* BI_FIRST */
|
798 | 9a64fbe4 | bellard | p = set_bootinfo_tag(p, 0x1010, 0, 0); |
799 | 9a64fbe4 | bellard | /* BI_CMD_LINE */
|
800 | 9a64fbe4 | bellard | p = set_bootinfo_tag(p, 0x1012, env->gpr[7] - env->gpr[6], |
801 | 7fd7b91f | bellard | env->gpr[6] + phys_ram_base);
|
802 | 9a64fbe4 | bellard | /* BI_MEM_SIZE */
|
803 | 9a64fbe4 | bellard | tmp = (void *)tmpi;
|
804 | a541f297 | bellard | tmp[0] = (mem_size >> 24) & 0xFF; |
805 | a541f297 | bellard | tmp[1] = (mem_size >> 16) & 0xFF; |
806 | a541f297 | bellard | tmp[2] = (mem_size >> 8) & 0xFF; |
807 | a541f297 | bellard | tmp[3] = mem_size & 0xFF; |
808 | 9a64fbe4 | bellard | p = set_bootinfo_tag(p, 0x1017, 4, tmpi); |
809 | 9a64fbe4 | bellard | /* BI_INITRD */
|
810 | 9a64fbe4 | bellard | tmp[0] = (env->gpr[4] >> 24) & 0xFF; |
811 | 9a64fbe4 | bellard | tmp[1] = (env->gpr[4] >> 16) & 0xFF; |
812 | 9a64fbe4 | bellard | tmp[2] = (env->gpr[4] >> 8) & 0xFF; |
813 | 9a64fbe4 | bellard | tmp[3] = env->gpr[4] & 0xFF; |
814 | 9a64fbe4 | bellard | tmp[4] = (env->gpr[5] >> 24) & 0xFF; |
815 | 9a64fbe4 | bellard | tmp[5] = (env->gpr[5] >> 16) & 0xFF; |
816 | 9a64fbe4 | bellard | tmp[6] = (env->gpr[5] >> 8) & 0xFF; |
817 | 9a64fbe4 | bellard | tmp[7] = env->gpr[5] & 0xFF; |
818 | 9a64fbe4 | bellard | p = set_bootinfo_tag(p, 0x1014, 8, tmpi); |
819 | a541f297 | bellard | env->gpr[4] = env->gpr[5] = 0; |
820 | 9a64fbe4 | bellard | /* BI_LAST */
|
821 | 9a64fbe4 | bellard | p = set_bootinfo_tag(p, 0x1011, 0, 0); |
822 | 9a64fbe4 | bellard | #else
|
823 | 9a64fbe4 | bellard | /* Set up MMU:
|
824 | 9a64fbe4 | bellard | * kernel is loaded at kernel_addr and wants to be seen at 0x01000000
|
825 | 9a64fbe4 | bellard | */
|
826 | 9a64fbe4 | bellard | setup_BAT(env, 0, 0x01000000, kernel_addr, 0x00400000, 1, 0, 2); |
827 | 9a64fbe4 | bellard | { |
828 | 9a64fbe4 | bellard | #if 0
|
829 | 7fd7b91f | bellard | uint32_t offset = get_le32(phys_ram_base + kernel_addr);
|
830 | 9a64fbe4 | bellard | #else
|
831 | 9a64fbe4 | bellard | uint32_t offset = 12;
|
832 | 9a64fbe4 | bellard | #endif
|
833 | 9a64fbe4 | bellard | env->nip = 0x01000000 | (kernel_addr + offset);
|
834 | 9a64fbe4 | bellard | printf("Start address: 0x%08x\n", env->nip);
|
835 | 9a64fbe4 | bellard | } |
836 | 9a64fbe4 | bellard | env->gpr[1] = env->nip + (1 << 22); |
837 | 7fd7b91f | bellard | p = phys_ram_base + stack_addr; |
838 | 9a64fbe4 | bellard | put_long(p - 32, stack_addr);
|
839 | 9a64fbe4 | bellard | env->gpr[1] -= 32; |
840 | 9a64fbe4 | bellard | printf("Kernel starts at 0x%08x stack 0x%08x\n", env->nip, env->gpr[1]); |
841 | 9a64fbe4 | bellard | /* We want all lower address not to be translated */
|
842 | 9a64fbe4 | bellard | setup_BAT(env, 1, 0x00000000, 0x00000000, 0x010000000, 1, 1, 2); |
843 | 9a64fbe4 | bellard | /* We also need a BAT to access OF */
|
844 | 9a64fbe4 | bellard | setup_BAT(env, 2, 0xFFFE0000, mem_size - 131072, 131072, 1, 0, 1); |
845 | 9a64fbe4 | bellard | /* Setup OF entry point */
|
846 | 9a64fbe4 | bellard | { |
847 | 9a64fbe4 | bellard | char *p;
|
848 | 9a64fbe4 | bellard | p = (char *)phys_ram_base + mem_size - 131072; |
849 | 9a64fbe4 | bellard | /* Special opcode to call OF */
|
850 | 9a64fbe4 | bellard | *p++ = 0x18; *p++ = 0x00; *p++ = 0x00; *p++ = 0x02; |
851 | 9a64fbe4 | bellard | /* blr */
|
852 | 9a64fbe4 | bellard | *p++ = 0x4E; *p++ = 0x80; *p++ = 0x00; *p++ = 0x20; |
853 | 9a64fbe4 | bellard | } |
854 | 9a64fbe4 | bellard | env->gpr[5] = 0xFFFE0000; |
855 | 9a64fbe4 | bellard | /* Register translations */
|
856 | 9a64fbe4 | bellard | { |
857 | 9a64fbe4 | bellard | OF_transl_t translations[3] = {
|
858 | 9a64fbe4 | bellard | { 0x01000000, 0x00400000, kernel_addr, 0x00000002, }, |
859 | 9a64fbe4 | bellard | { 0x00000000, 0x01000000, 0x00000000, 0x00000002, }, |
860 | 9a64fbe4 | bellard | { 0xFFFE0000, 0x00020000, mem_size - (128 * 1024), |
861 | 9a64fbe4 | bellard | 0x00000001, },
|
862 | 9a64fbe4 | bellard | }; |
863 | 9a64fbe4 | bellard | OF_register_translations(3, translations);
|
864 | 9a64fbe4 | bellard | } |
865 | 9a64fbe4 | bellard | /* Quite artificial, for now */
|
866 | 9a64fbe4 | bellard | OF_register_bus("isa", "isa"); |
867 | 9a64fbe4 | bellard | OF_register_serial("isa", "serial", 4, 0x3f8); |
868 | 9a64fbe4 | bellard | OF_register_stdio("serial", "serial"); |
869 | 9a64fbe4 | bellard | /* Set up RTAS service */
|
870 | 9a64fbe4 | bellard | RTAS_init(); |
871 | 9a64fbe4 | bellard | /* Command line: let's put it just over the stack */
|
872 | a541f297 | bellard | #if 0
|
873 | a541f297 | bellard | #if 0
|
874 | 7fd7b91f | bellard | p = phys_ram_base + kernel_addr +
|
875 | 7fd7b91f | bellard | kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1);
|
876 | a541f297 | bellard | #else
|
877 | 7fd7b91f | bellard | p = phys_ram_base + kernel_addr + 0x400000;
|
878 | a541f297 | bellard | #endif
|
879 | 9a64fbe4 | bellard | #if 1 |
880 | 9a64fbe4 | bellard | sprintf(p, "console=ttyS0,9600 root=%02x%02x mem=%dM",
|
881 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].major,
|
882 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].minor,
|
883 | a541f297 | bellard | mem_size >> 20);
|
884 | 9a64fbe4 | bellard | #else
|
885 | 9a64fbe4 | bellard | sprintf(p, "console=ttyS0,9600 root=%s mem=%dM ne2000=0x300,9",
|
886 | 9a64fbe4 | bellard | boot_devs[boot_device - 'a'].name,
|
887 | a541f297 | bellard | mem_size >> 20);
|
888 | 9a64fbe4 | bellard | #endif
|
889 | 9a64fbe4 | bellard | OF_register_bootargs(p); |
890 | 9a64fbe4 | bellard | #endif
|
891 | a541f297 | bellard | #endif
|
892 | 9a64fbe4 | bellard | } |
893 | 9a64fbe4 | bellard | |
894 | 9a64fbe4 | bellard | void PPC_end_init (void) |
895 | 9a64fbe4 | bellard | { |
896 | 9a64fbe4 | bellard | VGA_init(); |
897 | 9a64fbe4 | bellard | } |
898 | a541f297 | bellard | |
899 | a541f297 | bellard | /* PC hardware initialisation */
|
900 | a541f297 | bellard | void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, |
901 | a541f297 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
902 | a541f297 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
903 | a541f297 | bellard | const char *initrd_filename) |
904 | a541f297 | bellard | { |
905 | a541f297 | bellard | char buf[1024]; |
906 | a541f297 | bellard | int PPC_io_memory;
|
907 | a541f297 | bellard | int ret, linux_boot, initrd_size, i, nb_nics1, fd;
|
908 | a541f297 | bellard | |
909 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
910 | a541f297 | bellard | |
911 | a541f297 | bellard | /* allocate RAM */
|
912 | a541f297 | bellard | cpu_register_physical_memory(0, ram_size, 0); |
913 | a541f297 | bellard | |
914 | a541f297 | bellard | if (linux_boot) {
|
915 | a541f297 | bellard | /* now we can load the kernel */
|
916 | a541f297 | bellard | ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
917 | a541f297 | bellard | if (ret < 0) { |
918 | a541f297 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
919 | a541f297 | bellard | kernel_filename); |
920 | a541f297 | bellard | exit(1);
|
921 | a541f297 | bellard | } |
922 | a541f297 | bellard | /* load initrd */
|
923 | a541f297 | bellard | initrd_size = 0;
|
924 | a541f297 | bellard | #if 0
|
925 | a541f297 | bellard | if (initrd_filename) {
|
926 | a541f297 | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
|
927 | a541f297 | bellard | if (initrd_size < 0) {
|
928 | a541f297 | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
929 | a541f297 | bellard | initrd_filename);
|
930 | a541f297 | bellard | exit(1);
|
931 | a541f297 | bellard | }
|
932 | a541f297 | bellard | }
|
933 | a541f297 | bellard | #endif
|
934 | a541f297 | bellard | PPC_init_hw(/*env,*/ ram_size, KERNEL_LOAD_ADDR, ret,
|
935 | a541f297 | bellard | KERNEL_STACK_ADDR, boot_device, initrd_filename); |
936 | a541f297 | bellard | } else {
|
937 | a541f297 | bellard | /* allocate ROM */
|
938 | a541f297 | bellard | // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
|
939 | a541f297 | bellard | snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME); |
940 | a541f297 | bellard | printf("load BIOS at %p\n", phys_ram_base + 0x000f0000); |
941 | a541f297 | bellard | ret = load_image(buf, phys_ram_base + 0x000f0000);
|
942 | a541f297 | bellard | if (ret != 0x10000) { |
943 | a541f297 | bellard | fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
|
944 | a541f297 | bellard | buf, ret); |
945 | a541f297 | bellard | exit(1);
|
946 | a541f297 | bellard | } |
947 | a541f297 | bellard | } |
948 | a541f297 | bellard | |
949 | a541f297 | bellard | /* init basic PC hardware */
|
950 | a541f297 | bellard | vga_initialize(ds, phys_ram_base + ram_size, ram_size, |
951 | a541f297 | bellard | vga_ram_size); |
952 | a541f297 | bellard | rtc_init(0x70, 8); |
953 | a541f297 | bellard | pic_init(); |
954 | a541f297 | bellard | // pit_init(0x40, 0);
|
955 | a541f297 | bellard | |
956 | a541f297 | bellard | fd = serial_open_device(); |
957 | a541f297 | bellard | serial_init(0x3f8, 4, fd); |
958 | a541f297 | bellard | #if 1 |
959 | a541f297 | bellard | nb_nics1 = nb_nics; |
960 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
961 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
962 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
963 | a541f297 | bellard | ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
964 | a541f297 | bellard | } |
965 | a541f297 | bellard | #endif
|
966 | a541f297 | bellard | |
967 | a541f297 | bellard | for(i = 0; i < 2; i++) { |
968 | a541f297 | bellard | ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
969 | a541f297 | bellard | bs_table[2 * i], bs_table[2 * i + 1]); |
970 | a541f297 | bellard | } |
971 | a541f297 | bellard | kbd_init(); |
972 | a541f297 | bellard | AUD_init(); |
973 | a541f297 | bellard | DMA_init(); |
974 | a541f297 | bellard | // SB16_init();
|
975 | a541f297 | bellard | |
976 | a541f297 | bellard | fdctrl_init(6, 2, 0, 0x3f0, fd_table); |
977 | a541f297 | bellard | |
978 | a541f297 | bellard | /* Register 64 kB of IO space */
|
979 | a541f297 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
|
980 | a541f297 | bellard | cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory); |
981 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
982 | a541f297 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, NULL); |
983 | a541f297 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, NULL); |
984 | a541f297 | bellard | /* System control ports */
|
985 | a541f297 | bellard | register_ioport_write(0x0092, 0x1, 1, &PREP_io_800_writeb, NULL); |
986 | a541f297 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, NULL); |
987 | a541f297 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, NULL); |
988 | a541f297 | bellard | /* PCI intack location (0xfef00000 / 0xbffffff0) */
|
989 | a541f297 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_ioB_read, PPC_ioB_write);
|
990 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
991 | a541f297 | bellard | // cpu_register_physical_memory(0xFEF00000, 0x4, PPC_io_memory);
|
992 | a541f297 | bellard | prep_NVRAM_init(); |
993 | a541f297 | bellard | |
994 | a541f297 | bellard | PPC_end_init(); |
995 | a541f297 | bellard | } |