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1 | ff1f20a3 | bellard | /*
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2 | ff1f20a3 | bellard | * dyngen helpers
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3 | ff1f20a3 | bellard | *
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4 | ff1f20a3 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ff1f20a3 | bellard | *
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6 | ff1f20a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | ff1f20a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ff1f20a3 | bellard | * License as published by the Free Software Foundation; either
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9 | ff1f20a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ff1f20a3 | bellard | *
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11 | ff1f20a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ff1f20a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ff1f20a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ff1f20a3 | bellard | * Lesser General Public License for more details.
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15 | ff1f20a3 | bellard | *
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16 | ff1f20a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | ff1f20a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | ff1f20a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | ff1f20a3 | bellard | */
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20 | ff1f20a3 | bellard | |
21 | 03daf0e3 | bellard | int __op_param1, __op_param2, __op_param3;
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22 | c4687878 | bellard | int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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23 | c106152d | bellard | int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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24 | 03daf0e3 | bellard | |
25 | 03daf0e3 | bellard | #ifdef __i386__
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26 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
27 | 03daf0e3 | bellard | { |
28 | 03daf0e3 | bellard | } |
29 | 03daf0e3 | bellard | #endif
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30 | 03daf0e3 | bellard | |
31 | bc51c5c9 | bellard | #ifdef __x86_64__
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32 | bc51c5c9 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
33 | bc51c5c9 | bellard | { |
34 | bc51c5c9 | bellard | } |
35 | bc51c5c9 | bellard | #endif
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36 | bc51c5c9 | bellard | |
37 | 03daf0e3 | bellard | #ifdef __s390__
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38 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
39 | 03daf0e3 | bellard | { |
40 | 03daf0e3 | bellard | } |
41 | 03daf0e3 | bellard | #endif
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42 | 03daf0e3 | bellard | |
43 | 03daf0e3 | bellard | #ifdef __ia64__
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44 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
45 | 03daf0e3 | bellard | { |
46 | 03daf0e3 | bellard | } |
47 | 03daf0e3 | bellard | #endif
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48 | 03daf0e3 | bellard | |
49 | 03daf0e3 | bellard | #ifdef __powerpc__
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50 | 03daf0e3 | bellard | |
51 | 03daf0e3 | bellard | #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
52 | 03daf0e3 | bellard | |
53 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
54 | 03daf0e3 | bellard | { |
55 | 03daf0e3 | bellard | unsigned long p; |
56 | 03daf0e3 | bellard | |
57 | 03daf0e3 | bellard | p = start & ~(MIN_CACHE_LINE_SIZE - 1);
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58 | 03daf0e3 | bellard | stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
59 | 03daf0e3 | bellard | |
60 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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61 | 03daf0e3 | bellard | asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
62 | 03daf0e3 | bellard | } |
63 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
64 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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65 | 03daf0e3 | bellard | asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
66 | 03daf0e3 | bellard | } |
67 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
68 | 03daf0e3 | bellard | asm volatile ("isync" : : : "memory"); |
69 | 03daf0e3 | bellard | } |
70 | 03daf0e3 | bellard | #endif
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71 | 03daf0e3 | bellard | |
72 | 03daf0e3 | bellard | #ifdef __alpha__
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73 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
74 | 03daf0e3 | bellard | { |
75 | 03daf0e3 | bellard | asm ("imb"); |
76 | 03daf0e3 | bellard | } |
77 | 03daf0e3 | bellard | #endif
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78 | 03daf0e3 | bellard | |
79 | 03daf0e3 | bellard | #ifdef __sparc__
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80 | 03daf0e3 | bellard | |
81 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
82 | 03daf0e3 | bellard | { |
83 | 03daf0e3 | bellard | unsigned long p; |
84 | 03daf0e3 | bellard | |
85 | 03daf0e3 | bellard | p = start & ~(8UL - 1UL); |
86 | 03daf0e3 | bellard | stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
87 | 03daf0e3 | bellard | |
88 | 03daf0e3 | bellard | for (; p < stop; p += 8) |
89 | 03daf0e3 | bellard | __asm__ __volatile__("flush\t%0" : : "r" (p)); |
90 | 03daf0e3 | bellard | } |
91 | 03daf0e3 | bellard | |
92 | 03daf0e3 | bellard | #endif
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93 | 03daf0e3 | bellard | |
94 | 03daf0e3 | bellard | #ifdef __arm__
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95 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
96 | 03daf0e3 | bellard | { |
97 | 03daf0e3 | bellard | register unsigned long _beg __asm ("a1") = start; |
98 | 03daf0e3 | bellard | register unsigned long _end __asm ("a2") = stop; |
99 | 03daf0e3 | bellard | register unsigned long _flg __asm ("a3") = 0; |
100 | 03daf0e3 | bellard | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
101 | 03daf0e3 | bellard | } |
102 | 03daf0e3 | bellard | #endif
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103 | 03daf0e3 | bellard | |
104 | 38e584a0 | bellard | #ifdef __mc68000
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105 | 38e584a0 | bellard | #include <asm/cachectl.h> |
106 | 38e584a0 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
107 | 38e584a0 | bellard | { |
108 | 38e584a0 | bellard | cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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109 | 38e584a0 | bellard | } |
110 | 38e584a0 | bellard | #endif
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111 | 38e584a0 | bellard | |
112 | ff1f20a3 | bellard | #ifdef __alpha__
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113 | ff1f20a3 | bellard | |
114 | ff1f20a3 | bellard | register int gp asm("$29"); |
115 | ff1f20a3 | bellard | |
116 | ff1f20a3 | bellard | static inline void immediate_ldah(void *p, int val) { |
117 | ff1f20a3 | bellard | uint32_t *dest = p; |
118 | ff1f20a3 | bellard | long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
119 | ff1f20a3 | bellard | |
120 | ff1f20a3 | bellard | *dest &= ~0xffff;
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121 | ff1f20a3 | bellard | *dest |= high; |
122 | ff1f20a3 | bellard | *dest |= 31 << 16; |
123 | ff1f20a3 | bellard | } |
124 | ff1f20a3 | bellard | static inline void immediate_lda(void *dest, int val) { |
125 | ff1f20a3 | bellard | *(uint16_t *) dest = val; |
126 | ff1f20a3 | bellard | } |
127 | ff1f20a3 | bellard | void fix_bsr(void *p, int offset) { |
128 | ff1f20a3 | bellard | uint32_t *dest = p; |
129 | ff1f20a3 | bellard | *dest &= ~((1 << 21) - 1); |
130 | ff1f20a3 | bellard | *dest |= (offset >> 2) & ((1 << 21) - 1); |
131 | ff1f20a3 | bellard | } |
132 | ff1f20a3 | bellard | |
133 | ff1f20a3 | bellard | #endif /* __alpha__ */ |
134 | ff1f20a3 | bellard | |
135 | ff1f20a3 | bellard | #ifdef __arm__
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136 | ff1f20a3 | bellard | |
137 | ff1f20a3 | bellard | #define MAX_OP_SIZE (128 * 4) /* in bytes */ |
138 | ff1f20a3 | bellard | /* max size of the code that can be generated without calling arm_flush_ldr */
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139 | ff1f20a3 | bellard | #define MAX_FRAG_SIZE (1024 * 4) |
140 | ff1f20a3 | bellard | //#define MAX_FRAG_SIZE (135 * 4) /* for testing */
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141 | ff1f20a3 | bellard | |
142 | ff1f20a3 | bellard | typedef struct LDREntry { |
143 | ff1f20a3 | bellard | uint8_t *ptr; |
144 | ff1f20a3 | bellard | uint32_t *data_ptr; |
145 | ff1f20a3 | bellard | } LDREntry; |
146 | ff1f20a3 | bellard | |
147 | ff1f20a3 | bellard | static LDREntry arm_ldr_table[1024]; |
148 | ff1f20a3 | bellard | static uint32_t arm_data_table[1024]; |
149 | ff1f20a3 | bellard | |
150 | ff1f20a3 | bellard | extern char exec_loop; |
151 | ff1f20a3 | bellard | |
152 | ff1f20a3 | bellard | static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
153 | ff1f20a3 | bellard | { |
154 | ff1f20a3 | bellard | *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
155 | ff1f20a3 | bellard | } |
156 | ff1f20a3 | bellard | |
157 | ff1f20a3 | bellard | static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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158 | ff1f20a3 | bellard | LDREntry *ldr_start, LDREntry *ldr_end, |
159 | ff1f20a3 | bellard | uint32_t *data_start, uint32_t *data_end, |
160 | ff1f20a3 | bellard | int gen_jmp)
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161 | ff1f20a3 | bellard | { |
162 | ff1f20a3 | bellard | LDREntry *le; |
163 | ff1f20a3 | bellard | uint32_t *ptr; |
164 | ff1f20a3 | bellard | int offset, data_size, target;
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165 | ff1f20a3 | bellard | uint8_t *data_ptr; |
166 | ff1f20a3 | bellard | uint32_t insn; |
167 | ff1f20a3 | bellard | |
168 | ff1f20a3 | bellard | data_size = (uint8_t *)data_end - (uint8_t *)data_start; |
169 | ff1f20a3 | bellard | |
170 | 9621339d | bellard | if (gen_jmp) {
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171 | ff1f20a3 | bellard | /* generate branch to skip the data */
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172 | ff1f20a3 | bellard | if (data_size == 0) |
173 | ff1f20a3 | bellard | return gen_code_ptr;
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174 | ff1f20a3 | bellard | target = (long)gen_code_ptr + data_size + 4; |
175 | ff1f20a3 | bellard | arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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176 | ff1f20a3 | bellard | gen_code_ptr += 4;
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177 | ff1f20a3 | bellard | } |
178 | ff1f20a3 | bellard | |
179 | ff1f20a3 | bellard | /* copy the data */
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180 | ff1f20a3 | bellard | data_ptr = gen_code_ptr; |
181 | ff1f20a3 | bellard | memcpy(gen_code_ptr, data_start, data_size); |
182 | ff1f20a3 | bellard | gen_code_ptr += data_size; |
183 | ff1f20a3 | bellard | |
184 | ff1f20a3 | bellard | /* patch the ldr to point to the data */
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185 | ff1f20a3 | bellard | for(le = ldr_start; le < ldr_end; le++) {
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186 | ff1f20a3 | bellard | ptr = (uint32_t *)le->ptr; |
187 | ff1f20a3 | bellard | offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
188 | ff1f20a3 | bellard | (unsigned long)data_ptr - |
189 | ff1f20a3 | bellard | (unsigned long)ptr - 8; |
190 | ff1f20a3 | bellard | insn = *ptr & ~(0xfff | 0x00800000); |
191 | ff1f20a3 | bellard | if (offset < 0) { |
192 | ff1f20a3 | bellard | offset = - offset; |
193 | ff1f20a3 | bellard | } else {
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194 | ff1f20a3 | bellard | insn |= 0x00800000;
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195 | ff1f20a3 | bellard | } |
196 | ff1f20a3 | bellard | if (offset > 0xfff) { |
197 | ff1f20a3 | bellard | fprintf(stderr, "Error ldr offset\n");
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198 | ff1f20a3 | bellard | abort(); |
199 | ff1f20a3 | bellard | } |
200 | ff1f20a3 | bellard | insn |= offset; |
201 | ff1f20a3 | bellard | *ptr = insn; |
202 | ff1f20a3 | bellard | } |
203 | ff1f20a3 | bellard | return gen_code_ptr;
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204 | ff1f20a3 | bellard | } |
205 | ff1f20a3 | bellard | |
206 | ff1f20a3 | bellard | #endif /* __arm__ */ |