root / hw / cirrus_vga.c @ a8d3431a
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1 | e6e5ad80 | bellard | /*
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2 | aeb3c85f | bellard | * QEMU Cirrus CLGD 54xx VGA Emulator.
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3 | e6e5ad80 | bellard | *
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4 | e6e5ad80 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | aeb3c85f | bellard | * Copyright (c) 2004 Makoto Suzuki (suzu)
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6 | e6e5ad80 | bellard | *
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7 | e6e5ad80 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | e6e5ad80 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | e6e5ad80 | bellard | * in the Software without restriction, including without limitation the rights
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10 | e6e5ad80 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | e6e5ad80 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | e6e5ad80 | bellard | * furnished to do so, subject to the following conditions:
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13 | e6e5ad80 | bellard | *
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14 | e6e5ad80 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | e6e5ad80 | bellard | * all copies or substantial portions of the Software.
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16 | e6e5ad80 | bellard | *
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17 | e6e5ad80 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | e6e5ad80 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | e6e5ad80 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | e6e5ad80 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | e6e5ad80 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | e6e5ad80 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | e6e5ad80 | bellard | * THE SOFTWARE.
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24 | e6e5ad80 | bellard | */
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25 | aeb3c85f | bellard | /*
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26 | aeb3c85f | bellard | * Reference: Finn Thogersons' VGADOC4b
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27 | aeb3c85f | bellard | * available at http://home.worldonline.dk/~finth/
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28 | aeb3c85f | bellard | */
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29 | e6e5ad80 | bellard | #include "vl.h" |
30 | e6e5ad80 | bellard | #include "vga_int.h" |
31 | e6e5ad80 | bellard | |
32 | a5082316 | bellard | /*
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33 | a5082316 | bellard | * TODO:
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34 | a5082316 | bellard | * - add support for WRITEMASK (GR2F)
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35 | a5082316 | bellard | * - optimize linear mappings
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36 | a5082316 | bellard | * - optimize bitblt functions
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37 | a5082316 | bellard | */
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38 | a5082316 | bellard | |
39 | e36f36e1 | bellard | //#define DEBUG_CIRRUS
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40 | a21ae81d | bellard | //#define DEBUG_BITBLT
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41 | e36f36e1 | bellard | |
42 | e6e5ad80 | bellard | /***************************************
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43 | e6e5ad80 | bellard | *
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44 | e6e5ad80 | bellard | * definitions
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45 | e6e5ad80 | bellard | *
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46 | e6e5ad80 | bellard | ***************************************/
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47 | e6e5ad80 | bellard | |
48 | e6e5ad80 | bellard | #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
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49 | e6e5ad80 | bellard | |
50 | e6e5ad80 | bellard | // ID
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51 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5422 (0x23<<2) |
52 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5426 (0x24<<2) |
53 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5424 (0x25<<2) |
54 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5428 (0x26<<2) |
55 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5430 (0x28<<2) |
56 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5434 (0x2A<<2) |
57 | a21ae81d | bellard | #define CIRRUS_ID_CLGD5436 (0x2B<<2) |
58 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
59 | e6e5ad80 | bellard | |
60 | e6e5ad80 | bellard | // sequencer 0x07
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61 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_VGA 0x00 |
62 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_SVGA 0x01 |
63 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_MASK 0x0e |
64 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_8 0x00 |
65 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
66 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_24 0x04 |
67 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16 0x06 |
68 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_32 0x08 |
69 | e6e5ad80 | bellard | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
70 | e6e5ad80 | bellard | |
71 | e6e5ad80 | bellard | // sequencer 0x0f
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72 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_512k 0x08 |
73 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_1M 0x10 |
74 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_2M 0x18 |
75 | e6e5ad80 | bellard | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
76 | e6e5ad80 | bellard | |
77 | e6e5ad80 | bellard | // sequencer 0x12
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78 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_SHOW 0x01 |
79 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_HIDDENPEL 0x02 |
80 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
81 | e6e5ad80 | bellard | |
82 | e6e5ad80 | bellard | // sequencer 0x17
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83 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBFAST 0x10 |
84 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_PCI 0x20 |
85 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
86 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_ISA 0x38 |
87 | e6e5ad80 | bellard | #define CIRRUS_MMIO_ENABLE 0x04 |
88 | e6e5ad80 | bellard | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
89 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
90 | e6e5ad80 | bellard | |
91 | e6e5ad80 | bellard | // control 0x0b
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92 | e6e5ad80 | bellard | #define CIRRUS_BANKING_DUAL 0x01 |
93 | e6e5ad80 | bellard | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
94 | e6e5ad80 | bellard | |
95 | e6e5ad80 | bellard | // control 0x30
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96 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_BACKWARDS 0x01 |
97 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
98 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
99 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
100 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
101 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
102 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
103 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
104 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
105 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
106 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
107 | e6e5ad80 | bellard | |
108 | e6e5ad80 | bellard | // control 0x31
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109 | e6e5ad80 | bellard | #define CIRRUS_BLT_BUSY 0x01 |
110 | e6e5ad80 | bellard | #define CIRRUS_BLT_START 0x02 |
111 | e6e5ad80 | bellard | #define CIRRUS_BLT_RESET 0x04 |
112 | e6e5ad80 | bellard | #define CIRRUS_BLT_FIFOUSED 0x10 |
113 | a5082316 | bellard | #define CIRRUS_BLT_AUTOSTART 0x80 |
114 | e6e5ad80 | bellard | |
115 | e6e5ad80 | bellard | // control 0x32
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116 | e6e5ad80 | bellard | #define CIRRUS_ROP_0 0x00 |
117 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_DST 0x05 |
118 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOP 0x06 |
119 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
120 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTDST 0x0b |
121 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC 0x0d |
122 | e6e5ad80 | bellard | #define CIRRUS_ROP_1 0x0e |
123 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
124 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_XOR_DST 0x59 |
125 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_DST 0x6d |
126 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
127 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
128 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
129 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC 0xd0 |
130 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
131 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
132 | e6e5ad80 | bellard | |
133 | a5082316 | bellard | #define CIRRUS_ROP_NOP_INDEX 2 |
134 | a5082316 | bellard | #define CIRRUS_ROP_SRC_INDEX 5 |
135 | a5082316 | bellard | |
136 | a21ae81d | bellard | // control 0x33
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137 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
138 | 4c8732d7 | bellard | #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
139 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
140 | a21ae81d | bellard | |
141 | e6e5ad80 | bellard | // memory-mapped IO
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142 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
143 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
144 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
145 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
146 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
147 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
148 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
149 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
150 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
151 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODE 0x18 // byte |
152 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTROP 0x1a // byte |
153 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
154 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
155 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
156 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
157 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
158 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
159 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
160 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
161 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
162 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
163 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
164 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
165 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
166 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
167 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
168 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
169 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
170 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
171 | e6e5ad80 | bellard | |
172 | e6e5ad80 | bellard | // PCI 0x00: vendor, 0x02: device
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173 | e6e5ad80 | bellard | #define PCI_VENDOR_CIRRUS 0x1013 |
174 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5462 0x00d0 |
175 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5465 0x00d6 |
176 | a21ae81d | bellard | |
177 | e6e5ad80 | bellard | // PCI 0x04: command(word), 0x06(word): status
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178 | e6e5ad80 | bellard | #define PCI_COMMAND_IOACCESS 0x0001 |
179 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMACCESS 0x0002 |
180 | e6e5ad80 | bellard | #define PCI_COMMAND_BUSMASTER 0x0004 |
181 | e6e5ad80 | bellard | #define PCI_COMMAND_SPECIALCYCLE 0x0008 |
182 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMWRITEINVALID 0x0010 |
183 | e6e5ad80 | bellard | #define PCI_COMMAND_PALETTESNOOPING 0x0020 |
184 | e6e5ad80 | bellard | #define PCI_COMMAND_PARITYDETECTION 0x0040 |
185 | e6e5ad80 | bellard | #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080 |
186 | e6e5ad80 | bellard | #define PCI_COMMAND_SERR 0x0100 |
187 | e6e5ad80 | bellard | #define PCI_COMMAND_BACKTOBACKTRANS 0x0200 |
188 | e6e5ad80 | bellard | // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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189 | e6e5ad80 | bellard | #define PCI_CLASS_BASE_DISPLAY 0x03 |
190 | e6e5ad80 | bellard | // PCI 0x08, 0x00ff0000
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191 | e6e5ad80 | bellard | #define PCI_CLASS_SUB_VGA 0x00 |
192 | e6e5ad80 | bellard | // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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193 | e6e5ad80 | bellard | #define PCI_CLASS_HEADERTYPE_00h 0x00 |
194 | e6e5ad80 | bellard | // 0x10-0x3f (headertype 00h)
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195 | e6e5ad80 | bellard | // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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196 | e6e5ad80 | bellard | // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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197 | e6e5ad80 | bellard | #define PCI_MAP_MEM 0x0 |
198 | e6e5ad80 | bellard | #define PCI_MAP_IO 0x1 |
199 | e6e5ad80 | bellard | #define PCI_MAP_MEM_ADDR_MASK (~0xf) |
200 | e6e5ad80 | bellard | #define PCI_MAP_IO_ADDR_MASK (~0x3) |
201 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT 0x0 |
202 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1 |
203 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_64BIT 0x4 |
204 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8 |
205 | e6e5ad80 | bellard | // PCI 0x28: cardbus CIS pointer
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206 | e6e5ad80 | bellard | // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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207 | e6e5ad80 | bellard | // PCI 0x30: expansion ROM base address
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208 | e6e5ad80 | bellard | #define PCI_ROMBIOS_ENABLED 0x1 |
209 | e6e5ad80 | bellard | // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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210 | e6e5ad80 | bellard | // PCI 0x38: reserved
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211 | e6e5ad80 | bellard | // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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212 | e6e5ad80 | bellard | |
213 | a21ae81d | bellard | #define CIRRUS_PNPMMIO_SIZE 0x1000 |
214 | e6e5ad80 | bellard | |
215 | e6e5ad80 | bellard | |
216 | e6e5ad80 | bellard | /* I/O and memory hook */
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217 | e6e5ad80 | bellard | #define CIRRUS_HOOK_NOT_HANDLED 0 |
218 | e6e5ad80 | bellard | #define CIRRUS_HOOK_HANDLED 1 |
219 | e6e5ad80 | bellard | |
220 | a5082316 | bellard | struct CirrusVGAState;
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221 | a5082316 | bellard | typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, |
222 | a5082316 | bellard | uint8_t * dst, const uint8_t * src,
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223 | e6e5ad80 | bellard | int dstpitch, int srcpitch, |
224 | e6e5ad80 | bellard | int bltwidth, int bltheight); |
225 | a5082316 | bellard | typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
226 | a5082316 | bellard | uint8_t *dst, int dst_pitch, int width, int height); |
227 | e6e5ad80 | bellard | |
228 | e6e5ad80 | bellard | typedef struct CirrusVGAState { |
229 | 4e3e9d0b | bellard | VGA_STATE_COMMON |
230 | e6e5ad80 | bellard | |
231 | e6e5ad80 | bellard | int cirrus_linear_io_addr;
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232 | a5082316 | bellard | int cirrus_linear_bitblt_io_addr;
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233 | e6e5ad80 | bellard | int cirrus_mmio_io_addr;
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234 | e6e5ad80 | bellard | uint32_t cirrus_addr_mask; |
235 | 78e127ef | bellard | uint32_t linear_mmio_mask; |
236 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr0; |
237 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr1; |
238 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_lockindex; |
239 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_data; |
240 | e6e5ad80 | bellard | uint32_t cirrus_bank_base[2];
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241 | e6e5ad80 | bellard | uint32_t cirrus_bank_limit[2];
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242 | e6e5ad80 | bellard | uint8_t cirrus_hidden_palette[48];
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243 | a5082316 | bellard | uint32_t hw_cursor_x; |
244 | a5082316 | bellard | uint32_t hw_cursor_y; |
245 | e6e5ad80 | bellard | int cirrus_blt_pixelwidth;
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246 | e6e5ad80 | bellard | int cirrus_blt_width;
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247 | e6e5ad80 | bellard | int cirrus_blt_height;
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248 | e6e5ad80 | bellard | int cirrus_blt_dstpitch;
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249 | e6e5ad80 | bellard | int cirrus_blt_srcpitch;
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250 | a5082316 | bellard | uint32_t cirrus_blt_fgcol; |
251 | a5082316 | bellard | uint32_t cirrus_blt_bgcol; |
252 | e6e5ad80 | bellard | uint32_t cirrus_blt_dstaddr; |
253 | e6e5ad80 | bellard | uint32_t cirrus_blt_srcaddr; |
254 | e6e5ad80 | bellard | uint8_t cirrus_blt_mode; |
255 | a5082316 | bellard | uint8_t cirrus_blt_modeext; |
256 | e6e5ad80 | bellard | cirrus_bitblt_rop_t cirrus_rop; |
257 | a5082316 | bellard | #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
258 | e6e5ad80 | bellard | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
259 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr; |
260 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr_end; |
261 | e6e5ad80 | bellard | uint32_t cirrus_srccounter; |
262 | a5082316 | bellard | /* hwcursor display state */
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263 | a5082316 | bellard | int last_hw_cursor_size;
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264 | a5082316 | bellard | int last_hw_cursor_x;
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265 | a5082316 | bellard | int last_hw_cursor_y;
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266 | a5082316 | bellard | int last_hw_cursor_y_start;
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267 | a5082316 | bellard | int last_hw_cursor_y_end;
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268 | 78e127ef | bellard | int real_vram_size; /* XXX: suppress that */ |
269 | 8926b517 | bellard | CPUWriteMemoryFunc **cirrus_linear_write; |
270 | e6e5ad80 | bellard | } CirrusVGAState; |
271 | e6e5ad80 | bellard | |
272 | e6e5ad80 | bellard | typedef struct PCICirrusVGAState { |
273 | e6e5ad80 | bellard | PCIDevice dev; |
274 | e6e5ad80 | bellard | CirrusVGAState cirrus_vga; |
275 | e6e5ad80 | bellard | } PCICirrusVGAState; |
276 | e6e5ad80 | bellard | |
277 | a5082316 | bellard | static uint8_t rop_to_index[256]; |
278 | a5082316 | bellard | |
279 | e6e5ad80 | bellard | /***************************************
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280 | e6e5ad80 | bellard | *
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281 | e6e5ad80 | bellard | * prototypes.
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282 | e6e5ad80 | bellard | *
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283 | e6e5ad80 | bellard | ***************************************/
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284 | e6e5ad80 | bellard | |
285 | e6e5ad80 | bellard | |
286 | 8926b517 | bellard | static void cirrus_bitblt_reset(CirrusVGAState *s); |
287 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s); |
288 | e6e5ad80 | bellard | |
289 | e6e5ad80 | bellard | /***************************************
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290 | e6e5ad80 | bellard | *
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291 | e6e5ad80 | bellard | * raster operations
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292 | e6e5ad80 | bellard | *
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293 | e6e5ad80 | bellard | ***************************************/
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294 | e6e5ad80 | bellard | |
295 | a5082316 | bellard | static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
296 | a5082316 | bellard | uint8_t *dst,const uint8_t *src,
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297 | a5082316 | bellard | int dstpitch,int srcpitch, |
298 | a5082316 | bellard | int bltwidth,int bltheight) |
299 | a5082316 | bellard | { |
300 | e6e5ad80 | bellard | } |
301 | e6e5ad80 | bellard | |
302 | a5082316 | bellard | static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
303 | a5082316 | bellard | uint8_t *dst, |
304 | a5082316 | bellard | int dstpitch, int bltwidth,int bltheight) |
305 | e6e5ad80 | bellard | { |
306 | a5082316 | bellard | } |
307 | e6e5ad80 | bellard | |
308 | a5082316 | bellard | #define ROP_NAME 0 |
309 | a5082316 | bellard | #define ROP_OP(d, s) d = 0 |
310 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
311 | e6e5ad80 | bellard | |
312 | a5082316 | bellard | #define ROP_NAME src_and_dst
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313 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) & (d)
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314 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
315 | e6e5ad80 | bellard | |
316 | a5082316 | bellard | #define ROP_NAME src_and_notdst
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317 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) & (~(d))
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318 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
319 | e6e5ad80 | bellard | |
320 | a5082316 | bellard | #define ROP_NAME notdst
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321 | a5082316 | bellard | #define ROP_OP(d, s) d = ~(d)
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322 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
323 | e6e5ad80 | bellard | |
324 | a5082316 | bellard | #define ROP_NAME src
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325 | a5082316 | bellard | #define ROP_OP(d, s) d = s
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326 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
327 | e6e5ad80 | bellard | |
328 | a5082316 | bellard | #define ROP_NAME 1 |
329 | 4c8732d7 | bellard | #define ROP_OP(d, s) d = ~0 |
330 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
331 | a5082316 | bellard | |
332 | a5082316 | bellard | #define ROP_NAME notsrc_and_dst
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333 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) & (d)
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334 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
335 | a5082316 | bellard | |
336 | a5082316 | bellard | #define ROP_NAME src_xor_dst
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337 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) ^ (d)
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338 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
339 | a5082316 | bellard | |
340 | a5082316 | bellard | #define ROP_NAME src_or_dst
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341 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) | (d)
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342 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
343 | a5082316 | bellard | |
344 | a5082316 | bellard | #define ROP_NAME notsrc_or_notdst
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345 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) | (~(d))
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346 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
347 | a5082316 | bellard | |
348 | a5082316 | bellard | #define ROP_NAME src_notxor_dst
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349 | a5082316 | bellard | #define ROP_OP(d, s) d = ~((s) ^ (d))
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350 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
351 | e6e5ad80 | bellard | |
352 | a5082316 | bellard | #define ROP_NAME src_or_notdst
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353 | a5082316 | bellard | #define ROP_OP(d, s) d = (s) | (~(d))
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354 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
355 | a5082316 | bellard | |
356 | a5082316 | bellard | #define ROP_NAME notsrc
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357 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s))
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358 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
359 | a5082316 | bellard | |
360 | a5082316 | bellard | #define ROP_NAME notsrc_or_dst
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361 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) | (d)
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362 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
363 | a5082316 | bellard | |
364 | a5082316 | bellard | #define ROP_NAME notsrc_and_notdst
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365 | a5082316 | bellard | #define ROP_OP(d, s) d = (~(s)) & (~(d))
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366 | a5082316 | bellard | #include "cirrus_vga_rop.h" |
367 | a5082316 | bellard | |
368 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { |
369 | a5082316 | bellard | cirrus_bitblt_rop_fwd_0, |
370 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_dst, |
371 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
372 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_notdst, |
373 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notdst, |
374 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src, |
375 | a5082316 | bellard | cirrus_bitblt_rop_fwd_1, |
376 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_dst, |
377 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_xor_dst, |
378 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_dst, |
379 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_notdst, |
380 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_notxor_dst, |
381 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_notdst, |
382 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc, |
383 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_dst, |
384 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_notdst, |
385 | a5082316 | bellard | }; |
386 | a5082316 | bellard | |
387 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { |
388 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_0, |
389 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_dst, |
390 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
391 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_notdst, |
392 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notdst, |
393 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src, |
394 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_1, |
395 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_dst, |
396 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_xor_dst, |
397 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_dst, |
398 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_notdst, |
399 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_notxor_dst, |
400 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_notdst, |
401 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc, |
402 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_dst, |
403 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_notdst, |
404 | a5082316 | bellard | }; |
405 | a5082316 | bellard | |
406 | a5082316 | bellard | #define ROP2(name) {\
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407 | a5082316 | bellard | name ## _8,\ |
408 | a5082316 | bellard | name ## _16,\ |
409 | a5082316 | bellard | name ## _24,\ |
410 | a5082316 | bellard | name ## _32,\ |
411 | a5082316 | bellard | } |
412 | a5082316 | bellard | |
413 | a5082316 | bellard | #define ROP_NOP2(func) {\
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414 | a5082316 | bellard | func,\ |
415 | a5082316 | bellard | func,\ |
416 | a5082316 | bellard | func,\ |
417 | a5082316 | bellard | func,\ |
418 | a5082316 | bellard | } |
419 | a5082316 | bellard | |
420 | e69390ce | bellard | static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
421 | e69390ce | bellard | ROP2(cirrus_patternfill_0), |
422 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_dst), |
423 | e69390ce | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
424 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_notdst), |
425 | e69390ce | bellard | ROP2(cirrus_patternfill_notdst), |
426 | e69390ce | bellard | ROP2(cirrus_patternfill_src), |
427 | e69390ce | bellard | ROP2(cirrus_patternfill_1), |
428 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_dst), |
429 | e69390ce | bellard | ROP2(cirrus_patternfill_src_xor_dst), |
430 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_dst), |
431 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_notdst), |
432 | e69390ce | bellard | ROP2(cirrus_patternfill_src_notxor_dst), |
433 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_notdst), |
434 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc), |
435 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_dst), |
436 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_notdst), |
437 | e69390ce | bellard | }; |
438 | e69390ce | bellard | |
439 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
440 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_0), |
441 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_dst), |
442 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
443 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_notdst), |
444 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notdst), |
445 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src), |
446 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_1), |
447 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_dst), |
448 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_xor_dst), |
449 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_dst), |
450 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), |
451 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_notxor_dst), |
452 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_notdst), |
453 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc), |
454 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_dst), |
455 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
456 | a5082316 | bellard | }; |
457 | a5082316 | bellard | |
458 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
459 | a5082316 | bellard | ROP2(cirrus_colorexpand_0), |
460 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_dst), |
461 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
462 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_notdst), |
463 | a5082316 | bellard | ROP2(cirrus_colorexpand_notdst), |
464 | a5082316 | bellard | ROP2(cirrus_colorexpand_src), |
465 | a5082316 | bellard | ROP2(cirrus_colorexpand_1), |
466 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_dst), |
467 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_xor_dst), |
468 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_dst), |
469 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_notdst), |
470 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_notxor_dst), |
471 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_notdst), |
472 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc), |
473 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_dst), |
474 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_notdst), |
475 | a5082316 | bellard | }; |
476 | a5082316 | bellard | |
477 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
478 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_0), |
479 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
480 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
481 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
482 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notdst), |
483 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src), |
484 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_1), |
485 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
486 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
487 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
488 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
489 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
490 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
491 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
492 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
493 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
494 | b30d4608 | bellard | }; |
495 | b30d4608 | bellard | |
496 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
497 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_0), |
498 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_dst), |
499 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
500 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
501 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notdst), |
502 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src), |
503 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_1), |
504 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
505 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
506 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_dst), |
507 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
508 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
509 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
510 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc), |
511 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
512 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
513 | b30d4608 | bellard | }; |
514 | b30d4608 | bellard | |
515 | a5082316 | bellard | static const cirrus_fill_t cirrus_fill[16][4] = { |
516 | a5082316 | bellard | ROP2(cirrus_fill_0), |
517 | a5082316 | bellard | ROP2(cirrus_fill_src_and_dst), |
518 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_fill_nop), |
519 | a5082316 | bellard | ROP2(cirrus_fill_src_and_notdst), |
520 | a5082316 | bellard | ROP2(cirrus_fill_notdst), |
521 | a5082316 | bellard | ROP2(cirrus_fill_src), |
522 | a5082316 | bellard | ROP2(cirrus_fill_1), |
523 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_dst), |
524 | a5082316 | bellard | ROP2(cirrus_fill_src_xor_dst), |
525 | a5082316 | bellard | ROP2(cirrus_fill_src_or_dst), |
526 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_notdst), |
527 | a5082316 | bellard | ROP2(cirrus_fill_src_notxor_dst), |
528 | a5082316 | bellard | ROP2(cirrus_fill_src_or_notdst), |
529 | a5082316 | bellard | ROP2(cirrus_fill_notsrc), |
530 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_dst), |
531 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_notdst), |
532 | a5082316 | bellard | }; |
533 | a5082316 | bellard | |
534 | a5082316 | bellard | static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) |
535 | e6e5ad80 | bellard | { |
536 | a5082316 | bellard | unsigned int color; |
537 | a5082316 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
538 | a5082316 | bellard | case 1: |
539 | a5082316 | bellard | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; |
540 | a5082316 | bellard | break;
|
541 | a5082316 | bellard | case 2: |
542 | a5082316 | bellard | color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8); |
543 | a5082316 | bellard | s->cirrus_blt_fgcol = le16_to_cpu(color); |
544 | a5082316 | bellard | break;
|
545 | a5082316 | bellard | case 3: |
546 | a5082316 | bellard | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
547 | a5082316 | bellard | (s->gr[0x11] << 8) | (s->gr[0x13] << 16); |
548 | a5082316 | bellard | break;
|
549 | a5082316 | bellard | default:
|
550 | a5082316 | bellard | case 4: |
551 | a5082316 | bellard | color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) | |
552 | a5082316 | bellard | (s->gr[0x13] << 16) | (s->gr[0x15] << 24); |
553 | a5082316 | bellard | s->cirrus_blt_fgcol = le32_to_cpu(color); |
554 | a5082316 | bellard | break;
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555 | e6e5ad80 | bellard | } |
556 | e6e5ad80 | bellard | } |
557 | e6e5ad80 | bellard | |
558 | a5082316 | bellard | static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
559 | e6e5ad80 | bellard | { |
560 | a5082316 | bellard | unsigned int color; |
561 | e6e5ad80 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
562 | e6e5ad80 | bellard | case 1: |
563 | a5082316 | bellard | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
564 | a5082316 | bellard | break;
|
565 | e6e5ad80 | bellard | case 2: |
566 | a5082316 | bellard | color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8); |
567 | a5082316 | bellard | s->cirrus_blt_bgcol = le16_to_cpu(color); |
568 | a5082316 | bellard | break;
|
569 | e6e5ad80 | bellard | case 3: |
570 | a5082316 | bellard | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
571 | a5082316 | bellard | (s->gr[0x10] << 8) | (s->gr[0x12] << 16); |
572 | a5082316 | bellard | break;
|
573 | e6e5ad80 | bellard | default:
|
574 | a5082316 | bellard | case 4: |
575 | a5082316 | bellard | color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) | |
576 | a5082316 | bellard | (s->gr[0x12] << 16) | (s->gr[0x14] << 24); |
577 | a5082316 | bellard | s->cirrus_blt_bgcol = le32_to_cpu(color); |
578 | a5082316 | bellard | break;
|
579 | e6e5ad80 | bellard | } |
580 | e6e5ad80 | bellard | } |
581 | e6e5ad80 | bellard | |
582 | e6e5ad80 | bellard | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
583 | e6e5ad80 | bellard | int off_pitch, int bytesperline, |
584 | e6e5ad80 | bellard | int lines)
|
585 | e6e5ad80 | bellard | { |
586 | e6e5ad80 | bellard | int y;
|
587 | e6e5ad80 | bellard | int off_cur;
|
588 | e6e5ad80 | bellard | int off_cur_end;
|
589 | e6e5ad80 | bellard | |
590 | e6e5ad80 | bellard | for (y = 0; y < lines; y++) { |
591 | e6e5ad80 | bellard | off_cur = off_begin; |
592 | e6e5ad80 | bellard | off_cur_end = off_cur + bytesperline; |
593 | e6e5ad80 | bellard | off_cur &= TARGET_PAGE_MASK; |
594 | e6e5ad80 | bellard | while (off_cur < off_cur_end) {
|
595 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + off_cur); |
596 | e6e5ad80 | bellard | off_cur += TARGET_PAGE_SIZE; |
597 | e6e5ad80 | bellard | } |
598 | e6e5ad80 | bellard | off_begin += off_pitch; |
599 | e6e5ad80 | bellard | } |
600 | e6e5ad80 | bellard | } |
601 | e6e5ad80 | bellard | |
602 | e6e5ad80 | bellard | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
603 | e6e5ad80 | bellard | const uint8_t * src)
|
604 | e6e5ad80 | bellard | { |
605 | e6e5ad80 | bellard | uint8_t *dst; |
606 | e6e5ad80 | bellard | |
607 | e6e5ad80 | bellard | dst = s->vram_ptr + s->cirrus_blt_dstaddr; |
608 | e69390ce | bellard | (*s->cirrus_rop) (s, dst, src, |
609 | e69390ce | bellard | s->cirrus_blt_dstpitch, 0,
|
610 | e69390ce | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
611 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
612 | e69390ce | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
613 | e69390ce | bellard | s->cirrus_blt_height); |
614 | e6e5ad80 | bellard | return 1; |
615 | e6e5ad80 | bellard | } |
616 | e6e5ad80 | bellard | |
617 | a21ae81d | bellard | /* fill */
|
618 | a21ae81d | bellard | |
619 | a5082316 | bellard | static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
620 | a21ae81d | bellard | { |
621 | a5082316 | bellard | cirrus_fill_t rop_func; |
622 | a21ae81d | bellard | |
623 | a5082316 | bellard | rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
624 | a5082316 | bellard | rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr, |
625 | a5082316 | bellard | s->cirrus_blt_dstpitch, |
626 | a5082316 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
627 | a21ae81d | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
628 | a21ae81d | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
629 | a21ae81d | bellard | s->cirrus_blt_height); |
630 | a21ae81d | bellard | cirrus_bitblt_reset(s); |
631 | a21ae81d | bellard | return 1; |
632 | a21ae81d | bellard | } |
633 | a21ae81d | bellard | |
634 | e6e5ad80 | bellard | /***************************************
|
635 | e6e5ad80 | bellard | *
|
636 | e6e5ad80 | bellard | * bitblt (video-to-video)
|
637 | e6e5ad80 | bellard | *
|
638 | e6e5ad80 | bellard | ***************************************/
|
639 | e6e5ad80 | bellard | |
640 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
641 | e6e5ad80 | bellard | { |
642 | e6e5ad80 | bellard | return cirrus_bitblt_common_patterncopy(s,
|
643 | e69390ce | bellard | s->vram_ptr + |
644 | e69390ce | bellard | (s->cirrus_blt_srcaddr & ~7));
|
645 | e6e5ad80 | bellard | } |
646 | e6e5ad80 | bellard | |
647 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
648 | e6e5ad80 | bellard | { |
649 | a5082316 | bellard | (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr, |
650 | e6e5ad80 | bellard | s->vram_ptr + s->cirrus_blt_srcaddr, |
651 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
652 | e6e5ad80 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
653 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
654 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
655 | e6e5ad80 | bellard | s->cirrus_blt_height); |
656 | e6e5ad80 | bellard | return 1; |
657 | e6e5ad80 | bellard | } |
658 | e6e5ad80 | bellard | |
659 | e6e5ad80 | bellard | /***************************************
|
660 | e6e5ad80 | bellard | *
|
661 | e6e5ad80 | bellard | * bitblt (cpu-to-video)
|
662 | e6e5ad80 | bellard | *
|
663 | e6e5ad80 | bellard | ***************************************/
|
664 | e6e5ad80 | bellard | |
665 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
666 | e6e5ad80 | bellard | { |
667 | e6e5ad80 | bellard | int copy_count;
|
668 | a5082316 | bellard | uint8_t *end_ptr; |
669 | a5082316 | bellard | |
670 | e6e5ad80 | bellard | if (s->cirrus_srccounter > 0) { |
671 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
672 | a5082316 | bellard | cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); |
673 | a5082316 | bellard | the_end:
|
674 | a5082316 | bellard | s->cirrus_srccounter = 0;
|
675 | a5082316 | bellard | cirrus_bitblt_reset(s); |
676 | a5082316 | bellard | } else {
|
677 | a5082316 | bellard | /* at least one scan line */
|
678 | a5082316 | bellard | do {
|
679 | a5082316 | bellard | (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr, |
680 | a5082316 | bellard | s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); |
681 | a5082316 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
682 | a5082316 | bellard | s->cirrus_blt_width, 1);
|
683 | a5082316 | bellard | s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; |
684 | a5082316 | bellard | s->cirrus_srccounter -= s->cirrus_blt_srcpitch; |
685 | a5082316 | bellard | if (s->cirrus_srccounter <= 0) |
686 | a5082316 | bellard | goto the_end;
|
687 | a5082316 | bellard | /* more bytes than needed can be transfered because of
|
688 | a5082316 | bellard | word alignment, so we keep them for the next line */
|
689 | a5082316 | bellard | /* XXX: keep alignment to speed up transfer */
|
690 | a5082316 | bellard | end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
691 | a5082316 | bellard | copy_count = s->cirrus_srcptr_end - end_ptr; |
692 | a5082316 | bellard | memmove(s->cirrus_bltbuf, end_ptr, copy_count); |
693 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; |
694 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
695 | a5082316 | bellard | } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
|
696 | a5082316 | bellard | } |
697 | e6e5ad80 | bellard | } |
698 | e6e5ad80 | bellard | } |
699 | e6e5ad80 | bellard | |
700 | e6e5ad80 | bellard | /***************************************
|
701 | e6e5ad80 | bellard | *
|
702 | e6e5ad80 | bellard | * bitblt wrapper
|
703 | e6e5ad80 | bellard | *
|
704 | e6e5ad80 | bellard | ***************************************/
|
705 | e6e5ad80 | bellard | |
706 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s) |
707 | e6e5ad80 | bellard | { |
708 | e6e5ad80 | bellard | s->gr[0x31] &=
|
709 | e6e5ad80 | bellard | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
710 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
711 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
712 | e6e5ad80 | bellard | s->cirrus_srccounter = 0;
|
713 | 8926b517 | bellard | cirrus_update_memory_access(s); |
714 | e6e5ad80 | bellard | } |
715 | e6e5ad80 | bellard | |
716 | e6e5ad80 | bellard | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
717 | e6e5ad80 | bellard | { |
718 | a5082316 | bellard | int w;
|
719 | a5082316 | bellard | |
720 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
721 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
722 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
723 | e6e5ad80 | bellard | |
724 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
725 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
726 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8;
|
727 | e6e5ad80 | bellard | } else {
|
728 | b30d4608 | bellard | /* XXX: check for 24 bpp */
|
729 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
730 | e6e5ad80 | bellard | } |
731 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
732 | e6e5ad80 | bellard | } else {
|
733 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
734 | a5082316 | bellard | w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
735 | a5082316 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
|
736 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
737 | a5082316 | bellard | else
|
738 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 7) >> 3); |
739 | e6e5ad80 | bellard | } else {
|
740 | c9c0eae8 | bellard | /* always align input size to 32 bits */
|
741 | c9c0eae8 | bellard | s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; |
742 | e6e5ad80 | bellard | } |
743 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
744 | e6e5ad80 | bellard | } |
745 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf; |
746 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
747 | 8926b517 | bellard | cirrus_update_memory_access(s); |
748 | e6e5ad80 | bellard | return 1; |
749 | e6e5ad80 | bellard | } |
750 | e6e5ad80 | bellard | |
751 | e6e5ad80 | bellard | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
752 | e6e5ad80 | bellard | { |
753 | e6e5ad80 | bellard | /* XXX */
|
754 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
755 | e6e5ad80 | bellard | printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
756 | e6e5ad80 | bellard | #endif
|
757 | e6e5ad80 | bellard | return 0; |
758 | e6e5ad80 | bellard | } |
759 | e6e5ad80 | bellard | |
760 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
761 | e6e5ad80 | bellard | { |
762 | e6e5ad80 | bellard | int ret;
|
763 | e6e5ad80 | bellard | |
764 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
765 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_patterncopy(s); |
766 | e6e5ad80 | bellard | } else {
|
767 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_copy(s); |
768 | e6e5ad80 | bellard | } |
769 | e6e5ad80 | bellard | if (ret)
|
770 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
771 | e6e5ad80 | bellard | return ret;
|
772 | e6e5ad80 | bellard | } |
773 | e6e5ad80 | bellard | |
774 | e6e5ad80 | bellard | static void cirrus_bitblt_start(CirrusVGAState * s) |
775 | e6e5ad80 | bellard | { |
776 | e6e5ad80 | bellard | uint8_t blt_rop; |
777 | e6e5ad80 | bellard | |
778 | a5082316 | bellard | s->gr[0x31] |= CIRRUS_BLT_BUSY;
|
779 | a5082316 | bellard | |
780 | e6e5ad80 | bellard | s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1; |
781 | e6e5ad80 | bellard | s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1; |
782 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8)); |
783 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8)); |
784 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr = |
785 | e6e5ad80 | bellard | (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16)); |
786 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr = |
787 | e6e5ad80 | bellard | (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16)); |
788 | e6e5ad80 | bellard | s->cirrus_blt_mode = s->gr[0x30];
|
789 | a5082316 | bellard | s->cirrus_blt_modeext = s->gr[0x33];
|
790 | e6e5ad80 | bellard | blt_rop = s->gr[0x32];
|
791 | e6e5ad80 | bellard | |
792 | a21ae81d | bellard | #ifdef DEBUG_BITBLT
|
793 | 0b74ed78 | bellard | printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
|
794 | a21ae81d | bellard | blt_rop, |
795 | a21ae81d | bellard | s->cirrus_blt_mode, |
796 | a5082316 | bellard | s->cirrus_blt_modeext, |
797 | a21ae81d | bellard | s->cirrus_blt_width, |
798 | a21ae81d | bellard | s->cirrus_blt_height, |
799 | a21ae81d | bellard | s->cirrus_blt_dstpitch, |
800 | a21ae81d | bellard | s->cirrus_blt_srcpitch, |
801 | a21ae81d | bellard | s->cirrus_blt_dstaddr, |
802 | a5082316 | bellard | s->cirrus_blt_srcaddr, |
803 | a5082316 | bellard | s->sr[0x2f]);
|
804 | a21ae81d | bellard | #endif
|
805 | a21ae81d | bellard | |
806 | e6e5ad80 | bellard | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
807 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH8:
|
808 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 1;
|
809 | e6e5ad80 | bellard | break;
|
810 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH16:
|
811 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 2;
|
812 | e6e5ad80 | bellard | break;
|
813 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH24:
|
814 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 3;
|
815 | e6e5ad80 | bellard | break;
|
816 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH32:
|
817 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 4;
|
818 | e6e5ad80 | bellard | break;
|
819 | e6e5ad80 | bellard | default:
|
820 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
821 | e6e5ad80 | bellard | printf("cirrus: bitblt - pixel width is unknown\n");
|
822 | e6e5ad80 | bellard | #endif
|
823 | e6e5ad80 | bellard | goto bitblt_ignore;
|
824 | e6e5ad80 | bellard | } |
825 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
826 | e6e5ad80 | bellard | |
827 | e6e5ad80 | bellard | if ((s->
|
828 | e6e5ad80 | bellard | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
829 | e6e5ad80 | bellard | CIRRUS_BLTMODE_MEMSYSDEST)) |
830 | e6e5ad80 | bellard | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
831 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
832 | e6e5ad80 | bellard | printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
833 | e6e5ad80 | bellard | #endif
|
834 | e6e5ad80 | bellard | goto bitblt_ignore;
|
835 | e6e5ad80 | bellard | } |
836 | e6e5ad80 | bellard | |
837 | a5082316 | bellard | if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
|
838 | a21ae81d | bellard | (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
839 | a21ae81d | bellard | CIRRUS_BLTMODE_TRANSPARENTCOMP | |
840 | a21ae81d | bellard | CIRRUS_BLTMODE_PATTERNCOPY | |
841 | a21ae81d | bellard | CIRRUS_BLTMODE_COLOREXPAND)) == |
842 | a21ae81d | bellard | (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { |
843 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
844 | a5082316 | bellard | cirrus_bitblt_solidfill(s, blt_rop); |
845 | e6e5ad80 | bellard | } else {
|
846 | a5082316 | bellard | if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
|
847 | a5082316 | bellard | CIRRUS_BLTMODE_PATTERNCOPY)) == |
848 | a5082316 | bellard | CIRRUS_BLTMODE_COLOREXPAND) { |
849 | a5082316 | bellard | |
850 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
851 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
852 | 4c8732d7 | bellard | cirrus_bitblt_bgcol(s); |
853 | b30d4608 | bellard | else
|
854 | 4c8732d7 | bellard | cirrus_bitblt_fgcol(s); |
855 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
856 | a5082316 | bellard | } else {
|
857 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
858 | a5082316 | bellard | cirrus_bitblt_bgcol(s); |
859 | a5082316 | bellard | s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
860 | a5082316 | bellard | } |
861 | e69390ce | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
862 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
863 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
864 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
865 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
866 | b30d4608 | bellard | else
|
867 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
868 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
869 | b30d4608 | bellard | } else {
|
870 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
871 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
872 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
873 | b30d4608 | bellard | } |
874 | b30d4608 | bellard | } else {
|
875 | b30d4608 | bellard | s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
876 | b30d4608 | bellard | } |
877 | a21ae81d | bellard | } else {
|
878 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
879 | a5082316 | bellard | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
880 | a5082316 | bellard | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
881 | a5082316 | bellard | s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; |
882 | a5082316 | bellard | } else {
|
883 | a5082316 | bellard | s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; |
884 | a5082316 | bellard | } |
885 | a21ae81d | bellard | } |
886 | a21ae81d | bellard | |
887 | a21ae81d | bellard | // setup bitblt engine.
|
888 | a21ae81d | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
889 | a21ae81d | bellard | if (!cirrus_bitblt_cputovideo(s))
|
890 | a21ae81d | bellard | goto bitblt_ignore;
|
891 | a21ae81d | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
892 | a21ae81d | bellard | if (!cirrus_bitblt_videotocpu(s))
|
893 | a21ae81d | bellard | goto bitblt_ignore;
|
894 | a21ae81d | bellard | } else {
|
895 | a21ae81d | bellard | if (!cirrus_bitblt_videotovideo(s))
|
896 | a21ae81d | bellard | goto bitblt_ignore;
|
897 | a21ae81d | bellard | } |
898 | e6e5ad80 | bellard | } |
899 | e6e5ad80 | bellard | return;
|
900 | e6e5ad80 | bellard | bitblt_ignore:;
|
901 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
902 | e6e5ad80 | bellard | } |
903 | e6e5ad80 | bellard | |
904 | e6e5ad80 | bellard | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
905 | e6e5ad80 | bellard | { |
906 | e6e5ad80 | bellard | unsigned old_value;
|
907 | e6e5ad80 | bellard | |
908 | e6e5ad80 | bellard | old_value = s->gr[0x31];
|
909 | e6e5ad80 | bellard | s->gr[0x31] = reg_value;
|
910 | e6e5ad80 | bellard | |
911 | e6e5ad80 | bellard | if (((old_value & CIRRUS_BLT_RESET) != 0) && |
912 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
913 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
914 | e6e5ad80 | bellard | } else if (((old_value & CIRRUS_BLT_START) == 0) && |
915 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_START) != 0)) {
|
916 | e6e5ad80 | bellard | cirrus_bitblt_start(s); |
917 | e6e5ad80 | bellard | } |
918 | e6e5ad80 | bellard | } |
919 | e6e5ad80 | bellard | |
920 | e6e5ad80 | bellard | |
921 | e6e5ad80 | bellard | /***************************************
|
922 | e6e5ad80 | bellard | *
|
923 | e6e5ad80 | bellard | * basic parameters
|
924 | e6e5ad80 | bellard | *
|
925 | e6e5ad80 | bellard | ***************************************/
|
926 | e6e5ad80 | bellard | |
927 | e6e5ad80 | bellard | static void cirrus_get_offsets(VGAState *s1, |
928 | e6e5ad80 | bellard | uint32_t *pline_offset, |
929 | e6e5ad80 | bellard | uint32_t *pstart_addr) |
930 | e6e5ad80 | bellard | { |
931 | e6e5ad80 | bellard | CirrusVGAState * s = (CirrusVGAState *)s1; |
932 | e6e5ad80 | bellard | uint32_t start_addr; |
933 | e6e5ad80 | bellard | uint32_t line_offset; |
934 | e6e5ad80 | bellard | |
935 | e6e5ad80 | bellard | line_offset = s->cr[0x13]
|
936 | e36f36e1 | bellard | | ((s->cr[0x1b] & 0x10) << 4); |
937 | e6e5ad80 | bellard | line_offset <<= 3;
|
938 | e6e5ad80 | bellard | *pline_offset = line_offset; |
939 | e6e5ad80 | bellard | |
940 | e6e5ad80 | bellard | start_addr = (s->cr[0x0c] << 8) |
941 | e6e5ad80 | bellard | | s->cr[0x0d]
|
942 | e6e5ad80 | bellard | | ((s->cr[0x1b] & 0x01) << 16) |
943 | e6e5ad80 | bellard | | ((s->cr[0x1b] & 0x0c) << 15) |
944 | e6e5ad80 | bellard | | ((s->cr[0x1d] & 0x80) << 12); |
945 | e6e5ad80 | bellard | *pstart_addr = start_addr; |
946 | e6e5ad80 | bellard | } |
947 | e6e5ad80 | bellard | |
948 | e6e5ad80 | bellard | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
949 | e6e5ad80 | bellard | { |
950 | e6e5ad80 | bellard | uint32_t ret = 16;
|
951 | e6e5ad80 | bellard | |
952 | e6e5ad80 | bellard | switch (s->cirrus_hidden_dac_data & 0xf) { |
953 | e6e5ad80 | bellard | case 0: |
954 | e6e5ad80 | bellard | ret = 15;
|
955 | e6e5ad80 | bellard | break; /* Sierra HiColor */ |
956 | e6e5ad80 | bellard | case 1: |
957 | e6e5ad80 | bellard | ret = 16;
|
958 | e6e5ad80 | bellard | break; /* XGA HiColor */ |
959 | e6e5ad80 | bellard | default:
|
960 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
961 | e6e5ad80 | bellard | printf("cirrus: invalid DAC value %x in 16bpp\n",
|
962 | e6e5ad80 | bellard | (s->cirrus_hidden_dac_data & 0xf));
|
963 | e6e5ad80 | bellard | #endif
|
964 | e6e5ad80 | bellard | ret = 15; /* XXX */ |
965 | e6e5ad80 | bellard | break;
|
966 | e6e5ad80 | bellard | } |
967 | e6e5ad80 | bellard | return ret;
|
968 | e6e5ad80 | bellard | } |
969 | e6e5ad80 | bellard | |
970 | e6e5ad80 | bellard | static int cirrus_get_bpp(VGAState *s1) |
971 | e6e5ad80 | bellard | { |
972 | e6e5ad80 | bellard | CirrusVGAState * s = (CirrusVGAState *)s1; |
973 | e6e5ad80 | bellard | uint32_t ret = 8;
|
974 | e6e5ad80 | bellard | |
975 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) != 0) { |
976 | e6e5ad80 | bellard | /* Cirrus SVGA */
|
977 | e6e5ad80 | bellard | switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
978 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_8:
|
979 | e6e5ad80 | bellard | ret = 8;
|
980 | e6e5ad80 | bellard | break;
|
981 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
982 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
983 | e6e5ad80 | bellard | break;
|
984 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_24:
|
985 | e6e5ad80 | bellard | ret = 24;
|
986 | e6e5ad80 | bellard | break;
|
987 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16:
|
988 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
989 | e6e5ad80 | bellard | break;
|
990 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_32:
|
991 | e6e5ad80 | bellard | ret = 32;
|
992 | e6e5ad80 | bellard | break;
|
993 | e6e5ad80 | bellard | default:
|
994 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
995 | e6e5ad80 | bellard | printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]); |
996 | e6e5ad80 | bellard | #endif
|
997 | e6e5ad80 | bellard | ret = 8;
|
998 | e6e5ad80 | bellard | break;
|
999 | e6e5ad80 | bellard | } |
1000 | e6e5ad80 | bellard | } else {
|
1001 | e6e5ad80 | bellard | /* VGA */
|
1002 | aeb3c85f | bellard | ret = 0;
|
1003 | e6e5ad80 | bellard | } |
1004 | e6e5ad80 | bellard | |
1005 | e6e5ad80 | bellard | return ret;
|
1006 | e6e5ad80 | bellard | } |
1007 | e6e5ad80 | bellard | |
1008 | 78e127ef | bellard | static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight) |
1009 | 78e127ef | bellard | { |
1010 | 78e127ef | bellard | int width, height;
|
1011 | 78e127ef | bellard | |
1012 | 78e127ef | bellard | width = (s->cr[0x01] + 1) * 8; |
1013 | 78e127ef | bellard | height = s->cr[0x12] |
|
1014 | 78e127ef | bellard | ((s->cr[0x07] & 0x02) << 7) | |
1015 | 78e127ef | bellard | ((s->cr[0x07] & 0x40) << 3); |
1016 | 78e127ef | bellard | height = (height + 1);
|
1017 | 78e127ef | bellard | /* interlace support */
|
1018 | 78e127ef | bellard | if (s->cr[0x1a] & 0x01) |
1019 | 78e127ef | bellard | height = height * 2;
|
1020 | 78e127ef | bellard | *pwidth = width; |
1021 | 78e127ef | bellard | *pheight = height; |
1022 | 78e127ef | bellard | } |
1023 | 78e127ef | bellard | |
1024 | e6e5ad80 | bellard | /***************************************
|
1025 | e6e5ad80 | bellard | *
|
1026 | e6e5ad80 | bellard | * bank memory
|
1027 | e6e5ad80 | bellard | *
|
1028 | e6e5ad80 | bellard | ***************************************/
|
1029 | e6e5ad80 | bellard | |
1030 | e6e5ad80 | bellard | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1031 | e6e5ad80 | bellard | { |
1032 | e6e5ad80 | bellard | unsigned offset;
|
1033 | e6e5ad80 | bellard | unsigned limit;
|
1034 | e6e5ad80 | bellard | |
1035 | e6e5ad80 | bellard | if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */ |
1036 | e6e5ad80 | bellard | offset = s->gr[0x09 + bank_index];
|
1037 | e6e5ad80 | bellard | else /* single bank */ |
1038 | e6e5ad80 | bellard | offset = s->gr[0x09];
|
1039 | e6e5ad80 | bellard | |
1040 | e6e5ad80 | bellard | if ((s->gr[0x0b] & 0x20) != 0) |
1041 | e6e5ad80 | bellard | offset <<= 14;
|
1042 | e6e5ad80 | bellard | else
|
1043 | e6e5ad80 | bellard | offset <<= 12;
|
1044 | e6e5ad80 | bellard | |
1045 | e6e5ad80 | bellard | if (s->vram_size <= offset)
|
1046 | e6e5ad80 | bellard | limit = 0;
|
1047 | e6e5ad80 | bellard | else
|
1048 | e6e5ad80 | bellard | limit = s->vram_size - offset; |
1049 | e6e5ad80 | bellard | |
1050 | e6e5ad80 | bellard | if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1051 | e6e5ad80 | bellard | if (limit > 0x8000) { |
1052 | e6e5ad80 | bellard | offset += 0x8000;
|
1053 | e6e5ad80 | bellard | limit -= 0x8000;
|
1054 | e6e5ad80 | bellard | } else {
|
1055 | e6e5ad80 | bellard | limit = 0;
|
1056 | e6e5ad80 | bellard | } |
1057 | e6e5ad80 | bellard | } |
1058 | e6e5ad80 | bellard | |
1059 | e6e5ad80 | bellard | if (limit > 0) { |
1060 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = offset; |
1061 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = limit; |
1062 | e6e5ad80 | bellard | } else {
|
1063 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = 0;
|
1064 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = 0;
|
1065 | e6e5ad80 | bellard | } |
1066 | e6e5ad80 | bellard | } |
1067 | e6e5ad80 | bellard | |
1068 | e6e5ad80 | bellard | /***************************************
|
1069 | e6e5ad80 | bellard | *
|
1070 | e6e5ad80 | bellard | * I/O access between 0x3c4-0x3c5
|
1071 | e6e5ad80 | bellard | *
|
1072 | e6e5ad80 | bellard | ***************************************/
|
1073 | e6e5ad80 | bellard | |
1074 | e6e5ad80 | bellard | static int |
1075 | e6e5ad80 | bellard | cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1076 | e6e5ad80 | bellard | { |
1077 | e6e5ad80 | bellard | switch (reg_index) {
|
1078 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1079 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1080 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1081 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1082 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1083 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1084 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1085 | e6e5ad80 | bellard | *reg_value = s->sr[reg_index]; |
1086 | e6e5ad80 | bellard | break;
|
1087 | e6e5ad80 | bellard | case 0x10: |
1088 | e6e5ad80 | bellard | case 0x30: |
1089 | e6e5ad80 | bellard | case 0x50: |
1090 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1091 | e6e5ad80 | bellard | case 0x90: |
1092 | e6e5ad80 | bellard | case 0xb0: |
1093 | e6e5ad80 | bellard | case 0xd0: |
1094 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1095 | aeb3c85f | bellard | *reg_value = s->sr[0x10];
|
1096 | aeb3c85f | bellard | break;
|
1097 | e6e5ad80 | bellard | case 0x11: |
1098 | e6e5ad80 | bellard | case 0x31: |
1099 | e6e5ad80 | bellard | case 0x51: |
1100 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1101 | e6e5ad80 | bellard | case 0x91: |
1102 | e6e5ad80 | bellard | case 0xb1: |
1103 | e6e5ad80 | bellard | case 0xd1: |
1104 | a5082316 | bellard | case 0xf1: // Graphics Cursor Y |
1105 | aeb3c85f | bellard | *reg_value = s->sr[0x11];
|
1106 | aeb3c85f | bellard | break;
|
1107 | aeb3c85f | bellard | case 0x05: // ??? |
1108 | aeb3c85f | bellard | case 0x07: // Extended Sequencer Mode |
1109 | aeb3c85f | bellard | case 0x08: // EEPROM Control |
1110 | aeb3c85f | bellard | case 0x09: // Scratch Register 0 |
1111 | aeb3c85f | bellard | case 0x0a: // Scratch Register 1 |
1112 | aeb3c85f | bellard | case 0x0b: // VCLK 0 |
1113 | aeb3c85f | bellard | case 0x0c: // VCLK 1 |
1114 | aeb3c85f | bellard | case 0x0d: // VCLK 2 |
1115 | aeb3c85f | bellard | case 0x0e: // VCLK 3 |
1116 | aeb3c85f | bellard | case 0x0f: // DRAM Control |
1117 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1118 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1119 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1120 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1121 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1122 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1123 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1124 | e6e5ad80 | bellard | case 0x19: // Signal Generator Result |
1125 | e6e5ad80 | bellard | case 0x1a: // Signal Generator Result |
1126 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1127 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1128 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1129 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1130 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1131 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1132 | e6e5ad80 | bellard | printf("cirrus: handled inport sr_index %02x\n", reg_index);
|
1133 | e6e5ad80 | bellard | #endif
|
1134 | e6e5ad80 | bellard | *reg_value = s->sr[reg_index]; |
1135 | e6e5ad80 | bellard | break;
|
1136 | e6e5ad80 | bellard | default:
|
1137 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1138 | e6e5ad80 | bellard | printf("cirrus: inport sr_index %02x\n", reg_index);
|
1139 | e6e5ad80 | bellard | #endif
|
1140 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1141 | e6e5ad80 | bellard | break;
|
1142 | e6e5ad80 | bellard | } |
1143 | e6e5ad80 | bellard | |
1144 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1145 | e6e5ad80 | bellard | } |
1146 | e6e5ad80 | bellard | |
1147 | e6e5ad80 | bellard | static int |
1148 | e6e5ad80 | bellard | cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1149 | e6e5ad80 | bellard | { |
1150 | e6e5ad80 | bellard | switch (reg_index) {
|
1151 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1152 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1153 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1154 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1155 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1156 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1157 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1158 | e6e5ad80 | bellard | reg_value &= 0x17;
|
1159 | e6e5ad80 | bellard | if (reg_value == 0x12) { |
1160 | e6e5ad80 | bellard | s->sr[reg_index] = 0x12;
|
1161 | e6e5ad80 | bellard | } else {
|
1162 | e6e5ad80 | bellard | s->sr[reg_index] = 0x0f;
|
1163 | e6e5ad80 | bellard | } |
1164 | e6e5ad80 | bellard | break;
|
1165 | e6e5ad80 | bellard | case 0x10: |
1166 | e6e5ad80 | bellard | case 0x30: |
1167 | e6e5ad80 | bellard | case 0x50: |
1168 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1169 | e6e5ad80 | bellard | case 0x90: |
1170 | e6e5ad80 | bellard | case 0xb0: |
1171 | e6e5ad80 | bellard | case 0xd0: |
1172 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1173 | e6e5ad80 | bellard | s->sr[0x10] = reg_value;
|
1174 | a5082316 | bellard | s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5); |
1175 | e6e5ad80 | bellard | break;
|
1176 | e6e5ad80 | bellard | case 0x11: |
1177 | e6e5ad80 | bellard | case 0x31: |
1178 | e6e5ad80 | bellard | case 0x51: |
1179 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1180 | e6e5ad80 | bellard | case 0x91: |
1181 | e6e5ad80 | bellard | case 0xb1: |
1182 | e6e5ad80 | bellard | case 0xd1: |
1183 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1184 | e6e5ad80 | bellard | s->sr[0x11] = reg_value;
|
1185 | a5082316 | bellard | s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5); |
1186 | e6e5ad80 | bellard | break;
|
1187 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1188 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1189 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1190 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1191 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1192 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1193 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1194 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1195 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1196 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1197 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1198 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1199 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1200 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1201 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1202 | e6e5ad80 | bellard | case 0x19: // Signature Generator Result |
1203 | e6e5ad80 | bellard | case 0x1a: // Signature Generator Result |
1204 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1205 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1206 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1207 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1208 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1209 | e6e5ad80 | bellard | s->sr[reg_index] = reg_value; |
1210 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1211 | e6e5ad80 | bellard | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1212 | e6e5ad80 | bellard | reg_index, reg_value); |
1213 | e6e5ad80 | bellard | #endif
|
1214 | e6e5ad80 | bellard | break;
|
1215 | 8926b517 | bellard | case 0x17: // Configuration Readback and Extended Control |
1216 | 8926b517 | bellard | s->sr[reg_index] = reg_value; |
1217 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1218 | 8926b517 | bellard | break;
|
1219 | e6e5ad80 | bellard | default:
|
1220 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1221 | e6e5ad80 | bellard | printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
|
1222 | e6e5ad80 | bellard | reg_value); |
1223 | e6e5ad80 | bellard | #endif
|
1224 | e6e5ad80 | bellard | break;
|
1225 | e6e5ad80 | bellard | } |
1226 | e6e5ad80 | bellard | |
1227 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1228 | e6e5ad80 | bellard | } |
1229 | e6e5ad80 | bellard | |
1230 | e6e5ad80 | bellard | /***************************************
|
1231 | e6e5ad80 | bellard | *
|
1232 | e6e5ad80 | bellard | * I/O access at 0x3c6
|
1233 | e6e5ad80 | bellard | *
|
1234 | e6e5ad80 | bellard | ***************************************/
|
1235 | e6e5ad80 | bellard | |
1236 | e6e5ad80 | bellard | static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value) |
1237 | e6e5ad80 | bellard | { |
1238 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1239 | a21ae81d | bellard | if (++s->cirrus_hidden_dac_lockindex == 5) { |
1240 | a21ae81d | bellard | *reg_value = s->cirrus_hidden_dac_data; |
1241 | a21ae81d | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1242 | e6e5ad80 | bellard | } |
1243 | e6e5ad80 | bellard | } |
1244 | e6e5ad80 | bellard | |
1245 | e6e5ad80 | bellard | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1246 | e6e5ad80 | bellard | { |
1247 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1248 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = reg_value; |
1249 | a21ae81d | bellard | #if defined(DEBUG_CIRRUS)
|
1250 | e6e5ad80 | bellard | printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1251 | e6e5ad80 | bellard | #endif
|
1252 | e6e5ad80 | bellard | } |
1253 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1254 | e6e5ad80 | bellard | } |
1255 | e6e5ad80 | bellard | |
1256 | e6e5ad80 | bellard | /***************************************
|
1257 | e6e5ad80 | bellard | *
|
1258 | e6e5ad80 | bellard | * I/O access at 0x3c9
|
1259 | e6e5ad80 | bellard | *
|
1260 | e6e5ad80 | bellard | ***************************************/
|
1261 | e6e5ad80 | bellard | |
1262 | e6e5ad80 | bellard | static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value) |
1263 | e6e5ad80 | bellard | { |
1264 | e6e5ad80 | bellard | if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1265 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1266 | a5082316 | bellard | *reg_value = |
1267 | a5082316 | bellard | s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 + |
1268 | a5082316 | bellard | s->dac_sub_index]; |
1269 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
1270 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
1271 | e6e5ad80 | bellard | s->dac_read_index++; |
1272 | e6e5ad80 | bellard | } |
1273 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1274 | e6e5ad80 | bellard | } |
1275 | e6e5ad80 | bellard | |
1276 | e6e5ad80 | bellard | static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value) |
1277 | e6e5ad80 | bellard | { |
1278 | e6e5ad80 | bellard | if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1279 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1280 | e6e5ad80 | bellard | s->dac_cache[s->dac_sub_index] = reg_value; |
1281 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
1282 | a5082316 | bellard | memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3], |
1283 | a5082316 | bellard | s->dac_cache, 3);
|
1284 | a5082316 | bellard | /* XXX update cursor */
|
1285 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
1286 | e6e5ad80 | bellard | s->dac_write_index++; |
1287 | e6e5ad80 | bellard | } |
1288 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1289 | e6e5ad80 | bellard | } |
1290 | e6e5ad80 | bellard | |
1291 | e6e5ad80 | bellard | /***************************************
|
1292 | e6e5ad80 | bellard | *
|
1293 | e6e5ad80 | bellard | * I/O access between 0x3ce-0x3cf
|
1294 | e6e5ad80 | bellard | *
|
1295 | e6e5ad80 | bellard | ***************************************/
|
1296 | e6e5ad80 | bellard | |
1297 | e6e5ad80 | bellard | static int |
1298 | e6e5ad80 | bellard | cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1299 | e6e5ad80 | bellard | { |
1300 | e6e5ad80 | bellard | switch (reg_index) {
|
1301 | aeb3c85f | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1302 | aeb3c85f | bellard | *reg_value = s->cirrus_shadow_gr0; |
1303 | aeb3c85f | bellard | return CIRRUS_HOOK_HANDLED;
|
1304 | aeb3c85f | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1305 | aeb3c85f | bellard | *reg_value = s->cirrus_shadow_gr1; |
1306 | aeb3c85f | bellard | return CIRRUS_HOOK_HANDLED;
|
1307 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1308 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1309 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1310 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1311 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1312 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1313 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1314 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1315 | e6e5ad80 | bellard | default:
|
1316 | e6e5ad80 | bellard | break;
|
1317 | e6e5ad80 | bellard | } |
1318 | e6e5ad80 | bellard | |
1319 | e6e5ad80 | bellard | if (reg_index < 0x3a) { |
1320 | e6e5ad80 | bellard | *reg_value = s->gr[reg_index]; |
1321 | e6e5ad80 | bellard | } else {
|
1322 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1323 | e6e5ad80 | bellard | printf("cirrus: inport gr_index %02x\n", reg_index);
|
1324 | e6e5ad80 | bellard | #endif
|
1325 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1326 | e6e5ad80 | bellard | } |
1327 | e6e5ad80 | bellard | |
1328 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1329 | e6e5ad80 | bellard | } |
1330 | e6e5ad80 | bellard | |
1331 | e6e5ad80 | bellard | static int |
1332 | e6e5ad80 | bellard | cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1333 | e6e5ad80 | bellard | { |
1334 | a5082316 | bellard | #if defined(DEBUG_BITBLT) && 0 |
1335 | a5082316 | bellard | printf("gr%02x: %02x\n", reg_index, reg_value);
|
1336 | a5082316 | bellard | #endif
|
1337 | e6e5ad80 | bellard | switch (reg_index) {
|
1338 | e6e5ad80 | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1339 | aeb3c85f | bellard | s->cirrus_shadow_gr0 = reg_value; |
1340 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1341 | e6e5ad80 | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1342 | aeb3c85f | bellard | s->cirrus_shadow_gr1 = reg_value; |
1343 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1344 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1345 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1346 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1347 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1348 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1349 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1350 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1351 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1352 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x7f;
|
1353 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1354 | e6e5ad80 | bellard | break;
|
1355 | e6e5ad80 | bellard | case 0x09: // bank offset #0 |
1356 | e6e5ad80 | bellard | case 0x0A: // bank offset #1 |
1357 | 8926b517 | bellard | s->gr[reg_index] = reg_value; |
1358 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 0);
|
1359 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 1);
|
1360 | 8926b517 | bellard | break;
|
1361 | e6e5ad80 | bellard | case 0x0B: |
1362 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value; |
1363 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 0);
|
1364 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 1);
|
1365 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1366 | e6e5ad80 | bellard | break;
|
1367 | e6e5ad80 | bellard | case 0x10: // BGCOLOR 0x0000ff00 |
1368 | e6e5ad80 | bellard | case 0x11: // FGCOLOR 0x0000ff00 |
1369 | e6e5ad80 | bellard | case 0x12: // BGCOLOR 0x00ff0000 |
1370 | e6e5ad80 | bellard | case 0x13: // FGCOLOR 0x00ff0000 |
1371 | e6e5ad80 | bellard | case 0x14: // BGCOLOR 0xff000000 |
1372 | e6e5ad80 | bellard | case 0x15: // FGCOLOR 0xff000000 |
1373 | e6e5ad80 | bellard | case 0x20: // BLT WIDTH 0x0000ff |
1374 | e6e5ad80 | bellard | case 0x22: // BLT HEIGHT 0x0000ff |
1375 | e6e5ad80 | bellard | case 0x24: // BLT DEST PITCH 0x0000ff |
1376 | e6e5ad80 | bellard | case 0x26: // BLT SRC PITCH 0x0000ff |
1377 | e6e5ad80 | bellard | case 0x28: // BLT DEST ADDR 0x0000ff |
1378 | e6e5ad80 | bellard | case 0x29: // BLT DEST ADDR 0x00ff00 |
1379 | e6e5ad80 | bellard | case 0x2c: // BLT SRC ADDR 0x0000ff |
1380 | e6e5ad80 | bellard | case 0x2d: // BLT SRC ADDR 0x00ff00 |
1381 | a5082316 | bellard | case 0x2f: // BLT WRITEMASK |
1382 | e6e5ad80 | bellard | case 0x30: // BLT MODE |
1383 | e6e5ad80 | bellard | case 0x32: // RASTER OP |
1384 | a21ae81d | bellard | case 0x33: // BLT MODEEXT |
1385 | e6e5ad80 | bellard | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1386 | e6e5ad80 | bellard | case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1387 | e6e5ad80 | bellard | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1388 | e6e5ad80 | bellard | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1389 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value; |
1390 | e6e5ad80 | bellard | break;
|
1391 | e6e5ad80 | bellard | case 0x21: // BLT WIDTH 0x001f00 |
1392 | e6e5ad80 | bellard | case 0x23: // BLT HEIGHT 0x001f00 |
1393 | e6e5ad80 | bellard | case 0x25: // BLT DEST PITCH 0x001f00 |
1394 | e6e5ad80 | bellard | case 0x27: // BLT SRC PITCH 0x001f00 |
1395 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x1f;
|
1396 | e6e5ad80 | bellard | break;
|
1397 | e6e5ad80 | bellard | case 0x2a: // BLT DEST ADDR 0x3f0000 |
1398 | a5082316 | bellard | s->gr[reg_index] = reg_value & 0x3f;
|
1399 | a5082316 | bellard | /* if auto start mode, starts bit blt now */
|
1400 | a5082316 | bellard | if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
1401 | a5082316 | bellard | cirrus_bitblt_start(s); |
1402 | a5082316 | bellard | } |
1403 | a5082316 | bellard | break;
|
1404 | e6e5ad80 | bellard | case 0x2e: // BLT SRC ADDR 0x3f0000 |
1405 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x3f;
|
1406 | e6e5ad80 | bellard | break;
|
1407 | e6e5ad80 | bellard | case 0x31: // BLT STATUS/START |
1408 | e6e5ad80 | bellard | cirrus_write_bitblt(s, reg_value); |
1409 | e6e5ad80 | bellard | break;
|
1410 | e6e5ad80 | bellard | default:
|
1411 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1412 | e6e5ad80 | bellard | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1413 | e6e5ad80 | bellard | reg_value); |
1414 | e6e5ad80 | bellard | #endif
|
1415 | e6e5ad80 | bellard | break;
|
1416 | e6e5ad80 | bellard | } |
1417 | e6e5ad80 | bellard | |
1418 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1419 | e6e5ad80 | bellard | } |
1420 | e6e5ad80 | bellard | |
1421 | e6e5ad80 | bellard | /***************************************
|
1422 | e6e5ad80 | bellard | *
|
1423 | e6e5ad80 | bellard | * I/O access between 0x3d4-0x3d5
|
1424 | e6e5ad80 | bellard | *
|
1425 | e6e5ad80 | bellard | ***************************************/
|
1426 | e6e5ad80 | bellard | |
1427 | e6e5ad80 | bellard | static int |
1428 | e6e5ad80 | bellard | cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1429 | e6e5ad80 | bellard | { |
1430 | e6e5ad80 | bellard | switch (reg_index) {
|
1431 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1432 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1433 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1434 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1435 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1436 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1437 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1438 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1439 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1440 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1441 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1442 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1443 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1444 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1445 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1446 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1447 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1448 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1449 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1450 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1451 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1452 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1453 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1454 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1455 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1456 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1457 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1458 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1459 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1460 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1461 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1462 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1463 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1464 | e6e5ad80 | bellard | case 0x25: // Part Status |
1465 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1466 | e6e5ad80 | bellard | *reg_value = s->cr[reg_index]; |
1467 | e6e5ad80 | bellard | break;
|
1468 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1469 | e6e5ad80 | bellard | *reg_value = s->ar_index & 0x3f;
|
1470 | e6e5ad80 | bellard | break;
|
1471 | e6e5ad80 | bellard | default:
|
1472 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1473 | e6e5ad80 | bellard | printf("cirrus: inport cr_index %02x\n", reg_index);
|
1474 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1475 | e6e5ad80 | bellard | #endif
|
1476 | e6e5ad80 | bellard | break;
|
1477 | e6e5ad80 | bellard | } |
1478 | e6e5ad80 | bellard | |
1479 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1480 | e6e5ad80 | bellard | } |
1481 | e6e5ad80 | bellard | |
1482 | e6e5ad80 | bellard | static int |
1483 | e6e5ad80 | bellard | cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1484 | e6e5ad80 | bellard | { |
1485 | e6e5ad80 | bellard | switch (reg_index) {
|
1486 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1487 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1488 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1489 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1490 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1491 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1492 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1493 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1494 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1495 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1496 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1497 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1498 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1499 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1500 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1501 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1502 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1503 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1504 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1505 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1506 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1507 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1508 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1509 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1510 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1511 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1512 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1513 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1514 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1515 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1516 | ae184e4a | bellard | case 0x1d: // Overlay Extended Control |
1517 | e6e5ad80 | bellard | s->cr[reg_index] = reg_value; |
1518 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1519 | e6e5ad80 | bellard | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1520 | e6e5ad80 | bellard | reg_index, reg_value); |
1521 | e6e5ad80 | bellard | #endif
|
1522 | e6e5ad80 | bellard | break;
|
1523 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1524 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1525 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1526 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1527 | e6e5ad80 | bellard | break;
|
1528 | e6e5ad80 | bellard | case 0x25: // Part Status |
1529 | e6e5ad80 | bellard | default:
|
1530 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1531 | e6e5ad80 | bellard | printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
|
1532 | e6e5ad80 | bellard | reg_value); |
1533 | e6e5ad80 | bellard | #endif
|
1534 | e6e5ad80 | bellard | break;
|
1535 | e6e5ad80 | bellard | } |
1536 | e6e5ad80 | bellard | |
1537 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1538 | e6e5ad80 | bellard | } |
1539 | e6e5ad80 | bellard | |
1540 | e6e5ad80 | bellard | /***************************************
|
1541 | e6e5ad80 | bellard | *
|
1542 | e6e5ad80 | bellard | * memory-mapped I/O (bitblt)
|
1543 | e6e5ad80 | bellard | *
|
1544 | e6e5ad80 | bellard | ***************************************/
|
1545 | e6e5ad80 | bellard | |
1546 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1547 | e6e5ad80 | bellard | { |
1548 | e6e5ad80 | bellard | int value = 0xff; |
1549 | e6e5ad80 | bellard | |
1550 | e6e5ad80 | bellard | switch (address) {
|
1551 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1552 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x00, &value);
|
1553 | e6e5ad80 | bellard | break;
|
1554 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1555 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x10, &value);
|
1556 | e6e5ad80 | bellard | break;
|
1557 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1558 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x12, &value);
|
1559 | e6e5ad80 | bellard | break;
|
1560 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1561 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x14, &value);
|
1562 | e6e5ad80 | bellard | break;
|
1563 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1564 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x01, &value);
|
1565 | e6e5ad80 | bellard | break;
|
1566 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1567 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x11, &value);
|
1568 | e6e5ad80 | bellard | break;
|
1569 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1570 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x13, &value);
|
1571 | e6e5ad80 | bellard | break;
|
1572 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1573 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x15, &value);
|
1574 | e6e5ad80 | bellard | break;
|
1575 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1576 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x20, &value);
|
1577 | e6e5ad80 | bellard | break;
|
1578 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1579 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x21, &value);
|
1580 | e6e5ad80 | bellard | break;
|
1581 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1582 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x22, &value);
|
1583 | e6e5ad80 | bellard | break;
|
1584 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1585 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x23, &value);
|
1586 | e6e5ad80 | bellard | break;
|
1587 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1588 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x24, &value);
|
1589 | e6e5ad80 | bellard | break;
|
1590 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1591 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x25, &value);
|
1592 | e6e5ad80 | bellard | break;
|
1593 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1594 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x26, &value);
|
1595 | e6e5ad80 | bellard | break;
|
1596 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1597 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x27, &value);
|
1598 | e6e5ad80 | bellard | break;
|
1599 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1600 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x28, &value);
|
1601 | e6e5ad80 | bellard | break;
|
1602 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1603 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x29, &value);
|
1604 | e6e5ad80 | bellard | break;
|
1605 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1606 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2a, &value);
|
1607 | e6e5ad80 | bellard | break;
|
1608 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1609 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2c, &value);
|
1610 | e6e5ad80 | bellard | break;
|
1611 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1612 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2d, &value);
|
1613 | e6e5ad80 | bellard | break;
|
1614 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1615 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2e, &value);
|
1616 | e6e5ad80 | bellard | break;
|
1617 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1618 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2f, &value);
|
1619 | e6e5ad80 | bellard | break;
|
1620 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1621 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x30, &value);
|
1622 | e6e5ad80 | bellard | break;
|
1623 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1624 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x32, &value);
|
1625 | e6e5ad80 | bellard | break;
|
1626 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1627 | a21ae81d | bellard | cirrus_hook_read_gr(s, 0x33, &value);
|
1628 | a21ae81d | bellard | break;
|
1629 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1630 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x34, &value);
|
1631 | e6e5ad80 | bellard | break;
|
1632 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1633 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x35, &value);
|
1634 | e6e5ad80 | bellard | break;
|
1635 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1636 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x38, &value);
|
1637 | e6e5ad80 | bellard | break;
|
1638 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1639 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x39, &value);
|
1640 | e6e5ad80 | bellard | break;
|
1641 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1642 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x31, &value);
|
1643 | e6e5ad80 | bellard | break;
|
1644 | e6e5ad80 | bellard | default:
|
1645 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1646 | e6e5ad80 | bellard | printf("cirrus: mmio read - address 0x%04x\n", address);
|
1647 | e6e5ad80 | bellard | #endif
|
1648 | e6e5ad80 | bellard | break;
|
1649 | e6e5ad80 | bellard | } |
1650 | e6e5ad80 | bellard | |
1651 | e6e5ad80 | bellard | return (uint8_t) value;
|
1652 | e6e5ad80 | bellard | } |
1653 | e6e5ad80 | bellard | |
1654 | e6e5ad80 | bellard | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1655 | e6e5ad80 | bellard | uint8_t value) |
1656 | e6e5ad80 | bellard | { |
1657 | e6e5ad80 | bellard | switch (address) {
|
1658 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1659 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x00, value);
|
1660 | e6e5ad80 | bellard | break;
|
1661 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1662 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x10, value);
|
1663 | e6e5ad80 | bellard | break;
|
1664 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1665 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x12, value);
|
1666 | e6e5ad80 | bellard | break;
|
1667 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1668 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x14, value);
|
1669 | e6e5ad80 | bellard | break;
|
1670 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1671 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x01, value);
|
1672 | e6e5ad80 | bellard | break;
|
1673 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1674 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x11, value);
|
1675 | e6e5ad80 | bellard | break;
|
1676 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1677 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x13, value);
|
1678 | e6e5ad80 | bellard | break;
|
1679 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1680 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x15, value);
|
1681 | e6e5ad80 | bellard | break;
|
1682 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1683 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x20, value);
|
1684 | e6e5ad80 | bellard | break;
|
1685 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1686 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x21, value);
|
1687 | e6e5ad80 | bellard | break;
|
1688 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1689 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x22, value);
|
1690 | e6e5ad80 | bellard | break;
|
1691 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1692 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x23, value);
|
1693 | e6e5ad80 | bellard | break;
|
1694 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1695 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x24, value);
|
1696 | e6e5ad80 | bellard | break;
|
1697 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1698 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x25, value);
|
1699 | e6e5ad80 | bellard | break;
|
1700 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1701 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x26, value);
|
1702 | e6e5ad80 | bellard | break;
|
1703 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1704 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x27, value);
|
1705 | e6e5ad80 | bellard | break;
|
1706 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1707 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x28, value);
|
1708 | e6e5ad80 | bellard | break;
|
1709 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1710 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x29, value);
|
1711 | e6e5ad80 | bellard | break;
|
1712 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1713 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2a, value);
|
1714 | e6e5ad80 | bellard | break;
|
1715 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1716 | e6e5ad80 | bellard | /* ignored */
|
1717 | e6e5ad80 | bellard | break;
|
1718 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1719 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2c, value);
|
1720 | e6e5ad80 | bellard | break;
|
1721 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1722 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2d, value);
|
1723 | e6e5ad80 | bellard | break;
|
1724 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1725 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2e, value);
|
1726 | e6e5ad80 | bellard | break;
|
1727 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1728 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2f, value);
|
1729 | e6e5ad80 | bellard | break;
|
1730 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1731 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x30, value);
|
1732 | e6e5ad80 | bellard | break;
|
1733 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1734 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x32, value);
|
1735 | e6e5ad80 | bellard | break;
|
1736 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1737 | a21ae81d | bellard | cirrus_hook_write_gr(s, 0x33, value);
|
1738 | a21ae81d | bellard | break;
|
1739 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1740 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x34, value);
|
1741 | e6e5ad80 | bellard | break;
|
1742 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1743 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x35, value);
|
1744 | e6e5ad80 | bellard | break;
|
1745 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1746 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x38, value);
|
1747 | e6e5ad80 | bellard | break;
|
1748 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1749 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x39, value);
|
1750 | e6e5ad80 | bellard | break;
|
1751 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1752 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x31, value);
|
1753 | e6e5ad80 | bellard | break;
|
1754 | e6e5ad80 | bellard | default:
|
1755 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1756 | e6e5ad80 | bellard | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1757 | e6e5ad80 | bellard | address, value); |
1758 | e6e5ad80 | bellard | #endif
|
1759 | e6e5ad80 | bellard | break;
|
1760 | e6e5ad80 | bellard | } |
1761 | e6e5ad80 | bellard | } |
1762 | e6e5ad80 | bellard | |
1763 | e6e5ad80 | bellard | /***************************************
|
1764 | e6e5ad80 | bellard | *
|
1765 | e6e5ad80 | bellard | * write mode 4/5
|
1766 | e6e5ad80 | bellard | *
|
1767 | e6e5ad80 | bellard | * assume TARGET_PAGE_SIZE >= 16
|
1768 | e6e5ad80 | bellard | *
|
1769 | e6e5ad80 | bellard | ***************************************/
|
1770 | e6e5ad80 | bellard | |
1771 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1772 | e6e5ad80 | bellard | unsigned mode,
|
1773 | e6e5ad80 | bellard | unsigned offset,
|
1774 | e6e5ad80 | bellard | uint32_t mem_value) |
1775 | e6e5ad80 | bellard | { |
1776 | e6e5ad80 | bellard | int x;
|
1777 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1778 | e6e5ad80 | bellard | uint8_t *dst; |
1779 | e6e5ad80 | bellard | |
1780 | e6e5ad80 | bellard | dst = s->vram_ptr + offset; |
1781 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1782 | e6e5ad80 | bellard | if (val & 0x80) { |
1783 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1784 | e6e5ad80 | bellard | } else if (mode == 5) { |
1785 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1786 | e6e5ad80 | bellard | } |
1787 | e6e5ad80 | bellard | val <<= 1;
|
1788 | 0b74ed78 | bellard | dst++; |
1789 | e6e5ad80 | bellard | } |
1790 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1791 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
|
1792 | e6e5ad80 | bellard | } |
1793 | e6e5ad80 | bellard | |
1794 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1795 | e6e5ad80 | bellard | unsigned mode,
|
1796 | e6e5ad80 | bellard | unsigned offset,
|
1797 | e6e5ad80 | bellard | uint32_t mem_value) |
1798 | e6e5ad80 | bellard | { |
1799 | e6e5ad80 | bellard | int x;
|
1800 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1801 | e6e5ad80 | bellard | uint8_t *dst; |
1802 | e6e5ad80 | bellard | |
1803 | e6e5ad80 | bellard | dst = s->vram_ptr + offset; |
1804 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1805 | e6e5ad80 | bellard | if (val & 0x80) { |
1806 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1807 | 0b74ed78 | bellard | *(dst + 1) = s->gr[0x11]; |
1808 | e6e5ad80 | bellard | } else if (mode == 5) { |
1809 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1810 | 0b74ed78 | bellard | *(dst + 1) = s->gr[0x10]; |
1811 | e6e5ad80 | bellard | } |
1812 | e6e5ad80 | bellard | val <<= 1;
|
1813 | 0b74ed78 | bellard | dst += 2;
|
1814 | e6e5ad80 | bellard | } |
1815 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1816 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
|
1817 | e6e5ad80 | bellard | } |
1818 | e6e5ad80 | bellard | |
1819 | e6e5ad80 | bellard | /***************************************
|
1820 | e6e5ad80 | bellard | *
|
1821 | e6e5ad80 | bellard | * memory access between 0xa0000-0xbffff
|
1822 | e6e5ad80 | bellard | *
|
1823 | e6e5ad80 | bellard | ***************************************/
|
1824 | e6e5ad80 | bellard | |
1825 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) |
1826 | e6e5ad80 | bellard | { |
1827 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1828 | e6e5ad80 | bellard | unsigned bank_index;
|
1829 | e6e5ad80 | bellard | unsigned bank_offset;
|
1830 | e6e5ad80 | bellard | uint32_t val; |
1831 | e6e5ad80 | bellard | |
1832 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) == 0) { |
1833 | e6e5ad80 | bellard | return vga_mem_readb(s, addr);
|
1834 | e6e5ad80 | bellard | } |
1835 | e6e5ad80 | bellard | |
1836 | aeb3c85f | bellard | addr &= 0x1ffff;
|
1837 | aeb3c85f | bellard | |
1838 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1839 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
1840 | e6e5ad80 | bellard | /* video memory */
|
1841 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
1842 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
1843 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1844 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
1845 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
1846 | e6e5ad80 | bellard | bank_offset <<= 4;
|
1847 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
1848 | e6e5ad80 | bellard | bank_offset <<= 3;
|
1849 | e6e5ad80 | bellard | } |
1850 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
1851 | e6e5ad80 | bellard | val = *(s->vram_ptr + bank_offset); |
1852 | e6e5ad80 | bellard | } else
|
1853 | e6e5ad80 | bellard | val = 0xff;
|
1854 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
1855 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
1856 | e6e5ad80 | bellard | val = 0xff;
|
1857 | e6e5ad80 | bellard | if ((s->sr[0x17] & 0x44) == 0x04) { |
1858 | e6e5ad80 | bellard | val = cirrus_mmio_blt_read(s, addr & 0xff);
|
1859 | e6e5ad80 | bellard | } |
1860 | e6e5ad80 | bellard | } else {
|
1861 | e6e5ad80 | bellard | val = 0xff;
|
1862 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1863 | e6e5ad80 | bellard | printf("cirrus: mem_readb %06x\n", addr);
|
1864 | e6e5ad80 | bellard | #endif
|
1865 | e6e5ad80 | bellard | } |
1866 | e6e5ad80 | bellard | return val;
|
1867 | e6e5ad80 | bellard | } |
1868 | e6e5ad80 | bellard | |
1869 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
1870 | e6e5ad80 | bellard | { |
1871 | e6e5ad80 | bellard | uint32_t v; |
1872 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1873 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 8;
|
1874 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1);
|
1875 | e6e5ad80 | bellard | #else
|
1876 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
1877 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1878 | e6e5ad80 | bellard | #endif
|
1879 | e6e5ad80 | bellard | return v;
|
1880 | e6e5ad80 | bellard | } |
1881 | e6e5ad80 | bellard | |
1882 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
1883 | e6e5ad80 | bellard | { |
1884 | e6e5ad80 | bellard | uint32_t v; |
1885 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1886 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 24;
|
1887 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; |
1888 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; |
1889 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3);
|
1890 | e6e5ad80 | bellard | #else
|
1891 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
1892 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1893 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
1894 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
1895 | e6e5ad80 | bellard | #endif
|
1896 | e6e5ad80 | bellard | return v;
|
1897 | e6e5ad80 | bellard | } |
1898 | e6e5ad80 | bellard | |
1899 | e6e5ad80 | bellard | static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
1900 | e6e5ad80 | bellard | uint32_t mem_value) |
1901 | e6e5ad80 | bellard | { |
1902 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1903 | e6e5ad80 | bellard | unsigned bank_index;
|
1904 | e6e5ad80 | bellard | unsigned bank_offset;
|
1905 | e6e5ad80 | bellard | unsigned mode;
|
1906 | e6e5ad80 | bellard | |
1907 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) == 0) { |
1908 | e6e5ad80 | bellard | vga_mem_writeb(s, addr, mem_value); |
1909 | e6e5ad80 | bellard | return;
|
1910 | e6e5ad80 | bellard | } |
1911 | e6e5ad80 | bellard | |
1912 | aeb3c85f | bellard | addr &= 0x1ffff;
|
1913 | aeb3c85f | bellard | |
1914 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1915 | e6e5ad80 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
1916 | e6e5ad80 | bellard | /* bitblt */
|
1917 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) mem_value; |
1918 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
1919 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
1920 | e6e5ad80 | bellard | } |
1921 | e6e5ad80 | bellard | } else {
|
1922 | e6e5ad80 | bellard | /* video memory */
|
1923 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
1924 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
1925 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1926 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
1927 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
1928 | e6e5ad80 | bellard | bank_offset <<= 4;
|
1929 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
1930 | e6e5ad80 | bellard | bank_offset <<= 3;
|
1931 | e6e5ad80 | bellard | } |
1932 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
1933 | e6e5ad80 | bellard | mode = s->gr[0x05] & 0x7; |
1934 | e6e5ad80 | bellard | if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
1935 | e6e5ad80 | bellard | *(s->vram_ptr + bank_offset) = mem_value; |
1936 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + |
1937 | e6e5ad80 | bellard | bank_offset); |
1938 | e6e5ad80 | bellard | } else {
|
1939 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) != 0x14) { |
1940 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
1941 | e6e5ad80 | bellard | bank_offset, |
1942 | e6e5ad80 | bellard | mem_value); |
1943 | e6e5ad80 | bellard | } else {
|
1944 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
1945 | e6e5ad80 | bellard | bank_offset, |
1946 | e6e5ad80 | bellard | mem_value); |
1947 | e6e5ad80 | bellard | } |
1948 | e6e5ad80 | bellard | } |
1949 | e6e5ad80 | bellard | } |
1950 | e6e5ad80 | bellard | } |
1951 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
1952 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
1953 | e6e5ad80 | bellard | if ((s->sr[0x17] & 0x44) == 0x04) { |
1954 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
1955 | e6e5ad80 | bellard | } |
1956 | e6e5ad80 | bellard | } else {
|
1957 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1958 | e6e5ad80 | bellard | printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
|
1959 | e6e5ad80 | bellard | #endif
|
1960 | e6e5ad80 | bellard | } |
1961 | e6e5ad80 | bellard | } |
1962 | e6e5ad80 | bellard | |
1963 | e6e5ad80 | bellard | static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1964 | e6e5ad80 | bellard | { |
1965 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1966 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
1967 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); |
1968 | e6e5ad80 | bellard | #else
|
1969 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
1970 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
1971 | e6e5ad80 | bellard | #endif
|
1972 | e6e5ad80 | bellard | } |
1973 | e6e5ad80 | bellard | |
1974 | e6e5ad80 | bellard | static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1975 | e6e5ad80 | bellard | { |
1976 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1977 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
1978 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
1979 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
1980 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); |
1981 | e6e5ad80 | bellard | #else
|
1982 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
1983 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
1984 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
1985 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
1986 | e6e5ad80 | bellard | #endif
|
1987 | e6e5ad80 | bellard | } |
1988 | e6e5ad80 | bellard | |
1989 | e6e5ad80 | bellard | static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = { |
1990 | e6e5ad80 | bellard | cirrus_vga_mem_readb, |
1991 | e6e5ad80 | bellard | cirrus_vga_mem_readw, |
1992 | e6e5ad80 | bellard | cirrus_vga_mem_readl, |
1993 | e6e5ad80 | bellard | }; |
1994 | e6e5ad80 | bellard | |
1995 | e6e5ad80 | bellard | static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = { |
1996 | e6e5ad80 | bellard | cirrus_vga_mem_writeb, |
1997 | e6e5ad80 | bellard | cirrus_vga_mem_writew, |
1998 | e6e5ad80 | bellard | cirrus_vga_mem_writel, |
1999 | e6e5ad80 | bellard | }; |
2000 | e6e5ad80 | bellard | |
2001 | e6e5ad80 | bellard | /***************************************
|
2002 | e6e5ad80 | bellard | *
|
2003 | a5082316 | bellard | * hardware cursor
|
2004 | a5082316 | bellard | *
|
2005 | a5082316 | bellard | ***************************************/
|
2006 | a5082316 | bellard | |
2007 | a5082316 | bellard | static inline void invalidate_cursor1(CirrusVGAState *s) |
2008 | a5082316 | bellard | { |
2009 | a5082316 | bellard | if (s->last_hw_cursor_size) {
|
2010 | a5082316 | bellard | vga_invalidate_scanlines((VGAState *)s, |
2011 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
2012 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_end); |
2013 | a5082316 | bellard | } |
2014 | a5082316 | bellard | } |
2015 | a5082316 | bellard | |
2016 | a5082316 | bellard | static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) |
2017 | a5082316 | bellard | { |
2018 | a5082316 | bellard | const uint8_t *src;
|
2019 | a5082316 | bellard | uint32_t content; |
2020 | a5082316 | bellard | int y, y_min, y_max;
|
2021 | a5082316 | bellard | |
2022 | 78e127ef | bellard | src = s->vram_ptr + s->real_vram_size - 16 * 1024; |
2023 | a5082316 | bellard | if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2024 | a5082316 | bellard | src += (s->sr[0x13] & 0x3c) * 256; |
2025 | a5082316 | bellard | y_min = 64;
|
2026 | a5082316 | bellard | y_max = -1;
|
2027 | a5082316 | bellard | for(y = 0; y < 64; y++) { |
2028 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2029 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2030 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2031 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2032 | a5082316 | bellard | if (content) {
|
2033 | a5082316 | bellard | if (y < y_min)
|
2034 | a5082316 | bellard | y_min = y; |
2035 | a5082316 | bellard | if (y > y_max)
|
2036 | a5082316 | bellard | y_max = y; |
2037 | a5082316 | bellard | } |
2038 | a5082316 | bellard | src += 16;
|
2039 | a5082316 | bellard | } |
2040 | a5082316 | bellard | } else {
|
2041 | a5082316 | bellard | src += (s->sr[0x13] & 0x3f) * 256; |
2042 | a5082316 | bellard | y_min = 32;
|
2043 | a5082316 | bellard | y_max = -1;
|
2044 | a5082316 | bellard | for(y = 0; y < 32; y++) { |
2045 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2046 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2047 | a5082316 | bellard | if (content) {
|
2048 | a5082316 | bellard | if (y < y_min)
|
2049 | a5082316 | bellard | y_min = y; |
2050 | a5082316 | bellard | if (y > y_max)
|
2051 | a5082316 | bellard | y_max = y; |
2052 | a5082316 | bellard | } |
2053 | a5082316 | bellard | src += 4;
|
2054 | a5082316 | bellard | } |
2055 | a5082316 | bellard | } |
2056 | a5082316 | bellard | if (y_min > y_max) {
|
2057 | a5082316 | bellard | s->last_hw_cursor_y_start = 0;
|
2058 | a5082316 | bellard | s->last_hw_cursor_y_end = 0;
|
2059 | a5082316 | bellard | } else {
|
2060 | a5082316 | bellard | s->last_hw_cursor_y_start = y_min; |
2061 | a5082316 | bellard | s->last_hw_cursor_y_end = y_max + 1;
|
2062 | a5082316 | bellard | } |
2063 | a5082316 | bellard | } |
2064 | a5082316 | bellard | |
2065 | a5082316 | bellard | /* NOTE: we do not currently handle the cursor bitmap change, so we
|
2066 | a5082316 | bellard | update the cursor only if it moves. */
|
2067 | a5082316 | bellard | static void cirrus_cursor_invalidate(VGAState *s1) |
2068 | a5082316 | bellard | { |
2069 | a5082316 | bellard | CirrusVGAState *s = (CirrusVGAState *)s1; |
2070 | a5082316 | bellard | int size;
|
2071 | a5082316 | bellard | |
2072 | a5082316 | bellard | if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) { |
2073 | a5082316 | bellard | size = 0;
|
2074 | a5082316 | bellard | } else {
|
2075 | a5082316 | bellard | if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) |
2076 | a5082316 | bellard | size = 64;
|
2077 | a5082316 | bellard | else
|
2078 | a5082316 | bellard | size = 32;
|
2079 | a5082316 | bellard | } |
2080 | a5082316 | bellard | /* invalidate last cursor and new cursor if any change */
|
2081 | a5082316 | bellard | if (s->last_hw_cursor_size != size ||
|
2082 | a5082316 | bellard | s->last_hw_cursor_x != s->hw_cursor_x || |
2083 | a5082316 | bellard | s->last_hw_cursor_y != s->hw_cursor_y) { |
2084 | a5082316 | bellard | |
2085 | a5082316 | bellard | invalidate_cursor1(s); |
2086 | a5082316 | bellard | |
2087 | a5082316 | bellard | s->last_hw_cursor_size = size; |
2088 | a5082316 | bellard | s->last_hw_cursor_x = s->hw_cursor_x; |
2089 | a5082316 | bellard | s->last_hw_cursor_y = s->hw_cursor_y; |
2090 | a5082316 | bellard | /* compute the real cursor min and max y */
|
2091 | a5082316 | bellard | cirrus_cursor_compute_yrange(s); |
2092 | a5082316 | bellard | invalidate_cursor1(s); |
2093 | a5082316 | bellard | } |
2094 | a5082316 | bellard | } |
2095 | a5082316 | bellard | |
2096 | a5082316 | bellard | static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y) |
2097 | a5082316 | bellard | { |
2098 | a5082316 | bellard | CirrusVGAState *s = (CirrusVGAState *)s1; |
2099 | a5082316 | bellard | int w, h, bpp, x1, x2, poffset;
|
2100 | a5082316 | bellard | unsigned int color0, color1; |
2101 | a5082316 | bellard | const uint8_t *palette, *src;
|
2102 | a5082316 | bellard | uint32_t content; |
2103 | a5082316 | bellard | |
2104 | a5082316 | bellard | if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) |
2105 | a5082316 | bellard | return;
|
2106 | a5082316 | bellard | /* fast test to see if the cursor intersects with the scan line */
|
2107 | a5082316 | bellard | if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2108 | a5082316 | bellard | h = 64;
|
2109 | a5082316 | bellard | } else {
|
2110 | a5082316 | bellard | h = 32;
|
2111 | a5082316 | bellard | } |
2112 | a5082316 | bellard | if (scr_y < s->hw_cursor_y ||
|
2113 | a5082316 | bellard | scr_y >= (s->hw_cursor_y + h)) |
2114 | a5082316 | bellard | return;
|
2115 | a5082316 | bellard | |
2116 | 78e127ef | bellard | src = s->vram_ptr + s->real_vram_size - 16 * 1024; |
2117 | a5082316 | bellard | if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2118 | a5082316 | bellard | src += (s->sr[0x13] & 0x3c) * 256; |
2119 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 16;
|
2120 | a5082316 | bellard | poffset = 8;
|
2121 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2122 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2123 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2124 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2125 | a5082316 | bellard | } else {
|
2126 | a5082316 | bellard | src += (s->sr[0x13] & 0x3f) * 256; |
2127 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 4;
|
2128 | a5082316 | bellard | poffset = 128;
|
2129 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2130 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2131 | a5082316 | bellard | } |
2132 | a5082316 | bellard | /* if nothing to draw, no need to continue */
|
2133 | a5082316 | bellard | if (!content)
|
2134 | a5082316 | bellard | return;
|
2135 | a5082316 | bellard | w = h; |
2136 | a5082316 | bellard | |
2137 | a5082316 | bellard | x1 = s->hw_cursor_x; |
2138 | a5082316 | bellard | if (x1 >= s->last_scr_width)
|
2139 | a5082316 | bellard | return;
|
2140 | a5082316 | bellard | x2 = s->hw_cursor_x + w; |
2141 | a5082316 | bellard | if (x2 > s->last_scr_width)
|
2142 | a5082316 | bellard | x2 = s->last_scr_width; |
2143 | a5082316 | bellard | w = x2 - x1; |
2144 | a5082316 | bellard | palette = s->cirrus_hidden_palette; |
2145 | a5082316 | bellard | color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
2146 | a5082316 | bellard | c6_to_8(palette[0x0 * 3 + 1]), |
2147 | a5082316 | bellard | c6_to_8(palette[0x0 * 3 + 2])); |
2148 | a5082316 | bellard | color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]), |
2149 | a5082316 | bellard | c6_to_8(palette[0xf * 3 + 1]), |
2150 | a5082316 | bellard | c6_to_8(palette[0xf * 3 + 2])); |
2151 | a5082316 | bellard | bpp = ((s->ds->depth + 7) >> 3); |
2152 | a5082316 | bellard | d1 += x1 * bpp; |
2153 | a5082316 | bellard | switch(s->ds->depth) {
|
2154 | a5082316 | bellard | default:
|
2155 | a5082316 | bellard | break;
|
2156 | a5082316 | bellard | case 8: |
2157 | a5082316 | bellard | vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
|
2158 | a5082316 | bellard | break;
|
2159 | a5082316 | bellard | case 15: |
2160 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
|
2161 | a5082316 | bellard | break;
|
2162 | a5082316 | bellard | case 16: |
2163 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
|
2164 | a5082316 | bellard | break;
|
2165 | a5082316 | bellard | case 32: |
2166 | a5082316 | bellard | vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
|
2167 | a5082316 | bellard | break;
|
2168 | a5082316 | bellard | } |
2169 | a5082316 | bellard | } |
2170 | a5082316 | bellard | |
2171 | a5082316 | bellard | /***************************************
|
2172 | a5082316 | bellard | *
|
2173 | e6e5ad80 | bellard | * LFB memory access
|
2174 | e6e5ad80 | bellard | *
|
2175 | e6e5ad80 | bellard | ***************************************/
|
2176 | e6e5ad80 | bellard | |
2177 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) |
2178 | e6e5ad80 | bellard | { |
2179 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2180 | e6e5ad80 | bellard | uint32_t ret; |
2181 | e6e5ad80 | bellard | |
2182 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2183 | e6e5ad80 | bellard | |
2184 | 78e127ef | bellard | if (((s->sr[0x17] & 0x44) == 0x44) && |
2185 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2186 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2187 | e6e5ad80 | bellard | ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2188 | e6e5ad80 | bellard | } else if (0) { |
2189 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2190 | e6e5ad80 | bellard | ret = 0xff;
|
2191 | e6e5ad80 | bellard | } else {
|
2192 | e6e5ad80 | bellard | /* video memory */
|
2193 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2194 | e6e5ad80 | bellard | addr <<= 4;
|
2195 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2196 | e6e5ad80 | bellard | addr <<= 3;
|
2197 | e6e5ad80 | bellard | } |
2198 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2199 | e6e5ad80 | bellard | ret = *(s->vram_ptr + addr); |
2200 | e6e5ad80 | bellard | } |
2201 | e6e5ad80 | bellard | |
2202 | e6e5ad80 | bellard | return ret;
|
2203 | e6e5ad80 | bellard | } |
2204 | e6e5ad80 | bellard | |
2205 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) |
2206 | e6e5ad80 | bellard | { |
2207 | e6e5ad80 | bellard | uint32_t v; |
2208 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2209 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 8;
|
2210 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1);
|
2211 | e6e5ad80 | bellard | #else
|
2212 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2213 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2214 | e6e5ad80 | bellard | #endif
|
2215 | e6e5ad80 | bellard | return v;
|
2216 | e6e5ad80 | bellard | } |
2217 | e6e5ad80 | bellard | |
2218 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) |
2219 | e6e5ad80 | bellard | { |
2220 | e6e5ad80 | bellard | uint32_t v; |
2221 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2222 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 24;
|
2223 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 16; |
2224 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 8; |
2225 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3);
|
2226 | e6e5ad80 | bellard | #else
|
2227 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2228 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2229 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 16; |
2230 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3) << 24; |
2231 | e6e5ad80 | bellard | #endif
|
2232 | e6e5ad80 | bellard | return v;
|
2233 | e6e5ad80 | bellard | } |
2234 | e6e5ad80 | bellard | |
2235 | e6e5ad80 | bellard | static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, |
2236 | e6e5ad80 | bellard | uint32_t val) |
2237 | e6e5ad80 | bellard | { |
2238 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2239 | e6e5ad80 | bellard | unsigned mode;
|
2240 | e6e5ad80 | bellard | |
2241 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2242 | 78e127ef | bellard | |
2243 | 78e127ef | bellard | if (((s->sr[0x17] & 0x44) == 0x44) && |
2244 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2245 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2246 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2247 | e6e5ad80 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2248 | e6e5ad80 | bellard | /* bitblt */
|
2249 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2250 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2251 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2252 | e6e5ad80 | bellard | } |
2253 | e6e5ad80 | bellard | } else {
|
2254 | e6e5ad80 | bellard | /* video memory */
|
2255 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2256 | e6e5ad80 | bellard | addr <<= 4;
|
2257 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2258 | e6e5ad80 | bellard | addr <<= 3;
|
2259 | e6e5ad80 | bellard | } |
2260 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2261 | e6e5ad80 | bellard | |
2262 | e6e5ad80 | bellard | mode = s->gr[0x05] & 0x7; |
2263 | e6e5ad80 | bellard | if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
2264 | e6e5ad80 | bellard | *(s->vram_ptr + addr) = (uint8_t) val; |
2265 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2266 | e6e5ad80 | bellard | } else {
|
2267 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) != 0x14) { |
2268 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2269 | e6e5ad80 | bellard | } else {
|
2270 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2271 | e6e5ad80 | bellard | } |
2272 | e6e5ad80 | bellard | } |
2273 | e6e5ad80 | bellard | } |
2274 | e6e5ad80 | bellard | } |
2275 | e6e5ad80 | bellard | |
2276 | e6e5ad80 | bellard | static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, |
2277 | e6e5ad80 | bellard | uint32_t val) |
2278 | e6e5ad80 | bellard | { |
2279 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2280 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); |
2281 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, val & 0xff); |
2282 | e6e5ad80 | bellard | #else
|
2283 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2284 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2285 | e6e5ad80 | bellard | #endif
|
2286 | e6e5ad80 | bellard | } |
2287 | e6e5ad80 | bellard | |
2288 | e6e5ad80 | bellard | static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, |
2289 | e6e5ad80 | bellard | uint32_t val) |
2290 | e6e5ad80 | bellard | { |
2291 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2292 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); |
2293 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2294 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2295 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, val & 0xff); |
2296 | e6e5ad80 | bellard | #else
|
2297 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2298 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2299 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2300 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2301 | e6e5ad80 | bellard | #endif
|
2302 | e6e5ad80 | bellard | } |
2303 | e6e5ad80 | bellard | |
2304 | e6e5ad80 | bellard | |
2305 | e6e5ad80 | bellard | static CPUReadMemoryFunc *cirrus_linear_read[3] = { |
2306 | e6e5ad80 | bellard | cirrus_linear_readb, |
2307 | e6e5ad80 | bellard | cirrus_linear_readw, |
2308 | e6e5ad80 | bellard | cirrus_linear_readl, |
2309 | e6e5ad80 | bellard | }; |
2310 | e6e5ad80 | bellard | |
2311 | e6e5ad80 | bellard | static CPUWriteMemoryFunc *cirrus_linear_write[3] = { |
2312 | e6e5ad80 | bellard | cirrus_linear_writeb, |
2313 | e6e5ad80 | bellard | cirrus_linear_writew, |
2314 | e6e5ad80 | bellard | cirrus_linear_writel, |
2315 | e6e5ad80 | bellard | }; |
2316 | e6e5ad80 | bellard | |
2317 | 8926b517 | bellard | static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr, |
2318 | 8926b517 | bellard | uint32_t val) |
2319 | 8926b517 | bellard | { |
2320 | 8926b517 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2321 | 8926b517 | bellard | |
2322 | 8926b517 | bellard | addr &= s->cirrus_addr_mask; |
2323 | 8926b517 | bellard | *(s->vram_ptr + addr) = val; |
2324 | 8926b517 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2325 | 8926b517 | bellard | } |
2326 | 8926b517 | bellard | |
2327 | 8926b517 | bellard | static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr, |
2328 | 8926b517 | bellard | uint32_t val) |
2329 | 8926b517 | bellard | { |
2330 | 8926b517 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2331 | 8926b517 | bellard | |
2332 | 8926b517 | bellard | addr &= s->cirrus_addr_mask; |
2333 | 8926b517 | bellard | cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val); |
2334 | 8926b517 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2335 | 8926b517 | bellard | } |
2336 | 8926b517 | bellard | |
2337 | 8926b517 | bellard | static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr, |
2338 | 8926b517 | bellard | uint32_t val) |
2339 | 8926b517 | bellard | { |
2340 | 8926b517 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2341 | 8926b517 | bellard | |
2342 | 8926b517 | bellard | addr &= s->cirrus_addr_mask; |
2343 | 8926b517 | bellard | cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val); |
2344 | 8926b517 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2345 | 8926b517 | bellard | } |
2346 | 8926b517 | bellard | |
2347 | a5082316 | bellard | /***************************************
|
2348 | a5082316 | bellard | *
|
2349 | a5082316 | bellard | * system to screen memory access
|
2350 | a5082316 | bellard | *
|
2351 | a5082316 | bellard | ***************************************/
|
2352 | a5082316 | bellard | |
2353 | a5082316 | bellard | |
2354 | a5082316 | bellard | static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr) |
2355 | a5082316 | bellard | { |
2356 | a5082316 | bellard | uint32_t ret; |
2357 | a5082316 | bellard | |
2358 | a5082316 | bellard | /* XXX handle bitblt */
|
2359 | a5082316 | bellard | ret = 0xff;
|
2360 | a5082316 | bellard | return ret;
|
2361 | a5082316 | bellard | } |
2362 | a5082316 | bellard | |
2363 | a5082316 | bellard | static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr) |
2364 | a5082316 | bellard | { |
2365 | a5082316 | bellard | uint32_t v; |
2366 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2367 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
|
2368 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
|
2369 | a5082316 | bellard | #else
|
2370 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr); |
2371 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
2372 | a5082316 | bellard | #endif
|
2373 | a5082316 | bellard | return v;
|
2374 | a5082316 | bellard | } |
2375 | a5082316 | bellard | |
2376 | a5082316 | bellard | static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr) |
2377 | a5082316 | bellard | { |
2378 | a5082316 | bellard | uint32_t v; |
2379 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2380 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
|
2381 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16; |
2382 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8; |
2383 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
|
2384 | a5082316 | bellard | #else
|
2385 | a5082316 | bellard | v = cirrus_linear_bitblt_readb(opaque, addr); |
2386 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8; |
2387 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16; |
2388 | a5082316 | bellard | v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24; |
2389 | a5082316 | bellard | #endif
|
2390 | a5082316 | bellard | return v;
|
2391 | a5082316 | bellard | } |
2392 | a5082316 | bellard | |
2393 | a5082316 | bellard | static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, |
2394 | a5082316 | bellard | uint32_t val) |
2395 | a5082316 | bellard | { |
2396 | a5082316 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2397 | a5082316 | bellard | |
2398 | a5082316 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2399 | a5082316 | bellard | /* bitblt */
|
2400 | a5082316 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2401 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2402 | a5082316 | bellard | cirrus_bitblt_cputovideo_next(s); |
2403 | a5082316 | bellard | } |
2404 | a5082316 | bellard | } |
2405 | a5082316 | bellard | } |
2406 | a5082316 | bellard | |
2407 | a5082316 | bellard | static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr, |
2408 | a5082316 | bellard | uint32_t val) |
2409 | a5082316 | bellard | { |
2410 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2411 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff); |
2412 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff); |
2413 | a5082316 | bellard | #else
|
2414 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
|
2415 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2416 | a5082316 | bellard | #endif
|
2417 | a5082316 | bellard | } |
2418 | a5082316 | bellard | |
2419 | a5082316 | bellard | static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr, |
2420 | a5082316 | bellard | uint32_t val) |
2421 | a5082316 | bellard | { |
2422 | a5082316 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2423 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff); |
2424 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2425 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2426 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff); |
2427 | a5082316 | bellard | #else
|
2428 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
|
2429 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2430 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2431 | a5082316 | bellard | cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2432 | a5082316 | bellard | #endif
|
2433 | a5082316 | bellard | } |
2434 | a5082316 | bellard | |
2435 | a5082316 | bellard | |
2436 | a5082316 | bellard | static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = { |
2437 | a5082316 | bellard | cirrus_linear_bitblt_readb, |
2438 | a5082316 | bellard | cirrus_linear_bitblt_readw, |
2439 | a5082316 | bellard | cirrus_linear_bitblt_readl, |
2440 | a5082316 | bellard | }; |
2441 | a5082316 | bellard | |
2442 | a5082316 | bellard | static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = { |
2443 | a5082316 | bellard | cirrus_linear_bitblt_writeb, |
2444 | a5082316 | bellard | cirrus_linear_bitblt_writew, |
2445 | a5082316 | bellard | cirrus_linear_bitblt_writel, |
2446 | a5082316 | bellard | }; |
2447 | a5082316 | bellard | |
2448 | 8926b517 | bellard | /* Compute the memory access functions */
|
2449 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s) |
2450 | 8926b517 | bellard | { |
2451 | 8926b517 | bellard | unsigned mode;
|
2452 | 8926b517 | bellard | |
2453 | 8926b517 | bellard | if ((s->sr[0x17] & 0x44) == 0x44) { |
2454 | 8926b517 | bellard | goto generic_io;
|
2455 | 8926b517 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2456 | 8926b517 | bellard | goto generic_io;
|
2457 | 8926b517 | bellard | } else {
|
2458 | 8926b517 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2459 | 8926b517 | bellard | goto generic_io;
|
2460 | 8926b517 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2461 | 8926b517 | bellard | goto generic_io;
|
2462 | 8926b517 | bellard | } |
2463 | 8926b517 | bellard | |
2464 | 8926b517 | bellard | mode = s->gr[0x05] & 0x7; |
2465 | 8926b517 | bellard | if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
2466 | 8926b517 | bellard | s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
|
2467 | 8926b517 | bellard | s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
|
2468 | 8926b517 | bellard | s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
|
2469 | 8926b517 | bellard | } else {
|
2470 | 8926b517 | bellard | generic_io:
|
2471 | 8926b517 | bellard | s->cirrus_linear_write[0] = cirrus_linear_writeb;
|
2472 | 8926b517 | bellard | s->cirrus_linear_write[1] = cirrus_linear_writew;
|
2473 | 8926b517 | bellard | s->cirrus_linear_write[2] = cirrus_linear_writel;
|
2474 | 8926b517 | bellard | } |
2475 | 8926b517 | bellard | } |
2476 | 8926b517 | bellard | } |
2477 | 8926b517 | bellard | |
2478 | 8926b517 | bellard | |
2479 | e6e5ad80 | bellard | /* I/O ports */
|
2480 | e6e5ad80 | bellard | |
2481 | e6e5ad80 | bellard | static uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
2482 | e6e5ad80 | bellard | { |
2483 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2484 | e6e5ad80 | bellard | int val, index;
|
2485 | e6e5ad80 | bellard | |
2486 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2487 | e6e5ad80 | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2488 | e6e5ad80 | bellard | || (addr >= 0x3d0 && addr <= 0x3df |
2489 | e6e5ad80 | bellard | && !(s->msr & MSR_COLOR_EMULATION))) { |
2490 | e6e5ad80 | bellard | val = 0xff;
|
2491 | e6e5ad80 | bellard | } else {
|
2492 | e6e5ad80 | bellard | switch (addr) {
|
2493 | e6e5ad80 | bellard | case 0x3c0: |
2494 | e6e5ad80 | bellard | if (s->ar_flip_flop == 0) { |
2495 | e6e5ad80 | bellard | val = s->ar_index; |
2496 | e6e5ad80 | bellard | } else {
|
2497 | e6e5ad80 | bellard | val = 0;
|
2498 | e6e5ad80 | bellard | } |
2499 | e6e5ad80 | bellard | break;
|
2500 | e6e5ad80 | bellard | case 0x3c1: |
2501 | e6e5ad80 | bellard | index = s->ar_index & 0x1f;
|
2502 | e6e5ad80 | bellard | if (index < 21) |
2503 | e6e5ad80 | bellard | val = s->ar[index]; |
2504 | e6e5ad80 | bellard | else
|
2505 | e6e5ad80 | bellard | val = 0;
|
2506 | e6e5ad80 | bellard | break;
|
2507 | e6e5ad80 | bellard | case 0x3c2: |
2508 | e6e5ad80 | bellard | val = s->st00; |
2509 | e6e5ad80 | bellard | break;
|
2510 | e6e5ad80 | bellard | case 0x3c4: |
2511 | e6e5ad80 | bellard | val = s->sr_index; |
2512 | e6e5ad80 | bellard | break;
|
2513 | e6e5ad80 | bellard | case 0x3c5: |
2514 | e6e5ad80 | bellard | if (cirrus_hook_read_sr(s, s->sr_index, &val))
|
2515 | e6e5ad80 | bellard | break;
|
2516 | e6e5ad80 | bellard | val = s->sr[s->sr_index]; |
2517 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2518 | e6e5ad80 | bellard | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2519 | e6e5ad80 | bellard | #endif
|
2520 | e6e5ad80 | bellard | break;
|
2521 | e6e5ad80 | bellard | case 0x3c6: |
2522 | e6e5ad80 | bellard | cirrus_read_hidden_dac(s, &val); |
2523 | e6e5ad80 | bellard | break;
|
2524 | e6e5ad80 | bellard | case 0x3c7: |
2525 | e6e5ad80 | bellard | val = s->dac_state; |
2526 | e6e5ad80 | bellard | break;
|
2527 | ae184e4a | bellard | case 0x3c8: |
2528 | ae184e4a | bellard | val = s->dac_write_index; |
2529 | ae184e4a | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
2530 | ae184e4a | bellard | break;
|
2531 | ae184e4a | bellard | case 0x3c9: |
2532 | e6e5ad80 | bellard | if (cirrus_hook_read_palette(s, &val))
|
2533 | e6e5ad80 | bellard | break;
|
2534 | e6e5ad80 | bellard | val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
2535 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
2536 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2537 | e6e5ad80 | bellard | s->dac_read_index++; |
2538 | e6e5ad80 | bellard | } |
2539 | e6e5ad80 | bellard | break;
|
2540 | e6e5ad80 | bellard | case 0x3ca: |
2541 | e6e5ad80 | bellard | val = s->fcr; |
2542 | e6e5ad80 | bellard | break;
|
2543 | e6e5ad80 | bellard | case 0x3cc: |
2544 | e6e5ad80 | bellard | val = s->msr; |
2545 | e6e5ad80 | bellard | break;
|
2546 | e6e5ad80 | bellard | case 0x3ce: |
2547 | e6e5ad80 | bellard | val = s->gr_index; |
2548 | e6e5ad80 | bellard | break;
|
2549 | e6e5ad80 | bellard | case 0x3cf: |
2550 | e6e5ad80 | bellard | if (cirrus_hook_read_gr(s, s->gr_index, &val))
|
2551 | e6e5ad80 | bellard | break;
|
2552 | e6e5ad80 | bellard | val = s->gr[s->gr_index]; |
2553 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2554 | e6e5ad80 | bellard | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2555 | e6e5ad80 | bellard | #endif
|
2556 | e6e5ad80 | bellard | break;
|
2557 | e6e5ad80 | bellard | case 0x3b4: |
2558 | e6e5ad80 | bellard | case 0x3d4: |
2559 | e6e5ad80 | bellard | val = s->cr_index; |
2560 | e6e5ad80 | bellard | break;
|
2561 | e6e5ad80 | bellard | case 0x3b5: |
2562 | e6e5ad80 | bellard | case 0x3d5: |
2563 | e6e5ad80 | bellard | if (cirrus_hook_read_cr(s, s->cr_index, &val))
|
2564 | e6e5ad80 | bellard | break;
|
2565 | e6e5ad80 | bellard | val = s->cr[s->cr_index]; |
2566 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2567 | e6e5ad80 | bellard | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2568 | e6e5ad80 | bellard | #endif
|
2569 | e6e5ad80 | bellard | break;
|
2570 | e6e5ad80 | bellard | case 0x3ba: |
2571 | e6e5ad80 | bellard | case 0x3da: |
2572 | e6e5ad80 | bellard | /* just toggle to fool polling */
|
2573 | e6e5ad80 | bellard | s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE; |
2574 | e6e5ad80 | bellard | val = s->st01; |
2575 | e6e5ad80 | bellard | s->ar_flip_flop = 0;
|
2576 | e6e5ad80 | bellard | break;
|
2577 | e6e5ad80 | bellard | default:
|
2578 | e6e5ad80 | bellard | val = 0x00;
|
2579 | e6e5ad80 | bellard | break;
|
2580 | e6e5ad80 | bellard | } |
2581 | e6e5ad80 | bellard | } |
2582 | e6e5ad80 | bellard | #if defined(DEBUG_VGA)
|
2583 | e6e5ad80 | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2584 | e6e5ad80 | bellard | #endif
|
2585 | e6e5ad80 | bellard | return val;
|
2586 | e6e5ad80 | bellard | } |
2587 | e6e5ad80 | bellard | |
2588 | e6e5ad80 | bellard | static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
2589 | e6e5ad80 | bellard | { |
2590 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2591 | e6e5ad80 | bellard | int index;
|
2592 | e6e5ad80 | bellard | |
2593 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2594 | e6e5ad80 | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2595 | e6e5ad80 | bellard | || (addr >= 0x3d0 && addr <= 0x3df |
2596 | e6e5ad80 | bellard | && !(s->msr & MSR_COLOR_EMULATION))) |
2597 | e6e5ad80 | bellard | return;
|
2598 | e6e5ad80 | bellard | |
2599 | e6e5ad80 | bellard | #ifdef DEBUG_VGA
|
2600 | e6e5ad80 | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2601 | e6e5ad80 | bellard | #endif
|
2602 | e6e5ad80 | bellard | |
2603 | e6e5ad80 | bellard | switch (addr) {
|
2604 | e6e5ad80 | bellard | case 0x3c0: |
2605 | e6e5ad80 | bellard | if (s->ar_flip_flop == 0) { |
2606 | e6e5ad80 | bellard | val &= 0x3f;
|
2607 | e6e5ad80 | bellard | s->ar_index = val; |
2608 | e6e5ad80 | bellard | } else {
|
2609 | e6e5ad80 | bellard | index = s->ar_index & 0x1f;
|
2610 | e6e5ad80 | bellard | switch (index) {
|
2611 | e6e5ad80 | bellard | case 0x00 ... 0x0f: |
2612 | e6e5ad80 | bellard | s->ar[index] = val & 0x3f;
|
2613 | e6e5ad80 | bellard | break;
|
2614 | e6e5ad80 | bellard | case 0x10: |
2615 | e6e5ad80 | bellard | s->ar[index] = val & ~0x10;
|
2616 | e6e5ad80 | bellard | break;
|
2617 | e6e5ad80 | bellard | case 0x11: |
2618 | e6e5ad80 | bellard | s->ar[index] = val; |
2619 | e6e5ad80 | bellard | break;
|
2620 | e6e5ad80 | bellard | case 0x12: |
2621 | e6e5ad80 | bellard | s->ar[index] = val & ~0xc0;
|
2622 | e6e5ad80 | bellard | break;
|
2623 | e6e5ad80 | bellard | case 0x13: |
2624 | e6e5ad80 | bellard | s->ar[index] = val & ~0xf0;
|
2625 | e6e5ad80 | bellard | break;
|
2626 | e6e5ad80 | bellard | case 0x14: |
2627 | e6e5ad80 | bellard | s->ar[index] = val & ~0xf0;
|
2628 | e6e5ad80 | bellard | break;
|
2629 | e6e5ad80 | bellard | default:
|
2630 | e6e5ad80 | bellard | break;
|
2631 | e6e5ad80 | bellard | } |
2632 | e6e5ad80 | bellard | } |
2633 | e6e5ad80 | bellard | s->ar_flip_flop ^= 1;
|
2634 | e6e5ad80 | bellard | break;
|
2635 | e6e5ad80 | bellard | case 0x3c2: |
2636 | e6e5ad80 | bellard | s->msr = val & ~0x10;
|
2637 | e6e5ad80 | bellard | break;
|
2638 | e6e5ad80 | bellard | case 0x3c4: |
2639 | e6e5ad80 | bellard | s->sr_index = val; |
2640 | e6e5ad80 | bellard | break;
|
2641 | e6e5ad80 | bellard | case 0x3c5: |
2642 | e6e5ad80 | bellard | if (cirrus_hook_write_sr(s, s->sr_index, val))
|
2643 | e6e5ad80 | bellard | break;
|
2644 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2645 | e6e5ad80 | bellard | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2646 | e6e5ad80 | bellard | #endif
|
2647 | e6e5ad80 | bellard | s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
2648 | e6e5ad80 | bellard | break;
|
2649 | e6e5ad80 | bellard | case 0x3c6: |
2650 | e6e5ad80 | bellard | cirrus_write_hidden_dac(s, val); |
2651 | e6e5ad80 | bellard | break;
|
2652 | e6e5ad80 | bellard | case 0x3c7: |
2653 | e6e5ad80 | bellard | s->dac_read_index = val; |
2654 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2655 | e6e5ad80 | bellard | s->dac_state = 3;
|
2656 | e6e5ad80 | bellard | break;
|
2657 | e6e5ad80 | bellard | case 0x3c8: |
2658 | e6e5ad80 | bellard | s->dac_write_index = val; |
2659 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2660 | e6e5ad80 | bellard | s->dac_state = 0;
|
2661 | e6e5ad80 | bellard | break;
|
2662 | e6e5ad80 | bellard | case 0x3c9: |
2663 | e6e5ad80 | bellard | if (cirrus_hook_write_palette(s, val))
|
2664 | e6e5ad80 | bellard | break;
|
2665 | e6e5ad80 | bellard | s->dac_cache[s->dac_sub_index] = val; |
2666 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
2667 | e6e5ad80 | bellard | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); |
2668 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2669 | e6e5ad80 | bellard | s->dac_write_index++; |
2670 | e6e5ad80 | bellard | } |
2671 | e6e5ad80 | bellard | break;
|
2672 | e6e5ad80 | bellard | case 0x3ce: |
2673 | e6e5ad80 | bellard | s->gr_index = val; |
2674 | e6e5ad80 | bellard | break;
|
2675 | e6e5ad80 | bellard | case 0x3cf: |
2676 | e6e5ad80 | bellard | if (cirrus_hook_write_gr(s, s->gr_index, val))
|
2677 | e6e5ad80 | bellard | break;
|
2678 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2679 | e6e5ad80 | bellard | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2680 | e6e5ad80 | bellard | #endif
|
2681 | e6e5ad80 | bellard | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
2682 | e6e5ad80 | bellard | break;
|
2683 | e6e5ad80 | bellard | case 0x3b4: |
2684 | e6e5ad80 | bellard | case 0x3d4: |
2685 | e6e5ad80 | bellard | s->cr_index = val; |
2686 | e6e5ad80 | bellard | break;
|
2687 | e6e5ad80 | bellard | case 0x3b5: |
2688 | e6e5ad80 | bellard | case 0x3d5: |
2689 | e6e5ad80 | bellard | if (cirrus_hook_write_cr(s, s->cr_index, val))
|
2690 | e6e5ad80 | bellard | break;
|
2691 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2692 | e6e5ad80 | bellard | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2693 | e6e5ad80 | bellard | #endif
|
2694 | e6e5ad80 | bellard | /* handle CR0-7 protection */
|
2695 | 9bb34eac | bellard | if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) { |
2696 | e6e5ad80 | bellard | /* can always write bit 4 of CR7 */
|
2697 | e6e5ad80 | bellard | if (s->cr_index == 7) |
2698 | e6e5ad80 | bellard | s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); |
2699 | e6e5ad80 | bellard | return;
|
2700 | e6e5ad80 | bellard | } |
2701 | e6e5ad80 | bellard | switch (s->cr_index) {
|
2702 | e6e5ad80 | bellard | case 0x01: /* horizontal display end */ |
2703 | e6e5ad80 | bellard | case 0x07: |
2704 | e6e5ad80 | bellard | case 0x09: |
2705 | e6e5ad80 | bellard | case 0x0c: |
2706 | e6e5ad80 | bellard | case 0x0d: |
2707 | e6e5ad80 | bellard | case 0x12: /* veritcal display end */ |
2708 | e6e5ad80 | bellard | s->cr[s->cr_index] = val; |
2709 | e6e5ad80 | bellard | break;
|
2710 | e6e5ad80 | bellard | |
2711 | e6e5ad80 | bellard | default:
|
2712 | e6e5ad80 | bellard | s->cr[s->cr_index] = val; |
2713 | e6e5ad80 | bellard | break;
|
2714 | e6e5ad80 | bellard | } |
2715 | e6e5ad80 | bellard | break;
|
2716 | e6e5ad80 | bellard | case 0x3ba: |
2717 | e6e5ad80 | bellard | case 0x3da: |
2718 | e6e5ad80 | bellard | s->fcr = val & 0x10;
|
2719 | e6e5ad80 | bellard | break;
|
2720 | e6e5ad80 | bellard | } |
2721 | e6e5ad80 | bellard | } |
2722 | e6e5ad80 | bellard | |
2723 | e6e5ad80 | bellard | /***************************************
|
2724 | e6e5ad80 | bellard | *
|
2725 | e36f36e1 | bellard | * memory-mapped I/O access
|
2726 | e36f36e1 | bellard | *
|
2727 | e36f36e1 | bellard | ***************************************/
|
2728 | e36f36e1 | bellard | |
2729 | e36f36e1 | bellard | static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
2730 | e36f36e1 | bellard | { |
2731 | e36f36e1 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2732 | e36f36e1 | bellard | |
2733 | e36f36e1 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2734 | e36f36e1 | bellard | |
2735 | e36f36e1 | bellard | if (addr >= 0x100) { |
2736 | e36f36e1 | bellard | return cirrus_mmio_blt_read(s, addr - 0x100); |
2737 | e36f36e1 | bellard | } else {
|
2738 | e36f36e1 | bellard | return vga_ioport_read(s, addr + 0x3c0); |
2739 | e36f36e1 | bellard | } |
2740 | e36f36e1 | bellard | } |
2741 | e36f36e1 | bellard | |
2742 | e36f36e1 | bellard | static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
2743 | e36f36e1 | bellard | { |
2744 | e36f36e1 | bellard | uint32_t v; |
2745 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2746 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr) << 8;
|
2747 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1);
|
2748 | e36f36e1 | bellard | #else
|
2749 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2750 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2751 | e36f36e1 | bellard | #endif
|
2752 | e36f36e1 | bellard | return v;
|
2753 | e36f36e1 | bellard | } |
2754 | e36f36e1 | bellard | |
2755 | e36f36e1 | bellard | static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
2756 | e36f36e1 | bellard | { |
2757 | e36f36e1 | bellard | uint32_t v; |
2758 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2759 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr) << 24;
|
2760 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
2761 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
2762 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3);
|
2763 | e36f36e1 | bellard | #else
|
2764 | e36f36e1 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2765 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2766 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
2767 | e36f36e1 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
2768 | e36f36e1 | bellard | #endif
|
2769 | e36f36e1 | bellard | return v;
|
2770 | e36f36e1 | bellard | } |
2771 | e36f36e1 | bellard | |
2772 | e36f36e1 | bellard | static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
2773 | e36f36e1 | bellard | uint32_t val) |
2774 | e36f36e1 | bellard | { |
2775 | e36f36e1 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2776 | e36f36e1 | bellard | |
2777 | e36f36e1 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2778 | e36f36e1 | bellard | |
2779 | e36f36e1 | bellard | if (addr >= 0x100) { |
2780 | e36f36e1 | bellard | cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2781 | e36f36e1 | bellard | } else {
|
2782 | e36f36e1 | bellard | vga_ioport_write(s, addr + 0x3c0, val);
|
2783 | e36f36e1 | bellard | } |
2784 | e36f36e1 | bellard | } |
2785 | e36f36e1 | bellard | |
2786 | e36f36e1 | bellard | static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
2787 | e36f36e1 | bellard | uint32_t val) |
2788 | e36f36e1 | bellard | { |
2789 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2790 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
2791 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
2792 | e36f36e1 | bellard | #else
|
2793 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2794 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2795 | e36f36e1 | bellard | #endif
|
2796 | e36f36e1 | bellard | } |
2797 | e36f36e1 | bellard | |
2798 | e36f36e1 | bellard | static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
2799 | e36f36e1 | bellard | uint32_t val) |
2800 | e36f36e1 | bellard | { |
2801 | e36f36e1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2802 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
2803 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2804 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2805 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
2806 | e36f36e1 | bellard | #else
|
2807 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2808 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2809 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2810 | e36f36e1 | bellard | cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2811 | e36f36e1 | bellard | #endif
|
2812 | e36f36e1 | bellard | } |
2813 | e36f36e1 | bellard | |
2814 | e36f36e1 | bellard | |
2815 | e36f36e1 | bellard | static CPUReadMemoryFunc *cirrus_mmio_read[3] = { |
2816 | e36f36e1 | bellard | cirrus_mmio_readb, |
2817 | e36f36e1 | bellard | cirrus_mmio_readw, |
2818 | e36f36e1 | bellard | cirrus_mmio_readl, |
2819 | e36f36e1 | bellard | }; |
2820 | e36f36e1 | bellard | |
2821 | e36f36e1 | bellard | static CPUWriteMemoryFunc *cirrus_mmio_write[3] = { |
2822 | e36f36e1 | bellard | cirrus_mmio_writeb, |
2823 | e36f36e1 | bellard | cirrus_mmio_writew, |
2824 | e36f36e1 | bellard | cirrus_mmio_writel, |
2825 | e36f36e1 | bellard | }; |
2826 | e36f36e1 | bellard | |
2827 | 2c6ab832 | bellard | /* load/save state */
|
2828 | 2c6ab832 | bellard | |
2829 | 2c6ab832 | bellard | static void cirrus_vga_save(QEMUFile *f, void *opaque) |
2830 | 2c6ab832 | bellard | { |
2831 | 2c6ab832 | bellard | CirrusVGAState *s = opaque; |
2832 | 2c6ab832 | bellard | |
2833 | 2c6ab832 | bellard | qemu_put_be32s(f, &s->latch); |
2834 | 2c6ab832 | bellard | qemu_put_8s(f, &s->sr_index); |
2835 | 2c6ab832 | bellard | qemu_put_buffer(f, s->sr, 256);
|
2836 | 2c6ab832 | bellard | qemu_put_8s(f, &s->gr_index); |
2837 | 2c6ab832 | bellard | qemu_put_8s(f, &s->cirrus_shadow_gr0); |
2838 | 2c6ab832 | bellard | qemu_put_8s(f, &s->cirrus_shadow_gr1); |
2839 | 2c6ab832 | bellard | qemu_put_buffer(f, s->gr + 2, 254); |
2840 | 2c6ab832 | bellard | qemu_put_8s(f, &s->ar_index); |
2841 | 2c6ab832 | bellard | qemu_put_buffer(f, s->ar, 21);
|
2842 | 2c6ab832 | bellard | qemu_put_be32s(f, &s->ar_flip_flop); |
2843 | 2c6ab832 | bellard | qemu_put_8s(f, &s->cr_index); |
2844 | 2c6ab832 | bellard | qemu_put_buffer(f, s->cr, 256);
|
2845 | 2c6ab832 | bellard | qemu_put_8s(f, &s->msr); |
2846 | 2c6ab832 | bellard | qemu_put_8s(f, &s->fcr); |
2847 | 2c6ab832 | bellard | qemu_put_8s(f, &s->st00); |
2848 | 2c6ab832 | bellard | qemu_put_8s(f, &s->st01); |
2849 | 2c6ab832 | bellard | |
2850 | 2c6ab832 | bellard | qemu_put_8s(f, &s->dac_state); |
2851 | 2c6ab832 | bellard | qemu_put_8s(f, &s->dac_sub_index); |
2852 | 2c6ab832 | bellard | qemu_put_8s(f, &s->dac_read_index); |
2853 | 2c6ab832 | bellard | qemu_put_8s(f, &s->dac_write_index); |
2854 | 2c6ab832 | bellard | qemu_put_buffer(f, s->dac_cache, 3);
|
2855 | 2c6ab832 | bellard | qemu_put_buffer(f, s->palette, 768);
|
2856 | 2c6ab832 | bellard | |
2857 | 2c6ab832 | bellard | qemu_put_be32s(f, &s->bank_offset); |
2858 | 2c6ab832 | bellard | |
2859 | 2c6ab832 | bellard | qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex); |
2860 | 2c6ab832 | bellard | qemu_put_8s(f, &s->cirrus_hidden_dac_data); |
2861 | 2c6ab832 | bellard | |
2862 | 2c6ab832 | bellard | qemu_put_be32s(f, &s->hw_cursor_x); |
2863 | 2c6ab832 | bellard | qemu_put_be32s(f, &s->hw_cursor_y); |
2864 | 2c6ab832 | bellard | /* XXX: we do not save the bitblt state - we assume we do not save
|
2865 | 2c6ab832 | bellard | the state when the blitter is active */
|
2866 | 2c6ab832 | bellard | } |
2867 | 2c6ab832 | bellard | |
2868 | 2c6ab832 | bellard | static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id) |
2869 | 2c6ab832 | bellard | { |
2870 | 2c6ab832 | bellard | CirrusVGAState *s = opaque; |
2871 | 2c6ab832 | bellard | |
2872 | 2c6ab832 | bellard | if (version_id != 1) |
2873 | 2c6ab832 | bellard | return -EINVAL;
|
2874 | 2c6ab832 | bellard | |
2875 | 2c6ab832 | bellard | qemu_get_be32s(f, &s->latch); |
2876 | 2c6ab832 | bellard | qemu_get_8s(f, &s->sr_index); |
2877 | 2c6ab832 | bellard | qemu_get_buffer(f, s->sr, 256);
|
2878 | 2c6ab832 | bellard | qemu_get_8s(f, &s->gr_index); |
2879 | 2c6ab832 | bellard | qemu_get_8s(f, &s->cirrus_shadow_gr0); |
2880 | 2c6ab832 | bellard | qemu_get_8s(f, &s->cirrus_shadow_gr1); |
2881 | 2c6ab832 | bellard | s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
2882 | 2c6ab832 | bellard | s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; |
2883 | 2c6ab832 | bellard | qemu_get_buffer(f, s->gr + 2, 254); |
2884 | 2c6ab832 | bellard | qemu_get_8s(f, &s->ar_index); |
2885 | 2c6ab832 | bellard | qemu_get_buffer(f, s->ar, 21);
|
2886 | 2c6ab832 | bellard | qemu_get_be32s(f, &s->ar_flip_flop); |
2887 | 2c6ab832 | bellard | qemu_get_8s(f, &s->cr_index); |
2888 | 2c6ab832 | bellard | qemu_get_buffer(f, s->cr, 256);
|
2889 | 2c6ab832 | bellard | qemu_get_8s(f, &s->msr); |
2890 | 2c6ab832 | bellard | qemu_get_8s(f, &s->fcr); |
2891 | 2c6ab832 | bellard | qemu_get_8s(f, &s->st00); |
2892 | 2c6ab832 | bellard | qemu_get_8s(f, &s->st01); |
2893 | 2c6ab832 | bellard | |
2894 | 2c6ab832 | bellard | qemu_get_8s(f, &s->dac_state); |
2895 | 2c6ab832 | bellard | qemu_get_8s(f, &s->dac_sub_index); |
2896 | 2c6ab832 | bellard | qemu_get_8s(f, &s->dac_read_index); |
2897 | 2c6ab832 | bellard | qemu_get_8s(f, &s->dac_write_index); |
2898 | 2c6ab832 | bellard | qemu_get_buffer(f, s->dac_cache, 3);
|
2899 | 2c6ab832 | bellard | qemu_get_buffer(f, s->palette, 768);
|
2900 | 2c6ab832 | bellard | |
2901 | 2c6ab832 | bellard | qemu_get_be32s(f, &s->bank_offset); |
2902 | 2c6ab832 | bellard | |
2903 | 2c6ab832 | bellard | qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex); |
2904 | 2c6ab832 | bellard | qemu_get_8s(f, &s->cirrus_hidden_dac_data); |
2905 | 2c6ab832 | bellard | |
2906 | 2c6ab832 | bellard | qemu_get_be32s(f, &s->hw_cursor_x); |
2907 | 2c6ab832 | bellard | qemu_get_be32s(f, &s->hw_cursor_y); |
2908 | 2c6ab832 | bellard | |
2909 | 2c6ab832 | bellard | /* force refresh */
|
2910 | 2c6ab832 | bellard | s->graphic_mode = -1;
|
2911 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 0);
|
2912 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 1);
|
2913 | 2c6ab832 | bellard | return 0; |
2914 | 2c6ab832 | bellard | } |
2915 | 2c6ab832 | bellard | |
2916 | e36f36e1 | bellard | /***************************************
|
2917 | e36f36e1 | bellard | *
|
2918 | e6e5ad80 | bellard | * initialize
|
2919 | e6e5ad80 | bellard | *
|
2920 | e6e5ad80 | bellard | ***************************************/
|
2921 | e6e5ad80 | bellard | |
2922 | 78e127ef | bellard | static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) |
2923 | e6e5ad80 | bellard | { |
2924 | a5082316 | bellard | int vga_io_memory, i;
|
2925 | a5082316 | bellard | static int inited; |
2926 | a5082316 | bellard | |
2927 | a5082316 | bellard | if (!inited) {
|
2928 | a5082316 | bellard | inited = 1;
|
2929 | a5082316 | bellard | for(i = 0;i < 256; i++) |
2930 | a5082316 | bellard | rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
|
2931 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_0] = 0;
|
2932 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
|
2933 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOP] = 2;
|
2934 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
|
2935 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTDST] = 4;
|
2936 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC] = 5;
|
2937 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_1] = 6;
|
2938 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
|
2939 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
|
2940 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
|
2941 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
|
2942 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
|
2943 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
|
2944 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
|
2945 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
|
2946 | a5082316 | bellard | rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
|
2947 | a5082316 | bellard | } |
2948 | e6e5ad80 | bellard | |
2949 | e6e5ad80 | bellard | register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); |
2950 | e6e5ad80 | bellard | |
2951 | e6e5ad80 | bellard | register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); |
2952 | e6e5ad80 | bellard | register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); |
2953 | e6e5ad80 | bellard | register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); |
2954 | e6e5ad80 | bellard | register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); |
2955 | e6e5ad80 | bellard | |
2956 | e6e5ad80 | bellard | register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); |
2957 | e6e5ad80 | bellard | |
2958 | e6e5ad80 | bellard | register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); |
2959 | e6e5ad80 | bellard | register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); |
2960 | e6e5ad80 | bellard | register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); |
2961 | e6e5ad80 | bellard | register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); |
2962 | e6e5ad80 | bellard | |
2963 | e6e5ad80 | bellard | vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
|
2964 | e6e5ad80 | bellard | cirrus_vga_mem_write, s); |
2965 | e6e5ad80 | bellard | cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
2966 | e6e5ad80 | bellard | vga_io_memory); |
2967 | e6e5ad80 | bellard | |
2968 | e6e5ad80 | bellard | s->sr[0x06] = 0x0f; |
2969 | 78e127ef | bellard | if (device_id == CIRRUS_ID_CLGD5446) {
|
2970 | 78e127ef | bellard | /* 4MB 64 bit memory config, always PCI */
|
2971 | b30d4608 | bellard | s->sr[0x1F] = 0x2d; // MemClock |
2972 | b30d4608 | bellard | s->gr[0x18] = 0x0f; // fastest memory configuration |
2973 | 78e127ef | bellard | #if 1 |
2974 | 78e127ef | bellard | s->sr[0x0f] = 0x98; |
2975 | 78e127ef | bellard | s->sr[0x17] = 0x20; |
2976 | 78e127ef | bellard | s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ |
2977 | 78e127ef | bellard | s->real_vram_size = 4096 * 1024; |
2978 | 78e127ef | bellard | #else
|
2979 | 78e127ef | bellard | s->sr[0x0f] = 0x18; |
2980 | 78e127ef | bellard | s->sr[0x17] = 0x20; |
2981 | 78e127ef | bellard | s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
2982 | 78e127ef | bellard | s->real_vram_size = 2048 * 1024; |
2983 | 78e127ef | bellard | #endif
|
2984 | 78e127ef | bellard | } else {
|
2985 | b30d4608 | bellard | s->sr[0x1F] = 0x22; // MemClock |
2986 | 78e127ef | bellard | s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
2987 | 78e127ef | bellard | if (is_pci)
|
2988 | 78e127ef | bellard | s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
|
2989 | 78e127ef | bellard | else
|
2990 | 78e127ef | bellard | s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
|
2991 | 78e127ef | bellard | s->real_vram_size = 2048 * 1024; |
2992 | 78e127ef | bellard | s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
2993 | 78e127ef | bellard | } |
2994 | 20ba3ae1 | bellard | s->cr[0x27] = device_id;
|
2995 | e6e5ad80 | bellard | |
2996 | 78e127ef | bellard | /* Win2K seems to assume that the pattern buffer is at 0xff
|
2997 | 78e127ef | bellard | initially ! */
|
2998 | 78e127ef | bellard | memset(s->vram_ptr, 0xff, s->real_vram_size);
|
2999 | 78e127ef | bellard | |
3000 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 5;
|
3001 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = 0;
|
3002 | e6e5ad80 | bellard | |
3003 | e6e5ad80 | bellard | /* I/O handler for LFB */
|
3004 | e6e5ad80 | bellard | s->cirrus_linear_io_addr = |
3005 | e6e5ad80 | bellard | cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
|
3006 | e6e5ad80 | bellard | s); |
3007 | 8926b517 | bellard | s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr); |
3008 | 8926b517 | bellard | |
3009 | a5082316 | bellard | /* I/O handler for LFB */
|
3010 | a5082316 | bellard | s->cirrus_linear_bitblt_io_addr = |
3011 | a5082316 | bellard | cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
|
3012 | a5082316 | bellard | s); |
3013 | a5082316 | bellard | |
3014 | e6e5ad80 | bellard | /* I/O handler for memory-mapped I/O */
|
3015 | e6e5ad80 | bellard | s->cirrus_mmio_io_addr = |
3016 | e6e5ad80 | bellard | cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
|
3017 | e6e5ad80 | bellard | |
3018 | e6e5ad80 | bellard | /* XXX: s->vram_size must be a power of two */
|
3019 | 78e127ef | bellard | s->cirrus_addr_mask = s->real_vram_size - 1;
|
3020 | 78e127ef | bellard | s->linear_mmio_mask = s->real_vram_size - 256;
|
3021 | e6e5ad80 | bellard | |
3022 | e6e5ad80 | bellard | s->get_bpp = cirrus_get_bpp; |
3023 | e6e5ad80 | bellard | s->get_offsets = cirrus_get_offsets; |
3024 | 78e127ef | bellard | s->get_resolution = cirrus_get_resolution; |
3025 | a5082316 | bellard | s->cursor_invalidate = cirrus_cursor_invalidate; |
3026 | a5082316 | bellard | s->cursor_draw_line = cirrus_cursor_draw_line; |
3027 | 2c6ab832 | bellard | |
3028 | 2c6ab832 | bellard | register_savevm("cirrus_vga", 0, 1, cirrus_vga_save, cirrus_vga_load, s); |
3029 | e6e5ad80 | bellard | } |
3030 | e6e5ad80 | bellard | |
3031 | e6e5ad80 | bellard | /***************************************
|
3032 | e6e5ad80 | bellard | *
|
3033 | e6e5ad80 | bellard | * ISA bus support
|
3034 | e6e5ad80 | bellard | *
|
3035 | e6e5ad80 | bellard | ***************************************/
|
3036 | e6e5ad80 | bellard | |
3037 | e6e5ad80 | bellard | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
3038 | e6e5ad80 | bellard | unsigned long vga_ram_offset, int vga_ram_size) |
3039 | e6e5ad80 | bellard | { |
3040 | e6e5ad80 | bellard | CirrusVGAState *s; |
3041 | e6e5ad80 | bellard | |
3042 | e6e5ad80 | bellard | s = qemu_mallocz(sizeof(CirrusVGAState));
|
3043 | e6e5ad80 | bellard | |
3044 | e6e5ad80 | bellard | vga_common_init((VGAState *)s, |
3045 | e6e5ad80 | bellard | ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
3046 | 78e127ef | bellard | cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
|
3047 | e6e5ad80 | bellard | /* XXX ISA-LFB support */
|
3048 | e6e5ad80 | bellard | } |
3049 | e6e5ad80 | bellard | |
3050 | e6e5ad80 | bellard | /***************************************
|
3051 | e6e5ad80 | bellard | *
|
3052 | e6e5ad80 | bellard | * PCI bus support
|
3053 | e6e5ad80 | bellard | *
|
3054 | e6e5ad80 | bellard | ***************************************/
|
3055 | e6e5ad80 | bellard | |
3056 | e6e5ad80 | bellard | static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, |
3057 | e6e5ad80 | bellard | uint32_t addr, uint32_t size, int type)
|
3058 | e6e5ad80 | bellard | { |
3059 | e6e5ad80 | bellard | CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
3060 | e6e5ad80 | bellard | |
3061 | a5082316 | bellard | /* XXX: add byte swapping apertures */
|
3062 | e6e5ad80 | bellard | cpu_register_physical_memory(addr, s->vram_size, |
3063 | e6e5ad80 | bellard | s->cirrus_linear_io_addr); |
3064 | a5082316 | bellard | cpu_register_physical_memory(addr + 0x1000000, 0x400000, |
3065 | a5082316 | bellard | s->cirrus_linear_bitblt_io_addr); |
3066 | e6e5ad80 | bellard | } |
3067 | e6e5ad80 | bellard | |
3068 | e6e5ad80 | bellard | static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, |
3069 | e6e5ad80 | bellard | uint32_t addr, uint32_t size, int type)
|
3070 | e6e5ad80 | bellard | { |
3071 | e6e5ad80 | bellard | CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
3072 | e6e5ad80 | bellard | |
3073 | e6e5ad80 | bellard | cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE, |
3074 | e6e5ad80 | bellard | s->cirrus_mmio_io_addr); |
3075 | e6e5ad80 | bellard | } |
3076 | e6e5ad80 | bellard | |
3077 | 46e50e9d | bellard | void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
3078 | e6e5ad80 | bellard | unsigned long vga_ram_offset, int vga_ram_size) |
3079 | e6e5ad80 | bellard | { |
3080 | e6e5ad80 | bellard | PCICirrusVGAState *d; |
3081 | e6e5ad80 | bellard | uint8_t *pci_conf; |
3082 | e6e5ad80 | bellard | CirrusVGAState *s; |
3083 | 20ba3ae1 | bellard | int device_id;
|
3084 | 20ba3ae1 | bellard | |
3085 | 20ba3ae1 | bellard | device_id = CIRRUS_ID_CLGD5446; |
3086 | e6e5ad80 | bellard | |
3087 | e6e5ad80 | bellard | /* setup PCI configuration registers */
|
3088 | 46e50e9d | bellard | d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
|
3089 | e6e5ad80 | bellard | sizeof(PCICirrusVGAState),
|
3090 | 46e50e9d | bellard | -1, NULL, NULL); |
3091 | e6e5ad80 | bellard | pci_conf = d->dev.config; |
3092 | e6e5ad80 | bellard | pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff); |
3093 | e6e5ad80 | bellard | pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8); |
3094 | 20ba3ae1 | bellard | pci_conf[0x02] = (uint8_t) (device_id & 0xff); |
3095 | 20ba3ae1 | bellard | pci_conf[0x03] = (uint8_t) (device_id >> 8); |
3096 | e6e5ad80 | bellard | pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
|
3097 | e6e5ad80 | bellard | pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
|
3098 | e6e5ad80 | bellard | pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
|
3099 | e6e5ad80 | bellard | pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
|
3100 | e6e5ad80 | bellard | |
3101 | e6e5ad80 | bellard | /* setup VGA */
|
3102 | e6e5ad80 | bellard | s = &d->cirrus_vga; |
3103 | e6e5ad80 | bellard | vga_common_init((VGAState *)s, |
3104 | e6e5ad80 | bellard | ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
3105 | 78e127ef | bellard | cirrus_init_common(s, device_id, 1);
|
3106 | e6e5ad80 | bellard | |
3107 | e6e5ad80 | bellard | /* setup memory space */
|
3108 | e6e5ad80 | bellard | /* memory #0 LFB */
|
3109 | e6e5ad80 | bellard | /* memory #1 memory-mapped I/O */
|
3110 | e6e5ad80 | bellard | /* XXX: s->vram_size must be a power of two */
|
3111 | a5082316 | bellard | pci_register_io_region((PCIDevice *)d, 0, 0x2000000, |
3112 | a21ae81d | bellard | PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map); |
3113 | 20ba3ae1 | bellard | if (device_id == CIRRUS_ID_CLGD5446) {
|
3114 | a21ae81d | bellard | pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
3115 | a21ae81d | bellard | PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map); |
3116 | a21ae81d | bellard | } |
3117 | e6e5ad80 | bellard | /* XXX: ROM BIOS */
|
3118 | e6e5ad80 | bellard | } |