root / hw / slavio_serial.c @ a8d3431a
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/*
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* QEMU Sparc SLAVIO serial port emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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//#define DEBUG_SERIAL
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/* debug keyboard */
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//#define DEBUG_KBD
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/* debug keyboard : only mouse */
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//#define DEBUG_MOUSE
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/*
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* This is the serial port, mouse and keyboard part of chip STP2001
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* (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
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* mouse and keyboard ports don't implement all functions and they are
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* only asynchronous. There is no DMA.
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*
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*/
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typedef struct ChannelState { |
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int irq;
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int reg;
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int rxint, txint;
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uint8_t rx, tx, wregs[16], rregs[16]; |
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CharDriverState *chr; |
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} ChannelState; |
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struct SerialState {
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struct ChannelState chn[2]; |
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}; |
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#define SERIAL_MAXADDR 7 |
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static void slavio_serial_update_irq(ChannelState *s) |
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{ |
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if ((s->wregs[1] & 1) && // interrupts enabled |
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(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending |
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((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) && |
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s->rxint == 1) || // rx ints enabled, pending |
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((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p |
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pic_set_irq(s->irq, 1);
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} else {
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pic_set_irq(s->irq, 0);
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} |
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} |
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static void slavio_serial_reset_chn(ChannelState *s) |
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{ |
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int i;
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s->reg = 0;
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for (i = 0; i < SERIAL_MAXADDR; i++) { |
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s->rregs[i] = 0;
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s->wregs[i] = 0;
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} |
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s->wregs[4] = 4; |
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s->wregs[9] = 0xc0; |
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s->wregs[11] = 8; |
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s->wregs[14] = 0x30; |
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s->wregs[15] = 0xf8; |
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s->rregs[0] = 0x44; |
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s->rregs[1] = 6; |
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s->rx = s->tx = 0;
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s->rxint = s->txint = 0;
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} |
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static void slavio_serial_reset(void *opaque) |
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{ |
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SerialState *s = opaque; |
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slavio_serial_reset_chn(&s->chn[0]);
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slavio_serial_reset_chn(&s->chn[1]);
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} |
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static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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SerialState *ser = opaque; |
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ChannelState *s; |
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uint32_t saddr; |
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int newreg, channel;
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val &= 0xff;
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saddr = (addr & 3) >> 1; |
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channel = (addr & SERIAL_MAXADDR) >> 2;
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s = &ser->chn[channel]; |
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switch (saddr) {
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case 0: |
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newreg = 0;
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switch (s->reg) {
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case 0: |
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newreg = val & 7;
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val &= 0x38;
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switch (val) {
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case 8: |
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s->reg |= 0x8;
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break;
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case 0x20: |
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s->rxint = 0;
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break;
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case 0x28: |
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s->txint = 0;
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break;
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default:
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break;
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} |
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break;
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case 1 ... 8: |
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case 10 ... 15: |
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s->wregs[s->reg] = val; |
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break;
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case 9: |
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switch (val & 0xc0) { |
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case 0: |
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default:
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break;
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case 0x40: |
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slavio_serial_reset_chn(&ser->chn[1]);
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return;
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case 0x80: |
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slavio_serial_reset_chn(&ser->chn[0]);
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return;
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case 0xc0: |
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slavio_serial_reset(ser); |
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return;
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} |
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break;
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default:
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break;
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} |
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if (s->reg == 0) |
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s->reg = newreg; |
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else
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s->reg = 0;
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break;
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case 1: |
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if (s->wregs[5] & 8) { // tx enabled |
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s->tx = val; |
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if (s->chr)
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qemu_chr_write(s->chr, &s->tx, 1);
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s->txint = 1;
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} |
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break;
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default:
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break;
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} |
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} |
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static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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SerialState *ser = opaque; |
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ChannelState *s; |
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uint32_t saddr; |
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uint32_t ret; |
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int channel;
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saddr = (addr & 3) >> 1; |
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channel = (addr & SERIAL_MAXADDR) >> 2;
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s = &ser->chn[channel]; |
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switch (saddr) {
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case 0: |
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ret = s->rregs[s->reg]; |
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s->reg = 0;
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return ret;
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case 1: |
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s->rregs[0] &= ~1; |
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return s->rx;
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default:
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break;
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} |
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return 0; |
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} |
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static int serial_can_receive(void *opaque) |
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{ |
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ChannelState *s = opaque; |
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if (((s->wregs[3] & 1) == 0) // Rx not enabled |
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|| ((s->rregs[0] & 1) == 1)) // char already available |
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return 0; |
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else
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return 1; |
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} |
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static void serial_receive_byte(ChannelState *s, int ch) |
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{ |
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s->rregs[0] |= 1; |
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s->rx = ch; |
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s->rxint = 1;
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slavio_serial_update_irq(s); |
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} |
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static void serial_receive_break(ChannelState *s) |
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{ |
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s->rregs[0] |= 0x80; |
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slavio_serial_update_irq(s); |
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} |
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static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
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{ |
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ChannelState *s = opaque; |
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serial_receive_byte(s, buf[0]);
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} |
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static void serial_event(void *opaque, int event) |
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{ |
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ChannelState *s = opaque; |
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if (event == CHR_EVENT_BREAK)
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serial_receive_break(s); |
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} |
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static CPUReadMemoryFunc *slavio_serial_mem_read[3] = { |
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slavio_serial_mem_readb, |
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slavio_serial_mem_readb, |
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slavio_serial_mem_readb, |
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}; |
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static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = { |
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slavio_serial_mem_writeb, |
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slavio_serial_mem_writeb, |
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slavio_serial_mem_writeb, |
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}; |
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static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s) |
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{ |
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qemu_put_be32s(f, &s->irq); |
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qemu_put_be32s(f, &s->reg); |
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qemu_put_be32s(f, &s->rxint); |
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qemu_put_be32s(f, &s->txint); |
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qemu_put_8s(f, &s->rx); |
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qemu_put_8s(f, &s->tx); |
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qemu_put_buffer(f, s->wregs, 16);
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qemu_put_buffer(f, s->rregs, 16);
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} |
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static void slavio_serial_save(QEMUFile *f, void *opaque) |
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{ |
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SerialState *s = opaque; |
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slavio_serial_save_chn(f, &s->chn[0]);
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slavio_serial_save_chn(f, &s->chn[1]);
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} |
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static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id) |
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{ |
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if (version_id != 1) |
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return -EINVAL;
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qemu_get_be32s(f, &s->irq); |
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qemu_get_be32s(f, &s->reg); |
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qemu_get_be32s(f, &s->rxint); |
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qemu_get_be32s(f, &s->txint); |
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qemu_get_8s(f, &s->rx); |
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qemu_get_8s(f, &s->tx); |
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qemu_get_buffer(f, s->wregs, 16);
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qemu_get_buffer(f, s->rregs, 16);
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return 0; |
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} |
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static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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SerialState *s = opaque; |
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int ret;
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ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
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if (ret != 0) |
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return ret;
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ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
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return ret;
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} |
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SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2) |
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{ |
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int slavio_serial_io_memory;
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SerialState *s; |
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s = qemu_mallocz(sizeof(SerialState));
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if (!s)
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return NULL; |
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s->chn[0].irq = irq;
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s->chn[1].irq = irq;
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s->chn[0].chr = chr1;
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s->chn[1].chr = chr2;
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slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
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cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory); |
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if (chr1) {
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qemu_chr_add_read_handler(chr1, serial_can_receive, serial_receive1, &s->chn[0]);
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qemu_chr_add_event_handler(chr1, serial_event); |
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} |
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if (chr2) {
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qemu_chr_add_read_handler(chr2, serial_can_receive, serial_receive1, &s->chn[1]);
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qemu_chr_add_event_handler(chr2, serial_event); |
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} |
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register_savevm("slavio_serial", base, 1, slavio_serial_save, slavio_serial_load, s); |
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qemu_register_reset(slavio_serial_reset, s); |
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slavio_serial_reset(s); |
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return s;
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} |
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static void sunkbd_event(void *opaque, int ch) |
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{ |
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ChannelState *s = opaque; |
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// XXX: PC -> Sun Type 5 translation?
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serial_receive_byte(s, ch); |
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} |
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static void sunmouse_event(void *opaque, |
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int dx, int dy, int dz, int buttons_state) |
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{ |
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ChannelState *s = opaque; |
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int ch;
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// XXX
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ch = 0x42;
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serial_receive_byte(s, ch); |
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} |
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void slavio_serial_ms_kbd_init(int base, int irq) |
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{ |
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int slavio_serial_io_memory;
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SerialState *s; |
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s = qemu_mallocz(sizeof(SerialState));
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if (!s)
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return;
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s->chn[0].irq = irq;
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s->chn[1].irq = irq;
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s->chn[0].chr = NULL; |
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s->chn[1].chr = NULL; |
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slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
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cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory); |
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qemu_add_kbd_event_handler(sunkbd_event, &s->chn[0]);
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qemu_add_mouse_event_handler(sunmouse_event, &s->chn[1]);
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qemu_register_reset(slavio_serial_reset, s); |
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slavio_serial_reset(s); |
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} |