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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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25 | fbf9eeb3 | bellard | #undef EAX
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26 | fbf9eeb3 | bellard | #undef ECX
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27 | fbf9eeb3 | bellard | #undef EDX
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28 | fbf9eeb3 | bellard | #undef EBX
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29 | fbf9eeb3 | bellard | #undef ESP
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30 | fbf9eeb3 | bellard | #undef EBP
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31 | fbf9eeb3 | bellard | #undef ESI
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32 | fbf9eeb3 | bellard | #undef EDI
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33 | fbf9eeb3 | bellard | #undef EIP
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34 | fbf9eeb3 | bellard | #include <signal.h> |
35 | fbf9eeb3 | bellard | #include <sys/ucontext.h> |
36 | fbf9eeb3 | bellard | #endif
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37 | fbf9eeb3 | bellard | |
38 | 36bdbe54 | bellard | int tb_invalidated_flag;
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39 | 36bdbe54 | bellard | |
40 | dc99065b | bellard | //#define DEBUG_EXEC
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41 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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42 | 7d13299d | bellard | |
43 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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44 | e4533c7a | bellard | /* XXX: unify with i386 target */
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45 | e4533c7a | bellard | void cpu_loop_exit(void) |
46 | e4533c7a | bellard | { |
47 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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48 | e4533c7a | bellard | } |
49 | e4533c7a | bellard | #endif
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50 | 3475187d | bellard | #ifndef TARGET_SPARC
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51 | 3475187d | bellard | #define reg_T2
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52 | 3475187d | bellard | #endif
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53 | e4533c7a | bellard | |
54 | fbf9eeb3 | bellard | /* exit the current TB from a signal handler. The host registers are
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55 | fbf9eeb3 | bellard | restored in a state compatible with the CPU emulator
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56 | fbf9eeb3 | bellard | */
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57 | fbf9eeb3 | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc) |
58 | fbf9eeb3 | bellard | { |
59 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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60 | fbf9eeb3 | bellard | struct ucontext *uc = puc;
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61 | fbf9eeb3 | bellard | #endif
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62 | fbf9eeb3 | bellard | |
63 | fbf9eeb3 | bellard | env = env1; |
64 | fbf9eeb3 | bellard | |
65 | fbf9eeb3 | bellard | /* XXX: restore cpu registers saved in host registers */
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66 | fbf9eeb3 | bellard | |
67 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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68 | fbf9eeb3 | bellard | if (puc) {
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69 | fbf9eeb3 | bellard | /* XXX: use siglongjmp ? */
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70 | fbf9eeb3 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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71 | fbf9eeb3 | bellard | } |
72 | fbf9eeb3 | bellard | #endif
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73 | fbf9eeb3 | bellard | longjmp(env->jmp_env, 1);
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74 | fbf9eeb3 | bellard | } |
75 | fbf9eeb3 | bellard | |
76 | 7d13299d | bellard | /* main execution loop */
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77 | 7d13299d | bellard | |
78 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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79 | 7d13299d | bellard | { |
80 | 3475187d | bellard | int saved_T0, saved_T1;
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81 | 3475187d | bellard | #if defined(reg_T2)
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82 | 3475187d | bellard | int saved_T2;
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83 | 3475187d | bellard | #endif
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84 | e4533c7a | bellard | CPUState *saved_env; |
85 | 3475187d | bellard | #if defined(TARGET_I386)
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86 | 04369ff2 | bellard | #ifdef reg_EAX
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87 | 04369ff2 | bellard | int saved_EAX;
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88 | 04369ff2 | bellard | #endif
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89 | 04369ff2 | bellard | #ifdef reg_ECX
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90 | 04369ff2 | bellard | int saved_ECX;
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91 | 04369ff2 | bellard | #endif
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92 | 04369ff2 | bellard | #ifdef reg_EDX
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93 | 04369ff2 | bellard | int saved_EDX;
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94 | 04369ff2 | bellard | #endif
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95 | 04369ff2 | bellard | #ifdef reg_EBX
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96 | 04369ff2 | bellard | int saved_EBX;
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97 | 04369ff2 | bellard | #endif
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98 | 04369ff2 | bellard | #ifdef reg_ESP
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99 | 04369ff2 | bellard | int saved_ESP;
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100 | 04369ff2 | bellard | #endif
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101 | 04369ff2 | bellard | #ifdef reg_EBP
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102 | 04369ff2 | bellard | int saved_EBP;
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103 | 04369ff2 | bellard | #endif
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104 | 04369ff2 | bellard | #ifdef reg_ESI
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105 | 04369ff2 | bellard | int saved_ESI;
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106 | 04369ff2 | bellard | #endif
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107 | 04369ff2 | bellard | #ifdef reg_EDI
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108 | 04369ff2 | bellard | int saved_EDI;
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109 | 04369ff2 | bellard | #endif
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110 | 3475187d | bellard | #elif defined(TARGET_SPARC)
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111 | 3475187d | bellard | #if defined(reg_REGWPTR)
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112 | 3475187d | bellard | uint32_t *saved_regwptr; |
113 | 3475187d | bellard | #endif
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114 | 3475187d | bellard | #endif
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115 | 8c6939c0 | bellard | #ifdef __sparc__
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116 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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117 | 8c6939c0 | bellard | #endif
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118 | 68a79315 | bellard | int code_gen_size, ret, interrupt_request;
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119 | 7d13299d | bellard | void (*gen_func)(void); |
120 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
121 | c27004ec | bellard | target_ulong cs_base, pc; |
122 | c27004ec | bellard | uint8_t *tc_ptr; |
123 | 6dbad63e | bellard | unsigned int flags; |
124 | 8c6939c0 | bellard | |
125 | 7d13299d | bellard | /* first we save global registers */
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126 | c27004ec | bellard | saved_env = env; |
127 | c27004ec | bellard | env = env1; |
128 | 7d13299d | bellard | saved_T0 = T0; |
129 | 7d13299d | bellard | saved_T1 = T1; |
130 | 3475187d | bellard | #if defined(reg_T2)
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131 | e4533c7a | bellard | saved_T2 = T2; |
132 | 3475187d | bellard | #endif
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133 | e4533c7a | bellard | #ifdef __sparc__
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134 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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135 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
136 | e4533c7a | bellard | #endif
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137 | e4533c7a | bellard | |
138 | e4533c7a | bellard | #if defined(TARGET_I386)
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139 | 04369ff2 | bellard | #ifdef reg_EAX
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140 | 04369ff2 | bellard | saved_EAX = EAX; |
141 | 04369ff2 | bellard | #endif
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142 | 04369ff2 | bellard | #ifdef reg_ECX
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143 | 04369ff2 | bellard | saved_ECX = ECX; |
144 | 04369ff2 | bellard | #endif
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145 | 04369ff2 | bellard | #ifdef reg_EDX
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146 | 04369ff2 | bellard | saved_EDX = EDX; |
147 | 04369ff2 | bellard | #endif
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148 | 04369ff2 | bellard | #ifdef reg_EBX
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149 | 04369ff2 | bellard | saved_EBX = EBX; |
150 | 04369ff2 | bellard | #endif
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151 | 04369ff2 | bellard | #ifdef reg_ESP
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152 | 04369ff2 | bellard | saved_ESP = ESP; |
153 | 04369ff2 | bellard | #endif
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154 | 04369ff2 | bellard | #ifdef reg_EBP
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155 | 04369ff2 | bellard | saved_EBP = EBP; |
156 | 04369ff2 | bellard | #endif
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157 | 04369ff2 | bellard | #ifdef reg_ESI
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158 | 04369ff2 | bellard | saved_ESI = ESI; |
159 | 04369ff2 | bellard | #endif
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160 | 04369ff2 | bellard | #ifdef reg_EDI
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161 | 04369ff2 | bellard | saved_EDI = EDI; |
162 | 04369ff2 | bellard | #endif
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163 | 0d1a29f9 | bellard | |
164 | 0d1a29f9 | bellard | env_to_regs(); |
165 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
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166 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
167 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
168 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
169 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
170 | e4533c7a | bellard | #elif defined(TARGET_ARM)
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171 | e4533c7a | bellard | { |
172 | e4533c7a | bellard | unsigned int psr; |
173 | e4533c7a | bellard | psr = env->cpsr; |
174 | e4533c7a | bellard | env->CF = (psr >> 29) & 1; |
175 | e4533c7a | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
176 | e4533c7a | bellard | env->VF = (psr << 3) & 0x80000000; |
177 | 99c475ab | bellard | env->QF = (psr >> 27) & 1; |
178 | 99c475ab | bellard | env->cpsr = psr & ~CACHED_CPSR_BITS; |
179 | e4533c7a | bellard | } |
180 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
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181 | 3475187d | bellard | #if defined(reg_REGWPTR)
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182 | 3475187d | bellard | saved_regwptr = REGWPTR; |
183 | 3475187d | bellard | #endif
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184 | 67867308 | bellard | #elif defined(TARGET_PPC)
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185 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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186 | e4533c7a | bellard | #else
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187 | e4533c7a | bellard | #error unsupported target CPU
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188 | e4533c7a | bellard | #endif
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189 | 3fb2ded1 | bellard | env->exception_index = -1;
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190 | 9d27abd9 | bellard | |
191 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
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192 | 3fb2ded1 | bellard | for(;;) {
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193 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
194 | ee8b7021 | bellard | env->current_tb = NULL;
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195 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
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196 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
197 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
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198 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
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199 | 3fb2ded1 | bellard | ret = env->exception_index; |
200 | 3fb2ded1 | bellard | break;
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201 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
202 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
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203 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
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204 | 3fb2ded1 | bellard | loop */
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205 | 83479e77 | bellard | #if defined(TARGET_I386)
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206 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
207 | 3fb2ded1 | bellard | env->exception_is_int, |
208 | 3fb2ded1 | bellard | env->error_code, |
209 | 3fb2ded1 | bellard | env->exception_next_eip); |
210 | 83479e77 | bellard | #endif
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211 | 3fb2ded1 | bellard | ret = env->exception_index; |
212 | 3fb2ded1 | bellard | break;
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213 | 3fb2ded1 | bellard | } else {
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214 | 83479e77 | bellard | #if defined(TARGET_I386)
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215 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
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216 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
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217 | 3fb2ded1 | bellard | double or triple faults yet. */
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218 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
219 | 3fb2ded1 | bellard | env->exception_is_int, |
220 | 3fb2ded1 | bellard | env->error_code, |
221 | d05e66d2 | bellard | env->exception_next_eip, 0);
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222 | ce09776b | bellard | #elif defined(TARGET_PPC)
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223 | ce09776b | bellard | do_interrupt(env); |
224 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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225 | 6af0bf9c | bellard | do_interrupt(env); |
226 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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227 | 1a0c3292 | bellard | do_interrupt(env->exception_index); |
228 | 83479e77 | bellard | #endif
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229 | 3fb2ded1 | bellard | } |
230 | 3fb2ded1 | bellard | env->exception_index = -1;
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231 | 9df217a3 | bellard | } |
232 | 9df217a3 | bellard | #ifdef USE_KQEMU
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233 | 9df217a3 | bellard | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
234 | 9df217a3 | bellard | int ret;
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235 | 9df217a3 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
236 | 9df217a3 | bellard | ret = kqemu_cpu_exec(env); |
237 | 9df217a3 | bellard | /* put eflags in CPU temporary format */
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238 | 9df217a3 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
239 | 9df217a3 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
240 | 9df217a3 | bellard | CC_OP = CC_OP_EFLAGS; |
241 | 9df217a3 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
242 | 9df217a3 | bellard | if (ret == 1) { |
243 | 9df217a3 | bellard | /* exception */
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244 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
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245 | 9df217a3 | bellard | } else if (ret == 2) { |
246 | 9df217a3 | bellard | /* softmmu execution needed */
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247 | 9df217a3 | bellard | } else {
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248 | 9df217a3 | bellard | if (env->interrupt_request != 0) { |
249 | 9df217a3 | bellard | /* hardware interrupt will be executed just after */
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250 | 9df217a3 | bellard | } else {
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251 | 9df217a3 | bellard | /* otherwise, we restart */
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252 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
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253 | 9df217a3 | bellard | } |
254 | 9df217a3 | bellard | } |
255 | 3fb2ded1 | bellard | } |
256 | 9df217a3 | bellard | #endif
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257 | 9df217a3 | bellard | |
258 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
259 | 3fb2ded1 | bellard | for(;;) {
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260 | 8c6939c0 | bellard | #ifdef __sparc__
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261 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
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262 | 3fb2ded1 | bellard | tmp_T0 = T0; |
263 | 8c6939c0 | bellard | #endif
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264 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
265 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
266 | 68a79315 | bellard | #if defined(TARGET_I386)
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267 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
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268 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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269 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
270 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
271 | 68a79315 | bellard | int intno;
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272 | fbf9eeb3 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
273 | a541f297 | bellard | intno = cpu_get_pic_interrupt(env); |
274 | f193c797 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
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275 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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276 | 68a79315 | bellard | } |
277 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
278 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
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279 | 907a5b26 | bellard | the program flow was changed */
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280 | 907a5b26 | bellard | #ifdef __sparc__
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281 | 907a5b26 | bellard | tmp_T0 = 0;
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282 | 907a5b26 | bellard | #else
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283 | 907a5b26 | bellard | T0 = 0;
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284 | 907a5b26 | bellard | #endif
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285 | 68a79315 | bellard | } |
286 | ce09776b | bellard | #elif defined(TARGET_PPC)
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287 | 9fddaa0c | bellard | #if 0
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288 | 9fddaa0c | bellard | if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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289 | 9fddaa0c | bellard | cpu_ppc_reset(env);
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290 | 9fddaa0c | bellard | }
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291 | 9fddaa0c | bellard | #endif
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292 | 9fddaa0c | bellard | if (msr_ee != 0) { |
293 | ce09776b | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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294 | 9fddaa0c | bellard | /* Raise it */
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295 | 9fddaa0c | bellard | env->exception_index = EXCP_EXTERNAL; |
296 | 9fddaa0c | bellard | env->error_code = 0;
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297 | ce09776b | bellard | do_interrupt(env); |
298 | ce09776b | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
299 | 9fddaa0c | bellard | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
300 | 9fddaa0c | bellard | /* Raise it */
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301 | 9fddaa0c | bellard | env->exception_index = EXCP_DECR; |
302 | 9fddaa0c | bellard | env->error_code = 0;
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303 | 9fddaa0c | bellard | do_interrupt(env); |
304 | 9fddaa0c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
305 | 9fddaa0c | bellard | } |
306 | ce09776b | bellard | } |
307 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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308 | 6af0bf9c | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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309 | 6af0bf9c | bellard | (env->CP0_Status & (1 << CP0St_IE)) &&
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310 | 7ebab699 | bellard | (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
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311 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_EXL) && |
312 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_ERL) && |
313 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_DM)) { |
314 | 6af0bf9c | bellard | /* Raise it */
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315 | 6af0bf9c | bellard | env->exception_index = EXCP_EXT_INTERRUPT; |
316 | 6af0bf9c | bellard | env->error_code = 0;
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317 | 6af0bf9c | bellard | do_interrupt(env); |
318 | 6af0bf9c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
319 | 6af0bf9c | bellard | } |
320 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
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321 | 66321a11 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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322 | 66321a11 | bellard | (env->psret != 0)) {
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323 | 66321a11 | bellard | int pil = env->interrupt_index & 15; |
324 | 66321a11 | bellard | int type = env->interrupt_index & 0xf0; |
325 | 66321a11 | bellard | |
326 | 66321a11 | bellard | if (((type == TT_EXTINT) &&
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327 | 66321a11 | bellard | (pil == 15 || pil > env->psrpil)) ||
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328 | 66321a11 | bellard | type != TT_EXTINT) { |
329 | 66321a11 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
330 | 66321a11 | bellard | do_interrupt(env->interrupt_index); |
331 | 66321a11 | bellard | env->interrupt_index = 0;
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332 | 66321a11 | bellard | } |
333 | e95c8d51 | bellard | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
334 | e95c8d51 | bellard | //do_interrupt(0, 0, 0, 0, 0);
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335 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
336 | e95c8d51 | bellard | } |
337 | 68a79315 | bellard | #endif
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338 | bf3e8bf1 | bellard | if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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339 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
340 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
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341 | bf3e8bf1 | bellard | the program flow was changed */
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342 | bf3e8bf1 | bellard | #ifdef __sparc__
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343 | bf3e8bf1 | bellard | tmp_T0 = 0;
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344 | bf3e8bf1 | bellard | #else
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345 | bf3e8bf1 | bellard | T0 = 0;
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346 | bf3e8bf1 | bellard | #endif
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347 | bf3e8bf1 | bellard | } |
348 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
349 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
350 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
351 | 68a79315 | bellard | cpu_loop_exit(); |
352 | 68a79315 | bellard | } |
353 | 3fb2ded1 | bellard | } |
354 | 7d13299d | bellard | #ifdef DEBUG_EXEC
|
355 | c27004ec | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
356 | e4533c7a | bellard | #if defined(TARGET_I386)
|
357 | 3fb2ded1 | bellard | /* restore flags in standard format */
|
358 | fc9f715d | bellard | #ifdef reg_EAX
|
359 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
360 | fc9f715d | bellard | #endif
|
361 | fc9f715d | bellard | #ifdef reg_EBX
|
362 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
363 | fc9f715d | bellard | #endif
|
364 | fc9f715d | bellard | #ifdef reg_ECX
|
365 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
366 | fc9f715d | bellard | #endif
|
367 | fc9f715d | bellard | #ifdef reg_EDX
|
368 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
369 | fc9f715d | bellard | #endif
|
370 | fc9f715d | bellard | #ifdef reg_ESI
|
371 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
372 | fc9f715d | bellard | #endif
|
373 | fc9f715d | bellard | #ifdef reg_EDI
|
374 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
375 | fc9f715d | bellard | #endif
|
376 | fc9f715d | bellard | #ifdef reg_EBP
|
377 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
378 | fc9f715d | bellard | #endif
|
379 | fc9f715d | bellard | #ifdef reg_ESP
|
380 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
381 | fc9f715d | bellard | #endif
|
382 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
383 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
384 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
385 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
386 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
387 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
388 | 99c475ab | bellard | env->cpsr &= ~CACHED_CPSR_BITS; |
389 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
390 | 3475187d | bellard | REGWPTR = env->regbase + (env->cwp * 16);
|
391 | 3475187d | bellard | env->regwptr = REGWPTR; |
392 | 3475187d | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
393 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
394 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
395 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
396 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
397 | e4533c7a | bellard | #else
|
398 | e4533c7a | bellard | #error unsupported target CPU
|
399 | e4533c7a | bellard | #endif
|
400 | 3fb2ded1 | bellard | } |
401 | 7d13299d | bellard | #endif
|
402 | 3f337316 | bellard | /* we record a subset of the CPU state. It will
|
403 | 3f337316 | bellard | always be the same before a given translated block
|
404 | 3f337316 | bellard | is executed. */
|
405 | e4533c7a | bellard | #if defined(TARGET_I386)
|
406 | 2e255c6b | bellard | flags = env->hflags; |
407 | 3f337316 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
408 | 3fb2ded1 | bellard | cs_base = env->segs[R_CS].base; |
409 | 3fb2ded1 | bellard | pc = cs_base + env->eip; |
410 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
411 | b7bcbe95 | bellard | flags = env->thumb | (env->vfp.vec_len << 1)
|
412 | b7bcbe95 | bellard | | (env->vfp.vec_stride << 4);
|
413 | 3fb2ded1 | bellard | cs_base = 0;
|
414 | c27004ec | bellard | pc = env->regs[15];
|
415 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
416 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
417 | 3475187d | bellard | flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); |
418 | 3475187d | bellard | #else
|
419 | 3475187d | bellard | flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1); |
420 | 3475187d | bellard | #endif
|
421 | c27004ec | bellard | cs_base = env->npc; |
422 | c27004ec | bellard | pc = env->pc; |
423 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
424 | 111bfab3 | bellard | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
425 | 111bfab3 | bellard | (msr_se << MSR_SE) | (msr_le << MSR_LE); |
426 | 67867308 | bellard | cs_base = 0;
|
427 | c27004ec | bellard | pc = env->nip; |
428 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
429 | 6af0bf9c | bellard | flags = env->hflags & MIPS_HFLAGS_TMASK; |
430 | 6af0bf9c | bellard | cs_base = NULL;
|
431 | 6af0bf9c | bellard | pc = env->PC; |
432 | e4533c7a | bellard | #else
|
433 | e4533c7a | bellard | #error unsupported CPU
|
434 | e4533c7a | bellard | #endif
|
435 | c27004ec | bellard | tb = tb_find(&ptb, pc, cs_base, |
436 | 3fb2ded1 | bellard | flags); |
437 | d4e8164f | bellard | if (!tb) {
|
438 | 1376847f | bellard | TranslationBlock **ptb1; |
439 | 1376847f | bellard | unsigned int h; |
440 | 1376847f | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
441 | 1376847f | bellard | |
442 | 1376847f | bellard | |
443 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
444 | 1376847f | bellard | |
445 | 1376847f | bellard | tb_invalidated_flag = 0;
|
446 | 0d1a29f9 | bellard | |
447 | 0d1a29f9 | bellard | regs_to_env(); /* XXX: do it just before cpu_gen_code() */
|
448 | 1376847f | bellard | |
449 | 1376847f | bellard | /* find translated block using physical mappings */
|
450 | c27004ec | bellard | phys_pc = get_phys_addr_code(env, pc); |
451 | 1376847f | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
452 | 1376847f | bellard | phys_page2 = -1;
|
453 | 1376847f | bellard | h = tb_phys_hash_func(phys_pc); |
454 | 1376847f | bellard | ptb1 = &tb_phys_hash[h]; |
455 | 1376847f | bellard | for(;;) {
|
456 | 1376847f | bellard | tb = *ptb1; |
457 | 1376847f | bellard | if (!tb)
|
458 | 1376847f | bellard | goto not_found;
|
459 | c27004ec | bellard | if (tb->pc == pc &&
|
460 | 1376847f | bellard | tb->page_addr[0] == phys_page1 &&
|
461 | c27004ec | bellard | tb->cs_base == cs_base && |
462 | 1376847f | bellard | tb->flags == flags) { |
463 | 1376847f | bellard | /* check next page if needed */
|
464 | b516f85c | bellard | if (tb->page_addr[1] != -1) { |
465 | c27004ec | bellard | virt_page2 = (pc & TARGET_PAGE_MASK) + |
466 | b516f85c | bellard | TARGET_PAGE_SIZE; |
467 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
468 | 1376847f | bellard | if (tb->page_addr[1] == phys_page2) |
469 | 1376847f | bellard | goto found;
|
470 | 1376847f | bellard | } else {
|
471 | 1376847f | bellard | goto found;
|
472 | 1376847f | bellard | } |
473 | 1376847f | bellard | } |
474 | 1376847f | bellard | ptb1 = &tb->phys_hash_next; |
475 | 1376847f | bellard | } |
476 | 1376847f | bellard | not_found:
|
477 | 3fb2ded1 | bellard | /* if no translated code available, then translate it now */
|
478 | c27004ec | bellard | tb = tb_alloc(pc); |
479 | 3fb2ded1 | bellard | if (!tb) {
|
480 | 3fb2ded1 | bellard | /* flush must be done */
|
481 | b453b70b | bellard | tb_flush(env); |
482 | 3fb2ded1 | bellard | /* cannot fail at this point */
|
483 | c27004ec | bellard | tb = tb_alloc(pc); |
484 | 3fb2ded1 | bellard | /* don't forget to invalidate previous TB info */
|
485 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
486 | 3fb2ded1 | bellard | T0 = 0;
|
487 | 3fb2ded1 | bellard | } |
488 | 3fb2ded1 | bellard | tc_ptr = code_gen_ptr; |
489 | 3fb2ded1 | bellard | tb->tc_ptr = tc_ptr; |
490 | c27004ec | bellard | tb->cs_base = cs_base; |
491 | 3fb2ded1 | bellard | tb->flags = flags; |
492 | facc68be | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
493 | 1376847f | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
494 | 1376847f | bellard | |
495 | 1376847f | bellard | /* check next page if needed */
|
496 | c27004ec | bellard | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
497 | 1376847f | bellard | phys_page2 = -1;
|
498 | c27004ec | bellard | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
499 | 1376847f | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
500 | 1376847f | bellard | } |
501 | 1376847f | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
502 | 1376847f | bellard | |
503 | 1376847f | bellard | found:
|
504 | 36bdbe54 | bellard | if (tb_invalidated_flag) {
|
505 | 36bdbe54 | bellard | /* as some TB could have been invalidated because
|
506 | 36bdbe54 | bellard | of memory exceptions while generating the code, we
|
507 | 36bdbe54 | bellard | must recompute the hash index here */
|
508 | c27004ec | bellard | ptb = &tb_hash[tb_hash_func(pc)]; |
509 | 36bdbe54 | bellard | while (*ptb != NULL) |
510 | 36bdbe54 | bellard | ptb = &(*ptb)->hash_next; |
511 | 36bdbe54 | bellard | T0 = 0;
|
512 | 36bdbe54 | bellard | } |
513 | 1376847f | bellard | /* we add the TB in the virtual pc hash table */
|
514 | 3fb2ded1 | bellard | *ptb = tb; |
515 | 3fb2ded1 | bellard | tb->hash_next = NULL;
|
516 | 3fb2ded1 | bellard | tb_link(tb); |
517 | 25eb4484 | bellard | spin_unlock(&tb_lock); |
518 | 9de5e440 | bellard | } |
519 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
520 | c1135f61 | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
521 | c27004ec | bellard | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
522 | c27004ec | bellard | (long)tb->tc_ptr, tb->pc,
|
523 | c27004ec | bellard | lookup_symbol(tb->pc)); |
524 | 3fb2ded1 | bellard | } |
525 | 9d27abd9 | bellard | #endif
|
526 | 8c6939c0 | bellard | #ifdef __sparc__
|
527 | 3fb2ded1 | bellard | T0 = tmp_T0; |
528 | 8c6939c0 | bellard | #endif
|
529 | facc68be | bellard | /* see if we can patch the calling TB. */
|
530 | c27004ec | bellard | { |
531 | c27004ec | bellard | if (T0 != 0 |
532 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
533 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
534 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
535 | bf3e8bf1 | bellard | #endif
|
536 | bf3e8bf1 | bellard | ) { |
537 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
538 | c27004ec | bellard | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
539 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
540 | 97eb5b14 | bellard | /* propagates the FP use info */
|
541 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
542 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
543 | 97eb5b14 | bellard | #endif
|
544 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
545 | 3fb2ded1 | bellard | } |
546 | c27004ec | bellard | } |
547 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
548 | 83479e77 | bellard | env->current_tb = tb; |
549 | 3fb2ded1 | bellard | /* execute the generated code */
|
550 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
551 | 8c6939c0 | bellard | #if defined(__sparc__)
|
552 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
553 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
554 | 3fb2ded1 | bellard | : /* no outputs */
|
555 | 3fb2ded1 | bellard | : "r" (gen_func)
|
556 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
557 | 8c6939c0 | bellard | #elif defined(__arm__)
|
558 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
559 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
560 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
561 | 3fb2ded1 | bellard | : /* no outputs */
|
562 | 3fb2ded1 | bellard | : "r" (gen_func)
|
563 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
564 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
565 | bf3e8bf1 | bellard | { |
566 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
567 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
568 | 97eb5b14 | bellard | save_native_fp_state(env); |
569 | 97eb5b14 | bellard | } |
570 | bf3e8bf1 | bellard | gen_func(); |
571 | bf3e8bf1 | bellard | } else {
|
572 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
573 | 97eb5b14 | bellard | restore_native_fp_state(env); |
574 | 97eb5b14 | bellard | } |
575 | bf3e8bf1 | bellard | /* we work with native eflags */
|
576 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
577 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
578 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
579 | bf3e8bf1 | bellard | "\n"
|
580 | bf3e8bf1 | bellard | "debug1:\n"
|
581 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
582 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
583 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
584 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
585 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
586 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
587 | bf3e8bf1 | bellard | " popf\n"
|
588 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
589 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
590 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
591 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
592 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
593 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
594 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
595 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
596 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
597 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
598 | bf3e8bf1 | bellard | "exec_loop:\n"
|
599 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
600 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
601 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
602 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
603 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
604 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
605 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
606 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
607 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
608 | bf3e8bf1 | bellard | " pushf\n"
|
609 | bf3e8bf1 | bellard | " popl %%eax\n"
|
610 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
611 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
612 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
613 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
614 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
615 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
616 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
617 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
618 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
619 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
620 | bf3e8bf1 | bellard | : |
621 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
622 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
623 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
624 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
625 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
626 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
627 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
628 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
629 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
630 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
631 | bf3e8bf1 | bellard | "a" (gen_func),
|
632 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
633 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
634 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
635 | bf3e8bf1 | bellard | ); |
636 | bf3e8bf1 | bellard | } |
637 | bf3e8bf1 | bellard | } |
638 | b8076a74 | bellard | #elif defined(__ia64)
|
639 | b8076a74 | bellard | struct fptr {
|
640 | b8076a74 | bellard | void *ip;
|
641 | b8076a74 | bellard | void *gp;
|
642 | b8076a74 | bellard | } fp; |
643 | b8076a74 | bellard | |
644 | b8076a74 | bellard | fp.ip = tc_ptr; |
645 | b8076a74 | bellard | fp.gp = code_gen_buffer + 2 * (1 << 20); |
646 | b8076a74 | bellard | (*(void (*)(void)) &fp)(); |
647 | ae228531 | bellard | #else
|
648 | 3fb2ded1 | bellard | gen_func(); |
649 | ae228531 | bellard | #endif
|
650 | 83479e77 | bellard | env->current_tb = NULL;
|
651 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
652 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
653 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
654 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
655 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
656 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
657 | 4cbf74b6 | bellard | T0 = 0;
|
658 | 4cbf74b6 | bellard | } |
659 | 4cbf74b6 | bellard | #endif
|
660 | 3fb2ded1 | bellard | } |
661 | 3fb2ded1 | bellard | } else {
|
662 | 0d1a29f9 | bellard | env_to_regs(); |
663 | 7d13299d | bellard | } |
664 | 3fb2ded1 | bellard | } /* for(;;) */
|
665 | 3fb2ded1 | bellard | |
666 | 7d13299d | bellard | |
667 | e4533c7a | bellard | #if defined(TARGET_I386)
|
668 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
669 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
670 | 97eb5b14 | bellard | save_native_fp_state(env); |
671 | 97eb5b14 | bellard | } |
672 | 97eb5b14 | bellard | #endif
|
673 | 9de5e440 | bellard | /* restore flags in standard format */
|
674 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
675 | 9de5e440 | bellard | |
676 | 7d13299d | bellard | /* restore global registers */
|
677 | 04369ff2 | bellard | #ifdef reg_EAX
|
678 | 04369ff2 | bellard | EAX = saved_EAX; |
679 | 04369ff2 | bellard | #endif
|
680 | 04369ff2 | bellard | #ifdef reg_ECX
|
681 | 04369ff2 | bellard | ECX = saved_ECX; |
682 | 04369ff2 | bellard | #endif
|
683 | 04369ff2 | bellard | #ifdef reg_EDX
|
684 | 04369ff2 | bellard | EDX = saved_EDX; |
685 | 04369ff2 | bellard | #endif
|
686 | 04369ff2 | bellard | #ifdef reg_EBX
|
687 | 04369ff2 | bellard | EBX = saved_EBX; |
688 | 04369ff2 | bellard | #endif
|
689 | 04369ff2 | bellard | #ifdef reg_ESP
|
690 | 04369ff2 | bellard | ESP = saved_ESP; |
691 | 04369ff2 | bellard | #endif
|
692 | 04369ff2 | bellard | #ifdef reg_EBP
|
693 | 04369ff2 | bellard | EBP = saved_EBP; |
694 | 04369ff2 | bellard | #endif
|
695 | 04369ff2 | bellard | #ifdef reg_ESI
|
696 | 04369ff2 | bellard | ESI = saved_ESI; |
697 | 04369ff2 | bellard | #endif
|
698 | 04369ff2 | bellard | #ifdef reg_EDI
|
699 | 04369ff2 | bellard | EDI = saved_EDI; |
700 | 04369ff2 | bellard | #endif
|
701 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
702 | 1b21b62a | bellard | env->cpsr = compute_cpsr(); |
703 | b7bcbe95 | bellard | /* XXX: Save/restore host fpu exception state?. */
|
704 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
705 | 3475187d | bellard | #if defined(reg_REGWPTR)
|
706 | 3475187d | bellard | REGWPTR = saved_regwptr; |
707 | 3475187d | bellard | #endif
|
708 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
709 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
710 | e4533c7a | bellard | #else
|
711 | e4533c7a | bellard | #error unsupported target CPU
|
712 | e4533c7a | bellard | #endif
|
713 | 8c6939c0 | bellard | #ifdef __sparc__
|
714 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
715 | 8c6939c0 | bellard | #endif
|
716 | 7d13299d | bellard | T0 = saved_T0; |
717 | 7d13299d | bellard | T1 = saved_T1; |
718 | 3475187d | bellard | #if defined(reg_T2)
|
719 | e4533c7a | bellard | T2 = saved_T2; |
720 | 3475187d | bellard | #endif
|
721 | 7d13299d | bellard | env = saved_env; |
722 | 7d13299d | bellard | return ret;
|
723 | 7d13299d | bellard | } |
724 | 6dbad63e | bellard | |
725 | fbf9eeb3 | bellard | /* must only be called from the generated code as an exception can be
|
726 | fbf9eeb3 | bellard | generated */
|
727 | fbf9eeb3 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
728 | fbf9eeb3 | bellard | { |
729 | dc5d0b3d | bellard | /* XXX: cannot enable it yet because it yields to MMU exception
|
730 | dc5d0b3d | bellard | where NIP != read address on PowerPC */
|
731 | dc5d0b3d | bellard | #if 0
|
732 | fbf9eeb3 | bellard | target_ulong phys_addr;
|
733 | fbf9eeb3 | bellard | phys_addr = get_phys_addr_code(env, start);
|
734 | fbf9eeb3 | bellard | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
735 | dc5d0b3d | bellard | #endif
|
736 | fbf9eeb3 | bellard | } |
737 | fbf9eeb3 | bellard | |
738 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
739 | e4533c7a | bellard | |
740 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
741 | 6dbad63e | bellard | { |
742 | 6dbad63e | bellard | CPUX86State *saved_env; |
743 | 6dbad63e | bellard | |
744 | 6dbad63e | bellard | saved_env = env; |
745 | 6dbad63e | bellard | env = s; |
746 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
747 | a513fe19 | bellard | selector &= 0xffff;
|
748 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
749 | c27004ec | bellard | (selector << 4), 0xffff, 0); |
750 | a513fe19 | bellard | } else {
|
751 | b453b70b | bellard | load_seg(seg_reg, selector); |
752 | a513fe19 | bellard | } |
753 | 6dbad63e | bellard | env = saved_env; |
754 | 6dbad63e | bellard | } |
755 | 9de5e440 | bellard | |
756 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
757 | d0a1ffc9 | bellard | { |
758 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
759 | d0a1ffc9 | bellard | |
760 | d0a1ffc9 | bellard | saved_env = env; |
761 | d0a1ffc9 | bellard | env = s; |
762 | d0a1ffc9 | bellard | |
763 | c27004ec | bellard | helper_fsave((target_ulong)ptr, data32); |
764 | d0a1ffc9 | bellard | |
765 | d0a1ffc9 | bellard | env = saved_env; |
766 | d0a1ffc9 | bellard | } |
767 | d0a1ffc9 | bellard | |
768 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
769 | d0a1ffc9 | bellard | { |
770 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
771 | d0a1ffc9 | bellard | |
772 | d0a1ffc9 | bellard | saved_env = env; |
773 | d0a1ffc9 | bellard | env = s; |
774 | d0a1ffc9 | bellard | |
775 | c27004ec | bellard | helper_frstor((target_ulong)ptr, data32); |
776 | d0a1ffc9 | bellard | |
777 | d0a1ffc9 | bellard | env = saved_env; |
778 | d0a1ffc9 | bellard | } |
779 | d0a1ffc9 | bellard | |
780 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
781 | e4533c7a | bellard | |
782 | 67b915a5 | bellard | #if !defined(CONFIG_SOFTMMU)
|
783 | 67b915a5 | bellard | |
784 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
785 | 3fb2ded1 | bellard | |
786 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
787 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
788 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
789 | fd6ce8f6 | bellard | signal set which should be restored */
|
790 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
791 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
792 | bf3e8bf1 | bellard | void *puc)
|
793 | 9de5e440 | bellard | { |
794 | a513fe19 | bellard | TranslationBlock *tb; |
795 | a513fe19 | bellard | int ret;
|
796 | 68a79315 | bellard | |
797 | 83479e77 | bellard | if (cpu_single_env)
|
798 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
799 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
800 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
801 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
802 | 9de5e440 | bellard | #endif
|
803 | 25eb4484 | bellard | /* XXX: locking issue */
|
804 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
805 | fd6ce8f6 | bellard | return 1; |
806 | fd6ce8f6 | bellard | } |
807 | fbf9eeb3 | bellard | |
808 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
809 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
810 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
811 | 3fb2ded1 | bellard | if (ret < 0) |
812 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
813 | 3fb2ded1 | bellard | if (ret == 0) |
814 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
815 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
816 | a513fe19 | bellard | tb = tb_find_pc(pc); |
817 | a513fe19 | bellard | if (tb) {
|
818 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
819 | 9de5e440 | bellard | a virtual CPU fault */
|
820 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
821 | 3fb2ded1 | bellard | } |
822 | 4cbf74b6 | bellard | if (ret == 1) { |
823 | 3fb2ded1 | bellard | #if 0
|
824 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
825 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
826 | 3fb2ded1 | bellard | #endif
|
827 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
828 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
829 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
830 | 4cbf74b6 | bellard | raise_exception_err(EXCP0E_PAGE, env->error_code); |
831 | 4cbf74b6 | bellard | } else {
|
832 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
833 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
834 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
835 | 4cbf74b6 | bellard | } |
836 | 3fb2ded1 | bellard | /* never comes here */
|
837 | 3fb2ded1 | bellard | return 1; |
838 | 3fb2ded1 | bellard | } |
839 | 3fb2ded1 | bellard | |
840 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
841 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
842 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
843 | bf3e8bf1 | bellard | void *puc)
|
844 | 3fb2ded1 | bellard | { |
845 | 68016c62 | bellard | TranslationBlock *tb; |
846 | 68016c62 | bellard | int ret;
|
847 | 68016c62 | bellard | |
848 | 68016c62 | bellard | if (cpu_single_env)
|
849 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
850 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
851 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
852 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
853 | 68016c62 | bellard | #endif
|
854 | 9f0777ed | bellard | /* XXX: locking issue */
|
855 | 9f0777ed | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
856 | 9f0777ed | bellard | return 1; |
857 | 9f0777ed | bellard | } |
858 | 68016c62 | bellard | /* see if it is an MMU fault */
|
859 | 68016c62 | bellard | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
860 | 68016c62 | bellard | if (ret < 0) |
861 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
862 | 68016c62 | bellard | if (ret == 0) |
863 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
864 | 68016c62 | bellard | /* now we have a real cpu fault */
|
865 | 68016c62 | bellard | tb = tb_find_pc(pc); |
866 | 68016c62 | bellard | if (tb) {
|
867 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
868 | 68016c62 | bellard | a virtual CPU fault */
|
869 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
870 | 68016c62 | bellard | } |
871 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
872 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
873 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
874 | 68016c62 | bellard | cpu_loop_exit(); |
875 | 3fb2ded1 | bellard | } |
876 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
877 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
878 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
879 | bf3e8bf1 | bellard | void *puc)
|
880 | 93ac68bc | bellard | { |
881 | 68016c62 | bellard | TranslationBlock *tb; |
882 | 68016c62 | bellard | int ret;
|
883 | 68016c62 | bellard | |
884 | 68016c62 | bellard | if (cpu_single_env)
|
885 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
886 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
887 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
888 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
889 | 68016c62 | bellard | #endif
|
890 | b453b70b | bellard | /* XXX: locking issue */
|
891 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
892 | b453b70b | bellard | return 1; |
893 | b453b70b | bellard | } |
894 | 68016c62 | bellard | /* see if it is an MMU fault */
|
895 | 68016c62 | bellard | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
896 | 68016c62 | bellard | if (ret < 0) |
897 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
898 | 68016c62 | bellard | if (ret == 0) |
899 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
900 | 68016c62 | bellard | /* now we have a real cpu fault */
|
901 | 68016c62 | bellard | tb = tb_find_pc(pc); |
902 | 68016c62 | bellard | if (tb) {
|
903 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
904 | 68016c62 | bellard | a virtual CPU fault */
|
905 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
906 | 68016c62 | bellard | } |
907 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
908 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
909 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
910 | 68016c62 | bellard | cpu_loop_exit(); |
911 | 93ac68bc | bellard | } |
912 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
913 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
914 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
915 | bf3e8bf1 | bellard | void *puc)
|
916 | 67867308 | bellard | { |
917 | 67867308 | bellard | TranslationBlock *tb; |
918 | ce09776b | bellard | int ret;
|
919 | 67867308 | bellard | |
920 | 67867308 | bellard | if (cpu_single_env)
|
921 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
922 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
923 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
924 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
925 | 67867308 | bellard | #endif
|
926 | 67867308 | bellard | /* XXX: locking issue */
|
927 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
928 | 67867308 | bellard | return 1; |
929 | 67867308 | bellard | } |
930 | 67867308 | bellard | |
931 | ce09776b | bellard | /* see if it is an MMU fault */
|
932 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
933 | ce09776b | bellard | if (ret < 0) |
934 | ce09776b | bellard | return 0; /* not an MMU fault */ |
935 | ce09776b | bellard | if (ret == 0) |
936 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
937 | ce09776b | bellard | |
938 | 67867308 | bellard | /* now we have a real cpu fault */
|
939 | 67867308 | bellard | tb = tb_find_pc(pc); |
940 | 67867308 | bellard | if (tb) {
|
941 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
942 | 67867308 | bellard | a virtual CPU fault */
|
943 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
944 | 67867308 | bellard | } |
945 | ce09776b | bellard | if (ret == 1) { |
946 | 67867308 | bellard | #if 0
|
947 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
948 | ce09776b | bellard | env->nip, env->error_code, tb);
|
949 | 67867308 | bellard | #endif
|
950 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
951 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
952 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
953 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
954 | ce09776b | bellard | } else {
|
955 | ce09776b | bellard | /* activate soft MMU for this block */
|
956 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
957 | ce09776b | bellard | } |
958 | 67867308 | bellard | /* never comes here */
|
959 | 67867308 | bellard | return 1; |
960 | 67867308 | bellard | } |
961 | 6af0bf9c | bellard | |
962 | 6af0bf9c | bellard | #elif defined (TARGET_MIPS)
|
963 | 6af0bf9c | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
964 | 6af0bf9c | bellard | int is_write, sigset_t *old_set,
|
965 | 6af0bf9c | bellard | void *puc)
|
966 | 6af0bf9c | bellard | { |
967 | 6af0bf9c | bellard | TranslationBlock *tb; |
968 | 6af0bf9c | bellard | int ret;
|
969 | 6af0bf9c | bellard | |
970 | 6af0bf9c | bellard | if (cpu_single_env)
|
971 | 6af0bf9c | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
972 | 6af0bf9c | bellard | #if defined(DEBUG_SIGNAL)
|
973 | 6af0bf9c | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
974 | 6af0bf9c | bellard | pc, address, is_write, *(unsigned long *)old_set); |
975 | 6af0bf9c | bellard | #endif
|
976 | 6af0bf9c | bellard | /* XXX: locking issue */
|
977 | 6af0bf9c | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
978 | 6af0bf9c | bellard | return 1; |
979 | 6af0bf9c | bellard | } |
980 | 6af0bf9c | bellard | |
981 | 6af0bf9c | bellard | /* see if it is an MMU fault */
|
982 | 6af0bf9c | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
983 | 6af0bf9c | bellard | if (ret < 0) |
984 | 6af0bf9c | bellard | return 0; /* not an MMU fault */ |
985 | 6af0bf9c | bellard | if (ret == 0) |
986 | 6af0bf9c | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
987 | 6af0bf9c | bellard | |
988 | 6af0bf9c | bellard | /* now we have a real cpu fault */
|
989 | 6af0bf9c | bellard | tb = tb_find_pc(pc); |
990 | 6af0bf9c | bellard | if (tb) {
|
991 | 6af0bf9c | bellard | /* the PC is inside the translated code. It means that we have
|
992 | 6af0bf9c | bellard | a virtual CPU fault */
|
993 | 6af0bf9c | bellard | cpu_restore_state(tb, env, pc, puc); |
994 | 6af0bf9c | bellard | } |
995 | 6af0bf9c | bellard | if (ret == 1) { |
996 | 6af0bf9c | bellard | #if 0
|
997 | 6af0bf9c | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
998 | 6af0bf9c | bellard | env->nip, env->error_code, tb);
|
999 | 6af0bf9c | bellard | #endif
|
1000 | 6af0bf9c | bellard | /* we restore the process signal mask as the sigreturn should
|
1001 | 6af0bf9c | bellard | do it (XXX: use sigsetjmp) */
|
1002 | 6af0bf9c | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
1003 | 6af0bf9c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
1004 | 6af0bf9c | bellard | } else {
|
1005 | 6af0bf9c | bellard | /* activate soft MMU for this block */
|
1006 | 6af0bf9c | bellard | cpu_resume_from_signal(env, puc); |
1007 | 6af0bf9c | bellard | } |
1008 | 6af0bf9c | bellard | /* never comes here */
|
1009 | 6af0bf9c | bellard | return 1; |
1010 | 6af0bf9c | bellard | } |
1011 | 6af0bf9c | bellard | |
1012 | e4533c7a | bellard | #else
|
1013 | e4533c7a | bellard | #error unsupported target CPU
|
1014 | e4533c7a | bellard | #endif
|
1015 | 9de5e440 | bellard | |
1016 | 2b413144 | bellard | #if defined(__i386__)
|
1017 | 2b413144 | bellard | |
1018 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
1019 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
1020 | bf3e8bf1 | bellard | struct ucontext *uc)
|
1021 | bf3e8bf1 | bellard | { |
1022 | bf3e8bf1 | bellard | TranslationBlock *tb; |
1023 | bf3e8bf1 | bellard | |
1024 | bf3e8bf1 | bellard | if (cpu_single_env)
|
1025 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1026 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
1027 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
1028 | bf3e8bf1 | bellard | if (tb) {
|
1029 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
1030 | bf3e8bf1 | bellard | a virtual CPU fault */
|
1031 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
1032 | bf3e8bf1 | bellard | } |
1033 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
1034 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
1035 | bf3e8bf1 | bellard | } |
1036 | bf3e8bf1 | bellard | #endif
|
1037 | bf3e8bf1 | bellard | |
1038 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1039 | e4533c7a | bellard | void *puc)
|
1040 | 9de5e440 | bellard | { |
1041 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
1042 | 9de5e440 | bellard | unsigned long pc; |
1043 | bf3e8bf1 | bellard | int trapno;
|
1044 | 97eb5b14 | bellard | |
1045 | d691f669 | bellard | #ifndef REG_EIP
|
1046 | d691f669 | bellard | /* for glibc 2.1 */
|
1047 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
1048 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
1049 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
1050 | d691f669 | bellard | #endif
|
1051 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
1052 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
1053 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
1054 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
1055 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
1056 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
1057 | bf3e8bf1 | bellard | return 1; |
1058 | bf3e8bf1 | bellard | } else
|
1059 | bf3e8bf1 | bellard | #endif
|
1060 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1061 | bf3e8bf1 | bellard | trapno == 0xe ?
|
1062 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
1063 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1064 | 2b413144 | bellard | } |
1065 | 2b413144 | bellard | |
1066 | bc51c5c9 | bellard | #elif defined(__x86_64__)
|
1067 | bc51c5c9 | bellard | |
1068 | bc51c5c9 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1069 | bc51c5c9 | bellard | void *puc)
|
1070 | bc51c5c9 | bellard | { |
1071 | bc51c5c9 | bellard | struct ucontext *uc = puc;
|
1072 | bc51c5c9 | bellard | unsigned long pc; |
1073 | bc51c5c9 | bellard | |
1074 | bc51c5c9 | bellard | pc = uc->uc_mcontext.gregs[REG_RIP]; |
1075 | bc51c5c9 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1076 | bc51c5c9 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
1077 | bc51c5c9 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
1078 | bc51c5c9 | bellard | &uc->uc_sigmask, puc); |
1079 | bc51c5c9 | bellard | } |
1080 | bc51c5c9 | bellard | |
1081 | 83fb7adf | bellard | #elif defined(__powerpc__)
|
1082 | 2b413144 | bellard | |
1083 | 83fb7adf | bellard | /***********************************************************************
|
1084 | 83fb7adf | bellard | * signal context platform-specific definitions
|
1085 | 83fb7adf | bellard | * From Wine
|
1086 | 83fb7adf | bellard | */
|
1087 | 83fb7adf | bellard | #ifdef linux
|
1088 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
1089 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
1090 | 83fb7adf | bellard | /* Gpr Registers access */
|
1091 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
1092 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
1093 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
1094 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
1095 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
1096 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
1097 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
1098 | 83fb7adf | bellard | /* Float Registers access */
|
1099 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
1100 | 83fb7adf | bellard | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
1101 | 83fb7adf | bellard | /* Exception Registers access */
|
1102 | 83fb7adf | bellard | # define DAR_sig(context) REG_sig(dar, context)
|
1103 | 83fb7adf | bellard | # define DSISR_sig(context) REG_sig(dsisr, context)
|
1104 | 83fb7adf | bellard | # define TRAP_sig(context) REG_sig(trap, context)
|
1105 | 83fb7adf | bellard | #endif /* linux */ |
1106 | 83fb7adf | bellard | |
1107 | 83fb7adf | bellard | #ifdef __APPLE__
|
1108 | 83fb7adf | bellard | # include <sys/ucontext.h> |
1109 | 83fb7adf | bellard | typedef struct ucontext SIGCONTEXT; |
1110 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
1111 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
1112 | 83fb7adf | bellard | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
1113 | 83fb7adf | bellard | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
1114 | 83fb7adf | bellard | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
1115 | 83fb7adf | bellard | /* Gpr Registers access */
|
1116 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
1117 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
1118 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
1119 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context)
|
1120 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
1121 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
1122 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
1123 | 83fb7adf | bellard | /* Float Registers access */
|
1124 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
1125 | 83fb7adf | bellard | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
1126 | 83fb7adf | bellard | /* Exception Registers access */
|
1127 | 83fb7adf | bellard | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
1128 | 83fb7adf | bellard | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
1129 | 83fb7adf | bellard | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
1130 | 83fb7adf | bellard | #endif /* __APPLE__ */ |
1131 | 83fb7adf | bellard | |
1132 | d1d9f421 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1133 | e4533c7a | bellard | void *puc)
|
1134 | 2b413144 | bellard | { |
1135 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
1136 | 25eb4484 | bellard | unsigned long pc; |
1137 | 25eb4484 | bellard | int is_write;
|
1138 | 25eb4484 | bellard | |
1139 | 83fb7adf | bellard | pc = IAR_sig(uc); |
1140 | 25eb4484 | bellard | is_write = 0;
|
1141 | 25eb4484 | bellard | #if 0
|
1142 | 25eb4484 | bellard | /* ppc 4xx case */
|
1143 | 83fb7adf | bellard | if (DSISR_sig(uc) & 0x00800000)
|
1144 | 25eb4484 | bellard | is_write = 1;
|
1145 | 25eb4484 | bellard | #else
|
1146 | 83fb7adf | bellard | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
1147 | 25eb4484 | bellard | is_write = 1;
|
1148 | 25eb4484 | bellard | #endif
|
1149 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1150 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1151 | 2b413144 | bellard | } |
1152 | 2b413144 | bellard | |
1153 | 2f87c607 | bellard | #elif defined(__alpha__)
|
1154 | 2f87c607 | bellard | |
1155 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1156 | 2f87c607 | bellard | void *puc)
|
1157 | 2f87c607 | bellard | { |
1158 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
1159 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
1160 | 2f87c607 | bellard | uint32_t insn = *pc; |
1161 | 2f87c607 | bellard | int is_write = 0; |
1162 | 2f87c607 | bellard | |
1163 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1164 | 2f87c607 | bellard | switch (insn >> 26) { |
1165 | 2f87c607 | bellard | case 0x0d: // stw |
1166 | 2f87c607 | bellard | case 0x0e: // stb |
1167 | 2f87c607 | bellard | case 0x0f: // stq_u |
1168 | 2f87c607 | bellard | case 0x24: // stf |
1169 | 2f87c607 | bellard | case 0x25: // stg |
1170 | 2f87c607 | bellard | case 0x26: // sts |
1171 | 2f87c607 | bellard | case 0x27: // stt |
1172 | 2f87c607 | bellard | case 0x2c: // stl |
1173 | 2f87c607 | bellard | case 0x2d: // stq |
1174 | 2f87c607 | bellard | case 0x2e: // stl_c |
1175 | 2f87c607 | bellard | case 0x2f: // stq_c |
1176 | 2f87c607 | bellard | is_write = 1;
|
1177 | 2f87c607 | bellard | } |
1178 | 2f87c607 | bellard | |
1179 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1180 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1181 | 2f87c607 | bellard | } |
1182 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
1183 | 8c6939c0 | bellard | |
1184 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1185 | e4533c7a | bellard | void *puc)
|
1186 | 8c6939c0 | bellard | { |
1187 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
1188 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
1189 | 8c6939c0 | bellard | unsigned long pc; |
1190 | 8c6939c0 | bellard | int is_write;
|
1191 | 8c6939c0 | bellard | uint32_t insn; |
1192 | 8c6939c0 | bellard | |
1193 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
1194 | 8c6939c0 | bellard | pc = regs[1];
|
1195 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1196 | 8c6939c0 | bellard | is_write = 0;
|
1197 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
1198 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
1199 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
1200 | 8c6939c0 | bellard | case 0x05: // stb |
1201 | 8c6939c0 | bellard | case 0x06: // sth |
1202 | 8c6939c0 | bellard | case 0x04: // st |
1203 | 8c6939c0 | bellard | case 0x07: // std |
1204 | 8c6939c0 | bellard | case 0x24: // stf |
1205 | 8c6939c0 | bellard | case 0x27: // stdf |
1206 | 8c6939c0 | bellard | case 0x25: // stfsr |
1207 | 8c6939c0 | bellard | is_write = 1;
|
1208 | 8c6939c0 | bellard | break;
|
1209 | 8c6939c0 | bellard | } |
1210 | 8c6939c0 | bellard | } |
1211 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1212 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
1213 | 8c6939c0 | bellard | } |
1214 | 8c6939c0 | bellard | |
1215 | 8c6939c0 | bellard | #elif defined(__arm__)
|
1216 | 8c6939c0 | bellard | |
1217 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1218 | e4533c7a | bellard | void *puc)
|
1219 | 8c6939c0 | bellard | { |
1220 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
1221 | 8c6939c0 | bellard | unsigned long pc; |
1222 | 8c6939c0 | bellard | int is_write;
|
1223 | 8c6939c0 | bellard | |
1224 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
1225 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
1226 | 8c6939c0 | bellard | is_write = 0;
|
1227 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1228 | 8c6939c0 | bellard | is_write, |
1229 | 8c6939c0 | bellard | &uc->uc_sigmask); |
1230 | 8c6939c0 | bellard | } |
1231 | 8c6939c0 | bellard | |
1232 | 38e584a0 | bellard | #elif defined(__mc68000)
|
1233 | 38e584a0 | bellard | |
1234 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1235 | 38e584a0 | bellard | void *puc)
|
1236 | 38e584a0 | bellard | { |
1237 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
1238 | 38e584a0 | bellard | unsigned long pc; |
1239 | 38e584a0 | bellard | int is_write;
|
1240 | 38e584a0 | bellard | |
1241 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
1242 | 38e584a0 | bellard | /* XXX: compute is_write */
|
1243 | 38e584a0 | bellard | is_write = 0;
|
1244 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1245 | 38e584a0 | bellard | is_write, |
1246 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1247 | 38e584a0 | bellard | } |
1248 | 38e584a0 | bellard | |
1249 | b8076a74 | bellard | #elif defined(__ia64)
|
1250 | b8076a74 | bellard | |
1251 | b8076a74 | bellard | #ifndef __ISR_VALID
|
1252 | b8076a74 | bellard | /* This ought to be in <bits/siginfo.h>... */
|
1253 | b8076a74 | bellard | # define __ISR_VALID 1 |
1254 | b8076a74 | bellard | # define si_flags _sifields._sigfault._si_pad0
|
1255 | b8076a74 | bellard | #endif
|
1256 | b8076a74 | bellard | |
1257 | b8076a74 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) |
1258 | b8076a74 | bellard | { |
1259 | b8076a74 | bellard | struct ucontext *uc = puc;
|
1260 | b8076a74 | bellard | unsigned long ip; |
1261 | b8076a74 | bellard | int is_write = 0; |
1262 | b8076a74 | bellard | |
1263 | b8076a74 | bellard | ip = uc->uc_mcontext.sc_ip; |
1264 | b8076a74 | bellard | switch (host_signum) {
|
1265 | b8076a74 | bellard | case SIGILL:
|
1266 | b8076a74 | bellard | case SIGFPE:
|
1267 | b8076a74 | bellard | case SIGSEGV:
|
1268 | b8076a74 | bellard | case SIGBUS:
|
1269 | b8076a74 | bellard | case SIGTRAP:
|
1270 | b8076a74 | bellard | if (info->si_code && (info->si_flags & __ISR_VALID))
|
1271 | b8076a74 | bellard | /* ISR.W (write-access) is bit 33: */
|
1272 | b8076a74 | bellard | is_write = (info->si_isr >> 33) & 1; |
1273 | b8076a74 | bellard | break;
|
1274 | b8076a74 | bellard | |
1275 | b8076a74 | bellard | default:
|
1276 | b8076a74 | bellard | break;
|
1277 | b8076a74 | bellard | } |
1278 | b8076a74 | bellard | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
1279 | b8076a74 | bellard | is_write, |
1280 | b8076a74 | bellard | &uc->uc_sigmask, puc); |
1281 | b8076a74 | bellard | } |
1282 | b8076a74 | bellard | |
1283 | 90cb9493 | bellard | #elif defined(__s390__)
|
1284 | 90cb9493 | bellard | |
1285 | 90cb9493 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1286 | 90cb9493 | bellard | void *puc)
|
1287 | 90cb9493 | bellard | { |
1288 | 90cb9493 | bellard | struct ucontext *uc = puc;
|
1289 | 90cb9493 | bellard | unsigned long pc; |
1290 | 90cb9493 | bellard | int is_write;
|
1291 | 90cb9493 | bellard | |
1292 | 90cb9493 | bellard | pc = uc->uc_mcontext.psw.addr; |
1293 | 90cb9493 | bellard | /* XXX: compute is_write */
|
1294 | 90cb9493 | bellard | is_write = 0;
|
1295 | 90cb9493 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1296 | 90cb9493 | bellard | is_write, |
1297 | 90cb9493 | bellard | &uc->uc_sigmask, puc); |
1298 | 90cb9493 | bellard | } |
1299 | 90cb9493 | bellard | |
1300 | 9de5e440 | bellard | #else
|
1301 | 2b413144 | bellard | |
1302 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
1303 | 2b413144 | bellard | |
1304 | 9de5e440 | bellard | #endif
|
1305 | 67b915a5 | bellard | |
1306 | 67b915a5 | bellard | #endif /* !defined(CONFIG_SOFTMMU) */ |