Revision aa0bf00b target-mips/translate.c
b/target-mips/translate.c | ||
---|---|---|
423 | 423 |
}; |
424 | 424 |
|
425 | 425 |
/* global register indices */ |
426 |
static TCGv cpu_env, current_tc_gprs, current_tc_hi, cpu_T[2]; |
|
426 |
static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2]; |
|
427 |
|
|
428 |
/* FPU TNs, global for now. */ |
|
429 |
static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3]; |
|
427 | 430 |
|
428 | 431 |
static inline void tcg_gen_helper_0_1i(void *func, TCGv arg) |
429 | 432 |
{ |
... | ... | |
572 | 575 |
} |
573 | 576 |
|
574 | 577 |
/* Floating point register moves. */ |
575 |
#define FGEN32(func, NAME) \ |
|
576 |
static GenOpFunc *NAME ## _table [32] = { \ |
|
577 |
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
|
578 |
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
|
579 |
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
|
580 |
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
|
581 |
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
|
582 |
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
|
583 |
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
|
584 |
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
|
585 |
}; \ |
|
586 |
static always_inline void func(int n) \ |
|
587 |
{ \ |
|
588 |
NAME ## _table[n](); \ |
|
578 |
static inline void gen_load_fpr32 (TCGv t, int reg) |
|
579 |
{ |
|
580 |
tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX); |
|
589 | 581 |
} |
590 | 582 |
|
591 |
FGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr); |
|
592 |
FGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr); |
|
593 |
|
|
594 |
FGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr); |
|
595 |
FGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr); |
|
596 |
|
|
597 |
FGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr); |
|
598 |
FGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr); |
|
599 |
|
|
600 |
FGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr); |
|
601 |
FGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr); |
|
602 |
|
|
603 |
FGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr); |
|
604 |
FGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr); |
|
605 |
|
|
606 |
FGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr); |
|
607 |
FGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr); |
|
583 |
static inline void gen_store_fpr32 (TCGv t, int reg) |
|
584 |
{ |
|
585 |
tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX); |
|
586 |
} |
|
608 | 587 |
|
609 |
FGEN32(gen_op_load_fpr_WTH0, gen_op_load_fpr_WTH0_fpr); |
|
610 |
FGEN32(gen_op_store_fpr_WTH0, gen_op_store_fpr_WTH0_fpr); |
|
588 |
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg) |
|
589 |
{ |
|
590 |
if (ctx->hflags & MIPS_HFLAG_F64) { |
|
591 |
tcg_gen_ld_i64(t, current_fpu, 8 * reg); |
|
592 |
} else { |
|
593 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
|
594 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
|
595 |
|
|
596 |
tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX); |
|
597 |
tcg_gen_extu_i32_i64(t, r_tmp1); |
|
598 |
tcg_gen_shli_i64(t, t, 32); |
|
599 |
tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX); |
|
600 |
tcg_gen_extu_i32_i64(r_tmp2, r_tmp1); |
|
601 |
tcg_gen_or_i64(t, t, r_tmp2); |
|
602 |
tcg_temp_free(r_tmp1); |
|
603 |
tcg_temp_free(r_tmp2); |
|
604 |
} |
|
605 |
} |
|
611 | 606 |
|
612 |
FGEN32(gen_op_load_fpr_WTH1, gen_op_load_fpr_WTH1_fpr); |
|
613 |
FGEN32(gen_op_store_fpr_WTH1, gen_op_store_fpr_WTH1_fpr); |
|
607 |
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg) |
|
608 |
{ |
|
609 |
if (ctx->hflags & MIPS_HFLAG_F64) { |
|
610 |
tcg_gen_st_i64(t, current_fpu, 8 * reg); |
|
611 |
} else { |
|
612 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); |
|
614 | 613 |
|
615 |
FGEN32(gen_op_load_fpr_WTH2, gen_op_load_fpr_WTH2_fpr); |
|
616 |
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr); |
|
614 |
tcg_gen_trunc_i64_i32(r_tmp, t); |
|
615 |
tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX); |
|
616 |
tcg_gen_shri_i64(t, t, 32); |
|
617 |
tcg_gen_trunc_i64_i32(r_tmp, t); |
|
618 |
tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX); |
|
619 |
tcg_temp_free(r_tmp); |
|
620 |
} |
|
621 |
} |
|
617 | 622 |
|
618 |
#define GEN_LOAD_FREG_FTN(FTn, Fn) \
|
|
619 |
do { \
|
|
620 |
glue(gen_op_load_fpr_, FTn)(Fn); \
|
|
621 |
} while (0)
|
|
623 |
static inline void gen_load_fpr32h (TCGv t, int reg)
|
|
624 |
{
|
|
625 |
tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
|
|
626 |
} |
|
622 | 627 |
|
623 |
#define GEN_STORE_FTN_FREG(Fn, FTn) \
|
|
624 |
do { \
|
|
625 |
glue(gen_op_store_fpr_, FTn)(Fn); \
|
|
626 |
} while (0)
|
|
628 |
static inline void gen_store_fpr32h (TCGv t, int reg)
|
|
629 |
{
|
|
630 |
tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
|
|
631 |
} |
|
627 | 632 |
|
628 | 633 |
#define FOP_CONDS(type, fmt) \ |
629 | 634 |
static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \ |
... | ... | |
950 | 955 |
OP_LD_TABLE(wr); |
951 | 956 |
OP_ST_TABLE(wl); |
952 | 957 |
OP_ST_TABLE(wr); |
953 |
OP_LD_TABLE(wc1); |
|
954 |
OP_ST_TABLE(wc1); |
|
955 |
OP_LD_TABLE(dc1); |
|
956 |
OP_ST_TABLE(dc1); |
|
957 | 958 |
OP_LD_TABLE(uxc1); |
958 | 959 |
OP_ST_TABLE(uxc1); |
959 | 960 |
|
... | ... | |
1028 | 1029 |
#endif |
1029 | 1030 |
#undef OP_ST_ATOMIC |
1030 | 1031 |
|
1031 |
void inline op_ldst_lwc1(DisasContext *ctx) |
|
1032 |
{ |
|
1033 |
op_ldst(lwc1); |
|
1034 |
} |
|
1035 |
|
|
1036 |
void inline op_ldst_ldc1(DisasContext *ctx) |
|
1037 |
{ |
|
1038 |
op_ldst(ldc1); |
|
1039 |
} |
|
1040 |
|
|
1041 |
void inline op_ldst_swc1(DisasContext *ctx) |
|
1042 |
{ |
|
1043 |
op_ldst(swc1); |
|
1044 |
} |
|
1045 |
|
|
1046 |
void inline op_ldst_sdc1(DisasContext *ctx) |
|
1047 |
{ |
|
1048 |
op_ldst(sdc1); |
|
1049 |
} |
|
1050 |
|
|
1051 | 1032 |
/* Load and store */ |
1052 | 1033 |
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, |
1053 | 1034 |
int base, int16_t offset) |
... | ... | |
1218 | 1199 |
memory access. */ |
1219 | 1200 |
switch (opc) { |
1220 | 1201 |
case OPC_LWC1: |
1221 |
op_ldst_lwc1(ctx);
|
|
1222 |
GEN_STORE_FTN_FREG(ft, WT0);
|
|
1202 |
tcg_gen_qemu_ld32s(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
1203 |
gen_store_fpr32(fpu32_T[0], ft);
|
|
1223 | 1204 |
opn = "lwc1"; |
1224 | 1205 |
break; |
1225 | 1206 |
case OPC_SWC1: |
1226 |
GEN_LOAD_FREG_FTN(WT0, ft);
|
|
1227 |
op_ldst_swc1(ctx);
|
|
1207 |
gen_load_fpr32(fpu32_T[0], ft);
|
|
1208 |
tcg_gen_qemu_st32(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
1228 | 1209 |
opn = "swc1"; |
1229 | 1210 |
break; |
1230 | 1211 |
case OPC_LDC1: |
1231 |
op_ldst_ldc1(ctx);
|
|
1232 |
GEN_STORE_FTN_FREG(ft, DT0);
|
|
1212 |
tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
1213 |
gen_store_fpr64(ctx, fpu64_T[0], ft);
|
|
1233 | 1214 |
opn = "ldc1"; |
1234 | 1215 |
break; |
1235 | 1216 |
case OPC_SDC1: |
1236 |
GEN_LOAD_FREG_FTN(DT0, ft);
|
|
1237 |
op_ldst_sdc1(ctx);
|
|
1217 |
gen_load_fpr64(ctx, fpu64_T[0], ft);
|
|
1218 |
tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
1238 | 1219 |
opn = "sdc1"; |
1239 | 1220 |
break; |
1240 | 1221 |
default: |
... | ... | |
5073 | 5054 |
case 2: |
5074 | 5055 |
/* XXX: For now we support only a single FPU context. */ |
5075 | 5056 |
if (h == 0) { |
5076 |
GEN_LOAD_FREG_FTN(WT0, rt);
|
|
5077 |
gen_op_mfc1();
|
|
5057 |
gen_load_fpr32(fpu32_T[0], rt);
|
|
5058 |
tcg_gen_ext_i32_tl(cpu_T[0], fpu32_T[0]);
|
|
5078 | 5059 |
} else { |
5079 |
GEN_LOAD_FREG_FTN(WTH0, rt);
|
|
5080 |
gen_op_mfhc1();
|
|
5060 |
gen_load_fpr32h(fpu32h_T[0], rt);
|
|
5061 |
tcg_gen_ext_i32_tl(cpu_T[0], fpu32h_T[0]);
|
|
5081 | 5062 |
} |
5082 | 5063 |
break; |
5083 | 5064 |
case 3: |
... | ... | |
5237 | 5218 |
case 2: |
5238 | 5219 |
/* XXX: For now we support only a single FPU context. */ |
5239 | 5220 |
if (h == 0) { |
5240 |
gen_op_mtc1();
|
|
5241 |
GEN_STORE_FTN_FREG(rd, WT0);
|
|
5221 |
tcg_gen_trunc_tl_i32(fpu32_T[0], cpu_T[0]);
|
|
5222 |
gen_store_fpr32(fpu32_T[0], rd);
|
|
5242 | 5223 |
} else { |
5243 |
gen_op_mthc1();
|
|
5244 |
GEN_STORE_FTN_FREG(rd, WTH0);
|
|
5224 |
tcg_gen_trunc_tl_i32(fpu32h_T[0], cpu_T[0]);
|
|
5225 |
gen_store_fpr32h(fpu32h_T[0], rd);
|
|
5245 | 5226 |
} |
5246 | 5227 |
break; |
5247 | 5228 |
case 3: |
... | ... | |
5464 | 5445 |
|
5465 | 5446 |
switch (opc) { |
5466 | 5447 |
case OPC_MFC1: |
5467 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5468 |
gen_op_mfc1();
|
|
5448 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5449 |
tcg_gen_ext_i32_tl(cpu_T[0], fpu32_T[0]);
|
|
5469 | 5450 |
gen_store_gpr(cpu_T[0], rt); |
5470 | 5451 |
opn = "mfc1"; |
5471 | 5452 |
break; |
5472 | 5453 |
case OPC_MTC1: |
5473 | 5454 |
gen_load_gpr(cpu_T[0], rt); |
5474 |
gen_op_mtc1();
|
|
5475 |
GEN_STORE_FTN_FREG(fs, WT0);
|
|
5455 |
tcg_gen_trunc_tl_i32(fpu32_T[0], cpu_T[0]);
|
|
5456 |
gen_store_fpr32(fpu32_T[0], fs);
|
|
5476 | 5457 |
opn = "mtc1"; |
5477 | 5458 |
break; |
5478 | 5459 |
case OPC_CFC1: |
... | ... | |
5486 | 5467 |
opn = "ctc1"; |
5487 | 5468 |
break; |
5488 | 5469 |
case OPC_DMFC1: |
5489 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5490 |
gen_op_dmfc1();
|
|
5470 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5471 |
tcg_gen_mov_tl(cpu_T[0], fpu64_T[0]);
|
|
5491 | 5472 |
gen_store_gpr(cpu_T[0], rt); |
5492 | 5473 |
opn = "dmfc1"; |
5493 | 5474 |
break; |
5494 | 5475 |
case OPC_DMTC1: |
5495 | 5476 |
gen_load_gpr(cpu_T[0], rt); |
5496 |
gen_op_dmtc1();
|
|
5497 |
GEN_STORE_FTN_FREG(fs, DT0);
|
|
5477 |
tcg_gen_mov_tl(fpu64_T[0], cpu_T[0]);
|
|
5478 |
gen_store_fpr64(ctx, fpu64_T[0], fs);
|
|
5498 | 5479 |
opn = "dmtc1"; |
5499 | 5480 |
break; |
5500 | 5481 |
case OPC_MFHC1: |
5501 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
5502 |
gen_op_mfhc1();
|
|
5482 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
5483 |
tcg_gen_ext_i32_tl(cpu_T[0], fpu32h_T[0]);
|
|
5503 | 5484 |
gen_store_gpr(cpu_T[0], rt); |
5504 | 5485 |
opn = "mfhc1"; |
5505 | 5486 |
break; |
5506 | 5487 |
case OPC_MTHC1: |
5507 | 5488 |
gen_load_gpr(cpu_T[0], rt); |
5508 |
gen_op_mthc1();
|
|
5509 |
GEN_STORE_FTN_FREG(fs, WTH0);
|
|
5489 |
tcg_gen_trunc_tl_i32(fpu32h_T[0], cpu_T[0]);
|
|
5490 |
gen_store_fpr32h(fpu32h_T[0], fs);
|
|
5510 | 5491 |
opn = "mthc1"; |
5511 | 5492 |
break; |
5512 | 5493 |
default: |
... | ... | |
5614 | 5595 |
|
5615 | 5596 |
switch (ctx->opcode & FOP(0x3f, 0x1f)) { |
5616 | 5597 |
case FOP(0, 16): |
5617 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5618 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
5598 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5599 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
5619 | 5600 |
gen_op_float_add_s(); |
5620 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5601 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5621 | 5602 |
opn = "add.s"; |
5622 | 5603 |
optype = BINOP; |
5623 | 5604 |
break; |
5624 | 5605 |
case FOP(1, 16): |
5625 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5626 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
5606 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5607 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
5627 | 5608 |
gen_op_float_sub_s(); |
5628 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5609 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5629 | 5610 |
opn = "sub.s"; |
5630 | 5611 |
optype = BINOP; |
5631 | 5612 |
break; |
5632 | 5613 |
case FOP(2, 16): |
5633 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5634 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
5614 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5615 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
5635 | 5616 |
gen_op_float_mul_s(); |
5636 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5617 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5637 | 5618 |
opn = "mul.s"; |
5638 | 5619 |
optype = BINOP; |
5639 | 5620 |
break; |
5640 | 5621 |
case FOP(3, 16): |
5641 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5642 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
5622 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5623 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
5643 | 5624 |
gen_op_float_div_s(); |
5644 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5625 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5645 | 5626 |
opn = "div.s"; |
5646 | 5627 |
optype = BINOP; |
5647 | 5628 |
break; |
5648 | 5629 |
case FOP(4, 16): |
5649 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5630 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5650 | 5631 |
gen_op_float_sqrt_s(); |
5651 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5632 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5652 | 5633 |
opn = "sqrt.s"; |
5653 | 5634 |
break; |
5654 | 5635 |
case FOP(5, 16): |
5655 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5636 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5656 | 5637 |
gen_op_float_abs_s(); |
5657 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5638 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5658 | 5639 |
opn = "abs.s"; |
5659 | 5640 |
break; |
5660 | 5641 |
case FOP(6, 16): |
5661 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5642 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5662 | 5643 |
gen_op_float_mov_s(); |
5663 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5644 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5664 | 5645 |
opn = "mov.s"; |
5665 | 5646 |
break; |
5666 | 5647 |
case FOP(7, 16): |
5667 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5648 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5668 | 5649 |
gen_op_float_chs_s(); |
5669 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5650 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5670 | 5651 |
opn = "neg.s"; |
5671 | 5652 |
break; |
5672 | 5653 |
case FOP(8, 16): |
5673 | 5654 |
check_cp1_64bitmode(ctx); |
5674 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5655 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5675 | 5656 |
gen_op_float_roundl_s(); |
5676 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5657 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5677 | 5658 |
opn = "round.l.s"; |
5678 | 5659 |
break; |
5679 | 5660 |
case FOP(9, 16): |
5680 | 5661 |
check_cp1_64bitmode(ctx); |
5681 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5662 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5682 | 5663 |
gen_op_float_truncl_s(); |
5683 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5664 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5684 | 5665 |
opn = "trunc.l.s"; |
5685 | 5666 |
break; |
5686 | 5667 |
case FOP(10, 16): |
5687 | 5668 |
check_cp1_64bitmode(ctx); |
5688 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5669 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5689 | 5670 |
gen_op_float_ceill_s(); |
5690 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5671 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5691 | 5672 |
opn = "ceil.l.s"; |
5692 | 5673 |
break; |
5693 | 5674 |
case FOP(11, 16): |
5694 | 5675 |
check_cp1_64bitmode(ctx); |
5695 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5676 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5696 | 5677 |
gen_op_float_floorl_s(); |
5697 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5678 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5698 | 5679 |
opn = "floor.l.s"; |
5699 | 5680 |
break; |
5700 | 5681 |
case FOP(12, 16): |
5701 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5682 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5702 | 5683 |
gen_op_float_roundw_s(); |
5703 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5684 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5704 | 5685 |
opn = "round.w.s"; |
5705 | 5686 |
break; |
5706 | 5687 |
case FOP(13, 16): |
5707 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5688 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5708 | 5689 |
gen_op_float_truncw_s(); |
5709 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5690 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5710 | 5691 |
opn = "trunc.w.s"; |
5711 | 5692 |
break; |
5712 | 5693 |
case FOP(14, 16): |
5713 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5694 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5714 | 5695 |
gen_op_float_ceilw_s(); |
5715 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5696 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5716 | 5697 |
opn = "ceil.w.s"; |
5717 | 5698 |
break; |
5718 | 5699 |
case FOP(15, 16): |
5719 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5700 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5720 | 5701 |
gen_op_float_floorw_s(); |
5721 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5702 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5722 | 5703 |
opn = "floor.w.s"; |
5723 | 5704 |
break; |
5724 | 5705 |
case FOP(17, 16): |
5725 | 5706 |
gen_load_gpr(cpu_T[0], ft); |
5726 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5727 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
5707 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5708 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
5728 | 5709 |
gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1); |
5729 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5710 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5730 | 5711 |
opn = "movcf.s"; |
5731 | 5712 |
break; |
5732 | 5713 |
case FOP(18, 16): |
5733 | 5714 |
gen_load_gpr(cpu_T[0], ft); |
5734 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5735 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
5715 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5716 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
5736 | 5717 |
gen_op_float_movz_s(); |
5737 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5718 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5738 | 5719 |
opn = "movz.s"; |
5739 | 5720 |
break; |
5740 | 5721 |
case FOP(19, 16): |
5741 | 5722 |
gen_load_gpr(cpu_T[0], ft); |
5742 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5743 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
5723 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5724 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
5744 | 5725 |
gen_op_float_movn_s(); |
5745 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5726 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5746 | 5727 |
opn = "movn.s"; |
5747 | 5728 |
break; |
5748 | 5729 |
case FOP(21, 16): |
5749 | 5730 |
check_cop1x(ctx); |
5750 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5731 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5751 | 5732 |
gen_op_float_recip_s(); |
5752 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5733 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5753 | 5734 |
opn = "recip.s"; |
5754 | 5735 |
break; |
5755 | 5736 |
case FOP(22, 16): |
5756 | 5737 |
check_cop1x(ctx); |
5757 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5738 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5758 | 5739 |
gen_op_float_rsqrt_s(); |
5759 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5740 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5760 | 5741 |
opn = "rsqrt.s"; |
5761 | 5742 |
break; |
5762 | 5743 |
case FOP(28, 16): |
5763 | 5744 |
check_cp1_64bitmode(ctx); |
5764 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5765 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
5745 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5746 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
5766 | 5747 |
gen_op_float_recip2_s(); |
5767 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5748 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5768 | 5749 |
opn = "recip2.s"; |
5769 | 5750 |
break; |
5770 | 5751 |
case FOP(29, 16): |
5771 | 5752 |
check_cp1_64bitmode(ctx); |
5772 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5753 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5773 | 5754 |
gen_op_float_recip1_s(); |
5774 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5755 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5775 | 5756 |
opn = "recip1.s"; |
5776 | 5757 |
break; |
5777 | 5758 |
case FOP(30, 16): |
5778 | 5759 |
check_cp1_64bitmode(ctx); |
5779 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5760 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5780 | 5761 |
gen_op_float_rsqrt1_s(); |
5781 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5762 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5782 | 5763 |
opn = "rsqrt1.s"; |
5783 | 5764 |
break; |
5784 | 5765 |
case FOP(31, 16): |
5785 | 5766 |
check_cp1_64bitmode(ctx); |
5786 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5787 |
GEN_LOAD_FREG_FTN(WT2, ft);
|
|
5767 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5768 |
gen_load_fpr32(fpu32_T[2], ft);
|
|
5788 | 5769 |
gen_op_float_rsqrt2_s(); |
5789 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5770 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5790 | 5771 |
opn = "rsqrt2.s"; |
5791 | 5772 |
break; |
5792 | 5773 |
case FOP(33, 16): |
5793 | 5774 |
check_cp1_registers(ctx, fd); |
5794 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5775 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5795 | 5776 |
gen_op_float_cvtd_s(); |
5796 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5777 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5797 | 5778 |
opn = "cvt.d.s"; |
5798 | 5779 |
break; |
5799 | 5780 |
case FOP(36, 16): |
5800 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5781 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5801 | 5782 |
gen_op_float_cvtw_s(); |
5802 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5783 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5803 | 5784 |
opn = "cvt.w.s"; |
5804 | 5785 |
break; |
5805 | 5786 |
case FOP(37, 16): |
5806 | 5787 |
check_cp1_64bitmode(ctx); |
5807 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5788 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5808 | 5789 |
gen_op_float_cvtl_s(); |
5809 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5790 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5810 | 5791 |
opn = "cvt.l.s"; |
5811 | 5792 |
break; |
5812 | 5793 |
case FOP(38, 16): |
5813 | 5794 |
check_cp1_64bitmode(ctx); |
5814 |
GEN_LOAD_FREG_FTN(WT1, fs);
|
|
5815 |
GEN_LOAD_FREG_FTN(WT0, ft);
|
|
5795 |
gen_load_fpr32(fpu32_T[1], fs);
|
|
5796 |
gen_load_fpr32(fpu32_T[0], ft);
|
|
5816 | 5797 |
gen_op_float_cvtps_s(); |
5817 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5798 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5818 | 5799 |
opn = "cvt.ps.s"; |
5819 | 5800 |
break; |
5820 | 5801 |
case FOP(48, 16): |
... | ... | |
5833 | 5814 |
case FOP(61, 16): |
5834 | 5815 |
case FOP(62, 16): |
5835 | 5816 |
case FOP(63, 16): |
5836 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
5837 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
5817 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
5818 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
5838 | 5819 |
if (ctx->opcode & (1 << 6)) { |
5839 | 5820 |
check_cop1x(ctx); |
5840 | 5821 |
gen_cmpabs_s(func-48, cc); |
... | ... | |
5846 | 5827 |
break; |
5847 | 5828 |
case FOP(0, 17): |
5848 | 5829 |
check_cp1_registers(ctx, fs | ft | fd); |
5849 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5850 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
5830 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5831 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
5851 | 5832 |
gen_op_float_add_d(); |
5852 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5833 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5853 | 5834 |
opn = "add.d"; |
5854 | 5835 |
optype = BINOP; |
5855 | 5836 |
break; |
5856 | 5837 |
case FOP(1, 17): |
5857 | 5838 |
check_cp1_registers(ctx, fs | ft | fd); |
5858 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5859 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
5839 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5840 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
5860 | 5841 |
gen_op_float_sub_d(); |
5861 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5842 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5862 | 5843 |
opn = "sub.d"; |
5863 | 5844 |
optype = BINOP; |
5864 | 5845 |
break; |
5865 | 5846 |
case FOP(2, 17): |
5866 | 5847 |
check_cp1_registers(ctx, fs | ft | fd); |
5867 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5868 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
5848 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5849 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
5869 | 5850 |
gen_op_float_mul_d(); |
5870 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5851 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5871 | 5852 |
opn = "mul.d"; |
5872 | 5853 |
optype = BINOP; |
5873 | 5854 |
break; |
5874 | 5855 |
case FOP(3, 17): |
5875 | 5856 |
check_cp1_registers(ctx, fs | ft | fd); |
5876 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5877 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
5857 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5858 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
5878 | 5859 |
gen_op_float_div_d(); |
5879 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5860 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5880 | 5861 |
opn = "div.d"; |
5881 | 5862 |
optype = BINOP; |
5882 | 5863 |
break; |
5883 | 5864 |
case FOP(4, 17): |
5884 | 5865 |
check_cp1_registers(ctx, fs | fd); |
5885 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5866 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5886 | 5867 |
gen_op_float_sqrt_d(); |
5887 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5868 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5888 | 5869 |
opn = "sqrt.d"; |
5889 | 5870 |
break; |
5890 | 5871 |
case FOP(5, 17): |
5891 | 5872 |
check_cp1_registers(ctx, fs | fd); |
5892 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5873 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5893 | 5874 |
gen_op_float_abs_d(); |
5894 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5875 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5895 | 5876 |
opn = "abs.d"; |
5896 | 5877 |
break; |
5897 | 5878 |
case FOP(6, 17): |
5898 | 5879 |
check_cp1_registers(ctx, fs | fd); |
5899 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5880 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5900 | 5881 |
gen_op_float_mov_d(); |
5901 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5882 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5902 | 5883 |
opn = "mov.d"; |
5903 | 5884 |
break; |
5904 | 5885 |
case FOP(7, 17): |
5905 | 5886 |
check_cp1_registers(ctx, fs | fd); |
5906 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5887 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5907 | 5888 |
gen_op_float_chs_d(); |
5908 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5889 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5909 | 5890 |
opn = "neg.d"; |
5910 | 5891 |
break; |
5911 | 5892 |
case FOP(8, 17): |
5912 | 5893 |
check_cp1_64bitmode(ctx); |
5913 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5894 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5914 | 5895 |
gen_op_float_roundl_d(); |
5915 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5896 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5916 | 5897 |
opn = "round.l.d"; |
5917 | 5898 |
break; |
5918 | 5899 |
case FOP(9, 17): |
5919 | 5900 |
check_cp1_64bitmode(ctx); |
5920 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5901 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5921 | 5902 |
gen_op_float_truncl_d(); |
5922 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5903 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5923 | 5904 |
opn = "trunc.l.d"; |
5924 | 5905 |
break; |
5925 | 5906 |
case FOP(10, 17): |
5926 | 5907 |
check_cp1_64bitmode(ctx); |
5927 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5908 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5928 | 5909 |
gen_op_float_ceill_d(); |
5929 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5910 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5930 | 5911 |
opn = "ceil.l.d"; |
5931 | 5912 |
break; |
5932 | 5913 |
case FOP(11, 17): |
5933 | 5914 |
check_cp1_64bitmode(ctx); |
5934 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5915 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5935 | 5916 |
gen_op_float_floorl_d(); |
5936 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5917 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5937 | 5918 |
opn = "floor.l.d"; |
5938 | 5919 |
break; |
5939 | 5920 |
case FOP(12, 17): |
5940 | 5921 |
check_cp1_registers(ctx, fs); |
5941 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5922 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5942 | 5923 |
gen_op_float_roundw_d(); |
5943 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5924 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5944 | 5925 |
opn = "round.w.d"; |
5945 | 5926 |
break; |
5946 | 5927 |
case FOP(13, 17): |
5947 | 5928 |
check_cp1_registers(ctx, fs); |
5948 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5929 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5949 | 5930 |
gen_op_float_truncw_d(); |
5950 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5931 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5951 | 5932 |
opn = "trunc.w.d"; |
5952 | 5933 |
break; |
5953 | 5934 |
case FOP(14, 17): |
5954 | 5935 |
check_cp1_registers(ctx, fs); |
5955 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5936 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5956 | 5937 |
gen_op_float_ceilw_d(); |
5957 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5938 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5958 | 5939 |
opn = "ceil.w.d"; |
5959 | 5940 |
break; |
5960 | 5941 |
case FOP(15, 17): |
5961 | 5942 |
check_cp1_registers(ctx, fs); |
5962 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5943 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5963 | 5944 |
gen_op_float_floorw_d(); |
5964 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
5945 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
5965 | 5946 |
opn = "floor.w.d"; |
5966 | 5947 |
break; |
5967 | 5948 |
case FOP(17, 17): |
5968 | 5949 |
gen_load_gpr(cpu_T[0], ft); |
5969 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5970 |
GEN_LOAD_FREG_FTN(DT2, fd);
|
|
5950 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5951 |
gen_load_fpr64(ctx, fpu64_T[2], fd);
|
|
5971 | 5952 |
gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1); |
5972 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5953 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5973 | 5954 |
opn = "movcf.d"; |
5974 | 5955 |
break; |
5975 | 5956 |
case FOP(18, 17): |
5976 | 5957 |
gen_load_gpr(cpu_T[0], ft); |
5977 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5978 |
GEN_LOAD_FREG_FTN(DT2, fd);
|
|
5958 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5959 |
gen_load_fpr64(ctx, fpu64_T[2], fd);
|
|
5979 | 5960 |
gen_op_float_movz_d(); |
5980 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5961 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5981 | 5962 |
opn = "movz.d"; |
5982 | 5963 |
break; |
5983 | 5964 |
case FOP(19, 17): |
5984 | 5965 |
gen_load_gpr(cpu_T[0], ft); |
5985 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5986 |
GEN_LOAD_FREG_FTN(DT2, fd);
|
|
5966 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5967 |
gen_load_fpr64(ctx, fpu64_T[2], fd);
|
|
5987 | 5968 |
gen_op_float_movn_d(); |
5988 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5969 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5989 | 5970 |
opn = "movn.d"; |
5990 | 5971 |
break; |
5991 | 5972 |
case FOP(21, 17): |
5992 | 5973 |
check_cp1_64bitmode(ctx); |
5993 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5974 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5994 | 5975 |
gen_op_float_recip_d(); |
5995 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5976 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
5996 | 5977 |
opn = "recip.d"; |
5997 | 5978 |
break; |
5998 | 5979 |
case FOP(22, 17): |
5999 | 5980 |
check_cp1_64bitmode(ctx); |
6000 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5981 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6001 | 5982 |
gen_op_float_rsqrt_d(); |
6002 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5983 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6003 | 5984 |
opn = "rsqrt.d"; |
6004 | 5985 |
break; |
6005 | 5986 |
case FOP(28, 17): |
6006 | 5987 |
check_cp1_64bitmode(ctx); |
6007 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6008 |
GEN_LOAD_FREG_FTN(DT2, ft);
|
|
5988 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
5989 |
gen_load_fpr64(ctx, fpu64_T[2], ft);
|
|
6009 | 5990 |
gen_op_float_recip2_d(); |
6010 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5991 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6011 | 5992 |
opn = "recip2.d"; |
6012 | 5993 |
break; |
6013 | 5994 |
case FOP(29, 17): |
6014 | 5995 |
check_cp1_64bitmode(ctx); |
6015 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
5996 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6016 | 5997 |
gen_op_float_recip1_d(); |
6017 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
5998 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6018 | 5999 |
opn = "recip1.d"; |
6019 | 6000 |
break; |
6020 | 6001 |
case FOP(30, 17): |
6021 | 6002 |
check_cp1_64bitmode(ctx); |
6022 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6003 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6023 | 6004 |
gen_op_float_rsqrt1_d(); |
6024 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6005 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6025 | 6006 |
opn = "rsqrt1.d"; |
6026 | 6007 |
break; |
6027 | 6008 |
case FOP(31, 17): |
6028 | 6009 |
check_cp1_64bitmode(ctx); |
6029 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6030 |
GEN_LOAD_FREG_FTN(DT2, ft);
|
|
6010 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6011 |
gen_load_fpr64(ctx, fpu64_T[2], ft);
|
|
6031 | 6012 |
gen_op_float_rsqrt2_d(); |
6032 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6013 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6033 | 6014 |
opn = "rsqrt2.d"; |
6034 | 6015 |
break; |
6035 | 6016 |
case FOP(48, 17): |
... | ... | |
6048 | 6029 |
case FOP(61, 17): |
6049 | 6030 |
case FOP(62, 17): |
6050 | 6031 |
case FOP(63, 17): |
6051 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6052 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6032 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6033 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6053 | 6034 |
if (ctx->opcode & (1 << 6)) { |
6054 | 6035 |
check_cop1x(ctx); |
6055 | 6036 |
check_cp1_registers(ctx, fs | ft); |
... | ... | |
6063 | 6044 |
break; |
6064 | 6045 |
case FOP(32, 17): |
6065 | 6046 |
check_cp1_registers(ctx, fs); |
6066 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6047 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6067 | 6048 |
gen_op_float_cvts_d(); |
6068 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6049 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6069 | 6050 |
opn = "cvt.s.d"; |
6070 | 6051 |
break; |
6071 | 6052 |
case FOP(36, 17): |
6072 | 6053 |
check_cp1_registers(ctx, fs); |
6073 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6054 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6074 | 6055 |
gen_op_float_cvtw_d(); |
6075 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6056 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6076 | 6057 |
opn = "cvt.w.d"; |
6077 | 6058 |
break; |
6078 | 6059 |
case FOP(37, 17): |
6079 | 6060 |
check_cp1_64bitmode(ctx); |
6080 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6061 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6081 | 6062 |
gen_op_float_cvtl_d(); |
6082 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6063 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6083 | 6064 |
opn = "cvt.l.d"; |
6084 | 6065 |
break; |
6085 | 6066 |
case FOP(32, 20): |
6086 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6067 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6087 | 6068 |
gen_op_float_cvts_w(); |
6088 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6069 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6089 | 6070 |
opn = "cvt.s.w"; |
6090 | 6071 |
break; |
6091 | 6072 |
case FOP(33, 20): |
6092 | 6073 |
check_cp1_registers(ctx, fd); |
6093 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6074 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6094 | 6075 |
gen_op_float_cvtd_w(); |
6095 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6076 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6096 | 6077 |
opn = "cvt.d.w"; |
6097 | 6078 |
break; |
6098 | 6079 |
case FOP(32, 21): |
6099 | 6080 |
check_cp1_64bitmode(ctx); |
6100 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6081 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6101 | 6082 |
gen_op_float_cvts_l(); |
6102 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6083 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6103 | 6084 |
opn = "cvt.s.l"; |
6104 | 6085 |
break; |
6105 | 6086 |
case FOP(33, 21): |
6106 | 6087 |
check_cp1_64bitmode(ctx); |
6107 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6088 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6108 | 6089 |
gen_op_float_cvtd_l(); |
6109 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6090 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6110 | 6091 |
opn = "cvt.d.l"; |
6111 | 6092 |
break; |
6112 | 6093 |
case FOP(38, 20): |
6113 | 6094 |
check_cp1_64bitmode(ctx); |
6114 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6115 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6095 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6096 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6116 | 6097 |
gen_op_float_cvtps_pw(); |
6117 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6118 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6098 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6099 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6119 | 6100 |
opn = "cvt.ps.pw"; |
6120 | 6101 |
break; |
6121 | 6102 |
case FOP(0, 22): |
6122 | 6103 |
check_cp1_64bitmode(ctx); |
6123 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6124 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6125 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6126 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6104 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6105 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6106 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6107 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6127 | 6108 |
gen_op_float_add_ps(); |
6128 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6129 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6109 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6110 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6130 | 6111 |
opn = "add.ps"; |
6131 | 6112 |
break; |
6132 | 6113 |
case FOP(1, 22): |
6133 | 6114 |
check_cp1_64bitmode(ctx); |
6134 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6135 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6136 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6137 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6115 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6116 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6117 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6118 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6138 | 6119 |
gen_op_float_sub_ps(); |
6139 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6140 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6120 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6121 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6141 | 6122 |
opn = "sub.ps"; |
6142 | 6123 |
break; |
6143 | 6124 |
case FOP(2, 22): |
6144 | 6125 |
check_cp1_64bitmode(ctx); |
6145 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6146 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6147 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6148 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6126 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6127 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6128 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6129 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6149 | 6130 |
gen_op_float_mul_ps(); |
6150 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6151 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6131 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6132 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6152 | 6133 |
opn = "mul.ps"; |
6153 | 6134 |
break; |
6154 | 6135 |
case FOP(5, 22): |
6155 | 6136 |
check_cp1_64bitmode(ctx); |
6156 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6157 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6137 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6138 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6158 | 6139 |
gen_op_float_abs_ps(); |
6159 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6160 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6140 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6141 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6161 | 6142 |
opn = "abs.ps"; |
6162 | 6143 |
break; |
6163 | 6144 |
case FOP(6, 22): |
6164 | 6145 |
check_cp1_64bitmode(ctx); |
6165 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6166 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6146 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6147 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6167 | 6148 |
gen_op_float_mov_ps(); |
6168 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6169 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6149 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6150 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6170 | 6151 |
opn = "mov.ps"; |
6171 | 6152 |
break; |
6172 | 6153 |
case FOP(7, 22): |
6173 | 6154 |
check_cp1_64bitmode(ctx); |
6174 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6175 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6155 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6156 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6176 | 6157 |
gen_op_float_chs_ps(); |
6177 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6178 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6158 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6159 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6179 | 6160 |
opn = "neg.ps"; |
6180 | 6161 |
break; |
6181 | 6162 |
case FOP(17, 22): |
6182 | 6163 |
check_cp1_64bitmode(ctx); |
6183 | 6164 |
gen_load_gpr(cpu_T[0], ft); |
6184 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6185 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6186 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
6187 |
GEN_LOAD_FREG_FTN(WTH2, fd);
|
|
6165 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6166 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6167 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
6168 |
gen_load_fpr32h(fpu32h_T[2], fd);
|
|
6188 | 6169 |
if (ft & 0x1) |
6189 | 6170 |
gen_op_float_movt_ps ((ft >> 2) & 0x7); |
6190 | 6171 |
else |
6191 | 6172 |
gen_op_float_movf_ps ((ft >> 2) & 0x7); |
6192 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6193 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6173 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6174 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6194 | 6175 |
opn = "movcf.ps"; |
6195 | 6176 |
break; |
6196 | 6177 |
case FOP(18, 22): |
6197 | 6178 |
check_cp1_64bitmode(ctx); |
6198 | 6179 |
gen_load_gpr(cpu_T[0], ft); |
6199 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6200 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6201 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
6202 |
GEN_LOAD_FREG_FTN(WTH2, fd);
|
|
6180 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6181 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6182 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
6183 |
gen_load_fpr32h(fpu32h_T[2], fd);
|
|
6203 | 6184 |
gen_op_float_movz_ps(); |
6204 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6205 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6185 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6186 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6206 | 6187 |
opn = "movz.ps"; |
6207 | 6188 |
break; |
6208 | 6189 |
case FOP(19, 22): |
6209 | 6190 |
check_cp1_64bitmode(ctx); |
6210 | 6191 |
gen_load_gpr(cpu_T[0], ft); |
6211 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6212 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6213 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
6214 |
GEN_LOAD_FREG_FTN(WTH2, fd);
|
|
6192 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6193 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6194 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
6195 |
gen_load_fpr32h(fpu32h_T[2], fd);
|
|
6215 | 6196 |
gen_op_float_movn_ps(); |
6216 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6217 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6197 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6198 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6218 | 6199 |
opn = "movn.ps"; |
6219 | 6200 |
break; |
6220 | 6201 |
case FOP(24, 22): |
6221 | 6202 |
check_cp1_64bitmode(ctx); |
6222 |
GEN_LOAD_FREG_FTN(WT0, ft);
|
|
6223 |
GEN_LOAD_FREG_FTN(WTH0, ft);
|
|
6224 |
GEN_LOAD_FREG_FTN(WT1, fs);
|
|
6225 |
GEN_LOAD_FREG_FTN(WTH1, fs);
|
|
6203 |
gen_load_fpr32(fpu32_T[0], ft);
|
|
6204 |
gen_load_fpr32h(fpu32h_T[0], ft);
|
|
6205 |
gen_load_fpr32(fpu32_T[1], fs);
|
|
6206 |
gen_load_fpr32h(fpu32h_T[1], fs);
|
|
6226 | 6207 |
gen_op_float_addr_ps(); |
6227 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6228 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6208 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6209 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6229 | 6210 |
opn = "addr.ps"; |
6230 | 6211 |
break; |
6231 | 6212 |
case FOP(26, 22): |
6232 | 6213 |
check_cp1_64bitmode(ctx); |
6233 |
GEN_LOAD_FREG_FTN(WT0, ft);
|
|
6234 |
GEN_LOAD_FREG_FTN(WTH0, ft);
|
|
6235 |
GEN_LOAD_FREG_FTN(WT1, fs);
|
|
6236 |
GEN_LOAD_FREG_FTN(WTH1, fs);
|
|
6214 |
gen_load_fpr32(fpu32_T[0], ft);
|
|
6215 |
gen_load_fpr32h(fpu32h_T[0], ft);
|
|
6216 |
gen_load_fpr32(fpu32_T[1], fs);
|
|
6217 |
gen_load_fpr32h(fpu32h_T[1], fs);
|
|
6237 | 6218 |
gen_op_float_mulr_ps(); |
6238 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6239 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6219 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6220 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6240 | 6221 |
opn = "mulr.ps"; |
6241 | 6222 |
break; |
6242 | 6223 |
case FOP(28, 22): |
6243 | 6224 |
check_cp1_64bitmode(ctx); |
6244 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6245 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6246 |
GEN_LOAD_FREG_FTN(WT2, fd);
|
|
6247 |
GEN_LOAD_FREG_FTN(WTH2, fd);
|
|
6225 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6226 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6227 |
gen_load_fpr32(fpu32_T[2], fd);
|
|
6228 |
gen_load_fpr32h(fpu32h_T[2], fd);
|
|
6248 | 6229 |
gen_op_float_recip2_ps(); |
6249 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6250 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6230 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6231 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6251 | 6232 |
opn = "recip2.ps"; |
6252 | 6233 |
break; |
6253 | 6234 |
case FOP(29, 22): |
6254 | 6235 |
check_cp1_64bitmode(ctx); |
6255 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6256 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6236 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6237 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6257 | 6238 |
gen_op_float_recip1_ps(); |
6258 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6259 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6239 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6240 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6260 | 6241 |
opn = "recip1.ps"; |
6261 | 6242 |
break; |
6262 | 6243 |
case FOP(30, 22): |
6263 | 6244 |
check_cp1_64bitmode(ctx); |
6264 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6265 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6245 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6246 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6266 | 6247 |
gen_op_float_rsqrt1_ps(); |
6267 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6268 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6248 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6249 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6269 | 6250 |
opn = "rsqrt1.ps"; |
6270 | 6251 |
break; |
6271 | 6252 |
case FOP(31, 22): |
6272 | 6253 |
check_cp1_64bitmode(ctx); |
6273 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6274 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6275 |
GEN_LOAD_FREG_FTN(WT2, ft);
|
|
6276 |
GEN_LOAD_FREG_FTN(WTH2, ft);
|
|
6254 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6255 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6256 |
gen_load_fpr32(fpu32_T[2], ft);
|
|
6257 |
gen_load_fpr32h(fpu32h_T[2], ft);
|
|
6277 | 6258 |
gen_op_float_rsqrt2_ps(); |
6278 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6279 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6259 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6260 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6280 | 6261 |
opn = "rsqrt2.ps"; |
6281 | 6262 |
break; |
6282 | 6263 |
case FOP(32, 22): |
6283 | 6264 |
check_cp1_64bitmode(ctx); |
6284 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6265 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6285 | 6266 |
gen_op_float_cvts_pu(); |
6286 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6267 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6287 | 6268 |
opn = "cvt.s.pu"; |
6288 | 6269 |
break; |
6289 | 6270 |
case FOP(36, 22): |
6290 | 6271 |
check_cp1_64bitmode(ctx); |
6291 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6292 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6272 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6273 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6293 | 6274 |
gen_op_float_cvtpw_ps(); |
6294 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6295 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6275 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6276 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6296 | 6277 |
opn = "cvt.pw.ps"; |
6297 | 6278 |
break; |
6298 | 6279 |
case FOP(40, 22): |
6299 | 6280 |
check_cp1_64bitmode(ctx); |
6300 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6281 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6301 | 6282 |
gen_op_float_cvts_pl(); |
6302 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6283 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6303 | 6284 |
opn = "cvt.s.pl"; |
6304 | 6285 |
break; |
6305 | 6286 |
case FOP(44, 22): |
6306 | 6287 |
check_cp1_64bitmode(ctx); |
6307 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6308 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6288 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6289 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6309 | 6290 |
gen_op_float_pll_ps(); |
6310 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6291 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6311 | 6292 |
opn = "pll.ps"; |
6312 | 6293 |
break; |
6313 | 6294 |
case FOP(45, 22): |
6314 | 6295 |
check_cp1_64bitmode(ctx); |
6315 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6316 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6296 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6297 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6317 | 6298 |
gen_op_float_plu_ps(); |
6318 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6299 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6319 | 6300 |
opn = "plu.ps"; |
6320 | 6301 |
break; |
6321 | 6302 |
case FOP(46, 22): |
6322 | 6303 |
check_cp1_64bitmode(ctx); |
6323 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6324 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6304 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6305 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6325 | 6306 |
gen_op_float_pul_ps(); |
6326 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6307 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6327 | 6308 |
opn = "pul.ps"; |
6328 | 6309 |
break; |
6329 | 6310 |
case FOP(47, 22): |
6330 | 6311 |
check_cp1_64bitmode(ctx); |
6331 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6332 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6312 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6313 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6333 | 6314 |
gen_op_float_puu_ps(); |
6334 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6315 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6335 | 6316 |
opn = "puu.ps"; |
6336 | 6317 |
break; |
6337 | 6318 |
case FOP(48, 22): |
... | ... | |
6351 | 6332 |
case FOP(62, 22): |
6352 | 6333 |
case FOP(63, 22): |
6353 | 6334 |
check_cp1_64bitmode(ctx); |
6354 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6355 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6356 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6357 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6335 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6336 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6337 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6338 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6358 | 6339 |
if (ctx->opcode & (1 << 6)) { |
6359 | 6340 |
gen_cmpabs_ps(func-48, cc); |
6360 | 6341 |
opn = condnames_abs[func-48]; |
... | ... | |
6402 | 6383 |
switch (opc) { |
6403 | 6384 |
case OPC_LWXC1: |
6404 | 6385 |
check_cop1x(ctx); |
6405 |
op_ldst_lwc1(ctx);
|
|
6406 |
GEN_STORE_FTN_FREG(fd, WT0);
|
|
6386 |
tcg_gen_qemu_ld32s(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
6387 |
gen_store_fpr32(fpu32_T[0], fd);
|
|
6407 | 6388 |
opn = "lwxc1"; |
6408 | 6389 |
break; |
6409 | 6390 |
case OPC_LDXC1: |
6410 | 6391 |
check_cop1x(ctx); |
6411 | 6392 |
check_cp1_registers(ctx, fd); |
6412 |
op_ldst_ldc1(ctx);
|
|
6413 |
GEN_STORE_FTN_FREG(fd, DT0);
|
|
6393 |
tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
6394 |
gen_store_fpr64(ctx, fpu64_T[0], fd);
|
|
6414 | 6395 |
opn = "ldxc1"; |
6415 | 6396 |
break; |
6416 | 6397 |
case OPC_LUXC1: |
6417 | 6398 |
check_cp1_64bitmode(ctx); |
6418 | 6399 |
op_ldst(luxc1); |
6419 |
GEN_STORE_FTN_FREG(fd, DT0);
|
|
6400 |
gen_store_fpr64(ctx, fpu64_T[0], fd);
|
|
6420 | 6401 |
opn = "luxc1"; |
6421 | 6402 |
break; |
6422 | 6403 |
case OPC_SWXC1: |
6423 | 6404 |
check_cop1x(ctx); |
6424 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6425 |
op_ldst_swc1(ctx);
|
|
6405 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6406 |
tcg_gen_qemu_st32(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
6426 | 6407 |
opn = "swxc1"; |
6427 | 6408 |
store = 1; |
6428 | 6409 |
break; |
6429 | 6410 |
case OPC_SDXC1: |
6430 | 6411 |
check_cop1x(ctx); |
6431 | 6412 |
check_cp1_registers(ctx, fs); |
6432 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6433 |
op_ldst_sdc1(ctx);
|
|
6413 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6414 |
tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
6434 | 6415 |
opn = "sdxc1"; |
6435 | 6416 |
store = 1; |
6436 | 6417 |
break; |
6437 | 6418 |
case OPC_SUXC1: |
6438 | 6419 |
check_cp1_64bitmode(ctx); |
6439 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6420 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6440 | 6421 |
op_ldst(suxc1); |
6441 | 6422 |
opn = "suxc1"; |
6442 | 6423 |
store = 1; |
... | ... | |
6459 | 6440 |
case OPC_ALNV_PS: |
6460 | 6441 |
check_cp1_64bitmode(ctx); |
6461 | 6442 |
gen_load_gpr(cpu_T[0], fr); |
6462 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6463 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6443 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6444 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6464 | 6445 |
gen_op_float_alnv_ps(); |
6465 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6446 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6466 | 6447 |
opn = "alnv.ps"; |
6467 | 6448 |
break; |
6468 | 6449 |
case OPC_MADD_S: |
6469 | 6450 |
check_cop1x(ctx); |
6470 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6471 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6472 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6451 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6452 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6453 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6473 | 6454 |
gen_op_float_muladd_s(); |
6474 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6455 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6475 | 6456 |
opn = "madd.s"; |
6476 | 6457 |
break; |
6477 | 6458 |
case OPC_MADD_D: |
6478 | 6459 |
check_cop1x(ctx); |
6479 | 6460 |
check_cp1_registers(ctx, fd | fs | ft | fr); |
6480 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6481 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6482 |
GEN_LOAD_FREG_FTN(DT2, fr);
|
|
6461 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6462 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6463 |
gen_load_fpr64(ctx, fpu64_T[2], fr);
|
|
6483 | 6464 |
gen_op_float_muladd_d(); |
6484 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6465 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6485 | 6466 |
opn = "madd.d"; |
6486 | 6467 |
break; |
6487 | 6468 |
case OPC_MADD_PS: |
6488 | 6469 |
check_cp1_64bitmode(ctx); |
6489 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6490 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6491 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6492 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6493 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6494 |
GEN_LOAD_FREG_FTN(WTH2, fr);
|
|
6470 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6471 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6472 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6473 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6474 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6475 |
gen_load_fpr32h(fpu32h_T[2], fr);
|
|
6495 | 6476 |
gen_op_float_muladd_ps(); |
6496 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6497 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6477 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6478 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6498 | 6479 |
opn = "madd.ps"; |
6499 | 6480 |
break; |
6500 | 6481 |
case OPC_MSUB_S: |
6501 | 6482 |
check_cop1x(ctx); |
6502 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6503 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6504 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6483 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6484 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6485 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6505 | 6486 |
gen_op_float_mulsub_s(); |
6506 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6487 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6507 | 6488 |
opn = "msub.s"; |
6508 | 6489 |
break; |
6509 | 6490 |
case OPC_MSUB_D: |
6510 | 6491 |
check_cop1x(ctx); |
6511 | 6492 |
check_cp1_registers(ctx, fd | fs | ft | fr); |
6512 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6513 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6514 |
GEN_LOAD_FREG_FTN(DT2, fr);
|
|
6493 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6494 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6495 |
gen_load_fpr64(ctx, fpu64_T[2], fr);
|
|
6515 | 6496 |
gen_op_float_mulsub_d(); |
6516 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6497 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6517 | 6498 |
opn = "msub.d"; |
6518 | 6499 |
break; |
6519 | 6500 |
case OPC_MSUB_PS: |
6520 | 6501 |
check_cp1_64bitmode(ctx); |
6521 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6522 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6523 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6524 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6525 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6526 |
GEN_LOAD_FREG_FTN(WTH2, fr);
|
|
6502 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6503 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6504 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6505 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6506 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6507 |
gen_load_fpr32h(fpu32h_T[2], fr);
|
|
6527 | 6508 |
gen_op_float_mulsub_ps(); |
6528 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6529 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6509 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6510 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6530 | 6511 |
opn = "msub.ps"; |
6531 | 6512 |
break; |
6532 | 6513 |
case OPC_NMADD_S: |
6533 | 6514 |
check_cop1x(ctx); |
6534 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6535 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6536 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6515 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6516 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6517 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6537 | 6518 |
gen_op_float_nmuladd_s(); |
6538 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6519 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6539 | 6520 |
opn = "nmadd.s"; |
6540 | 6521 |
break; |
6541 | 6522 |
case OPC_NMADD_D: |
6542 | 6523 |
check_cop1x(ctx); |
6543 | 6524 |
check_cp1_registers(ctx, fd | fs | ft | fr); |
6544 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6545 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6546 |
GEN_LOAD_FREG_FTN(DT2, fr);
|
|
6525 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6526 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6527 |
gen_load_fpr64(ctx, fpu64_T[2], fr);
|
|
6547 | 6528 |
gen_op_float_nmuladd_d(); |
6548 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6529 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6549 | 6530 |
opn = "nmadd.d"; |
6550 | 6531 |
break; |
6551 | 6532 |
case OPC_NMADD_PS: |
6552 | 6533 |
check_cp1_64bitmode(ctx); |
6553 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6554 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6555 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6556 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6557 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6558 |
GEN_LOAD_FREG_FTN(WTH2, fr);
|
|
6534 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6535 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6536 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6537 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6538 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6539 |
gen_load_fpr32h(fpu32h_T[2], fr);
|
|
6559 | 6540 |
gen_op_float_nmuladd_ps(); |
6560 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6561 |
GEN_STORE_FTN_FREG(fd, WTH2);
|
|
6541 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6542 |
gen_store_fpr32h(fpu32h_T[2], fd);
|
|
6562 | 6543 |
opn = "nmadd.ps"; |
6563 | 6544 |
break; |
6564 | 6545 |
case OPC_NMSUB_S: |
6565 | 6546 |
check_cop1x(ctx); |
6566 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6567 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6568 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6547 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6548 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6549 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6569 | 6550 |
gen_op_float_nmulsub_s(); |
6570 |
GEN_STORE_FTN_FREG(fd, WT2);
|
|
6551 |
gen_store_fpr32(fpu32_T[2], fd);
|
|
6571 | 6552 |
opn = "nmsub.s"; |
6572 | 6553 |
break; |
6573 | 6554 |
case OPC_NMSUB_D: |
6574 | 6555 |
check_cop1x(ctx); |
6575 | 6556 |
check_cp1_registers(ctx, fd | fs | ft | fr); |
6576 |
GEN_LOAD_FREG_FTN(DT0, fs);
|
|
6577 |
GEN_LOAD_FREG_FTN(DT1, ft);
|
|
6578 |
GEN_LOAD_FREG_FTN(DT2, fr);
|
|
6557 |
gen_load_fpr64(ctx, fpu64_T[0], fs);
|
|
6558 |
gen_load_fpr64(ctx, fpu64_T[1], ft);
|
|
6559 |
gen_load_fpr64(ctx, fpu64_T[2], fr);
|
|
6579 | 6560 |
gen_op_float_nmulsub_d(); |
6580 |
GEN_STORE_FTN_FREG(fd, DT2);
|
|
6561 |
gen_store_fpr64(ctx, fpu64_T[2], fd);
|
|
6581 | 6562 |
opn = "nmsub.d"; |
6582 | 6563 |
break; |
6583 | 6564 |
case OPC_NMSUB_PS: |
6584 | 6565 |
check_cp1_64bitmode(ctx); |
6585 |
GEN_LOAD_FREG_FTN(WT0, fs);
|
|
6586 |
GEN_LOAD_FREG_FTN(WTH0, fs);
|
|
6587 |
GEN_LOAD_FREG_FTN(WT1, ft);
|
|
6588 |
GEN_LOAD_FREG_FTN(WTH1, ft);
|
|
6589 |
GEN_LOAD_FREG_FTN(WT2, fr);
|
|
6590 |
GEN_LOAD_FREG_FTN(WTH2, fr);
|
|
6566 |
gen_load_fpr32(fpu32_T[0], fs);
|
|
6567 |
gen_load_fpr32h(fpu32h_T[0], fs);
|
|
6568 |
gen_load_fpr32(fpu32_T[1], ft);
|
|
6569 |
gen_load_fpr32h(fpu32h_T[1], ft);
|
|
6570 |
gen_load_fpr32(fpu32_T[2], fr);
|
|
6571 |
gen_load_fpr32h(fpu32h_T[2], fr);
|
|
6591 | 6572 |
gen_op_float_nmulsub_ps(); |
6592 |
GEN_STORE_FTN_FREG(fd, WT2); |
|
6593 |
GEN_STORE_FTN_FREG(fd, WTH2); |
|
6573 |
gen_store_fpr32(fpu32_T[2], fd); |
|
6574 |
gen_store_fpr32h(fpu32h_T[2], fd); |
Also available in: Unified diff