Revision aa328add target-mips/helper.c

b/target-mips/helper.c
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void do_interrupt (CPUState *env)
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{
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    target_ulong pc, offset;
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    target_ulong offset;
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    int cause = -1;
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    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
......
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    set_DEPC:
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        if (env->hflags & MIPS_HFLAG_BMASK) {
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            /* If the exception was raised from a delay slot,
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             * come back to the jump
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             */
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               come back to the jump.  */
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            env->CP0_DEPC = env->PC - 4;
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            env->hflags &= ~MIPS_HFLAG_BMASK;
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        } else {
......
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    enter_debug_mode:
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        env->hflags |= MIPS_HFLAG_DM;
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        /* EJTAG probe trap enable is not implemented... */
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        pc = 0xBFC00480;
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        env->PC = 0xBFC00480;
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        break;
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    case EXCP_RESET:
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#ifdef MIPS_USES_R4K_TLB
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        env->CP0_random = MIPS_TLB_NB - 1;
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#endif
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        env->CP0_Wired = 0;
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        env->CP0_Config0 = MIPS_CONFIG0;
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        env->CP0_Config1 = MIPS_CONFIG1;
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        env->CP0_Config2 = MIPS_CONFIG2;
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        env->CP0_Config3 = MIPS_CONFIG3;
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        env->CP0_WatchLo = 0;
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        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
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        goto set_error_EPC;
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        cpu_reset(env);
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        break;
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    case EXCP_SRESET:
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        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
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            (1 << CP0St_SR);
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        env->CP0_Status = (1 << CP0St_SR);
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        env->CP0_WatchLo = 0;
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        goto set_error_EPC;
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    case EXCP_NMI:
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        env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
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            (1 << CP0St_NMI);
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        env->CP0_Status = (1 << CP0St_NMI);
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    set_error_EPC:
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        if (env->hflags & MIPS_HFLAG_BMASK) {
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            /* If the exception was raised from a delay slot,
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             * come back to the jump
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             */
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               come back to the jump.  */
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            env->CP0_ErrorEPC = env->PC - 4;
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            env->hflags &= ~MIPS_HFLAG_BMASK;
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        } else {
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            env->CP0_ErrorEPC = env->PC;
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        }
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        env->hflags |= MIPS_HFLAG_ERL;
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	env->CP0_Status |= (1 << CP0St_ERL);
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        pc = 0xBFC00000;
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	env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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        env->PC = 0xBFC00000;
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        break;
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    case EXCP_MCHECK:
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        cause = 24;
......
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            offset = 0x000;
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        goto set_EPC;
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    set_EPC:
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        if (env->CP0_Status & (1 << CP0St_BEV)) {
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            pc = 0xBFC00200;
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        } else {
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            pc = 0x80000000;
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        }
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        env->hflags |= MIPS_HFLAG_EXL;
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	env->CP0_Status |= (1 << CP0St_EXL);
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        pc += offset;
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        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
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        if (env->hflags & MIPS_HFLAG_BMASK) {
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            /* If the exception was raised from a delay slot,
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             * come back to the jump
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             */
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               come back to the jump.  */
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            env->CP0_EPC = env->PC - 4;
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            env->CP0_Cause |= 0x80000000;
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            env->hflags &= ~MIPS_HFLAG_BMASK;
......
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            env->CP0_EPC = env->PC;
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            env->CP0_Cause &= ~0x80000000;
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        }
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        if (env->CP0_Status & (1 << CP0St_BEV)) {
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            env->PC = 0xBFC00200;
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        } else {
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            env->PC = 0x80000000;
389
        }
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        env->hflags |= MIPS_HFLAG_EXL;
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        env->CP0_Status |= (1 << CP0St_EXL);
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        env->PC += offset;
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        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
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        break;
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    default:
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        if (logfile) {
......
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        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
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        exit(1);
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    }
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    env->PC = pc;
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    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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        fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
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                "    S %08x C %08x A %08x D %08x\n",

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