Revision aa328add target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 2817 | 2817 |
{
|
| 2818 | 2818 |
const char *opn = "unk"; |
| 2819 | 2819 |
|
| 2820 |
if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
|
|
| 2821 |
(ctx->hflags & MIPS_HFLAG_UM) &&
|
|
| 2820 |
if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
|
|
| 2821 |
(ctx->hflags & MIPS_HFLAG_UM)) &&
|
|
| 2822 | 2822 |
!(ctx->hflags & MIPS_HFLAG_ERL) && |
| 2823 | 2823 |
!(ctx->hflags & MIPS_HFLAG_EXL)) {
|
| 2824 | 2824 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
| ... | ... | |
| 4048 | 4048 |
tlb_flush(env, 1); |
| 4049 | 4049 |
|
| 4050 | 4050 |
/* Minimal init */ |
| 4051 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
|
| 4052 |
/* If the exception was raised from a delay slot, |
|
| 4053 |
* come back to the jump. */ |
|
| 4054 |
env->CP0_ErrorEPC = env->PC - 4; |
|
| 4055 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
|
| 4056 |
} else {
|
|
| 4057 |
env->CP0_ErrorEPC = env->PC; |
|
| 4058 |
} |
|
| 4051 | 4059 |
env->PC = 0xBFC00000; |
| 4052 | 4060 |
#if defined (MIPS_USES_R4K_TLB) |
| 4053 | 4061 |
env->CP0_random = MIPS_TLB_NB - 1; |
| ... | ... | |
| 4060 | 4068 |
env->CP0_Config1 = MIPS_CONFIG1; |
| 4061 | 4069 |
env->CP0_Config2 = MIPS_CONFIG2; |
| 4062 | 4070 |
env->CP0_Config3 = MIPS_CONFIG3; |
| 4063 |
env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
|
|
| 4071 |
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
|
|
| 4064 | 4072 |
env->CP0_WatchLo = 0; |
| 4065 | 4073 |
env->hflags = MIPS_HFLAG_ERL; |
| 4066 | 4074 |
/* Count register increments in debug mode, EJTAG version 1 */ |
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