Revision aa941b94
| b/ecc.h | ||
|---|---|---|
| 75 | 75 |
s->cp = 0x00; |
| 76 | 76 |
s->count = 0; |
| 77 | 77 |
} |
| 78 |
|
|
| 79 |
/* Save/restore */ |
|
| 80 |
static inline void ecc_put(QEMUFile *f, struct ecc_state_s *s) |
|
| 81 |
{
|
|
| 82 |
qemu_put_8s(f, &s->cp); |
|
| 83 |
qemu_put_be16s(f, &s->lp[0]); |
|
| 84 |
qemu_put_be16s(f, &s->lp[1]); |
|
| 85 |
qemu_put_be16s(f, &s->count); |
|
| 86 |
} |
|
| 87 |
|
|
| 88 |
static inline void ecc_get(QEMUFile *f, struct ecc_state_s *s) |
|
| 89 |
{
|
|
| 90 |
qemu_get_8s(f, &s->cp); |
|
| 91 |
qemu_get_be16s(f, &s->lp[0]); |
|
| 92 |
qemu_get_be16s(f, &s->lp[1]); |
|
| 93 |
qemu_get_be16s(f, &s->count); |
|
| 94 |
} |
|
| b/hw/ads7846.c | ||
|---|---|---|
| 104 | 104 |
if (s->pressure == !buttons_state) {
|
| 105 | 105 |
s->pressure = !!buttons_state; |
| 106 | 106 |
|
| 107 |
ads7846_int_update(s);
|
|
| 107 |
ads7846_int_update(s); |
|
| 108 | 108 |
} |
| 109 | 109 |
} |
| 110 | 110 |
|
| 111 |
static void ads7846_save(QEMUFile *f, void *opaque) |
|
| 112 |
{
|
|
| 113 |
struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; |
|
| 114 |
int i; |
|
| 115 |
|
|
| 116 |
for (i = 0; i < 8; i ++) |
|
| 117 |
qemu_put_be32(f, s->input[i]); |
|
| 118 |
qemu_put_be32(f, s->noise); |
|
| 119 |
qemu_put_be32(f, s->cycle); |
|
| 120 |
qemu_put_be32(f, s->output); |
|
| 121 |
} |
|
| 122 |
|
|
| 123 |
static int ads7846_load(QEMUFile *f, void *opaque, int version_id) |
|
| 124 |
{
|
|
| 125 |
struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; |
|
| 126 |
int i; |
|
| 127 |
|
|
| 128 |
for (i = 0; i < 8; i ++) |
|
| 129 |
s->input[i] = qemu_get_be32(f); |
|
| 130 |
s->noise = qemu_get_be32(f); |
|
| 131 |
s->cycle = qemu_get_be32(f); |
|
| 132 |
s->output = qemu_get_be32(f); |
|
| 133 |
|
|
| 134 |
s->pressure = 0; |
|
| 135 |
ads7846_int_update(s); |
|
| 136 |
|
|
| 137 |
return 0; |
|
| 138 |
} |
|
| 139 |
|
|
| 140 |
static int ads7846_iid = 0; |
|
| 141 |
|
|
| 111 | 142 |
struct ads7846_state_s *ads7846_init(qemu_irq penirq) |
| 112 | 143 |
{
|
| 113 | 144 |
struct ads7846_state_s *s; |
| ... | ... | |
| 127 | 158 |
"QEMU ADS7846-driven Touchscreen"); |
| 128 | 159 |
|
| 129 | 160 |
ads7846_int_update(s); |
| 161 |
|
|
| 162 |
register_savevm("ads7846", ads7846_iid ++, 0,
|
|
| 163 |
ads7846_save, ads7846_load, s); |
|
| 164 |
|
|
| 130 | 165 |
return s; |
| 131 | 166 |
} |
| b/hw/i2c.c | ||
|---|---|---|
| 115 | 115 |
dev->event(dev, I2C_NACK); |
| 116 | 116 |
} |
| 117 | 117 |
|
| 118 |
void i2c_bus_save(QEMUFile *f, i2c_bus *bus) |
|
| 119 |
{
|
|
| 120 |
qemu_put_byte(f, bus->current_dev ? bus->current_dev->address : 0x00); |
|
| 121 |
} |
|
| 122 |
|
|
| 123 |
void i2c_bus_load(QEMUFile *f, i2c_bus *bus) |
|
| 124 |
{
|
|
| 125 |
i2c_slave *dev; |
|
| 126 |
uint8_t address = qemu_get_byte(f); |
|
| 127 |
|
|
| 128 |
if (address) {
|
|
| 129 |
for (dev = bus->dev; dev; dev = dev->next) |
|
| 130 |
if (dev->address == address) {
|
|
| 131 |
bus->current_dev = dev; |
|
| 132 |
return; |
|
| 133 |
} |
|
| 134 |
|
|
| 135 |
fprintf(stderr, "%s: I2C slave with address %02x disappeared\n", |
|
| 136 |
__FUNCTION__, address); |
|
| 137 |
} |
|
| 138 |
} |
|
| 139 |
|
|
| 140 |
void i2c_slave_save(QEMUFile *f, i2c_slave *dev) |
|
| 141 |
{
|
|
| 142 |
qemu_put_byte(f, dev->address); |
|
| 143 |
} |
|
| 144 |
|
|
| 145 |
void i2c_slave_load(QEMUFile *f, i2c_slave *dev) |
|
| 146 |
{
|
|
| 147 |
dev->address = qemu_get_byte(f); |
|
| 148 |
} |
|
| b/hw/i2c.h | ||
|---|---|---|
| 45 | 45 |
void i2c_nack(i2c_bus *bus); |
| 46 | 46 |
int i2c_send(i2c_bus *bus, uint8_t data); |
| 47 | 47 |
int i2c_recv(i2c_bus *bus); |
| 48 |
void i2c_bus_save(QEMUFile *f, i2c_bus *bus); |
|
| 49 |
void i2c_bus_load(QEMUFile *f, i2c_bus *bus); |
|
| 50 |
void i2c_slave_save(QEMUFile *f, i2c_slave *dev); |
|
| 51 |
void i2c_slave_load(QEMUFile *f, i2c_slave *dev); |
|
| 48 | 52 |
|
| 49 | 53 |
/* max7310.c */ |
| 50 | 54 |
i2c_slave *max7310_init(i2c_bus *bus); |
| b/hw/ide.c | ||
|---|---|---|
| 2416 | 2416 |
register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state); |
| 2417 | 2417 |
} |
| 2418 | 2418 |
|
| 2419 |
/* save per IDE drive data */ |
|
| 2420 |
static void ide_save(QEMUFile* f, IDEState *s) |
|
| 2421 |
{
|
|
| 2422 |
qemu_put_be32s(f, &s->mult_sectors); |
|
| 2423 |
qemu_put_be32s(f, &s->identify_set); |
|
| 2424 |
if (s->identify_set) {
|
|
| 2425 |
qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512); |
|
| 2426 |
} |
|
| 2427 |
qemu_put_8s(f, &s->feature); |
|
| 2428 |
qemu_put_8s(f, &s->error); |
|
| 2429 |
qemu_put_be32s(f, &s->nsector); |
|
| 2430 |
qemu_put_8s(f, &s->sector); |
|
| 2431 |
qemu_put_8s(f, &s->lcyl); |
|
| 2432 |
qemu_put_8s(f, &s->hcyl); |
|
| 2433 |
qemu_put_8s(f, &s->hob_feature); |
|
| 2434 |
qemu_put_8s(f, &s->hob_nsector); |
|
| 2435 |
qemu_put_8s(f, &s->hob_sector); |
|
| 2436 |
qemu_put_8s(f, &s->hob_lcyl); |
|
| 2437 |
qemu_put_8s(f, &s->hob_hcyl); |
|
| 2438 |
qemu_put_8s(f, &s->select); |
|
| 2439 |
qemu_put_8s(f, &s->status); |
|
| 2440 |
qemu_put_8s(f, &s->lba48); |
|
| 2441 |
|
|
| 2442 |
qemu_put_8s(f, &s->sense_key); |
|
| 2443 |
qemu_put_8s(f, &s->asc); |
|
| 2444 |
/* XXX: if a transfer is pending, we do not save it yet */ |
|
| 2445 |
} |
|
| 2446 |
|
|
| 2447 |
/* load per IDE drive data */ |
|
| 2448 |
static void ide_load(QEMUFile* f, IDEState *s) |
|
| 2449 |
{
|
|
| 2450 |
qemu_get_be32s(f, &s->mult_sectors); |
|
| 2451 |
qemu_get_be32s(f, &s->identify_set); |
|
| 2452 |
if (s->identify_set) {
|
|
| 2453 |
qemu_get_buffer(f, (uint8_t *)s->identify_data, 512); |
|
| 2454 |
} |
|
| 2455 |
qemu_get_8s(f, &s->feature); |
|
| 2456 |
qemu_get_8s(f, &s->error); |
|
| 2457 |
qemu_get_be32s(f, &s->nsector); |
|
| 2458 |
qemu_get_8s(f, &s->sector); |
|
| 2459 |
qemu_get_8s(f, &s->lcyl); |
|
| 2460 |
qemu_get_8s(f, &s->hcyl); |
|
| 2461 |
qemu_get_8s(f, &s->hob_feature); |
|
| 2462 |
qemu_get_8s(f, &s->hob_nsector); |
|
| 2463 |
qemu_get_8s(f, &s->hob_sector); |
|
| 2464 |
qemu_get_8s(f, &s->hob_lcyl); |
|
| 2465 |
qemu_get_8s(f, &s->hob_hcyl); |
|
| 2466 |
qemu_get_8s(f, &s->select); |
|
| 2467 |
qemu_get_8s(f, &s->status); |
|
| 2468 |
qemu_get_8s(f, &s->lba48); |
|
| 2469 |
|
|
| 2470 |
qemu_get_8s(f, &s->sense_key); |
|
| 2471 |
qemu_get_8s(f, &s->asc); |
|
| 2472 |
/* XXX: if a transfer is pending, we do not save it yet */ |
|
| 2473 |
} |
|
| 2474 |
|
|
| 2419 | 2475 |
/***********************************************************/ |
| 2420 | 2476 |
/* ISA IDE definitions */ |
| 2421 | 2477 |
|
| ... | ... | |
| 2731 | 2787 |
|
| 2732 | 2788 |
/* per IDE drive data */ |
| 2733 | 2789 |
for(i = 0; i < 4; i++) {
|
| 2734 |
IDEState *s = &d->ide_if[i]; |
|
| 2735 |
qemu_put_be32s(f, &s->mult_sectors); |
|
| 2736 |
qemu_put_be32s(f, &s->identify_set); |
|
| 2737 |
if (s->identify_set) {
|
|
| 2738 |
qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512); |
|
| 2739 |
} |
|
| 2740 |
qemu_put_8s(f, &s->feature); |
|
| 2741 |
qemu_put_8s(f, &s->error); |
|
| 2742 |
qemu_put_be32s(f, &s->nsector); |
|
| 2743 |
qemu_put_8s(f, &s->sector); |
|
| 2744 |
qemu_put_8s(f, &s->lcyl); |
|
| 2745 |
qemu_put_8s(f, &s->hcyl); |
|
| 2746 |
qemu_put_8s(f, &s->hob_feature); |
|
| 2747 |
qemu_put_8s(f, &s->hob_nsector); |
|
| 2748 |
qemu_put_8s(f, &s->hob_sector); |
|
| 2749 |
qemu_put_8s(f, &s->hob_lcyl); |
|
| 2750 |
qemu_put_8s(f, &s->hob_hcyl); |
|
| 2751 |
qemu_put_8s(f, &s->select); |
|
| 2752 |
qemu_put_8s(f, &s->status); |
|
| 2753 |
qemu_put_8s(f, &s->lba48); |
|
| 2754 |
|
|
| 2755 |
qemu_put_8s(f, &s->sense_key); |
|
| 2756 |
qemu_put_8s(f, &s->asc); |
|
| 2757 |
/* XXX: if a transfer is pending, we do not save it yet */ |
|
| 2790 |
ide_save(f, &d->ide_if[i]); |
|
| 2758 | 2791 |
} |
| 2759 | 2792 |
} |
| 2760 | 2793 |
|
| ... | ... | |
| 2788 | 2821 |
|
| 2789 | 2822 |
/* per IDE drive data */ |
| 2790 | 2823 |
for(i = 0; i < 4; i++) {
|
| 2791 |
IDEState *s = &d->ide_if[i]; |
|
| 2792 |
qemu_get_be32s(f, &s->mult_sectors); |
|
| 2793 |
qemu_get_be32s(f, &s->identify_set); |
|
| 2794 |
if (s->identify_set) {
|
|
| 2795 |
qemu_get_buffer(f, (uint8_t *)s->identify_data, 512); |
|
| 2796 |
} |
|
| 2797 |
qemu_get_8s(f, &s->feature); |
|
| 2798 |
qemu_get_8s(f, &s->error); |
|
| 2799 |
qemu_get_be32s(f, &s->nsector); |
|
| 2800 |
qemu_get_8s(f, &s->sector); |
|
| 2801 |
qemu_get_8s(f, &s->lcyl); |
|
| 2802 |
qemu_get_8s(f, &s->hcyl); |
|
| 2803 |
qemu_get_8s(f, &s->hob_feature); |
|
| 2804 |
qemu_get_8s(f, &s->hob_nsector); |
|
| 2805 |
qemu_get_8s(f, &s->hob_sector); |
|
| 2806 |
qemu_get_8s(f, &s->hob_lcyl); |
|
| 2807 |
qemu_get_8s(f, &s->hob_hcyl); |
|
| 2808 |
qemu_get_8s(f, &s->select); |
|
| 2809 |
qemu_get_8s(f, &s->status); |
|
| 2810 |
qemu_get_8s(f, &s->lba48); |
|
| 2811 |
|
|
| 2812 |
qemu_get_8s(f, &s->sense_key); |
|
| 2813 |
qemu_get_8s(f, &s->asc); |
|
| 2814 |
/* XXX: if a transfer is pending, we do not save it yet */ |
|
| 2824 |
ide_load(f, &d->ide_if[i]); |
|
| 2815 | 2825 |
} |
| 2816 | 2826 |
return 0; |
| 2817 | 2827 |
} |
| ... | ... | |
| 3255 | 3265 |
} |
| 3256 | 3266 |
} |
| 3257 | 3267 |
|
| 3268 |
static void md_save(QEMUFile *f, void *opaque) |
|
| 3269 |
{
|
|
| 3270 |
struct md_s *s = (struct md_s *) opaque; |
|
| 3271 |
int i; |
|
| 3272 |
uint8_t drive1_selected; |
|
| 3273 |
|
|
| 3274 |
qemu_put_8s(f, &s->opt); |
|
| 3275 |
qemu_put_8s(f, &s->stat); |
|
| 3276 |
qemu_put_8s(f, &s->pins); |
|
| 3277 |
|
|
| 3278 |
qemu_put_8s(f, &s->ctrl); |
|
| 3279 |
qemu_put_be16s(f, &s->io); |
|
| 3280 |
qemu_put_byte(f, s->cycle); |
|
| 3281 |
|
|
| 3282 |
drive1_selected = (s->ide->cur_drive != s->ide); |
|
| 3283 |
qemu_put_8s(f, &s->ide->cmd); |
|
| 3284 |
qemu_put_8s(f, &drive1_selected); |
|
| 3285 |
|
|
| 3286 |
for (i = 0; i < 2; i ++) |
|
| 3287 |
ide_save(f, &s->ide[i]); |
|
| 3288 |
} |
|
| 3289 |
|
|
| 3290 |
static int md_load(QEMUFile *f, void *opaque, int version_id) |
|
| 3291 |
{
|
|
| 3292 |
struct md_s *s = (struct md_s *) opaque; |
|
| 3293 |
int i; |
|
| 3294 |
uint8_t drive1_selected; |
|
| 3295 |
|
|
| 3296 |
qemu_get_8s(f, &s->opt); |
|
| 3297 |
qemu_get_8s(f, &s->stat); |
|
| 3298 |
qemu_get_8s(f, &s->pins); |
|
| 3299 |
|
|
| 3300 |
qemu_get_8s(f, &s->ctrl); |
|
| 3301 |
qemu_get_be16s(f, &s->io); |
|
| 3302 |
s->cycle = qemu_get_byte(f); |
|
| 3303 |
|
|
| 3304 |
qemu_get_8s(f, &s->ide->cmd); |
|
| 3305 |
qemu_get_8s(f, &drive1_selected); |
|
| 3306 |
s->ide->cur_drive = &s->ide[(drive1_selected != 0)]; |
|
| 3307 |
|
|
| 3308 |
for (i = 0; i < 2; i ++) |
|
| 3309 |
ide_load(f, &s->ide[i]); |
|
| 3310 |
|
|
| 3311 |
return 0; |
|
| 3312 |
} |
|
| 3313 |
|
|
| 3314 |
static int md_iid = 0; |
|
| 3315 |
|
|
| 3258 | 3316 |
static const uint8_t dscm1xxxx_cis[0x14a] = {
|
| 3259 | 3317 |
[0x000] = CISTPL_DEVICE, /* 5V Device Information */ |
| 3260 | 3318 |
[0x002] = 0x03, /* Tuple length = 4 bytes */ |
| ... | ... | |
| 3480 | 3538 |
md->ide->is_cf = 1; |
| 3481 | 3539 |
md->ide->mdata_size = METADATA_SIZE; |
| 3482 | 3540 |
md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE); |
| 3541 |
|
|
| 3542 |
register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md);
|
|
| 3543 |
|
|
| 3483 | 3544 |
return &md->card; |
| 3484 | 3545 |
} |
| b/hw/max111x.c | ||
|---|---|---|
| 89 | 89 |
qemu_irq_raise(s->interrupt); |
| 90 | 90 |
} |
| 91 | 91 |
|
| 92 |
static void max111x_save(QEMUFile *f, void *opaque) |
|
| 93 |
{
|
|
| 94 |
struct max111x_s *s = (struct max111x_s *) opaque; |
|
| 95 |
int i; |
|
| 96 |
|
|
| 97 |
qemu_put_8s(f, &s->tb1); |
|
| 98 |
qemu_put_8s(f, &s->rb2); |
|
| 99 |
qemu_put_8s(f, &s->rb3); |
|
| 100 |
qemu_put_be32(f, s->inputs); |
|
| 101 |
qemu_put_be32(f, s->com); |
|
| 102 |
for (i = 0; i < s->inputs; i ++) |
|
| 103 |
qemu_put_byte(f, s->input[i]); |
|
| 104 |
} |
|
| 105 |
|
|
| 106 |
static int max111x_load(QEMUFile *f, void *opaque, int version_id) |
|
| 107 |
{
|
|
| 108 |
struct max111x_s *s = (struct max111x_s *) opaque; |
|
| 109 |
int i; |
|
| 110 |
|
|
| 111 |
qemu_get_8s(f, &s->tb1); |
|
| 112 |
qemu_get_8s(f, &s->rb2); |
|
| 113 |
qemu_get_8s(f, &s->rb3); |
|
| 114 |
if (s->inputs != qemu_get_be32(f)) |
|
| 115 |
return -EINVAL; |
|
| 116 |
s->com = qemu_get_be32(f); |
|
| 117 |
for (i = 0; i < s->inputs; i ++) |
|
| 118 |
s->input[i] = qemu_get_byte(f); |
|
| 119 |
|
|
| 120 |
return 0; |
|
| 121 |
} |
|
| 122 |
|
|
| 123 |
static int max111x_iid = 0; |
|
| 124 |
|
|
| 92 | 125 |
static struct max111x_s *max111x_init(qemu_irq cb) |
| 93 | 126 |
{
|
| 94 | 127 |
struct max111x_s *s; |
| ... | ... | |
| 108 | 141 |
s->input[6] = 0x90; |
| 109 | 142 |
s->input[7] = 0x80; |
| 110 | 143 |
s->com = 0; |
| 144 |
|
|
| 145 |
register_savevm("max111x", max111x_iid ++, 0,
|
|
| 146 |
max111x_save, max111x_load, s); |
|
| 147 |
|
|
| 111 | 148 |
return s; |
| 112 | 149 |
} |
| 113 | 150 |
|
| b/hw/max7310.c | ||
|---|---|---|
| 143 | 143 |
} |
| 144 | 144 |
} |
| 145 | 145 |
|
| 146 |
static void max7310_save(QEMUFile *f, void *opaque) |
|
| 147 |
{
|
|
| 148 |
struct max7310_s *s = (struct max7310_s *) opaque; |
|
| 149 |
|
|
| 150 |
qemu_put_be32(f, s->i2c_command_byte); |
|
| 151 |
qemu_put_be32(f, s->len); |
|
| 152 |
|
|
| 153 |
qemu_put_8s(f, &s->level); |
|
| 154 |
qemu_put_8s(f, &s->direction); |
|
| 155 |
qemu_put_8s(f, &s->polarity); |
|
| 156 |
qemu_put_8s(f, &s->status); |
|
| 157 |
qemu_put_8s(f, &s->command); |
|
| 158 |
|
|
| 159 |
i2c_slave_save(f, &s->i2c); |
|
| 160 |
} |
|
| 161 |
|
|
| 162 |
static int max7310_load(QEMUFile *f, void *opaque, int version_id) |
|
| 163 |
{
|
|
| 164 |
struct max7310_s *s = (struct max7310_s *) opaque; |
|
| 165 |
|
|
| 166 |
s->i2c_command_byte = qemu_get_be32(f); |
|
| 167 |
s->len = qemu_get_be32(f); |
|
| 168 |
|
|
| 169 |
qemu_get_8s(f, &s->level); |
|
| 170 |
qemu_get_8s(f, &s->direction); |
|
| 171 |
qemu_get_8s(f, &s->polarity); |
|
| 172 |
qemu_get_8s(f, &s->status); |
|
| 173 |
qemu_get_8s(f, &s->command); |
|
| 174 |
|
|
| 175 |
i2c_slave_load(f, &s->i2c); |
|
| 176 |
return 0; |
|
| 177 |
} |
|
| 178 |
|
|
| 179 |
static int max7310_iid = 0; |
|
| 180 |
|
|
| 146 | 181 |
static void max7310_gpio_set(void *opaque, int line, int level) |
| 147 | 182 |
{
|
| 148 | 183 |
struct max7310_s *s = (struct max7310_s *) opaque; |
| ... | ... | |
| 169 | 204 |
|
| 170 | 205 |
max7310_reset(&s->i2c); |
| 171 | 206 |
|
| 207 |
register_savevm("max7310", max7310_iid ++, 0,
|
|
| 208 |
max7310_save, max7310_load, s); |
|
| 209 |
|
|
| 172 | 210 |
return &s->i2c; |
| 173 | 211 |
} |
| 174 | 212 |
|
| b/hw/nand.c | ||
|---|---|---|
| 273 | 273 |
} |
| 274 | 274 |
} |
| 275 | 275 |
|
| 276 |
static void nand_save(QEMUFile *f, void *opaque) |
|
| 277 |
{
|
|
| 278 |
struct nand_flash_s *s = (struct nand_flash_s *) opaque; |
|
| 279 |
qemu_put_byte(f, s->cle); |
|
| 280 |
qemu_put_byte(f, s->ale); |
|
| 281 |
qemu_put_byte(f, s->ce); |
|
| 282 |
qemu_put_byte(f, s->wp); |
|
| 283 |
qemu_put_byte(f, s->gnd); |
|
| 284 |
qemu_put_buffer(f, s->io, sizeof(s->io)); |
|
| 285 |
qemu_put_be32(f, s->ioaddr - s->io); |
|
| 286 |
qemu_put_be32(f, s->iolen); |
|
| 287 |
|
|
| 288 |
qemu_put_be32s(f, &s->cmd); |
|
| 289 |
qemu_put_be32s(f, &s->addr); |
|
| 290 |
qemu_put_be32(f, s->addrlen); |
|
| 291 |
qemu_put_be32(f, s->status); |
|
| 292 |
qemu_put_be32(f, s->offset); |
|
| 293 |
/* XXX: do we want to save s->storage too? */ |
|
| 294 |
} |
|
| 295 |
|
|
| 296 |
static int nand_load(QEMUFile *f, void *opaque, int version_id) |
|
| 297 |
{
|
|
| 298 |
struct nand_flash_s *s = (struct nand_flash_s *) opaque; |
|
| 299 |
s->cle = qemu_get_byte(f); |
|
| 300 |
s->ale = qemu_get_byte(f); |
|
| 301 |
s->ce = qemu_get_byte(f); |
|
| 302 |
s->wp = qemu_get_byte(f); |
|
| 303 |
s->gnd = qemu_get_byte(f); |
|
| 304 |
qemu_get_buffer(f, s->io, sizeof(s->io)); |
|
| 305 |
s->ioaddr = s->io + qemu_get_be32(f); |
|
| 306 |
s->iolen = qemu_get_be32(f); |
|
| 307 |
if (s->ioaddr >= s->io + sizeof(s->io) || s->ioaddr < s->io) |
|
| 308 |
return -EINVAL; |
|
| 309 |
|
|
| 310 |
qemu_get_be32s(f, &s->cmd); |
|
| 311 |
qemu_get_be32s(f, &s->addr); |
|
| 312 |
s->addrlen = qemu_get_be32(f); |
|
| 313 |
s->status = qemu_get_be32(f); |
|
| 314 |
s->offset = qemu_get_be32(f); |
|
| 315 |
return 0; |
|
| 316 |
} |
|
| 317 |
|
|
| 318 |
static int nand_iid = 0; |
|
| 319 |
|
|
| 276 | 320 |
/* |
| 277 | 321 |
* Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip |
| 278 | 322 |
* outputs are R/B and eight I/O pins. |
| ... | ... | |
| 443 | 487 |
if (pagesize) |
| 444 | 488 |
s->storage = (uint8_t *) memset(qemu_malloc(s->pages * pagesize), |
| 445 | 489 |
0xff, s->pages * pagesize); |
| 490 |
|
|
| 491 |
register_savevm("nand", nand_iid ++, 0, nand_save, nand_load, s);
|
|
| 492 |
|
|
| 446 | 493 |
return s; |
| 447 | 494 |
} |
| 448 | 495 |
|
| b/hw/pxa2xx.c | ||
|---|---|---|
| 141 | 141 |
pxa2xx_pm_write, |
| 142 | 142 |
}; |
| 143 | 143 |
|
| 144 |
static void pxa2xx_pm_save(QEMUFile *f, void *opaque) |
|
| 145 |
{
|
|
| 146 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 147 |
int i; |
|
| 148 |
|
|
| 149 |
for (i = 0; i < 0x40; i ++) |
|
| 150 |
qemu_put_be32s(f, &s->pm_regs[i]); |
|
| 151 |
} |
|
| 152 |
|
|
| 153 |
static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 154 |
{
|
|
| 155 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 156 |
int i; |
|
| 157 |
|
|
| 158 |
for (i = 0; i < 0x40; i ++) |
|
| 159 |
qemu_get_be32s(f, &s->pm_regs[i]); |
|
| 160 |
|
|
| 161 |
return 0; |
|
| 162 |
} |
|
| 163 |
|
|
| 144 | 164 |
#define CCCR 0x00 /* Core Clock Configuration register */ |
| 145 | 165 |
#define CKEN 0x04 /* Clock Enable register */ |
| 146 | 166 |
#define OSCC 0x08 /* Oscillator Configuration register */ |
| ... | ... | |
| 204 | 224 |
pxa2xx_cm_write, |
| 205 | 225 |
}; |
| 206 | 226 |
|
| 227 |
static void pxa2xx_cm_save(QEMUFile *f, void *opaque) |
|
| 228 |
{
|
|
| 229 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 230 |
int i; |
|
| 231 |
|
|
| 232 |
for (i = 0; i < 4; i ++) |
|
| 233 |
qemu_put_be32s(f, &s->cm_regs[i]); |
|
| 234 |
qemu_put_be32s(f, &s->clkcfg); |
|
| 235 |
qemu_put_be32s(f, &s->pmnc); |
|
| 236 |
} |
|
| 237 |
|
|
| 238 |
static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 239 |
{
|
|
| 240 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 241 |
int i; |
|
| 242 |
|
|
| 243 |
for (i = 0; i < 4; i ++) |
|
| 244 |
qemu_get_be32s(f, &s->cm_regs[i]); |
|
| 245 |
qemu_get_be32s(f, &s->clkcfg); |
|
| 246 |
qemu_get_be32s(f, &s->pmnc); |
|
| 247 |
|
|
| 248 |
return 0; |
|
| 249 |
} |
|
| 250 |
|
|
| 207 | 251 |
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) |
| 208 | 252 |
{
|
| 209 | 253 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
| ... | ... | |
| 482 | 526 |
pxa2xx_mm_write, |
| 483 | 527 |
}; |
| 484 | 528 |
|
| 529 |
static void pxa2xx_mm_save(QEMUFile *f, void *opaque) |
|
| 530 |
{
|
|
| 531 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 532 |
int i; |
|
| 533 |
|
|
| 534 |
for (i = 0; i < 0x1a; i ++) |
|
| 535 |
qemu_put_be32s(f, &s->mm_regs[i]); |
|
| 536 |
} |
|
| 537 |
|
|
| 538 |
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id) |
|
| 539 |
{
|
|
| 540 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 541 |
int i; |
|
| 542 |
|
|
| 543 |
for (i = 0; i < 0x1a; i ++) |
|
| 544 |
qemu_get_be32s(f, &s->mm_regs[i]); |
|
| 545 |
|
|
| 546 |
return 0; |
|
| 547 |
} |
|
| 548 |
|
|
| 485 | 549 |
/* Synchronous Serial Ports */ |
| 486 | 550 |
struct pxa2xx_ssp_s {
|
| 487 | 551 |
target_phys_addr_t base; |
| ... | ... | |
| 761 | 825 |
pxa2xx_ssp_write, |
| 762 | 826 |
}; |
| 763 | 827 |
|
| 828 |
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) |
|
| 829 |
{
|
|
| 830 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
|
| 831 |
int i; |
|
| 832 |
|
|
| 833 |
qemu_put_be32(f, s->enable); |
|
| 834 |
|
|
| 835 |
qemu_put_be32s(f, &s->sscr[0]); |
|
| 836 |
qemu_put_be32s(f, &s->sscr[1]); |
|
| 837 |
qemu_put_be32s(f, &s->sspsp); |
|
| 838 |
qemu_put_be32s(f, &s->ssto); |
|
| 839 |
qemu_put_be32s(f, &s->ssitr); |
|
| 840 |
qemu_put_be32s(f, &s->sssr); |
|
| 841 |
qemu_put_8s(f, &s->sstsa); |
|
| 842 |
qemu_put_8s(f, &s->ssrsa); |
|
| 843 |
qemu_put_8s(f, &s->ssacd); |
|
| 844 |
|
|
| 845 |
qemu_put_byte(f, s->rx_level); |
|
| 846 |
for (i = 0; i < s->rx_level; i ++) |
|
| 847 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]); |
|
| 848 |
} |
|
| 849 |
|
|
| 850 |
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) |
|
| 851 |
{
|
|
| 852 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
|
| 853 |
int i; |
|
| 854 |
|
|
| 855 |
s->enable = qemu_get_be32(f); |
|
| 856 |
|
|
| 857 |
qemu_get_be32s(f, &s->sscr[0]); |
|
| 858 |
qemu_get_be32s(f, &s->sscr[1]); |
|
| 859 |
qemu_get_be32s(f, &s->sspsp); |
|
| 860 |
qemu_get_be32s(f, &s->ssto); |
|
| 861 |
qemu_get_be32s(f, &s->ssitr); |
|
| 862 |
qemu_get_be32s(f, &s->sssr); |
|
| 863 |
qemu_get_8s(f, &s->sstsa); |
|
| 864 |
qemu_get_8s(f, &s->ssrsa); |
|
| 865 |
qemu_get_8s(f, &s->ssacd); |
|
| 866 |
|
|
| 867 |
s->rx_level = qemu_get_byte(f); |
|
| 868 |
s->rx_start = 0; |
|
| 869 |
for (i = 0; i < s->rx_level; i ++) |
|
| 870 |
s->rx_fifo[i] = qemu_get_byte(f); |
|
| 871 |
|
|
| 872 |
return 0; |
|
| 873 |
} |
|
| 874 |
|
|
| 764 | 875 |
/* Real-Time Clock */ |
| 765 | 876 |
#define RCNR 0x00 /* RTC Counter register */ |
| 766 | 877 |
#define RTAR 0x04 /* RTC Alarm register */ |
| ... | ... | |
| 1052 | 1163 |
} |
| 1053 | 1164 |
} |
| 1054 | 1165 |
|
| 1055 |
static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s) |
|
| 1166 |
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
|
| 1167 |
pxa2xx_rtc_read, |
|
| 1168 |
pxa2xx_rtc_read, |
|
| 1169 |
pxa2xx_rtc_read, |
|
| 1170 |
}; |
|
| 1171 |
|
|
| 1172 |
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
|
| 1173 |
pxa2xx_rtc_write, |
|
| 1174 |
pxa2xx_rtc_write, |
|
| 1175 |
pxa2xx_rtc_write, |
|
| 1176 |
}; |
|
| 1177 |
|
|
| 1178 |
static void pxa2xx_rtc_init(struct pxa2xx_state_s *s) |
|
| 1056 | 1179 |
{
|
| 1057 | 1180 |
struct tm *tm; |
| 1058 | 1181 |
time_t ti; |
| ... | ... | |
| 1086 | 1209 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
| 1087 | 1210 |
} |
| 1088 | 1211 |
|
| 1089 |
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
|
| 1090 |
pxa2xx_rtc_read, |
|
| 1091 |
pxa2xx_rtc_read, |
|
| 1092 |
pxa2xx_rtc_read, |
|
| 1093 |
}; |
|
| 1212 |
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) |
|
| 1213 |
{
|
|
| 1214 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 1094 | 1215 |
|
| 1095 |
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
|
| 1096 |
pxa2xx_rtc_write, |
|
| 1097 |
pxa2xx_rtc_write, |
|
| 1098 |
pxa2xx_rtc_write, |
|
| 1099 |
}; |
|
| 1216 |
pxa2xx_rtc_hzupdate(s); |
|
| 1217 |
pxa2xx_rtc_piupdate(s); |
|
| 1218 |
pxa2xx_rtc_swupdate(s); |
|
| 1219 |
|
|
| 1220 |
qemu_put_be32s(f, &s->rttr); |
|
| 1221 |
qemu_put_be32s(f, &s->rtsr); |
|
| 1222 |
qemu_put_be32s(f, &s->rtar); |
|
| 1223 |
qemu_put_be32s(f, &s->rdar1); |
|
| 1224 |
qemu_put_be32s(f, &s->rdar2); |
|
| 1225 |
qemu_put_be32s(f, &s->ryar1); |
|
| 1226 |
qemu_put_be32s(f, &s->ryar2); |
|
| 1227 |
qemu_put_be32s(f, &s->swar1); |
|
| 1228 |
qemu_put_be32s(f, &s->swar2); |
|
| 1229 |
qemu_put_be32s(f, &s->piar); |
|
| 1230 |
qemu_put_be32s(f, &s->last_rcnr); |
|
| 1231 |
qemu_put_be32s(f, &s->last_rdcr); |
|
| 1232 |
qemu_put_be32s(f, &s->last_rycr); |
|
| 1233 |
qemu_put_be32s(f, &s->last_swcr); |
|
| 1234 |
qemu_put_be32s(f, &s->last_rtcpicr); |
|
| 1235 |
qemu_put_be64s(f, &s->last_hz); |
|
| 1236 |
qemu_put_be64s(f, &s->last_sw); |
|
| 1237 |
qemu_put_be64s(f, &s->last_pi); |
|
| 1238 |
} |
|
| 1239 |
|
|
| 1240 |
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1241 |
{
|
|
| 1242 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
|
| 1243 |
|
|
| 1244 |
qemu_get_be32s(f, &s->rttr); |
|
| 1245 |
qemu_get_be32s(f, &s->rtsr); |
|
| 1246 |
qemu_get_be32s(f, &s->rtar); |
|
| 1247 |
qemu_get_be32s(f, &s->rdar1); |
|
| 1248 |
qemu_get_be32s(f, &s->rdar2); |
|
| 1249 |
qemu_get_be32s(f, &s->ryar1); |
|
| 1250 |
qemu_get_be32s(f, &s->ryar2); |
|
| 1251 |
qemu_get_be32s(f, &s->swar1); |
|
| 1252 |
qemu_get_be32s(f, &s->swar2); |
|
| 1253 |
qemu_get_be32s(f, &s->piar); |
|
| 1254 |
qemu_get_be32s(f, &s->last_rcnr); |
|
| 1255 |
qemu_get_be32s(f, &s->last_rdcr); |
|
| 1256 |
qemu_get_be32s(f, &s->last_rycr); |
|
| 1257 |
qemu_get_be32s(f, &s->last_swcr); |
|
| 1258 |
qemu_get_be32s(f, &s->last_rtcpicr); |
|
| 1259 |
qemu_get_be64s(f, &s->last_hz); |
|
| 1260 |
qemu_get_be64s(f, &s->last_sw); |
|
| 1261 |
qemu_get_be64s(f, &s->last_pi); |
|
| 1262 |
|
|
| 1263 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
|
| 1264 |
|
|
| 1265 |
return 0; |
|
| 1266 |
} |
|
| 1100 | 1267 |
|
| 1101 | 1268 |
/* I2C Interface */ |
| 1102 | 1269 |
struct pxa2xx_i2c_s {
|
| ... | ... | |
| 1289 | 1456 |
pxa2xx_i2c_write, |
| 1290 | 1457 |
}; |
| 1291 | 1458 |
|
| 1459 |
static void pxa2xx_i2c_save(QEMUFile *f, void *opaque) |
|
| 1460 |
{
|
|
| 1461 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1462 |
|
|
| 1463 |
qemu_put_be16s(f, &s->control); |
|
| 1464 |
qemu_put_be16s(f, &s->status); |
|
| 1465 |
qemu_put_8s(f, &s->ibmr); |
|
| 1466 |
qemu_put_8s(f, &s->data); |
|
| 1467 |
|
|
| 1468 |
i2c_bus_save(f, s->bus); |
|
| 1469 |
i2c_slave_save(f, &s->slave); |
|
| 1470 |
} |
|
| 1471 |
|
|
| 1472 |
static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1473 |
{
|
|
| 1474 |
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; |
|
| 1475 |
|
|
| 1476 |
qemu_get_be16s(f, &s->control); |
|
| 1477 |
qemu_get_be16s(f, &s->status); |
|
| 1478 |
qemu_get_8s(f, &s->ibmr); |
|
| 1479 |
qemu_get_8s(f, &s->data); |
|
| 1480 |
|
|
| 1481 |
i2c_bus_load(f, s->bus); |
|
| 1482 |
i2c_slave_load(f, &s->slave); |
|
| 1483 |
return 0; |
|
| 1484 |
} |
|
| 1485 |
|
|
| 1292 | 1486 |
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, |
| 1293 | 1487 |
qemu_irq irq, int ioregister) |
| 1294 | 1488 |
{
|
| ... | ... | |
| 1309 | 1503 |
cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype); |
| 1310 | 1504 |
} |
| 1311 | 1505 |
|
| 1506 |
register_savevm("pxa2xx_i2c", base, 0,
|
|
| 1507 |
pxa2xx_i2c_save, pxa2xx_i2c_load, s); |
|
| 1508 |
|
|
| 1312 | 1509 |
return s; |
| 1313 | 1510 |
} |
| 1314 | 1511 |
|
| ... | ... | |
| 1470 | 1667 |
pxa2xx_i2s_write, |
| 1471 | 1668 |
}; |
| 1472 | 1669 |
|
| 1670 |
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque) |
|
| 1671 |
{
|
|
| 1672 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
|
| 1673 |
|
|
| 1674 |
qemu_put_be32s(f, &s->control[0]); |
|
| 1675 |
qemu_put_be32s(f, &s->control[1]); |
|
| 1676 |
qemu_put_be32s(f, &s->status); |
|
| 1677 |
qemu_put_be32s(f, &s->mask); |
|
| 1678 |
qemu_put_be32s(f, &s->clk); |
|
| 1679 |
|
|
| 1680 |
qemu_put_be32(f, s->enable); |
|
| 1681 |
qemu_put_be32(f, s->rx_len); |
|
| 1682 |
qemu_put_be32(f, s->tx_len); |
|
| 1683 |
qemu_put_be32(f, s->fifo_len); |
|
| 1684 |
} |
|
| 1685 |
|
|
| 1686 |
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1687 |
{
|
|
| 1688 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
|
| 1689 |
|
|
| 1690 |
qemu_get_be32s(f, &s->control[0]); |
|
| 1691 |
qemu_get_be32s(f, &s->control[1]); |
|
| 1692 |
qemu_get_be32s(f, &s->status); |
|
| 1693 |
qemu_get_be32s(f, &s->mask); |
|
| 1694 |
qemu_get_be32s(f, &s->clk); |
|
| 1695 |
|
|
| 1696 |
s->enable = qemu_get_be32(f); |
|
| 1697 |
s->rx_len = qemu_get_be32(f); |
|
| 1698 |
s->tx_len = qemu_get_be32(f); |
|
| 1699 |
s->fifo_len = qemu_get_be32(f); |
|
| 1700 |
|
|
| 1701 |
return 0; |
|
| 1702 |
} |
|
| 1703 |
|
|
| 1473 | 1704 |
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
| 1474 | 1705 |
{
|
| 1475 | 1706 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
| ... | ... | |
| 1510 | 1741 |
pxa2xx_i2s_writefn, s); |
| 1511 | 1742 |
cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype); |
| 1512 | 1743 |
|
| 1744 |
register_savevm("pxa2xx_i2s", base, 0,
|
|
| 1745 |
pxa2xx_i2s_save, pxa2xx_i2s_load, s); |
|
| 1746 |
|
|
| 1513 | 1747 |
return s; |
| 1514 | 1748 |
} |
| 1515 | 1749 |
|
| ... | ... | |
| 1712 | 1946 |
{
|
| 1713 | 1947 |
} |
| 1714 | 1948 |
|
| 1949 |
static void pxa2xx_fir_save(QEMUFile *f, void *opaque) |
|
| 1950 |
{
|
|
| 1951 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
|
| 1952 |
int i; |
|
| 1953 |
|
|
| 1954 |
qemu_put_be32(f, s->enable); |
|
| 1955 |
|
|
| 1956 |
qemu_put_8s(f, &s->control[0]); |
|
| 1957 |
qemu_put_8s(f, &s->control[1]); |
|
| 1958 |
qemu_put_8s(f, &s->control[2]); |
|
| 1959 |
qemu_put_8s(f, &s->status[0]); |
|
| 1960 |
qemu_put_8s(f, &s->status[1]); |
|
| 1961 |
|
|
| 1962 |
qemu_put_byte(f, s->rx_len); |
|
| 1963 |
for (i = 0; i < s->rx_len; i ++) |
|
| 1964 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]); |
|
| 1965 |
} |
|
| 1966 |
|
|
| 1967 |
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) |
|
| 1968 |
{
|
|
| 1969 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
|
| 1970 |
int i; |
|
| 1971 |
|
|
| 1972 |
s->enable = qemu_get_be32(f); |
|
| 1973 |
|
|
| 1974 |
qemu_get_8s(f, &s->control[0]); |
|
| 1975 |
qemu_get_8s(f, &s->control[1]); |
|
| 1976 |
qemu_get_8s(f, &s->control[2]); |
|
| 1977 |
qemu_get_8s(f, &s->status[0]); |
|
| 1978 |
qemu_get_8s(f, &s->status[1]); |
|
| 1979 |
|
|
| 1980 |
s->rx_len = qemu_get_byte(f); |
|
| 1981 |
s->rx_start = 0; |
|
| 1982 |
for (i = 0; i < s->rx_len; i ++) |
|
| 1983 |
s->rx_fifo[i] = qemu_get_byte(f); |
|
| 1984 |
|
|
| 1985 |
return 0; |
|
| 1986 |
} |
|
| 1987 |
|
|
| 1715 | 1988 |
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, |
| 1716 | 1989 |
qemu_irq irq, struct pxa2xx_dma_state_s *dma, |
| 1717 | 1990 |
CharDriverState *chr) |
| ... | ... | |
| 1735 | 2008 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
| 1736 | 2009 |
pxa2xx_fir_rx, pxa2xx_fir_event, s); |
| 1737 | 2010 |
|
| 2011 |
register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
|
|
| 2012 |
|
|
| 1738 | 2013 |
return s; |
| 1739 | 2014 |
} |
| 1740 | 2015 |
|
| ... | ... | |
| 1763 | 2038 |
|
| 1764 | 2039 |
s->env = cpu_init(); |
| 1765 | 2040 |
cpu_arm_set_model(s->env, revision ?: "pxa270"); |
| 2041 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
|
|
| 1766 | 2042 |
|
| 1767 | 2043 |
/* SDRAM & Internal Memory Storage */ |
| 1768 | 2044 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, |
| ... | ... | |
| 1800 | 2076 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, |
| 1801 | 2077 |
pxa2xx_cm_writefn, s); |
| 1802 | 2078 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); |
| 2079 |
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
|
|
| 1803 | 2080 |
|
| 1804 | 2081 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); |
| 1805 | 2082 |
|
| ... | ... | |
| 1810 | 2087 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, |
| 1811 | 2088 |
pxa2xx_mm_writefn, s); |
| 1812 | 2089 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); |
| 2090 |
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
|
|
| 1813 | 2091 |
|
| 1814 | 2092 |
for (i = 0; pxa27x_ssp[i].io_base; i ++); |
| 1815 | 2093 |
s->ssp = (struct pxa2xx_ssp_s **) |
| ... | ... | |
| 1824 | 2102 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
| 1825 | 2103 |
pxa2xx_ssp_writefn, &ssp[i]); |
| 1826 | 2104 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); |
| 2105 |
register_savevm("pxa2xx_ssp", i, 0,
|
|
| 2106 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
|
| 1827 | 2107 |
} |
| 1828 | 2108 |
|
| 1829 | 2109 |
if (usb_enabled) {
|
| ... | ... | |
| 1837 | 2117 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, |
| 1838 | 2118 |
pxa2xx_rtc_writefn, s); |
| 1839 | 2119 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1840 |
pxa2xx_rtc_reset(s); |
|
| 2120 |
pxa2xx_rtc_init(s); |
|
| 2121 |
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
|
|
| 1841 | 2122 |
|
| 1842 | 2123 |
/* Note that PM registers are in the same page with PWRI2C registers. |
| 1843 | 2124 |
* As a workaround we don't map PWRI2C into memory and we expect |
| ... | ... | |
| 1849 | 2130 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1850 | 2131 |
pxa2xx_pm_writefn, s); |
| 1851 | 2132 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype); |
| 2133 |
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
|
|
| 1852 | 2134 |
|
| 1853 | 2135 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
| 1854 | 2136 |
|
| ... | ... | |
| 1869 | 2151 |
|
| 1870 | 2152 |
s->env = cpu_init(); |
| 1871 | 2153 |
cpu_arm_set_model(s->env, "pxa255"); |
| 2154 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
|
|
| 1872 | 2155 |
|
| 1873 | 2156 |
/* SDRAM & Internal Memory Storage */ |
| 1874 | 2157 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, |
| ... | ... | |
| 1905 | 2188 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn, |
| 1906 | 2189 |
pxa2xx_cm_writefn, s); |
| 1907 | 2190 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype); |
| 2191 |
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
|
|
| 1908 | 2192 |
|
| 1909 | 2193 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); |
| 1910 | 2194 |
|
| ... | ... | |
| 1915 | 2199 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn, |
| 1916 | 2200 |
pxa2xx_mm_writefn, s); |
| 1917 | 2201 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype); |
| 2202 |
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
|
|
| 1918 | 2203 |
|
| 1919 | 2204 |
for (i = 0; pxa255_ssp[i].io_base; i ++); |
| 1920 | 2205 |
s->ssp = (struct pxa2xx_ssp_s **) |
| ... | ... | |
| 1929 | 2214 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn, |
| 1930 | 2215 |
pxa2xx_ssp_writefn, &ssp[i]); |
| 1931 | 2216 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype); |
| 2217 |
register_savevm("pxa2xx_ssp", i, 0,
|
|
| 2218 |
pxa2xx_ssp_save, pxa2xx_ssp_load, s); |
|
| 1932 | 2219 |
} |
| 1933 | 2220 |
|
| 1934 | 2221 |
if (usb_enabled) {
|
| ... | ... | |
| 1942 | 2229 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn, |
| 1943 | 2230 |
pxa2xx_rtc_writefn, s); |
| 1944 | 2231 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype); |
| 1945 |
pxa2xx_rtc_reset(s); |
|
| 2232 |
pxa2xx_rtc_init(s); |
|
| 2233 |
register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
|
|
| 1946 | 2234 |
|
| 1947 | 2235 |
/* Note that PM registers are in the same page with PWRI2C registers. |
| 1948 | 2236 |
* As a workaround we don't map PWRI2C into memory and we expect |
| ... | ... | |
| 1954 | 2242 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn, |
| 1955 | 2243 |
pxa2xx_pm_writefn, s); |
| 1956 | 2244 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype); |
| 2245 |
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
|
|
| 1957 | 2246 |
|
| 1958 | 2247 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
| 1959 | 2248 |
|
| b/hw/pxa2xx_dma.c | ||
|---|---|---|
| 430 | 430 |
pxa2xx_dma_write |
| 431 | 431 |
}; |
| 432 | 432 |
|
| 433 |
static void pxa2xx_dma_save(QEMUFile *f, void *opaque) |
|
| 434 |
{
|
|
| 435 |
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
|
| 436 |
int i; |
|
| 437 |
|
|
| 438 |
qemu_put_be32(f, s->channels); |
|
| 439 |
|
|
| 440 |
qemu_put_be32s(f, &s->stopintr); |
|
| 441 |
qemu_put_be32s(f, &s->eorintr); |
|
| 442 |
qemu_put_be32s(f, &s->rasintr); |
|
| 443 |
qemu_put_be32s(f, &s->startintr); |
|
| 444 |
qemu_put_be32s(f, &s->endintr); |
|
| 445 |
qemu_put_be32s(f, &s->align); |
|
| 446 |
qemu_put_be32s(f, &s->pio); |
|
| 447 |
|
|
| 448 |
qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
|
| 449 |
for (i = 0; i < s->channels; i ++) {
|
|
| 450 |
qemu_put_betl(f, s->chan[i].descr); |
|
| 451 |
qemu_put_betl(f, s->chan[i].src); |
|
| 452 |
qemu_put_betl(f, s->chan[i].dest); |
|
| 453 |
qemu_put_be32s(f, &s->chan[i].cmd); |
|
| 454 |
qemu_put_be32s(f, &s->chan[i].state); |
|
| 455 |
qemu_put_be32(f, s->chan[i].request); |
|
| 456 |
}; |
|
| 457 |
} |
|
| 458 |
|
|
| 459 |
static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) |
|
| 460 |
{
|
|
| 461 |
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
|
| 462 |
int i; |
|
| 463 |
|
|
| 464 |
if (qemu_get_be32(f) != s->channels) |
|
| 465 |
return -EINVAL; |
|
| 466 |
|
|
| 467 |
qemu_get_be32s(f, &s->stopintr); |
|
| 468 |
qemu_get_be32s(f, &s->eorintr); |
|
| 469 |
qemu_get_be32s(f, &s->rasintr); |
|
| 470 |
qemu_get_be32s(f, &s->startintr); |
|
| 471 |
qemu_get_be32s(f, &s->endintr); |
|
| 472 |
qemu_get_be32s(f, &s->align); |
|
| 473 |
qemu_get_be32s(f, &s->pio); |
|
| 474 |
|
|
| 475 |
qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
|
| 476 |
for (i = 0; i < s->channels; i ++) {
|
|
| 477 |
s->chan[i].descr = qemu_get_betl(f); |
|
| 478 |
s->chan[i].src = qemu_get_betl(f); |
|
| 479 |
s->chan[i].dest = qemu_get_betl(f); |
|
| 480 |
qemu_get_be32s(f, &s->chan[i].cmd); |
|
| 481 |
qemu_get_be32s(f, &s->chan[i].state); |
|
| 482 |
s->chan[i].request = qemu_get_be32(f); |
|
| 483 |
}; |
|
| 484 |
|
|
| 485 |
return 0; |
|
| 486 |
} |
|
| 487 |
|
|
| 433 | 488 |
static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base, |
| 434 | 489 |
qemu_irq irq, int channels) |
| 435 | 490 |
{
|
| ... | ... | |
| 455 | 510 |
pxa2xx_dma_writefn, s); |
| 456 | 511 |
cpu_register_physical_memory(base, 0x0000ffff, iomemtype); |
| 457 | 512 |
|
| 513 |
register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
|
|
| 514 |
|
|
| 458 | 515 |
return s; |
| 459 | 516 |
} |
| 460 | 517 |
|
| b/hw/pxa2xx_gpio.c | ||
|---|---|---|
| 247 | 247 |
pxa2xx_gpio_write |
| 248 | 248 |
}; |
| 249 | 249 |
|
| 250 |
static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) |
|
| 251 |
{
|
|
| 252 |
struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
|
| 253 |
int i; |
|
| 254 |
|
|
| 255 |
qemu_put_be32(f, s->lines); |
|
| 256 |
|
|
| 257 |
for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
|
|
| 258 |
qemu_put_be32s(f, &s->ilevel[i]); |
|
| 259 |
qemu_put_be32s(f, &s->olevel[i]); |
|
| 260 |
qemu_put_be32s(f, &s->dir[i]); |
|
| 261 |
qemu_put_be32s(f, &s->rising[i]); |
|
| 262 |
qemu_put_be32s(f, &s->falling[i]); |
|
| 263 |
qemu_put_be32s(f, &s->status[i]); |
|
| 264 |
qemu_put_be32s(f, &s->gafr[i * 2 + 0]); |
|
| 265 |
qemu_put_be32s(f, &s->gafr[i * 2 + 1]); |
|
| 266 |
|
|
| 267 |
qemu_put_be32s(f, &s->prev_level[i]); |
|
| 268 |
} |
|
| 269 |
} |
|
| 270 |
|
|
| 271 |
static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) |
|
| 272 |
{
|
|
| 273 |
struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
|
| 274 |
int i; |
|
| 275 |
|
|
| 276 |
if (qemu_get_be32(f) != s->lines) |
|
| 277 |
return -EINVAL; |
|
| 278 |
|
|
| 279 |
for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
|
|
| 280 |
qemu_get_be32s(f, &s->ilevel[i]); |
|
| 281 |
qemu_get_be32s(f, &s->olevel[i]); |
|
| 282 |
qemu_get_be32s(f, &s->dir[i]); |
|
| 283 |
qemu_get_be32s(f, &s->rising[i]); |
|
| 284 |
qemu_get_be32s(f, &s->falling[i]); |
|
| 285 |
qemu_get_be32s(f, &s->status[i]); |
|
| 286 |
qemu_get_be32s(f, &s->gafr[i * 2 + 0]); |
|
| 287 |
qemu_get_be32s(f, &s->gafr[i * 2 + 1]); |
|
| 288 |
|
|
| 289 |
qemu_get_be32s(f, &s->prev_level[i]); |
|
| 290 |
} |
|
| 291 |
|
|
| 292 |
return 0; |
|
| 293 |
} |
|
| 294 |
|
|
| 250 | 295 |
struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, |
| 251 | 296 |
CPUState *env, qemu_irq *pic, int lines) |
| 252 | 297 |
{
|
| ... | ... | |
| 265 | 310 |
pxa2xx_gpio_writefn, s); |
| 266 | 311 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
| 267 | 312 |
|
| 313 |
register_savevm("pxa2xx_gpio", 0, 0,
|
|
| 314 |
pxa2xx_gpio_save, pxa2xx_gpio_load, s); |
|
| 315 |
|
|
| 268 | 316 |
return s; |
| 269 | 317 |
} |
| 270 | 318 |
|
| b/hw/pxa2xx_lcd.c | ||
|---|---|---|
| 924 | 924 |
pxa2xx_lcdc_resize(s); |
| 925 | 925 |
} |
| 926 | 926 |
|
| 927 |
static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) |
|
| 928 |
{
|
|
| 929 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
|
| 930 |
int i; |
|
| 931 |
|
|
| 932 |
qemu_put_be32(f, s->irqlevel); |
|
| 933 |
qemu_put_be32(f, s->transp); |
|
| 934 |
|
|
| 935 |
for (i = 0; i < 6; i ++) |
|
| 936 |
qemu_put_be32s(f, &s->control[i]); |
|
| 937 |
for (i = 0; i < 2; i ++) |
|
| 938 |
qemu_put_be32s(f, &s->status[i]); |
|
| 939 |
for (i = 0; i < 2; i ++) |
|
| 940 |
qemu_put_be32s(f, &s->ovl1c[i]); |
|
| 941 |
for (i = 0; i < 2; i ++) |
|
| 942 |
qemu_put_be32s(f, &s->ovl2c[i]); |
|
| 943 |
qemu_put_be32s(f, &s->ccr); |
|
| 944 |
qemu_put_be32s(f, &s->cmdcr); |
|
| 945 |
qemu_put_be32s(f, &s->trgbr); |
|
| 946 |
qemu_put_be32s(f, &s->tcr); |
|
| 947 |
qemu_put_be32s(f, &s->liidr); |
|
| 948 |
qemu_put_8s(f, &s->bscntr); |
|
| 949 |
|
|
| 950 |
for (i = 0; i < 7; i ++) {
|
|
| 951 |
qemu_put_betl(f, s->dma_ch[i].branch); |
|
| 952 |
qemu_put_byte(f, s->dma_ch[i].up); |
|
| 953 |
qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer)); |
|
| 954 |
|
|
| 955 |
qemu_put_betl(f, s->dma_ch[i].descriptor); |
|
| 956 |
qemu_put_betl(f, s->dma_ch[i].source); |
|
| 957 |
qemu_put_be32s(f, &s->dma_ch[i].id); |
|
| 958 |
qemu_put_be32s(f, &s->dma_ch[i].command); |
|
| 959 |
} |
|
| 960 |
} |
|
| 961 |
|
|
| 962 |
static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) |
|
| 963 |
{
|
|
| 964 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
|
| 965 |
int i; |
|
| 966 |
|
|
| 967 |
s->irqlevel = qemu_get_be32(f); |
|
| 968 |
s->transp = qemu_get_be32(f); |
|
| 969 |
|
|
| 970 |
for (i = 0; i < 6; i ++) |
|
| 971 |
qemu_get_be32s(f, &s->control[i]); |
|
| 972 |
for (i = 0; i < 2; i ++) |
|
| 973 |
qemu_get_be32s(f, &s->status[i]); |
|
| 974 |
for (i = 0; i < 2; i ++) |
|
| 975 |
qemu_get_be32s(f, &s->ovl1c[i]); |
|
| 976 |
for (i = 0; i < 2; i ++) |
|
| 977 |
qemu_get_be32s(f, &s->ovl2c[i]); |
|
| 978 |
qemu_get_be32s(f, &s->ccr); |
|
| 979 |
qemu_get_be32s(f, &s->cmdcr); |
|
| 980 |
qemu_get_be32s(f, &s->trgbr); |
|
| 981 |
qemu_get_be32s(f, &s->tcr); |
|
| 982 |
qemu_get_be32s(f, &s->liidr); |
|
| 983 |
qemu_get_8s(f, &s->bscntr); |
|
| 984 |
|
|
| 985 |
for (i = 0; i < 7; i ++) {
|
|
| 986 |
s->dma_ch[i].branch = qemu_get_betl(f); |
|
| 987 |
s->dma_ch[i].up = qemu_get_byte(f); |
|
| 988 |
qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer)); |
|
| 989 |
|
|
| 990 |
s->dma_ch[i].descriptor = qemu_get_betl(f); |
|
| 991 |
s->dma_ch[i].source = qemu_get_betl(f); |
|
| 992 |
qemu_get_be32s(f, &s->dma_ch[i].id); |
|
| 993 |
qemu_get_be32s(f, &s->dma_ch[i].command); |
|
| 994 |
} |
|
| 995 |
|
|
| 996 |
s->bpp = LCCR3_BPP(s->control[3]); |
|
| 997 |
s->xres = s->yres = s->pal_for = -1; |
|
| 998 |
|
|
| 999 |
return 0; |
|
| 1000 |
} |
|
| 1001 |
|
|
| 927 | 1002 |
#define BITS 8 |
| 928 | 1003 |
#include "pxa2xx_template.h" |
| 929 | 1004 |
#define BITS 15 |
| ... | ... | |
| 989 | 1064 |
fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__); |
| 990 | 1065 |
exit(1); |
| 991 | 1066 |
} |
| 1067 |
|
|
| 1068 |
register_savevm("pxa2xx_lcdc", 0, 0,
|
|
| 1069 |
pxa2xx_lcdc_save, pxa2xx_lcdc_load, s); |
|
| 1070 |
|
|
| 992 | 1071 |
return s; |
| 993 | 1072 |
} |
| 994 | 1073 |
|
| b/hw/pxa2xx_mmci.c | ||
|---|---|---|
| 443 | 443 |
pxa2xx_mmci_writew |
| 444 | 444 |
}; |
| 445 | 445 |
|
| 446 |
static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) |
|
| 447 |
{
|
|
| 448 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
|
| 449 |
int i; |
|
| 450 |
|
|
| 451 |
qemu_put_be32s(f, &s->status); |
|
| 452 |
qemu_put_be32s(f, &s->clkrt); |
|
| 453 |
qemu_put_be32s(f, &s->spi); |
|
| 454 |
qemu_put_be32s(f, &s->cmdat); |
|
| 455 |
qemu_put_be32s(f, &s->resp_tout); |
|
| 456 |
qemu_put_be32s(f, &s->read_tout); |
|
| 457 |
qemu_put_be32(f, s->blklen); |
|
| 458 |
qemu_put_be32(f, s->numblk); |
|
| 459 |
qemu_put_be32s(f, &s->intmask); |
|
| 460 |
qemu_put_be32s(f, &s->intreq); |
|
| 461 |
qemu_put_be32(f, s->cmd); |
|
| 462 |
qemu_put_be32s(f, &s->arg); |
|
| 463 |
qemu_put_be32(f, s->cmdreq); |
|
| 464 |
qemu_put_be32(f, s->active); |
|
| 465 |
qemu_put_be32(f, s->bytesleft); |
|
| 466 |
|
|
| 467 |
qemu_put_byte(f, s->tx_len); |
|
| 468 |
for (i = 0; i < s->tx_len; i ++) |
|
| 469 |
qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]); |
|
| 470 |
|
|
| 471 |
qemu_put_byte(f, s->rx_len); |
|
| 472 |
for (i = 0; i < s->rx_len; i ++) |
|
| 473 |
qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]); |
|
| 474 |
|
|
| 475 |
qemu_put_byte(f, s->resp_len); |
|
| 476 |
for (i = s->resp_len; i < 9; i ++) |
|
| 477 |
qemu_put_be16s(f, &s->resp_fifo[i]); |
|
| 478 |
} |
|
| 479 |
|
|
| 480 |
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) |
|
| 481 |
{
|
|
| 482 |
struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
|
| 483 |
int i; |
|
| 484 |
|
|
| 485 |
qemu_get_be32s(f, &s->status); |
|
| 486 |
qemu_get_be32s(f, &s->clkrt); |
|
| 487 |
qemu_get_be32s(f, &s->spi); |
|
| 488 |
qemu_get_be32s(f, &s->cmdat); |
|
| 489 |
qemu_get_be32s(f, &s->resp_tout); |
|
| 490 |
qemu_get_be32s(f, &s->read_tout); |
|
| 491 |
s->blklen = qemu_get_be32(f); |
|
| 492 |
s->numblk = qemu_get_be32(f); |
|
| 493 |
qemu_get_be32s(f, &s->intmask); |
|
| 494 |
qemu_get_be32s(f, &s->intreq); |
|
| 495 |
s->cmd = qemu_get_be32(f); |
|
| 496 |
qemu_get_be32s(f, &s->arg); |
|
| 497 |
s->cmdreq = qemu_get_be32(f); |
|
| 498 |
s->active = qemu_get_be32(f); |
|
| 499 |
s->bytesleft = qemu_get_be32(f); |
|
| 500 |
|
|
| 501 |
s->tx_len = qemu_get_byte(f); |
|
| 502 |
s->tx_start = 0; |
|
| 503 |
if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) |
|
| 504 |
return -EINVAL; |
|
| 505 |
for (i = 0; i < s->tx_len; i ++) |
|
| 506 |
s->tx_fifo[i] = qemu_get_byte(f); |
|
| 507 |
|
|
| 508 |
s->rx_len = qemu_get_byte(f); |
|
| 509 |
s->rx_start = 0; |
|
| 510 |
if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) |
|
| 511 |
return -EINVAL; |
|
| 512 |
for (i = 0; i < s->rx_len; i ++) |
|
| 513 |
s->rx_fifo[i] = qemu_get_byte(f); |
|
| 514 |
|
|
| 515 |
s->resp_len = qemu_get_byte(f); |
|
| 516 |
if (s->resp_len > 9 || s->resp_len < 0) |
|
| 517 |
return -EINVAL; |
|
| 518 |
for (i = s->resp_len; i < 9; i ++) |
|
| 519 |
qemu_get_be16s(f, &s->resp_fifo[i]); |
|
| 520 |
|
|
| 521 |
return 0; |
|
| 522 |
} |
|
| 523 |
|
|
| 446 | 524 |
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, |
| 447 | 525 |
qemu_irq irq, void *dma) |
| 448 | 526 |
{
|
| ... | ... | |
| 461 | 539 |
/* Instantiate the actual storage */ |
| 462 | 540 |
s->card = sd_init(sd_bdrv); |
| 463 | 541 |
|
| 542 |
register_savevm("pxa2xx_mmci", 0, 0,
|
|
| 543 |
pxa2xx_mmci_save, pxa2xx_mmci_load, s); |
|
| 544 |
|
|
| 464 | 545 |
return s; |
| 465 | 546 |
} |
| 466 | 547 |
|
| b/hw/pxa2xx_pic.c | ||
|---|---|---|
| 245 | 245 |
pxa2xx_pic_mem_write, |
| 246 | 246 |
}; |
| 247 | 247 |
|
| 248 |
static void pxa2xx_pic_save(QEMUFile *f, void *opaque) |
|
| 249 |
{
|
|
| 250 |
struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
|
| 251 |
int i; |
|
| 252 |
|
|
| 253 |
for (i = 0; i < 2; i ++) |
|
| 254 |
qemu_put_be32s(f, &s->int_enabled[i]); |
|
| 255 |
for (i = 0; i < 2; i ++) |
|
| 256 |
qemu_put_be32s(f, &s->int_pending[i]); |
|
| 257 |
for (i = 0; i < 2; i ++) |
|
| 258 |
qemu_put_be32s(f, &s->is_fiq[i]); |
|
| 259 |
qemu_put_be32s(f, &s->int_idle); |
|
| 260 |
for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
|
| 261 |
qemu_put_be32s(f, &s->priority[i]); |
|
| 262 |
} |
|
| 263 |
|
|
| 264 |
static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) |
|
| 265 |
{
|
|
| 266 |
struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
|
| 267 |
int i; |
|
| 268 |
|
|
| 269 |
for (i = 0; i < 2; i ++) |
|
| 270 |
qemu_get_be32s(f, &s->int_enabled[i]); |
|
| 271 |
for (i = 0; i < 2; i ++) |
|
| 272 |
qemu_get_be32s(f, &s->int_pending[i]); |
|
| 273 |
for (i = 0; i < 2; i ++) |
|
| 274 |
qemu_get_be32s(f, &s->is_fiq[i]); |
|
| 275 |
qemu_get_be32s(f, &s->int_idle); |
|
| 276 |
for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
|
| 277 |
qemu_get_be32s(f, &s->priority[i]); |
|
| 278 |
|
|
| 279 |
pxa2xx_pic_update(opaque); |
|
| 280 |
return 0; |
|
| 281 |
} |
|
| 282 |
|
|
| 248 | 283 |
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) |
| 249 | 284 |
{
|
| 250 | 285 |
struct pxa2xx_pic_state_s *s; |
| ... | ... | |
| 276 | 311 |
/* Enable IC coprocessor access. */ |
| 277 | 312 |
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); |
| 278 | 313 |
|
| 314 |
register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s);
|
|
| 315 |
|
|
| 279 | 316 |
return qi; |
| 280 | 317 |
} |
| b/hw/pxa2xx_timer.c | ||
|---|---|---|
| 364 | 364 |
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4); |
| 365 | 365 |
} |
| 366 | 366 |
|
| 367 |
static void pxa2xx_timer_save(QEMUFile *f, void *opaque) |
|
| 368 |
{
|
|
| 369 |
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
|
| 370 |
int i; |
|
| 371 |
|
|
| 372 |
qemu_put_be32s(f, &s->clock); |
|
| 373 |
qemu_put_be32s(f, &s->oldclock); |
|
| 374 |
qemu_put_be64s(f, &s->lastload); |
|
| 375 |
|
|
| 376 |
for (i = 0; i < 4; i ++) {
|
|
| 377 |
qemu_put_be32s(f, &s->timer[i].value); |
|
| 378 |
qemu_put_be32(f, s->timer[i].level); |
|
| 379 |
} |
|
| 380 |
if (s->tm4) |
|
| 381 |
for (i = 0; i < 8; i ++) {
|
|
| 382 |
qemu_put_be32s(f, &s->tm4[i].tm.value); |
|
| 383 |
qemu_put_be32(f, s->tm4[i].tm.level); |
|
| 384 |
qemu_put_be32s(f, &s->tm4[i].oldclock); |
|
| 385 |
qemu_put_be32s(f, &s->tm4[i].clock); |
|
| 386 |
qemu_put_be64s(f, &s->tm4[i].lastload); |
|
| 387 |
qemu_put_be32s(f, &s->tm4[i].freq); |
|
| 388 |
qemu_put_be32s(f, &s->tm4[i].control); |
|
| 389 |
} |
|
| 390 |
|
|
| 391 |
qemu_put_be32s(f, &s->events); |
|
| 392 |
qemu_put_be32s(f, &s->irq_enabled); |
|
| 393 |
qemu_put_be32s(f, &s->reset3); |
|
| 394 |
qemu_put_be32s(f, &s->snapshot); |
|
| 395 |
} |
|
| 396 |
|
|
| 397 |
static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id) |
|
| 398 |
{
|
|
| 399 |
pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
|
| 400 |
int64_t now; |
|
| 401 |
int i; |
|
| 402 |
|
|
| 403 |
qemu_get_be32s(f, &s->clock); |
|
| 404 |
qemu_get_be32s(f, &s->oldclock); |
|
| 405 |
qemu_get_be64s(f, &s->lastload); |
|
| 406 |
|
|
| 407 |
now = qemu_get_clock(vm_clock); |
|
| 408 |
for (i = 0; i < 4; i ++) {
|
|
| 409 |
qemu_get_be32s(f, &s->timer[i].value); |
|
| 410 |
s->timer[i].level = qemu_get_be32(f); |
|
| 411 |
} |
|
| 412 |
pxa2xx_timer_update(s, now); |
|
| 413 |
|
|
| 414 |
if (s->tm4) |
|
| 415 |
for (i = 0; i < 8; i ++) {
|
|
| 416 |
qemu_get_be32s(f, &s->tm4[i].tm.value); |
|
| 417 |
s->tm4[i].tm.level = qemu_get_be32(f); |
|
| 418 |
qemu_get_be32s(f, &s->tm4[i].oldclock); |
|
| 419 |
qemu_get_be32s(f, &s->tm4[i].clock); |
|
| 420 |
qemu_get_be64s(f, &s->tm4[i].lastload); |
|
| 421 |
qemu_get_be32s(f, &s->tm4[i].freq); |
|
| 422 |
qemu_get_be32s(f, &s->tm4[i].control); |
|
| 423 |
pxa2xx_timer_update4(s, now, i); |
|
| 424 |
} |
|
| 425 |
|
|
| 426 |
qemu_get_be32s(f, &s->events); |
|
| 427 |
qemu_get_be32s(f, &s->irq_enabled); |
|
| 428 |
qemu_get_be32s(f, &s->reset3); |
|
| 429 |
qemu_get_be32s(f, &s->snapshot); |
|
| 430 |
|
|
| 431 |
return 0; |
|
| 432 |
} |
|
| 433 |
|
|
| 367 | 434 |
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, |
| 368 | 435 |
qemu_irq *irqs) |
| 369 | 436 |
{
|
| ... | ... | |
| 392 | 459 |
iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn, |
| 393 | 460 |
pxa2xx_timer_writefn, s); |
| 394 | 461 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
| 462 |
|
|
| 463 |
register_savevm("pxa2xx_timer", 0, 0,
|
|
| 464 |
pxa2xx_timer_save, pxa2xx_timer_load, s); |
|
| 465 |
|
|
| 395 | 466 |
return s; |
| 396 | 467 |
} |
| 397 | 468 |
|
| b/hw/spitz.c | ||
|---|---|---|
| 109 | 109 |
} |
| 110 | 110 |
} |
| 111 | 111 |
|
| 112 |
static void sl_save(QEMUFile *f, void *opaque) |
|
| 113 |
{
|
|
| 114 |
struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
|
| 115 |
|
|
| 116 |
qemu_put_8s(f, &s->ctl); |
|
| 117 |
ecc_put(f, &s->ecc); |
|
| 118 |
} |
|
| 119 |
|
|
| 120 |
static int sl_load(QEMUFile *f, void *opaque, int version_id) |
|
Also available in: Unified diff