root / target-mips / exec.h @ aaa9128a
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#if !defined(__QEMU_MIPS_EXEC_H__)
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#define __QEMU_MIPS_EXEC_H__
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//#define DEBUG_OP
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#include "config.h" |
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#include "mips-defs.h" |
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#include "dyngen-exec.h" |
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#include "cpu-defs.h" |
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register struct CPUMIPSState *env asm(AREG0); |
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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#define T0 (env->t0)
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#define T1 (env->t1)
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#else
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register target_ulong T0 asm(AREG1); |
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register target_ulong T1 asm(AREG2); |
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#endif
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#if defined (USE_HOST_FLOAT_REGS)
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#error "implement me." |
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#else
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#define FDT0 (env->fpu->ft0.fd)
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#define FDT1 (env->fpu->ft1.fd)
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#define FDT2 (env->fpu->ft2.fd)
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#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
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#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
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#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
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#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
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#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
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#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
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#define DT0 (env->fpu->ft0.d)
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#define DT1 (env->fpu->ft1.d)
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#define DT2 (env->fpu->ft2.d)
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#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
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#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
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#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
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#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
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#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
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#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
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#endif
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#include "cpu.h" |
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#include "exec-all.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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#if defined(TARGET_MIPS64)
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void do_dsll (void); |
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void do_dsll32 (void); |
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void do_dsra (void); |
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void do_dsra32 (void); |
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void do_dsrl (void); |
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void do_dsrl32 (void); |
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void do_drotr (void); |
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void do_drotr32 (void); |
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void do_dsllv (void); |
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void do_dsrav (void); |
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void do_dsrlv (void); |
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void do_drotrv (void); |
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void do_dclo (void); |
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void do_dclz (void); |
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#endif
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#endif
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#if HOST_LONG_BITS < 64 |
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void do_div (void); |
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#endif
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void do_mult (void); |
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void do_multu (void); |
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void do_madd (void); |
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void do_maddu (void); |
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void do_msub (void); |
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void do_msubu (void); |
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void do_muls (void); |
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void do_mulsu (void); |
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void do_macc (void); |
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void do_macchi (void); |
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void do_maccu (void); |
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void do_macchiu (void); |
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void do_msac (void); |
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void do_msachi (void); |
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void do_msacu (void); |
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void do_msachiu (void); |
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void do_mulhi (void); |
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void do_mulhiu (void); |
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void do_mulshi (void); |
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void do_mulshiu (void); |
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#endif
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#if defined(TARGET_MIPS64)
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void do_ddiv (void); |
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void do_ddivu (void); |
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#endif
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#endif
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void do_mfc0_random(void); |
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void do_mfc0_count(void); |
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void do_mtc0_entryhi(uint32_t in);
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void do_mtc0_status_debug(uint32_t old, uint32_t val);
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void do_mtc0_status_irqraise_debug(void); |
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void dump_fpu(CPUState *env);
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void fpu_dump_state(CPUState *env, FILE *f,
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
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int flags);
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void dump_sc (void); |
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void do_pmon (int function); |
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void dump_sc (void); |
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu); |
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void do_interrupt (CPUState *env);
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void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
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void cpu_loop_exit(void); |
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void do_raise_exception_err (uint32_t exception, int error_code); |
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void do_raise_exception (uint32_t exception);
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void do_raise_exception_direct_err (uint32_t exception, int error_code); |
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void do_raise_exception_direct (uint32_t exception);
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void cpu_dump_state(CPUState *env, FILE *f,
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int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
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int flags);
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void cpu_mips_irqctrl_init (void); |
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uint32_t cpu_mips_get_random (CPUState *env); |
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uint32_t cpu_mips_get_count (CPUState *env); |
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void cpu_mips_store_count (CPUState *env, uint32_t value);
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void cpu_mips_store_compare (CPUState *env, uint32_t value);
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void cpu_mips_start_count(CPUState *env);
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void cpu_mips_stop_count(CPUState *env);
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void cpu_mips_update_irq (CPUState *env);
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void cpu_mips_clock_init (CPUState *env);
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void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
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void do_cfc1 (int reg); |
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void do_ctc1 (int reg); |
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#define FOP_PROTO(op) \
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void do_float_ ## op ## _s(void); \ |
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void do_float_ ## op ## _d(void); |
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FOP_PROTO(roundl) |
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FOP_PROTO(roundw) |
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FOP_PROTO(truncl) |
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FOP_PROTO(truncw) |
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FOP_PROTO(ceill) |
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FOP_PROTO(ceilw) |
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FOP_PROTO(floorl) |
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FOP_PROTO(floorw) |
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FOP_PROTO(rsqrt) |
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FOP_PROTO(recip) |
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#undef FOP_PROTO
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#define FOP_PROTO(op) \
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void do_float_ ## op ## _s(void); \ |
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void do_float_ ## op ## _d(void); \ |
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void do_float_ ## op ## _ps(void); |
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FOP_PROTO(add) |
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FOP_PROTO(sub) |
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FOP_PROTO(mul) |
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FOP_PROTO(div) |
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FOP_PROTO(recip1) |
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FOP_PROTO(recip2) |
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FOP_PROTO(rsqrt1) |
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FOP_PROTO(rsqrt2) |
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#undef FOP_PROTO
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void do_float_cvtd_s(void); |
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void do_float_cvtd_w(void); |
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void do_float_cvtd_l(void); |
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void do_float_cvtl_d(void); |
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void do_float_cvtl_s(void); |
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void do_float_cvtps_pw(void); |
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void do_float_cvtpw_ps(void); |
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void do_float_cvts_d(void); |
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void do_float_cvts_w(void); |
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void do_float_cvts_l(void); |
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void do_float_cvts_pl(void); |
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void do_float_cvts_pu(void); |
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void do_float_cvtw_s(void); |
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void do_float_cvtw_d(void); |
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void do_float_addr_ps(void); |
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void do_float_mulr_ps(void); |
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#define FOP_PROTO(op) \
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void do_cmp_d_ ## op(long cc); \ |
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void do_cmpabs_d_ ## op(long cc); \ |
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void do_cmp_s_ ## op(long cc); \ |
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void do_cmpabs_s_ ## op(long cc); \ |
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void do_cmp_ps_ ## op(long cc); \ |
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void do_cmpabs_ps_ ## op(long cc); |
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FOP_PROTO(f) |
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FOP_PROTO(un) |
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FOP_PROTO(eq) |
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FOP_PROTO(ueq) |
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FOP_PROTO(olt) |
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FOP_PROTO(ult) |
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FOP_PROTO(ole) |
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FOP_PROTO(ule) |
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FOP_PROTO(sf) |
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FOP_PROTO(ngle) |
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FOP_PROTO(seq) |
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FOP_PROTO(ngl) |
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FOP_PROTO(lt) |
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FOP_PROTO(nge) |
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FOP_PROTO(le) |
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FOP_PROTO(ngt) |
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#undef FOP_PROTO
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static always_inline void env_to_regs(void) |
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{
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} |
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static always_inline void regs_to_env(void) |
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{
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} |
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static always_inline int cpu_halted(CPUState *env) |
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{
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if (!env->halted)
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return 0; |
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if (env->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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env->halted = 0;
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return 0; |
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} |
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return EXCP_HALTED;
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} |
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static always_inline void compute_hflags(CPUState *env) |
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{
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); |
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if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
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} |
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#if defined(TARGET_MIPS64)
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if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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(env->CP0_Status & (1 << CP0St_PX)) ||
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(env->CP0_Status & (1 << CP0St_UX)))
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env->hflags |= MIPS_HFLAG_64; |
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#endif
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if ((env->CP0_Status & (1 << CP0St_CU0)) || |
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!(env->hflags & MIPS_HFLAG_KSU)) |
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env->hflags |= MIPS_HFLAG_CP0; |
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if (env->CP0_Status & (1 << CP0St_CU1)) |
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env->hflags |= MIPS_HFLAG_FPU; |
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if (env->CP0_Status & (1 << CP0St_FR)) |
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env->hflags |= MIPS_HFLAG_F64; |
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if (env->insn_flags & ISA_MIPS32R2) {
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if (env->fpu->fcr0 & (1 << FCR0_F64)) |
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env->hflags |= MIPS_HFLAG_COP1X; |
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} else if (env->insn_flags & ISA_MIPS32) { |
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if (env->hflags & MIPS_HFLAG_64)
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env->hflags |= MIPS_HFLAG_COP1X; |
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} else if (env->insn_flags & ISA_MIPS4) { |
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/* All supported MIPS IV CPUs use the XX (CU3) to enable
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and disable the MIPS IV extensions to the MIPS III ISA.
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Some other MIPS IV CPUs ignore the bit, so the check here
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would be too restrictive for them. */
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if (env->CP0_Status & (1 << CP0St_CU3)) |
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env->hflags |= MIPS_HFLAG_COP1X; |
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} |
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} |
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#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |