Revision ab3b491f target-sparc/helper.c
b/target-sparc/helper.c | ||
---|---|---|
16 | 16 |
* You should have received a copy of the GNU Lesser General Public |
17 | 17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | 18 |
*/ |
19 |
#include <stdarg.h> |
|
20 |
#include <stdlib.h> |
|
21 |
#include <stdio.h> |
|
22 |
#include <string.h> |
|
23 |
#include <inttypes.h> |
|
24 | 19 |
|
25 | 20 |
#include "cpu.h" |
26 |
#include "qemu-common.h" |
|
27 | 21 |
|
28 | 22 |
//#define DEBUG_MMU |
29 |
//#define DEBUG_FEATURES |
|
30 | 23 |
|
31 | 24 |
#ifdef DEBUG_MMU |
32 | 25 |
#define DPRINTF_MMU(fmt, ...) \ |
... | ... | |
35 | 28 |
#define DPRINTF_MMU(fmt, ...) do {} while (0) |
36 | 29 |
#endif |
37 | 30 |
|
38 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
|
39 |
|
|
40 | 31 |
/* Sparc MMU emulation */ |
41 | 32 |
|
42 | 33 |
#if defined(CONFIG_USER_ONLY) |
... | ... | |
358 | 349 |
} |
359 | 350 |
} |
360 | 351 |
|
361 |
#if !defined(CONFIG_USER_ONLY) |
|
362 |
|
|
363 | 352 |
/* Gdb expects all registers windows to be flushed in ram. This function handles |
364 | 353 |
* reads (and only reads) in stack frames as if windows were flushed. We assume |
365 | 354 |
* that the sparc ABI is followed. |
... | ... | |
440 | 429 |
return cpu_memory_rw_debug(env, addr, buf, len, is_write); |
441 | 430 |
} |
442 | 431 |
|
443 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
|
444 |
|
|
445 | 432 |
#else /* !TARGET_SPARC64 */ |
446 | 433 |
|
447 | 434 |
// 41 bit physical address space |
... | ... | |
839 | 826 |
} |
840 | 827 |
|
841 | 828 |
#endif /* TARGET_SPARC64 */ |
842 |
#endif /* !CONFIG_USER_ONLY */ |
|
843 |
|
|
844 | 829 |
|
845 |
#if !defined(CONFIG_USER_ONLY) |
|
846 | 830 |
static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys, |
847 | 831 |
target_ulong addr, int rw, int mmu_idx) |
848 | 832 |
{ |
... | ... | |
882 | 866 |
return phys_addr; |
883 | 867 |
} |
884 | 868 |
#endif |
885 |
|
|
886 |
#ifdef TARGET_SPARC64 |
|
887 |
#ifdef DEBUG_PCALL |
|
888 |
static const char * const excp_names[0x80] = { |
|
889 |
[TT_TFAULT] = "Instruction Access Fault", |
|
890 |
[TT_TMISS] = "Instruction Access MMU Miss", |
|
891 |
[TT_CODE_ACCESS] = "Instruction Access Error", |
|
892 |
[TT_ILL_INSN] = "Illegal Instruction", |
|
893 |
[TT_PRIV_INSN] = "Privileged Instruction", |
|
894 |
[TT_NFPU_INSN] = "FPU Disabled", |
|
895 |
[TT_FP_EXCP] = "FPU Exception", |
|
896 |
[TT_TOVF] = "Tag Overflow", |
|
897 |
[TT_CLRWIN] = "Clean Windows", |
|
898 |
[TT_DIV_ZERO] = "Division By Zero", |
|
899 |
[TT_DFAULT] = "Data Access Fault", |
|
900 |
[TT_DMISS] = "Data Access MMU Miss", |
|
901 |
[TT_DATA_ACCESS] = "Data Access Error", |
|
902 |
[TT_DPROT] = "Data Protection Error", |
|
903 |
[TT_UNALIGNED] = "Unaligned Memory Access", |
|
904 |
[TT_PRIV_ACT] = "Privileged Action", |
|
905 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
|
906 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
|
907 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
|
908 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
|
909 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
|
910 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
|
911 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
|
912 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
|
913 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
|
914 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
|
915 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
|
916 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
|
917 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
|
918 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
|
919 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
|
920 |
}; |
|
921 |
#endif |
|
922 |
|
|
923 |
void do_interrupt(CPUState *env) |
|
924 |
{ |
|
925 |
int intno = env->exception_index; |
|
926 |
trap_state *tsptr; |
|
927 |
|
|
928 |
#ifdef DEBUG_PCALL |
|
929 |
if (qemu_loglevel_mask(CPU_LOG_INT)) { |
|
930 |
static int count; |
|
931 |
const char *name; |
|
932 |
|
|
933 |
if (intno < 0 || intno >= 0x180) { |
|
934 |
name = "Unknown"; |
|
935 |
} else if (intno >= 0x100) { |
|
936 |
name = "Trap Instruction"; |
|
937 |
} else if (intno >= 0xc0) { |
|
938 |
name = "Window Fill"; |
|
939 |
} else if (intno >= 0x80) { |
|
940 |
name = "Window Spill"; |
|
941 |
} else { |
|
942 |
name = excp_names[intno]; |
|
943 |
if (!name) { |
|
944 |
name = "Unknown"; |
|
945 |
} |
|
946 |
} |
|
947 |
|
|
948 |
qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
|
949 |
" SP=%016" PRIx64 "\n", |
|
950 |
count, name, intno, |
|
951 |
env->pc, |
|
952 |
env->npc, env->regwptr[6]); |
|
953 |
log_cpu_state(env, 0); |
|
954 |
#if 0 |
|
955 |
{ |
|
956 |
int i; |
|
957 |
uint8_t *ptr; |
|
958 |
|
|
959 |
qemu_log(" code="); |
|
960 |
ptr = (uint8_t *)env->pc; |
|
961 |
for (i = 0; i < 16; i++) { |
|
962 |
qemu_log(" %02x", ldub(ptr + i)); |
|
963 |
} |
|
964 |
qemu_log("\n"); |
|
965 |
} |
|
966 |
#endif |
|
967 |
count++; |
|
968 |
} |
|
969 |
#endif |
|
970 |
#if !defined(CONFIG_USER_ONLY) |
|
971 |
if (env->tl >= env->maxtl) { |
|
972 |
cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," |
|
973 |
" Error state", env->exception_index, env->tl, env->maxtl); |
|
974 |
return; |
|
975 |
} |
|
976 |
#endif |
|
977 |
if (env->tl < env->maxtl - 1) { |
|
978 |
env->tl++; |
|
979 |
} else { |
|
980 |
env->pstate |= PS_RED; |
|
981 |
if (env->tl < env->maxtl) { |
|
982 |
env->tl++; |
|
983 |
} |
|
984 |
} |
|
985 |
tsptr = cpu_tsptr(env); |
|
986 |
|
|
987 |
tsptr->tstate = (cpu_get_ccr(env) << 32) | |
|
988 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
|
989 |
cpu_get_cwp64(env); |
|
990 |
tsptr->tpc = env->pc; |
|
991 |
tsptr->tnpc = env->npc; |
|
992 |
tsptr->tt = intno; |
|
993 |
|
|
994 |
switch (intno) { |
|
995 |
case TT_IVEC: |
|
996 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); |
|
997 |
break; |
|
998 |
case TT_TFAULT: |
|
999 |
case TT_DFAULT: |
|
1000 |
case TT_TMISS ... TT_TMISS + 3: |
|
1001 |
case TT_DMISS ... TT_DMISS + 3: |
|
1002 |
case TT_DPROT ... TT_DPROT + 3: |
|
1003 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); |
|
1004 |
break; |
|
1005 |
default: |
|
1006 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); |
|
1007 |
break; |
|
1008 |
} |
|
1009 |
|
|
1010 |
if (intno == TT_CLRWIN) { |
|
1011 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); |
|
1012 |
} else if ((intno & 0x1c0) == TT_SPILL) { |
|
1013 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); |
|
1014 |
} else if ((intno & 0x1c0) == TT_FILL) { |
|
1015 |
cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); |
|
1016 |
} |
|
1017 |
env->tbr &= ~0x7fffULL; |
|
1018 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
|
1019 |
env->pc = env->tbr; |
|
1020 |
env->npc = env->pc + 4; |
|
1021 |
env->exception_index = -1; |
|
1022 |
} |
|
1023 |
#else |
|
1024 |
#ifdef DEBUG_PCALL |
|
1025 |
static const char * const excp_names[0x80] = { |
|
1026 |
[TT_TFAULT] = "Instruction Access Fault", |
|
1027 |
[TT_ILL_INSN] = "Illegal Instruction", |
|
1028 |
[TT_PRIV_INSN] = "Privileged Instruction", |
|
1029 |
[TT_NFPU_INSN] = "FPU Disabled", |
|
1030 |
[TT_WIN_OVF] = "Window Overflow", |
|
1031 |
[TT_WIN_UNF] = "Window Underflow", |
|
1032 |
[TT_UNALIGNED] = "Unaligned Memory Access", |
|
1033 |
[TT_FP_EXCP] = "FPU Exception", |
|
1034 |
[TT_DFAULT] = "Data Access Fault", |
|
1035 |
[TT_TOVF] = "Tag Overflow", |
|
1036 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
|
1037 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
|
1038 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
|
1039 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
|
1040 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
|
1041 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
|
1042 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
|
1043 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
|
1044 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
|
1045 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
|
1046 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
|
1047 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
|
1048 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
|
1049 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
|
1050 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
|
1051 |
[TT_TOVF] = "Tag Overflow", |
|
1052 |
[TT_CODE_ACCESS] = "Instruction Access Error", |
|
1053 |
[TT_DATA_ACCESS] = "Data Access Error", |
|
1054 |
[TT_DIV_ZERO] = "Division By Zero", |
|
1055 |
[TT_NCP_INSN] = "Coprocessor Disabled", |
|
1056 |
}; |
|
1057 |
#endif |
|
1058 |
|
|
1059 |
void do_interrupt(CPUState *env) |
|
1060 |
{ |
|
1061 |
int cwp, intno = env->exception_index; |
|
1062 |
|
|
1063 |
#ifdef DEBUG_PCALL |
|
1064 |
if (qemu_loglevel_mask(CPU_LOG_INT)) { |
|
1065 |
static int count; |
|
1066 |
const char *name; |
|
1067 |
|
|
1068 |
if (intno < 0 || intno >= 0x100) { |
|
1069 |
name = "Unknown"; |
|
1070 |
} else if (intno >= 0x80) { |
|
1071 |
name = "Trap Instruction"; |
|
1072 |
} else { |
|
1073 |
name = excp_names[intno]; |
|
1074 |
if (!name) { |
|
1075 |
name = "Unknown"; |
|
1076 |
} |
|
1077 |
} |
|
1078 |
|
|
1079 |
qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", |
|
1080 |
count, name, intno, |
|
1081 |
env->pc, |
|
1082 |
env->npc, env->regwptr[6]); |
|
1083 |
log_cpu_state(env, 0); |
|
1084 |
#if 0 |
|
1085 |
{ |
|
1086 |
int i; |
|
1087 |
uint8_t *ptr; |
|
1088 |
|
|
1089 |
qemu_log(" code="); |
|
1090 |
ptr = (uint8_t *)env->pc; |
|
1091 |
for (i = 0; i < 16; i++) { |
|
1092 |
qemu_log(" %02x", ldub(ptr + i)); |
|
1093 |
} |
|
1094 |
qemu_log("\n"); |
|
1095 |
} |
|
1096 |
#endif |
|
1097 |
count++; |
|
1098 |
} |
|
1099 |
#endif |
|
1100 |
#if !defined(CONFIG_USER_ONLY) |
|
1101 |
if (env->psret == 0) { |
|
1102 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", |
|
1103 |
env->exception_index); |
|
1104 |
return; |
|
1105 |
} |
|
1106 |
#endif |
|
1107 |
env->psret = 0; |
|
1108 |
cwp = cpu_cwp_dec(env, env->cwp - 1); |
|
1109 |
cpu_set_cwp(env, cwp); |
|
1110 |
env->regwptr[9] = env->pc; |
|
1111 |
env->regwptr[10] = env->npc; |
|
1112 |
env->psrps = env->psrs; |
|
1113 |
env->psrs = 1; |
|
1114 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); |
|
1115 |
env->pc = env->tbr; |
|
1116 |
env->npc = env->pc + 4; |
|
1117 |
env->exception_index = -1; |
|
1118 |
|
|
1119 |
#if !defined(CONFIG_USER_ONLY) |
|
1120 |
/* IRQ acknowledgment */ |
|
1121 |
if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { |
|
1122 |
env->qemu_irq_ack(env->irq_manager, intno); |
|
1123 |
} |
|
1124 |
#endif |
|
1125 |
} |
|
1126 |
#endif |
|
1127 |
|
|
1128 |
void cpu_reset(CPUSPARCState *env) |
|
1129 |
{ |
|
1130 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
|
1131 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); |
|
1132 |
log_cpu_state(env, 0); |
|
1133 |
} |
|
1134 |
|
|
1135 |
tlb_flush(env, 1); |
|
1136 |
env->cwp = 0; |
|
1137 |
#ifndef TARGET_SPARC64 |
|
1138 |
env->wim = 1; |
|
1139 |
#endif |
|
1140 |
env->regwptr = env->regbase + (env->cwp * 16); |
|
1141 |
CC_OP = CC_OP_FLAGS; |
|
1142 |
#if defined(CONFIG_USER_ONLY) |
|
1143 |
#ifdef TARGET_SPARC64 |
|
1144 |
env->cleanwin = env->nwindows - 2; |
|
1145 |
env->cansave = env->nwindows - 2; |
|
1146 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
|
1147 |
env->asi = 0x82; /* Primary no-fault */ |
|
1148 |
#endif |
|
1149 |
#else |
|
1150 |
#if !defined(TARGET_SPARC64) |
|
1151 |
env->psret = 0; |
|
1152 |
env->psrs = 1; |
|
1153 |
env->psrps = 1; |
|
1154 |
#endif |
|
1155 |
#ifdef TARGET_SPARC64 |
|
1156 |
env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG; |
|
1157 |
env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0; |
|
1158 |
env->tl = env->maxtl; |
|
1159 |
cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
|
1160 |
env->lsu = 0; |
|
1161 |
#else |
|
1162 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
|
1163 |
env->mmuregs[0] |= env->def->mmu_bm; |
|
1164 |
#endif |
|
1165 |
env->pc = 0; |
|
1166 |
env->npc = env->pc + 4; |
|
1167 |
#endif |
|
1168 |
env->cache_control = 0; |
|
1169 |
} |
|
1170 |
|
|
1171 |
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
|
1172 |
{ |
|
1173 |
sparc_def_t def1, *def = &def1; |
|
1174 |
|
|
1175 |
if (cpu_sparc_find_by_name(def, cpu_model) < 0) { |
|
1176 |
return -1; |
|
1177 |
} |
|
1178 |
|
|
1179 |
env->def = g_malloc0(sizeof(*def)); |
|
1180 |
memcpy(env->def, def, sizeof(*def)); |
|
1181 |
#if defined(CONFIG_USER_ONLY) |
|
1182 |
if ((env->def->features & CPU_FEATURE_FLOAT)) { |
|
1183 |
env->def->features |= CPU_FEATURE_FLOAT128; |
|
1184 |
} |
|
1185 |
#endif |
|
1186 |
env->cpu_model_str = cpu_model; |
|
1187 |
env->version = def->iu_version; |
|
1188 |
env->fsr = def->fpu_version; |
|
1189 |
env->nwindows = def->nwindows; |
|
1190 |
#if !defined(TARGET_SPARC64) |
|
1191 |
env->mmuregs[0] |= def->mmu_version; |
|
1192 |
cpu_sparc_set_id(env, 0); |
|
1193 |
env->mxccregs[7] |= def->mxcc_version; |
|
1194 |
#else |
|
1195 |
env->mmu_version = def->mmu_version; |
|
1196 |
env->maxtl = def->maxtl; |
|
1197 |
env->version |= def->maxtl << 8; |
|
1198 |
env->version |= def->nwindows - 1; |
|
1199 |
#endif |
|
1200 |
return 0; |
|
1201 |
} |
|
1202 |
|
|
1203 |
static void cpu_sparc_close(CPUSPARCState *env) |
|
1204 |
{ |
|
1205 |
free(env->def); |
|
1206 |
free(env); |
|
1207 |
} |
|
1208 |
|
|
1209 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
|
1210 |
{ |
|
1211 |
CPUSPARCState *env; |
|
1212 |
|
|
1213 |
env = g_malloc0(sizeof(CPUSPARCState)); |
|
1214 |
cpu_exec_init(env); |
|
1215 |
|
|
1216 |
gen_intermediate_code_init(env); |
|
1217 |
|
|
1218 |
if (cpu_sparc_register(env, cpu_model) < 0) { |
|
1219 |
cpu_sparc_close(env); |
|
1220 |
return NULL; |
|
1221 |
} |
|
1222 |
qemu_init_vcpu(env); |
|
1223 |
|
|
1224 |
return env; |
|
1225 |
} |
|
1226 |
|
|
1227 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
|
1228 |
{ |
|
1229 |
#if !defined(TARGET_SPARC64) |
|
1230 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
|
1231 |
#endif |
|
1232 |
} |
|
1233 |
|
|
1234 |
static const sparc_def_t sparc_defs[] = { |
|
1235 |
#ifdef TARGET_SPARC64 |
|
1236 |
{ |
|
1237 |
.name = "Fujitsu Sparc64", |
|
1238 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
|
1239 |
.fpu_version = 0x00000000, |
|
1240 |
.mmu_version = mmu_us_12, |
|
1241 |
.nwindows = 4, |
|
1242 |
.maxtl = 4, |
|
1243 |
.features = CPU_DEFAULT_FEATURES, |
|
1244 |
}, |
|
1245 |
{ |
|
1246 |
.name = "Fujitsu Sparc64 III", |
|
1247 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
|
1248 |
.fpu_version = 0x00000000, |
|
1249 |
.mmu_version = mmu_us_12, |
|
1250 |
.nwindows = 5, |
|
1251 |
.maxtl = 4, |
|
1252 |
.features = CPU_DEFAULT_FEATURES, |
|
1253 |
}, |
|
1254 |
{ |
|
1255 |
.name = "Fujitsu Sparc64 IV", |
|
1256 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
|
1257 |
.fpu_version = 0x00000000, |
|
1258 |
.mmu_version = mmu_us_12, |
|
1259 |
.nwindows = 8, |
|
1260 |
.maxtl = 5, |
|
1261 |
.features = CPU_DEFAULT_FEATURES, |
|
1262 |
}, |
|
1263 |
{ |
|
1264 |
.name = "Fujitsu Sparc64 V", |
|
1265 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
|
1266 |
.fpu_version = 0x00000000, |
|
1267 |
.mmu_version = mmu_us_12, |
|
1268 |
.nwindows = 8, |
|
1269 |
.maxtl = 5, |
|
1270 |
.features = CPU_DEFAULT_FEATURES, |
|
1271 |
}, |
|
1272 |
{ |
|
1273 |
.name = "TI UltraSparc I", |
|
1274 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
|
1275 |
.fpu_version = 0x00000000, |
|
1276 |
.mmu_version = mmu_us_12, |
|
1277 |
.nwindows = 8, |
|
1278 |
.maxtl = 5, |
|
1279 |
.features = CPU_DEFAULT_FEATURES, |
|
1280 |
}, |
|
1281 |
{ |
|
1282 |
.name = "TI UltraSparc II", |
|
1283 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
|
1284 |
.fpu_version = 0x00000000, |
|
1285 |
.mmu_version = mmu_us_12, |
|
1286 |
.nwindows = 8, |
|
1287 |
.maxtl = 5, |
|
1288 |
.features = CPU_DEFAULT_FEATURES, |
|
1289 |
}, |
|
1290 |
{ |
|
1291 |
.name = "TI UltraSparc IIi", |
|
1292 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
|
1293 |
.fpu_version = 0x00000000, |
|
1294 |
.mmu_version = mmu_us_12, |
|
1295 |
.nwindows = 8, |
|
1296 |
.maxtl = 5, |
|
1297 |
.features = CPU_DEFAULT_FEATURES, |
|
1298 |
}, |
|
1299 |
{ |
|
1300 |
.name = "TI UltraSparc IIe", |
|
1301 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
|
1302 |
.fpu_version = 0x00000000, |
|
1303 |
.mmu_version = mmu_us_12, |
|
1304 |
.nwindows = 8, |
|
1305 |
.maxtl = 5, |
|
1306 |
.features = CPU_DEFAULT_FEATURES, |
|
1307 |
}, |
|
1308 |
{ |
|
1309 |
.name = "Sun UltraSparc III", |
|
1310 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
|
1311 |
.fpu_version = 0x00000000, |
|
1312 |
.mmu_version = mmu_us_12, |
|
1313 |
.nwindows = 8, |
|
1314 |
.maxtl = 5, |
|
1315 |
.features = CPU_DEFAULT_FEATURES, |
|
1316 |
}, |
|
1317 |
{ |
|
1318 |
.name = "Sun UltraSparc III Cu", |
|
1319 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
|
1320 |
.fpu_version = 0x00000000, |
|
1321 |
.mmu_version = mmu_us_3, |
|
1322 |
.nwindows = 8, |
|
1323 |
.maxtl = 5, |
|
1324 |
.features = CPU_DEFAULT_FEATURES, |
|
1325 |
}, |
|
1326 |
{ |
|
1327 |
.name = "Sun UltraSparc IIIi", |
|
1328 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
|
1329 |
.fpu_version = 0x00000000, |
|
1330 |
.mmu_version = mmu_us_12, |
|
1331 |
.nwindows = 8, |
|
1332 |
.maxtl = 5, |
|
1333 |
.features = CPU_DEFAULT_FEATURES, |
|
1334 |
}, |
|
1335 |
{ |
|
1336 |
.name = "Sun UltraSparc IV", |
|
1337 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
|
1338 |
.fpu_version = 0x00000000, |
|
1339 |
.mmu_version = mmu_us_4, |
|
1340 |
.nwindows = 8, |
|
1341 |
.maxtl = 5, |
|
1342 |
.features = CPU_DEFAULT_FEATURES, |
|
1343 |
}, |
|
1344 |
{ |
|
1345 |
.name = "Sun UltraSparc IV+", |
|
1346 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
|
1347 |
.fpu_version = 0x00000000, |
|
1348 |
.mmu_version = mmu_us_12, |
|
1349 |
.nwindows = 8, |
|
1350 |
.maxtl = 5, |
|
1351 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
|
1352 |
}, |
|
1353 |
{ |
|
1354 |
.name = "Sun UltraSparc IIIi+", |
|
1355 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
|
1356 |
.fpu_version = 0x00000000, |
|
1357 |
.mmu_version = mmu_us_3, |
|
1358 |
.nwindows = 8, |
|
1359 |
.maxtl = 5, |
|
1360 |
.features = CPU_DEFAULT_FEATURES, |
|
1361 |
}, |
|
1362 |
{ |
|
1363 |
.name = "Sun UltraSparc T1", |
|
1364 |
/* defined in sparc_ifu_fdp.v and ctu.h */ |
|
1365 |
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
|
1366 |
.fpu_version = 0x00000000, |
|
1367 |
.mmu_version = mmu_sun4v, |
|
1368 |
.nwindows = 8, |
|
1369 |
.maxtl = 6, |
|
1370 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
|
1371 |
| CPU_FEATURE_GL, |
|
1372 |
}, |
|
1373 |
{ |
|
1374 |
.name = "Sun UltraSparc T2", |
|
1375 |
/* defined in tlu_asi_ctl.v and n2_revid_cust.v */ |
|
1376 |
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
|
1377 |
.fpu_version = 0x00000000, |
|
1378 |
.mmu_version = mmu_sun4v, |
|
1379 |
.nwindows = 8, |
|
1380 |
.maxtl = 6, |
|
1381 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
|
1382 |
| CPU_FEATURE_GL, |
|
1383 |
}, |
|
1384 |
{ |
|
1385 |
.name = "NEC UltraSparc I", |
|
1386 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
|
1387 |
.fpu_version = 0x00000000, |
|
1388 |
.mmu_version = mmu_us_12, |
|
1389 |
.nwindows = 8, |
|
1390 |
.maxtl = 5, |
|
1391 |
.features = CPU_DEFAULT_FEATURES, |
|
1392 |
}, |
|
1393 |
#else |
|
1394 |
{ |
|
1395 |
.name = "Fujitsu MB86900", |
|
1396 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
|
1397 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1398 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
|
1399 |
.mmu_bm = 0x00004000, |
|
1400 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1401 |
.mmu_cxr_mask = 0x0000003f, |
|
1402 |
.mmu_sfsr_mask = 0xffffffff, |
|
1403 |
.mmu_trcr_mask = 0xffffffff, |
|
1404 |
.nwindows = 7, |
|
1405 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
|
1406 |
}, |
|
1407 |
{ |
|
1408 |
.name = "Fujitsu MB86904", |
|
1409 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
|
1410 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1411 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
|
1412 |
.mmu_bm = 0x00004000, |
|
1413 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
1414 |
.mmu_cxr_mask = 0x000000ff, |
|
1415 |
.mmu_sfsr_mask = 0x00016fff, |
|
1416 |
.mmu_trcr_mask = 0x00ffffff, |
|
1417 |
.nwindows = 8, |
|
1418 |
.features = CPU_DEFAULT_FEATURES, |
|
1419 |
}, |
|
1420 |
{ |
|
1421 |
.name = "Fujitsu MB86907", |
|
1422 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
|
1423 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1424 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
|
1425 |
.mmu_bm = 0x00004000, |
|
1426 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1427 |
.mmu_cxr_mask = 0x000000ff, |
|
1428 |
.mmu_sfsr_mask = 0x00016fff, |
|
1429 |
.mmu_trcr_mask = 0xffffffff, |
|
1430 |
.nwindows = 8, |
|
1431 |
.features = CPU_DEFAULT_FEATURES, |
|
1432 |
}, |
|
1433 |
{ |
|
1434 |
.name = "LSI L64811", |
|
1435 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
|
1436 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
|
1437 |
.mmu_version = 0x10 << 24, |
|
1438 |
.mmu_bm = 0x00004000, |
|
1439 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1440 |
.mmu_cxr_mask = 0x0000003f, |
|
1441 |
.mmu_sfsr_mask = 0xffffffff, |
|
1442 |
.mmu_trcr_mask = 0xffffffff, |
|
1443 |
.nwindows = 8, |
|
1444 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
|
1445 |
CPU_FEATURE_FSMULD, |
|
1446 |
}, |
|
1447 |
{ |
|
1448 |
.name = "Cypress CY7C601", |
|
1449 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
|
1450 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
|
1451 |
.mmu_version = 0x10 << 24, |
|
1452 |
.mmu_bm = 0x00004000, |
|
1453 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1454 |
.mmu_cxr_mask = 0x0000003f, |
|
1455 |
.mmu_sfsr_mask = 0xffffffff, |
|
1456 |
.mmu_trcr_mask = 0xffffffff, |
|
1457 |
.nwindows = 8, |
|
1458 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
|
1459 |
CPU_FEATURE_FSMULD, |
|
1460 |
}, |
|
1461 |
{ |
|
1462 |
.name = "Cypress CY7C611", |
|
1463 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
|
1464 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
|
1465 |
.mmu_version = 0x10 << 24, |
|
1466 |
.mmu_bm = 0x00004000, |
|
1467 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1468 |
.mmu_cxr_mask = 0x0000003f, |
|
1469 |
.mmu_sfsr_mask = 0xffffffff, |
|
1470 |
.mmu_trcr_mask = 0xffffffff, |
|
1471 |
.nwindows = 8, |
|
1472 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
|
1473 |
CPU_FEATURE_FSMULD, |
|
1474 |
}, |
|
1475 |
{ |
|
1476 |
.name = "TI MicroSparc I", |
|
1477 |
.iu_version = 0x41000000, |
|
1478 |
.fpu_version = 4 << 17, |
|
1479 |
.mmu_version = 0x41000000, |
|
1480 |
.mmu_bm = 0x00004000, |
|
1481 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1482 |
.mmu_cxr_mask = 0x0000003f, |
|
1483 |
.mmu_sfsr_mask = 0x00016fff, |
|
1484 |
.mmu_trcr_mask = 0x0000003f, |
|
1485 |
.nwindows = 7, |
|
1486 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
|
1487 |
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
|
1488 |
CPU_FEATURE_FMUL, |
|
1489 |
}, |
|
1490 |
{ |
|
1491 |
.name = "TI MicroSparc II", |
|
1492 |
.iu_version = 0x42000000, |
|
1493 |
.fpu_version = 4 << 17, |
|
1494 |
.mmu_version = 0x02000000, |
|
1495 |
.mmu_bm = 0x00004000, |
|
1496 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
1497 |
.mmu_cxr_mask = 0x000000ff, |
|
1498 |
.mmu_sfsr_mask = 0x00016fff, |
|
1499 |
.mmu_trcr_mask = 0x00ffffff, |
|
1500 |
.nwindows = 8, |
|
1501 |
.features = CPU_DEFAULT_FEATURES, |
|
1502 |
}, |
|
1503 |
{ |
|
1504 |
.name = "TI MicroSparc IIep", |
|
1505 |
.iu_version = 0x42000000, |
|
1506 |
.fpu_version = 4 << 17, |
|
1507 |
.mmu_version = 0x04000000, |
|
1508 |
.mmu_bm = 0x00004000, |
|
1509 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
1510 |
.mmu_cxr_mask = 0x000000ff, |
|
1511 |
.mmu_sfsr_mask = 0x00016bff, |
|
1512 |
.mmu_trcr_mask = 0x00ffffff, |
|
1513 |
.nwindows = 8, |
|
1514 |
.features = CPU_DEFAULT_FEATURES, |
|
1515 |
}, |
|
1516 |
{ |
|
1517 |
.name = "TI SuperSparc 40", /* STP1020NPGA */ |
|
1518 |
.iu_version = 0x41000000, /* SuperSPARC 2.x */ |
|
1519 |
.fpu_version = 0 << 17, |
|
1520 |
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ |
|
1521 |
.mmu_bm = 0x00002000, |
|
1522 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1523 |
.mmu_cxr_mask = 0x0000ffff, |
|
1524 |
.mmu_sfsr_mask = 0xffffffff, |
|
1525 |
.mmu_trcr_mask = 0xffffffff, |
|
1526 |
.nwindows = 8, |
|
1527 |
.features = CPU_DEFAULT_FEATURES, |
|
1528 |
}, |
|
1529 |
{ |
|
1530 |
.name = "TI SuperSparc 50", /* STP1020PGA */ |
|
1531 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
|
1532 |
.fpu_version = 0 << 17, |
|
1533 |
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
|
1534 |
.mmu_bm = 0x00002000, |
|
1535 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1536 |
.mmu_cxr_mask = 0x0000ffff, |
|
1537 |
.mmu_sfsr_mask = 0xffffffff, |
|
1538 |
.mmu_trcr_mask = 0xffffffff, |
|
1539 |
.nwindows = 8, |
|
1540 |
.features = CPU_DEFAULT_FEATURES, |
|
1541 |
}, |
|
1542 |
{ |
|
1543 |
.name = "TI SuperSparc 51", |
|
1544 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
|
1545 |
.fpu_version = 0 << 17, |
|
1546 |
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
|
1547 |
.mmu_bm = 0x00002000, |
|
1548 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1549 |
.mmu_cxr_mask = 0x0000ffff, |
|
1550 |
.mmu_sfsr_mask = 0xffffffff, |
|
1551 |
.mmu_trcr_mask = 0xffffffff, |
|
1552 |
.mxcc_version = 0x00000104, |
|
1553 |
.nwindows = 8, |
|
1554 |
.features = CPU_DEFAULT_FEATURES, |
|
1555 |
}, |
|
1556 |
{ |
|
1557 |
.name = "TI SuperSparc 60", /* STP1020APGA */ |
|
1558 |
.iu_version = 0x40000000, /* SuperSPARC 3.x */ |
|
1559 |
.fpu_version = 0 << 17, |
|
1560 |
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ |
|
1561 |
.mmu_bm = 0x00002000, |
|
1562 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1563 |
.mmu_cxr_mask = 0x0000ffff, |
|
1564 |
.mmu_sfsr_mask = 0xffffffff, |
|
1565 |
.mmu_trcr_mask = 0xffffffff, |
|
1566 |
.nwindows = 8, |
|
1567 |
.features = CPU_DEFAULT_FEATURES, |
|
1568 |
}, |
|
1569 |
{ |
|
1570 |
.name = "TI SuperSparc 61", |
|
1571 |
.iu_version = 0x44000000, /* SuperSPARC 3.x */ |
|
1572 |
.fpu_version = 0 << 17, |
|
1573 |
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ |
|
1574 |
.mmu_bm = 0x00002000, |
|
1575 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1576 |
.mmu_cxr_mask = 0x0000ffff, |
|
1577 |
.mmu_sfsr_mask = 0xffffffff, |
|
1578 |
.mmu_trcr_mask = 0xffffffff, |
|
1579 |
.mxcc_version = 0x00000104, |
|
1580 |
.nwindows = 8, |
|
1581 |
.features = CPU_DEFAULT_FEATURES, |
|
1582 |
}, |
|
1583 |
{ |
|
1584 |
.name = "TI SuperSparc II", |
|
1585 |
.iu_version = 0x40000000, /* SuperSPARC II 1.x */ |
|
1586 |
.fpu_version = 0 << 17, |
|
1587 |
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ |
|
1588 |
.mmu_bm = 0x00002000, |
|
1589 |
.mmu_ctpr_mask = 0xffffffc0, |
|
1590 |
.mmu_cxr_mask = 0x0000ffff, |
|
1591 |
.mmu_sfsr_mask = 0xffffffff, |
|
1592 |
.mmu_trcr_mask = 0xffffffff, |
|
1593 |
.mxcc_version = 0x00000104, |
|
1594 |
.nwindows = 8, |
|
1595 |
.features = CPU_DEFAULT_FEATURES, |
|
1596 |
}, |
|
1597 |
{ |
|
1598 |
.name = "Ross RT625", |
|
1599 |
.iu_version = 0x1e000000, |
|
1600 |
.fpu_version = 1 << 17, |
|
1601 |
.mmu_version = 0x1e000000, |
|
1602 |
.mmu_bm = 0x00004000, |
|
1603 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1604 |
.mmu_cxr_mask = 0x0000003f, |
|
1605 |
.mmu_sfsr_mask = 0xffffffff, |
|
1606 |
.mmu_trcr_mask = 0xffffffff, |
|
1607 |
.nwindows = 8, |
|
1608 |
.features = CPU_DEFAULT_FEATURES, |
|
1609 |
}, |
|
1610 |
{ |
|
1611 |
.name = "Ross RT620", |
|
1612 |
.iu_version = 0x1f000000, |
|
1613 |
.fpu_version = 1 << 17, |
|
1614 |
.mmu_version = 0x1f000000, |
|
1615 |
.mmu_bm = 0x00004000, |
|
1616 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1617 |
.mmu_cxr_mask = 0x0000003f, |
|
1618 |
.mmu_sfsr_mask = 0xffffffff, |
|
1619 |
.mmu_trcr_mask = 0xffffffff, |
|
1620 |
.nwindows = 8, |
|
1621 |
.features = CPU_DEFAULT_FEATURES, |
|
1622 |
}, |
|
1623 |
{ |
|
1624 |
.name = "BIT B5010", |
|
1625 |
.iu_version = 0x20000000, |
|
1626 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
|
1627 |
.mmu_version = 0x20000000, |
|
1628 |
.mmu_bm = 0x00004000, |
|
1629 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1630 |
.mmu_cxr_mask = 0x0000003f, |
|
1631 |
.mmu_sfsr_mask = 0xffffffff, |
|
1632 |
.mmu_trcr_mask = 0xffffffff, |
|
1633 |
.nwindows = 8, |
|
1634 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
|
1635 |
CPU_FEATURE_FSMULD, |
|
1636 |
}, |
|
1637 |
{ |
|
1638 |
.name = "Matsushita MN10501", |
|
1639 |
.iu_version = 0x50000000, |
|
1640 |
.fpu_version = 0 << 17, |
|
1641 |
.mmu_version = 0x50000000, |
|
1642 |
.mmu_bm = 0x00004000, |
|
1643 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1644 |
.mmu_cxr_mask = 0x0000003f, |
|
1645 |
.mmu_sfsr_mask = 0xffffffff, |
|
1646 |
.mmu_trcr_mask = 0xffffffff, |
|
1647 |
.nwindows = 8, |
|
1648 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
|
1649 |
CPU_FEATURE_FSMULD, |
|
1650 |
}, |
|
1651 |
{ |
|
1652 |
.name = "Weitek W8601", |
|
1653 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
|
1654 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
|
1655 |
.mmu_version = 0x10 << 24, |
|
1656 |
.mmu_bm = 0x00004000, |
|
1657 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1658 |
.mmu_cxr_mask = 0x0000003f, |
|
1659 |
.mmu_sfsr_mask = 0xffffffff, |
|
1660 |
.mmu_trcr_mask = 0xffffffff, |
|
1661 |
.nwindows = 8, |
|
1662 |
.features = CPU_DEFAULT_FEATURES, |
|
1663 |
}, |
|
1664 |
{ |
|
1665 |
.name = "LEON2", |
|
1666 |
.iu_version = 0xf2000000, |
|
1667 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1668 |
.mmu_version = 0xf2000000, |
|
1669 |
.mmu_bm = 0x00004000, |
|
1670 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1671 |
.mmu_cxr_mask = 0x0000003f, |
|
1672 |
.mmu_sfsr_mask = 0xffffffff, |
|
1673 |
.mmu_trcr_mask = 0xffffffff, |
|
1674 |
.nwindows = 8, |
|
1675 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, |
|
1676 |
}, |
|
1677 |
{ |
|
1678 |
.name = "LEON3", |
|
1679 |
.iu_version = 0xf3000000, |
|
1680 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1681 |
.mmu_version = 0xf3000000, |
|
1682 |
.mmu_bm = 0x00000000, |
|
1683 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1684 |
.mmu_cxr_mask = 0x0000003f, |
|
1685 |
.mmu_sfsr_mask = 0xffffffff, |
|
1686 |
.mmu_trcr_mask = 0xffffffff, |
|
1687 |
.nwindows = 8, |
|
1688 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | |
|
1689 |
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL, |
|
1690 |
}, |
|
1691 |
#endif |
|
1692 |
}; |
|
1693 |
|
|
1694 |
static const char * const feature_name[] = { |
|
1695 |
"float", |
|
1696 |
"float128", |
|
1697 |
"swap", |
|
1698 |
"mul", |
|
1699 |
"div", |
|
1700 |
"flush", |
|
1701 |
"fsqrt", |
|
1702 |
"fmul", |
|
1703 |
"vis1", |
|
1704 |
"vis2", |
|
1705 |
"fsmuld", |
|
1706 |
"hypv", |
|
1707 |
"cmt", |
|
1708 |
"gl", |
|
1709 |
}; |
|
1710 |
|
|
1711 |
static void print_features(FILE *f, fprintf_function cpu_fprintf, |
|
1712 |
uint32_t features, const char *prefix) |
|
1713 |
{ |
|
1714 |
unsigned int i; |
|
1715 |
|
|
1716 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) { |
|
1717 |
if (feature_name[i] && (features & (1 << i))) { |
|
1718 |
if (prefix) { |
|
1719 |
(*cpu_fprintf)(f, "%s", prefix); |
|
1720 |
} |
|
1721 |
(*cpu_fprintf)(f, "%s ", feature_name[i]); |
|
1722 |
} |
|
1723 |
} |
|
1724 |
} |
|
1725 |
|
|
1726 |
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
|
1727 |
{ |
|
1728 |
unsigned int i; |
|
1729 |
|
|
1730 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) { |
|
1731 |
if (feature_name[i] && !strcmp(flagname, feature_name[i])) { |
|
1732 |
*features |= 1 << i; |
|
1733 |
return; |
|
1734 |
} |
|
1735 |
} |
|
1736 |
fprintf(stderr, "CPU feature %s not found\n", flagname); |
|
1737 |
} |
|
1738 |
|
|
1739 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
|
1740 |
{ |
|
1741 |
unsigned int i; |
|
1742 |
const sparc_def_t *def = NULL; |
|
1743 |
char *s = strdup(cpu_model); |
|
1744 |
char *featurestr, *name = strtok(s, ","); |
|
1745 |
uint32_t plus_features = 0; |
|
1746 |
uint32_t minus_features = 0; |
|
1747 |
uint64_t iu_version; |
|
1748 |
uint32_t fpu_version, mmu_version, nwindows; |
|
1749 |
|
|
1750 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
|
1751 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
|
1752 |
def = &sparc_defs[i]; |
|
1753 |
} |
|
1754 |
} |
|
1755 |
if (!def) { |
|
1756 |
goto error; |
|
1757 |
} |
|
1758 |
memcpy(cpu_def, def, sizeof(*def)); |
|
1759 |
|
|
1760 |
featurestr = strtok(NULL, ","); |
|
1761 |
while (featurestr) { |
|
1762 |
char *val; |
|
1763 |
|
|
1764 |
if (featurestr[0] == '+') { |
|
1765 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features); |
|
1766 |
} else if (featurestr[0] == '-') { |
|
1767 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features); |
|
1768 |
} else if ((val = strchr(featurestr, '='))) { |
|
1769 |
*val = 0; val++; |
|
1770 |
if (!strcmp(featurestr, "iu_version")) { |
|
1771 |
char *err; |
|
1772 |
|
|
1773 |
iu_version = strtoll(val, &err, 0); |
|
1774 |
if (!*val || *err) { |
|
1775 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
1776 |
goto error; |
|
1777 |
} |
|
1778 |
cpu_def->iu_version = iu_version; |
|
1779 |
#ifdef DEBUG_FEATURES |
|
1780 |
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version); |
|
1781 |
#endif |
|
1782 |
} else if (!strcmp(featurestr, "fpu_version")) { |
|
1783 |
char *err; |
|
1784 |
|
|
1785 |
fpu_version = strtol(val, &err, 0); |
|
1786 |
if (!*val || *err) { |
|
1787 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
1788 |
goto error; |
|
1789 |
} |
|
1790 |
cpu_def->fpu_version = fpu_version; |
|
1791 |
#ifdef DEBUG_FEATURES |
|
1792 |
fprintf(stderr, "fpu_version %x\n", fpu_version); |
|
1793 |
#endif |
|
1794 |
} else if (!strcmp(featurestr, "mmu_version")) { |
|
1795 |
char *err; |
|
1796 |
|
|
1797 |
mmu_version = strtol(val, &err, 0); |
|
1798 |
if (!*val || *err) { |
|
1799 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
1800 |
goto error; |
|
1801 |
} |
|
1802 |
cpu_def->mmu_version = mmu_version; |
|
1803 |
#ifdef DEBUG_FEATURES |
|
1804 |
fprintf(stderr, "mmu_version %x\n", mmu_version); |
|
1805 |
#endif |
|
1806 |
} else if (!strcmp(featurestr, "nwindows")) { |
|
1807 |
char *err; |
|
1808 |
|
|
1809 |
nwindows = strtol(val, &err, 0); |
|
1810 |
if (!*val || *err || nwindows > MAX_NWINDOWS || |
|
1811 |
nwindows < MIN_NWINDOWS) { |
|
1812 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
1813 |
goto error; |
|
1814 |
} |
|
1815 |
cpu_def->nwindows = nwindows; |
|
1816 |
#ifdef DEBUG_FEATURES |
|
1817 |
fprintf(stderr, "nwindows %d\n", nwindows); |
|
1818 |
#endif |
|
1819 |
} else { |
|
1820 |
fprintf(stderr, "unrecognized feature %s\n", featurestr); |
|
1821 |
goto error; |
|
1822 |
} |
|
1823 |
} else { |
|
1824 |
fprintf(stderr, "feature string `%s' not in format " |
|
1825 |
"(+feature|-feature|feature=xyz)\n", featurestr); |
|
1826 |
goto error; |
|
1827 |
} |
|
1828 |
featurestr = strtok(NULL, ","); |
|
1829 |
} |
|
1830 |
cpu_def->features |= plus_features; |
|
1831 |
cpu_def->features &= ~minus_features; |
|
1832 |
#ifdef DEBUG_FEATURES |
|
1833 |
print_features(stderr, fprintf, cpu_def->features, NULL); |
|
1834 |
#endif |
|
1835 |
free(s); |
|
1836 |
return 0; |
|
1837 |
|
|
1838 |
error: |
|
1839 |
free(s); |
|
1840 |
return -1; |
|
1841 |
} |
|
1842 |
|
|
1843 |
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf) |
|
1844 |
{ |
|
1845 |
unsigned int i; |
|
1846 |
|
|
1847 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
|
1848 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx |
|
1849 |
" FPU %08x MMU %08x NWINS %d ", |
|
1850 |
sparc_defs[i].name, |
|
1851 |
sparc_defs[i].iu_version, |
|
1852 |
sparc_defs[i].fpu_version, |
|
1853 |
sparc_defs[i].mmu_version, |
|
1854 |
sparc_defs[i].nwindows); |
|
1855 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
|
1856 |
~sparc_defs[i].features, "-"); |
|
1857 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
|
1858 |
sparc_defs[i].features, "+"); |
|
1859 |
(*cpu_fprintf)(f, "\n"); |
|
1860 |
} |
|
1861 |
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): "); |
|
1862 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL); |
|
1863 |
(*cpu_fprintf)(f, "\n"); |
|
1864 |
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): "); |
|
1865 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL); |
|
1866 |
(*cpu_fprintf)(f, "\n"); |
|
1867 |
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version " |
|
1868 |
"fpu_version mmu_version nwindows\n"); |
|
1869 |
} |
|
1870 |
|
|
1871 |
static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, |
|
1872 |
uint32_t cc) |
|
1873 |
{ |
|
1874 |
cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-', |
|
1875 |
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-', |
|
1876 |
cc & PSR_CARRY ? 'C' : '-'); |
|
1877 |
} |
|
1878 |
|
|
1879 |
#ifdef TARGET_SPARC64 |
|
1880 |
#define REGS_PER_LINE 4 |
|
1881 |
#else |
|
1882 |
#define REGS_PER_LINE 8 |
|
1883 |
#endif |
|
1884 |
|
|
1885 |
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
|
1886 |
int flags) |
|
1887 |
{ |
|
1888 |
int i, x; |
|
1889 |
|
|
1890 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
|
1891 |
env->npc); |
|
1892 |
cpu_fprintf(f, "General Registers:\n"); |
|
1893 |
|
|
1894 |
for (i = 0; i < 8; i++) { |
|
1895 |
if (i % REGS_PER_LINE == 0) { |
|
1896 |
cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); |
|
1897 |
} |
|
1898 |
cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); |
|
1899 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
|
1900 |
cpu_fprintf(f, "\n"); |
|
1901 |
} |
|
1902 |
} |
|
1903 |
cpu_fprintf(f, "\nCurrent Register Window:\n"); |
|
1904 |
for (x = 0; x < 3; x++) { |
|
1905 |
for (i = 0; i < 8; i++) { |
|
1906 |
if (i % REGS_PER_LINE == 0) { |
|
1907 |
cpu_fprintf(f, "%%%c%d-%d: ", |
|
1908 |
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), |
|
1909 |
i, i + REGS_PER_LINE - 1); |
|
1910 |
} |
|
1911 |
cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); |
|
1912 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
|
1913 |
cpu_fprintf(f, "\n"); |
|
1914 |
} |
|
1915 |
} |
|
1916 |
} |
|
1917 |
cpu_fprintf(f, "\nFloating Point Registers:\n"); |
|
1918 |
for (i = 0; i < TARGET_FPREGS; i++) { |
|
1919 |
if ((i & 3) == 0) { |
|
1920 |
cpu_fprintf(f, "%%f%02d:", i); |
|
1921 |
} |
|
1922 |
cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
|
1923 |
if ((i & 3) == 3) { |
|
1924 |
cpu_fprintf(f, "\n"); |
|
1925 |
} |
|
1926 |
} |
|
1927 |
#ifdef TARGET_SPARC64 |
|
1928 |
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, |
|
1929 |
(unsigned)cpu_get_ccr(env)); |
|
1930 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); |
|
1931 |
cpu_fprintf(f, " xcc: "); |
|
1932 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); |
|
1933 |
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl, |
|
1934 |
env->psrpil); |
|
1935 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " |
|
1936 |
"cleanwin: %d cwp: %d\n", |
|
1937 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
|
1938 |
env->cleanwin, env->nwindows - 1 - env->cwp); |
|
1939 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " |
|
1940 |
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); |
|
1941 |
#else |
|
1942 |
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); |
|
1943 |
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); |
|
1944 |
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', |
|
1945 |
env->psrps ? 'P' : '-', env->psret ? 'E' : '-', |
|
1946 |
env->wim); |
|
1947 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", |
|
1948 |
env->fsr, env->y); |
|
1949 |
#endif |
|
1950 |
} |
Also available in: Unified diff