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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU SPARC iommu emulation
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3 | 420557e8 | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | /* debug iommu */
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28 | 420557e8 | bellard | //#define DEBUG_IOMMU
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29 | 420557e8 | bellard | |
30 | 66321a11 | bellard | #ifdef DEBUG_IOMMU
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31 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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32 | 66321a11 | bellard | do { printf("IOMMU: " fmt , ##args); } while (0) |
33 | 66321a11 | bellard | #else
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34 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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35 | 66321a11 | bellard | #endif
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36 | 420557e8 | bellard | |
37 | e5e38121 | blueswir1 | #define IOMMU_NREGS (4*4096/4) |
38 | 4e3b1ea1 | bellard | #define IOMMU_CTRL (0x0000 >> 2) |
39 | 420557e8 | bellard | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
40 | 420557e8 | bellard | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
41 | 420557e8 | bellard | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
42 | 420557e8 | bellard | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
43 | 420557e8 | bellard | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
44 | 420557e8 | bellard | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
45 | 420557e8 | bellard | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
46 | 420557e8 | bellard | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
47 | 420557e8 | bellard | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
48 | 420557e8 | bellard | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
49 | 420557e8 | bellard | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
50 | 420557e8 | bellard | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
51 | 4e3b1ea1 | bellard | #define IOMMU_CTRL_MASK 0x0000001d |
52 | 4e3b1ea1 | bellard | |
53 | 4e3b1ea1 | bellard | #define IOMMU_BASE (0x0004 >> 2) |
54 | 4e3b1ea1 | bellard | #define IOMMU_BASE_MASK 0x07fffc00 |
55 | 4e3b1ea1 | bellard | |
56 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH (0x0014 >> 2) |
57 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH_MASK 0xffffffff |
58 | 4e3b1ea1 | bellard | |
59 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH (0x0018 >> 2) |
60 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH_MASK 0xffffffff |
61 | 4e3b1ea1 | bellard | |
62 | 225d4be7 | blueswir1 | #define IOMMU_AFSR (0x1000 >> 2) |
63 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
64 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
65 | 5ad6bb97 | blueswir1 | transaction */
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66 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
67 | 5ad6bb97 | blueswir1 | 12.8 us. */
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68 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
69 | 5ad6bb97 | blueswir1 | acknowledge */
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70 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
71 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
72 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
73 | 5ad6bb97 | blueswir1 | hardware */
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74 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
75 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
76 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
77 | c52428fc | blueswir1 | #define IOMMU_AFSR_MASK 0xff0fffff |
78 | 225d4be7 | blueswir1 | |
79 | 225d4be7 | blueswir1 | #define IOMMU_AFAR (0x1004 >> 2) |
80 | 225d4be7 | blueswir1 | |
81 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
82 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
83 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
84 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
85 | 5ad6bb97 | blueswir1 | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
86 | 5ad6bb97 | blueswir1 | bypass enabled */
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87 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
88 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
89 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
90 | f930d07e | blueswir1 | produced by this device as pure
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91 | 4e3b1ea1 | bellard | physical. */
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92 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_MASK 0x00010003 |
93 | 4e3b1ea1 | bellard | |
94 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
95 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN_MASK 0x001f0000 |
96 | 4e3b1ea1 | bellard | #define IOMMU_MID 0x00000008 |
97 | 420557e8 | bellard | |
98 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
99 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID_MASK 0x00ffffff |
100 | e5e38121 | blueswir1 | |
101 | e5e38121 | blueswir1 | #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
102 | e5e38121 | blueswir1 | #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
103 | e5e38121 | blueswir1 | |
104 | 420557e8 | bellard | /* The format of an iopte in the page tables */
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105 | 498fbd8a | blueswir1 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
106 | 5ad6bb97 | blueswir1 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
107 | 5ad6bb97 | blueswir1 | Viking/MXCC) */
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108 | 420557e8 | bellard | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
109 | 420557e8 | bellard | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
110 | 420557e8 | bellard | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
111 | 420557e8 | bellard | |
112 | 420557e8 | bellard | #define PAGE_SHIFT 12 |
113 | 420557e8 | bellard | #define PAGE_SIZE (1 << PAGE_SHIFT) |
114 | f930d07e | blueswir1 | #define PAGE_MASK (PAGE_SIZE - 1) |
115 | 420557e8 | bellard | |
116 | 420557e8 | bellard | typedef struct IOMMUState { |
117 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
118 | 66321a11 | bellard | uint32_t regs[IOMMU_NREGS]; |
119 | 5dcb6b91 | blueswir1 | target_phys_addr_t iostart; |
120 | 7fbfb139 | blueswir1 | uint32_t version; |
121 | ff403da6 | blueswir1 | qemu_irq irq; |
122 | 420557e8 | bellard | } IOMMUState; |
123 | 420557e8 | bellard | |
124 | 7c560456 | blueswir1 | static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
125 | 420557e8 | bellard | { |
126 | 420557e8 | bellard | IOMMUState *s = opaque; |
127 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
128 | ff403da6 | blueswir1 | uint32_t ret; |
129 | 420557e8 | bellard | |
130 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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131 | 420557e8 | bellard | switch (saddr) {
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132 | 420557e8 | bellard | default:
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133 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
134 | ff403da6 | blueswir1 | break;
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135 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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136 | ff403da6 | blueswir1 | case IOMMU_AFSR:
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137 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
138 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
139 | f930d07e | blueswir1 | break;
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140 | 420557e8 | bellard | } |
141 | ff403da6 | blueswir1 | DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
142 | ff403da6 | blueswir1 | return ret;
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143 | 420557e8 | bellard | } |
144 | 420557e8 | bellard | |
145 | 7c560456 | blueswir1 | static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
146 | 5ad6bb97 | blueswir1 | uint32_t val) |
147 | 420557e8 | bellard | { |
148 | 420557e8 | bellard | IOMMUState *s = opaque; |
149 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
150 | 420557e8 | bellard | |
151 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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152 | 981a2e99 | blueswir1 | DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
153 | 420557e8 | bellard | switch (saddr) {
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154 | 4e3b1ea1 | bellard | case IOMMU_CTRL:
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155 | f930d07e | blueswir1 | switch (val & IOMMU_CTRL_RNGE) {
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156 | f930d07e | blueswir1 | case IOMMU_RNGE_16MB:
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157 | f930d07e | blueswir1 | s->iostart = 0xffffffffff000000ULL;
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158 | f930d07e | blueswir1 | break;
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159 | f930d07e | blueswir1 | case IOMMU_RNGE_32MB:
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160 | f930d07e | blueswir1 | s->iostart = 0xfffffffffe000000ULL;
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161 | f930d07e | blueswir1 | break;
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162 | f930d07e | blueswir1 | case IOMMU_RNGE_64MB:
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163 | f930d07e | blueswir1 | s->iostart = 0xfffffffffc000000ULL;
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164 | f930d07e | blueswir1 | break;
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165 | f930d07e | blueswir1 | case IOMMU_RNGE_128MB:
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166 | f930d07e | blueswir1 | s->iostart = 0xfffffffff8000000ULL;
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167 | f930d07e | blueswir1 | break;
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168 | f930d07e | blueswir1 | case IOMMU_RNGE_256MB:
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169 | f930d07e | blueswir1 | s->iostart = 0xfffffffff0000000ULL;
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170 | f930d07e | blueswir1 | break;
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171 | f930d07e | blueswir1 | case IOMMU_RNGE_512MB:
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172 | f930d07e | blueswir1 | s->iostart = 0xffffffffe0000000ULL;
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173 | f930d07e | blueswir1 | break;
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174 | f930d07e | blueswir1 | case IOMMU_RNGE_1GB:
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175 | f930d07e | blueswir1 | s->iostart = 0xffffffffc0000000ULL;
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176 | f930d07e | blueswir1 | break;
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177 | f930d07e | blueswir1 | default:
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178 | f930d07e | blueswir1 | case IOMMU_RNGE_2GB:
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179 | f930d07e | blueswir1 | s->iostart = 0xffffffff80000000ULL;
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180 | f930d07e | blueswir1 | break;
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181 | f930d07e | blueswir1 | } |
182 | f930d07e | blueswir1 | DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
183 | 7fbfb139 | blueswir1 | s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
184 | f930d07e | blueswir1 | break;
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185 | 4e3b1ea1 | bellard | case IOMMU_BASE:
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186 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_BASE_MASK; |
187 | f930d07e | blueswir1 | break;
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188 | 4e3b1ea1 | bellard | case IOMMU_TLBFLUSH:
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189 | f930d07e | blueswir1 | DPRINTF("tlb flush %x\n", val);
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190 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
191 | f930d07e | blueswir1 | break;
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192 | 4e3b1ea1 | bellard | case IOMMU_PGFLUSH:
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193 | f930d07e | blueswir1 | DPRINTF("page flush %x\n", val);
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194 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
195 | f930d07e | blueswir1 | break;
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196 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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197 | ff403da6 | blueswir1 | s->regs[saddr] = val; |
198 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
199 | ff403da6 | blueswir1 | break;
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200 | c52428fc | blueswir1 | case IOMMU_AFSR:
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201 | c52428fc | blueswir1 | s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
202 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
203 | c52428fc | blueswir1 | break;
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204 | 4e3b1ea1 | bellard | case IOMMU_SBCFG0:
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205 | 4e3b1ea1 | bellard | case IOMMU_SBCFG1:
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206 | 4e3b1ea1 | bellard | case IOMMU_SBCFG2:
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207 | 4e3b1ea1 | bellard | case IOMMU_SBCFG3:
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208 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
209 | f930d07e | blueswir1 | break;
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210 | 4e3b1ea1 | bellard | case IOMMU_ARBEN:
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211 | 4e3b1ea1 | bellard | // XXX implement SBus probing: fault when reading unmapped
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212 | 4e3b1ea1 | bellard | // addresses, fault cause and address stored to MMU/IOMMU
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213 | f930d07e | blueswir1 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
214 | f930d07e | blueswir1 | break;
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215 | e5e38121 | blueswir1 | case IOMMU_MASK_ID:
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216 | e5e38121 | blueswir1 | s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
217 | e5e38121 | blueswir1 | break;
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218 | 420557e8 | bellard | default:
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219 | f930d07e | blueswir1 | s->regs[saddr] = val; |
220 | f930d07e | blueswir1 | break;
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221 | 420557e8 | bellard | } |
222 | 420557e8 | bellard | } |
223 | 420557e8 | bellard | |
224 | 420557e8 | bellard | static CPUReadMemoryFunc *iommu_mem_read[3] = { |
225 | 7c560456 | blueswir1 | NULL,
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226 | 7c560456 | blueswir1 | NULL,
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227 | 7c560456 | blueswir1 | iommu_mem_readl, |
228 | 420557e8 | bellard | }; |
229 | 420557e8 | bellard | |
230 | 420557e8 | bellard | static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
231 | 7c560456 | blueswir1 | NULL,
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232 | 7c560456 | blueswir1 | NULL,
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233 | 7c560456 | blueswir1 | iommu_mem_writel, |
234 | 420557e8 | bellard | }; |
235 | 420557e8 | bellard | |
236 | 5dcb6b91 | blueswir1 | static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
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237 | 420557e8 | bellard | { |
238 | 5e3b100b | blueswir1 | uint32_t ret; |
239 | 5e3b100b | blueswir1 | target_phys_addr_t iopte; |
240 | 981a2e99 | blueswir1 | #ifdef DEBUG_IOMMU
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241 | 981a2e99 | blueswir1 | target_phys_addr_t pa = addr; |
242 | 981a2e99 | blueswir1 | #endif
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243 | 420557e8 | bellard | |
244 | 981a2e99 | blueswir1 | iopte = s->regs[IOMMU_BASE] << 4;
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245 | 66321a11 | bellard | addr &= ~s->iostart; |
246 | 66321a11 | bellard | iopte += (addr >> (PAGE_SHIFT - 2)) & ~3; |
247 | 5e3b100b | blueswir1 | cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
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248 | 748e4993 | blueswir1 | tswap32s(&ret); |
249 | 5e3b100b | blueswir1 | DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
250 | 5e3b100b | blueswir1 | ", *pte = %x\n", pa, iopte, ret);
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251 | 981a2e99 | blueswir1 | |
252 | 981a2e99 | blueswir1 | return ret;
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253 | a917d384 | pbrook | } |
254 | a917d384 | pbrook | |
255 | 22548760 | blueswir1 | static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
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256 | 5dcb6b91 | blueswir1 | uint32_t pte) |
257 | a917d384 | pbrook | { |
258 | a917d384 | pbrook | uint32_t tmppte; |
259 | 5dcb6b91 | blueswir1 | target_phys_addr_t pa; |
260 | 5dcb6b91 | blueswir1 | |
261 | 5dcb6b91 | blueswir1 | tmppte = pte; |
262 | 5dcb6b91 | blueswir1 | pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
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263 | 5dcb6b91 | blueswir1 | DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
264 | 5dcb6b91 | blueswir1 | " (iopte = %x)\n", addr, pa, tmppte);
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265 | a917d384 | pbrook | |
266 | 66321a11 | bellard | return pa;
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267 | 420557e8 | bellard | } |
268 | 420557e8 | bellard | |
269 | 5ad6bb97 | blueswir1 | static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
270 | 5ad6bb97 | blueswir1 | int is_write)
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271 | 225d4be7 | blueswir1 | { |
272 | 225d4be7 | blueswir1 | DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
273 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
274 | 225d4be7 | blueswir1 | IOMMU_AFSR_FAV; |
275 | 225d4be7 | blueswir1 | if (!is_write)
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276 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
277 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFAR] = addr; |
278 | ff403da6 | blueswir1 | qemu_irq_raise(s->irq); |
279 | 225d4be7 | blueswir1 | } |
280 | 225d4be7 | blueswir1 | |
281 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
282 | 67e999be | bellard | uint8_t *buf, int len, int is_write) |
283 | a917d384 | pbrook | { |
284 | 5dcb6b91 | blueswir1 | int l;
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285 | 5dcb6b91 | blueswir1 | uint32_t flags; |
286 | 5dcb6b91 | blueswir1 | target_phys_addr_t page, phys_addr; |
287 | a917d384 | pbrook | |
288 | a917d384 | pbrook | while (len > 0) { |
289 | a917d384 | pbrook | page = addr & TARGET_PAGE_MASK; |
290 | a917d384 | pbrook | l = (page + TARGET_PAGE_SIZE) - addr; |
291 | a917d384 | pbrook | if (l > len)
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292 | a917d384 | pbrook | l = len; |
293 | a917d384 | pbrook | flags = iommu_page_get_flags(opaque, page); |
294 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_VALID)) {
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295 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
296 | a917d384 | pbrook | return;
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297 | 225d4be7 | blueswir1 | } |
298 | 22548760 | blueswir1 | phys_addr = iommu_translate_pa(addr, flags); |
299 | a917d384 | pbrook | if (is_write) {
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300 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_WRITE)) {
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301 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
302 | a917d384 | pbrook | return;
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303 | 225d4be7 | blueswir1 | } |
304 | a917d384 | pbrook | cpu_physical_memory_write(phys_addr, buf, len); |
305 | a917d384 | pbrook | } else {
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306 | a917d384 | pbrook | cpu_physical_memory_read(phys_addr, buf, len); |
307 | a917d384 | pbrook | } |
308 | a917d384 | pbrook | len -= l; |
309 | a917d384 | pbrook | buf += l; |
310 | a917d384 | pbrook | addr += l; |
311 | a917d384 | pbrook | } |
312 | a917d384 | pbrook | } |
313 | a917d384 | pbrook | |
314 | e80cfcfc | bellard | static void iommu_save(QEMUFile *f, void *opaque) |
315 | e80cfcfc | bellard | { |
316 | e80cfcfc | bellard | IOMMUState *s = opaque; |
317 | e80cfcfc | bellard | int i;
|
318 | 3b46e624 | ths | |
319 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
320 | f930d07e | blueswir1 | qemu_put_be32s(f, &s->regs[i]); |
321 | 5dcb6b91 | blueswir1 | qemu_put_be64s(f, &s->iostart); |
322 | e80cfcfc | bellard | } |
323 | e80cfcfc | bellard | |
324 | e80cfcfc | bellard | static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
325 | e80cfcfc | bellard | { |
326 | e80cfcfc | bellard | IOMMUState *s = opaque; |
327 | e80cfcfc | bellard | int i;
|
328 | 3b46e624 | ths | |
329 | 5dcb6b91 | blueswir1 | if (version_id != 2) |
330 | e80cfcfc | bellard | return -EINVAL;
|
331 | e80cfcfc | bellard | |
332 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
333 | fda77c2d | blueswir1 | qemu_get_be32s(f, &s->regs[i]); |
334 | 5dcb6b91 | blueswir1 | qemu_get_be64s(f, &s->iostart); |
335 | e80cfcfc | bellard | |
336 | e80cfcfc | bellard | return 0; |
337 | e80cfcfc | bellard | } |
338 | e80cfcfc | bellard | |
339 | e80cfcfc | bellard | static void iommu_reset(void *opaque) |
340 | e80cfcfc | bellard | { |
341 | e80cfcfc | bellard | IOMMUState *s = opaque; |
342 | e80cfcfc | bellard | |
343 | 66321a11 | bellard | memset(s->regs, 0, IOMMU_NREGS * 4); |
344 | e80cfcfc | bellard | s->iostart = 0;
|
345 | 7fbfb139 | blueswir1 | s->regs[IOMMU_CTRL] = s->version; |
346 | 7fbfb139 | blueswir1 | s->regs[IOMMU_ARBEN] = IOMMU_MID; |
347 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
348 | e5e38121 | blueswir1 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
349 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
350 | e80cfcfc | bellard | } |
351 | e80cfcfc | bellard | |
352 | ff403da6 | blueswir1 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
|
353 | 420557e8 | bellard | { |
354 | 420557e8 | bellard | IOMMUState *s; |
355 | 8d5f07fa | bellard | int iommu_io_memory;
|
356 | 420557e8 | bellard | |
357 | 420557e8 | bellard | s = qemu_mallocz(sizeof(IOMMUState));
|
358 | 420557e8 | bellard | if (!s)
|
359 | e80cfcfc | bellard | return NULL; |
360 | 420557e8 | bellard | |
361 | 8d5f07fa | bellard | s->addr = addr; |
362 | 7fbfb139 | blueswir1 | s->version = version; |
363 | ff403da6 | blueswir1 | s->irq = irq; |
364 | 8d5f07fa | bellard | |
365 | 5ad6bb97 | blueswir1 | iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
|
366 | 5ad6bb97 | blueswir1 | iommu_mem_write, s); |
367 | 66321a11 | bellard | cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
|
368 | 3b46e624 | ths | |
369 | 5dcb6b91 | blueswir1 | register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); |
370 | e80cfcfc | bellard | qemu_register_reset(iommu_reset, s); |
371 | 7fbfb139 | blueswir1 | iommu_reset(s); |
372 | e80cfcfc | bellard | return s;
|
373 | 420557e8 | bellard | } |