root / hw / omap.h @ ab7d9131
History | View | Annotate | Download (35.8 kB)
1 | c3d2689d | balrog | /*
|
---|---|---|---|
2 | c3d2689d | balrog | * Texas Instruments OMAP processors.
|
3 | c3d2689d | balrog | *
|
4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
|
5 | c3d2689d | balrog | *
|
6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
|
7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
|
8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
|
9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
|
10 | c3d2689d | balrog | *
|
11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
|
12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 | c3d2689d | balrog | * GNU General Public License for more details.
|
15 | c3d2689d | balrog | *
|
16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
|
17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
|
18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
19 | c3d2689d | balrog | * MA 02111-1307 USA
|
20 | c3d2689d | balrog | */
|
21 | c3d2689d | balrog | #ifndef hw_omap_h
|
22 | c3d2689d | balrog | # define hw_omap_h "omap.h" |
23 | c3d2689d | balrog | |
24 | c3d2689d | balrog | # define OMAP_EMIFS_BASE 0x00000000 |
25 | 827df9f3 | balrog | # define OMAP2_Q0_BASE 0x00000000 |
26 | c3d2689d | balrog | # define OMAP_CS0_BASE 0x00000000 |
27 | c3d2689d | balrog | # define OMAP_CS1_BASE 0x04000000 |
28 | c3d2689d | balrog | # define OMAP_CS2_BASE 0x08000000 |
29 | c3d2689d | balrog | # define OMAP_CS3_BASE 0x0c000000 |
30 | c3d2689d | balrog | # define OMAP_EMIFF_BASE 0x10000000 |
31 | c3d2689d | balrog | # define OMAP_IMIF_BASE 0x20000000 |
32 | c3d2689d | balrog | # define OMAP_LOCALBUS_BASE 0x30000000 |
33 | 827df9f3 | balrog | # define OMAP2_Q1_BASE 0x40000000 |
34 | 827df9f3 | balrog | # define OMAP2_L4_BASE 0x48000000 |
35 | 827df9f3 | balrog | # define OMAP2_SRAM_BASE 0x40200000 |
36 | 827df9f3 | balrog | # define OMAP2_L3_BASE 0x68000000 |
37 | 827df9f3 | balrog | # define OMAP2_Q2_BASE 0x80000000 |
38 | 827df9f3 | balrog | # define OMAP2_Q3_BASE 0xc0000000 |
39 | c3d2689d | balrog | # define OMAP_MPUI_BASE 0xe1000000 |
40 | c3d2689d | balrog | |
41 | c3d2689d | balrog | # define OMAP730_SRAM_SIZE 0x00032000 |
42 | c3d2689d | balrog | # define OMAP15XX_SRAM_SIZE 0x00030000 |
43 | c3d2689d | balrog | # define OMAP16XX_SRAM_SIZE 0x00004000 |
44 | c3d2689d | balrog | # define OMAP1611_SRAM_SIZE 0x0003e800 |
45 | 827df9f3 | balrog | # define OMAP242X_SRAM_SIZE 0x000a0000 |
46 | 827df9f3 | balrog | # define OMAP243X_SRAM_SIZE 0x00010000 |
47 | c3d2689d | balrog | # define OMAP_CS0_SIZE 0x04000000 |
48 | c3d2689d | balrog | # define OMAP_CS1_SIZE 0x04000000 |
49 | c3d2689d | balrog | # define OMAP_CS2_SIZE 0x04000000 |
50 | c3d2689d | balrog | # define OMAP_CS3_SIZE 0x04000000 |
51 | c3d2689d | balrog | |
52 | 827df9f3 | balrog | /* omap_clk.c */
|
53 | c3d2689d | balrog | struct omap_mpu_state_s;
|
54 | c3d2689d | balrog | typedef struct clk *omap_clk; |
55 | c3d2689d | balrog | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
56 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu); |
57 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
58 | c3d2689d | balrog | void omap_clk_get(omap_clk clk);
|
59 | c3d2689d | balrog | void omap_clk_put(omap_clk clk);
|
60 | c3d2689d | balrog | void omap_clk_onoff(omap_clk clk, int on); |
61 | c3d2689d | balrog | void omap_clk_canidle(omap_clk clk, int can); |
62 | c3d2689d | balrog | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
63 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk); |
64 | c3d2689d | balrog | void omap_clk_reparent(omap_clk clk, omap_clk parent);
|
65 | c3d2689d | balrog | |
66 | b4e3104b | balrog | /* omap[123].c */
|
67 | 827df9f3 | balrog | struct omap_l4_s;
|
68 | 827df9f3 | balrog | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
69 | 827df9f3 | balrog | |
70 | 827df9f3 | balrog | struct omap_target_agent_s;
|
71 | 827df9f3 | balrog | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); |
72 | 827df9f3 | balrog | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
73 | 827df9f3 | balrog | int iotype);
|
74 | c66fb5bc | balrog | # define l4_register_io_memory cpu_register_io_memory
|
75 | 827df9f3 | balrog | |
76 | c3d2689d | balrog | struct omap_intr_handler_s;
|
77 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
78 | 827df9f3 | balrog | unsigned long size, unsigned char nbanks, qemu_irq **pins, |
79 | 106627d0 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
80 | 827df9f3 | balrog | struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
|
81 | 827df9f3 | balrog | int size, int nbanks, qemu_irq **pins, |
82 | 827df9f3 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, |
83 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
84 | 827df9f3 | balrog | void omap_inth_reset(struct omap_intr_handler_s *s); |
85 | 827df9f3 | balrog | |
86 | 827df9f3 | balrog | struct omap_prcm_s;
|
87 | 827df9f3 | balrog | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
88 | 827df9f3 | balrog | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
89 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu);
|
90 | 827df9f3 | balrog | |
91 | 827df9f3 | balrog | struct omap_sysctl_s;
|
92 | 827df9f3 | balrog | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
93 | 827df9f3 | balrog | omap_clk iclk, struct omap_mpu_state_s *mpu);
|
94 | 827df9f3 | balrog | |
95 | 827df9f3 | balrog | struct omap_sdrc_s;
|
96 | 827df9f3 | balrog | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
|
97 | 827df9f3 | balrog | |
98 | 827df9f3 | balrog | struct omap_gpmc_s;
|
99 | 827df9f3 | balrog | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
|
100 | 827df9f3 | balrog | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
101 | 827df9f3 | balrog | void (*base_upd)(void *opaque, target_phys_addr_t new), |
102 | 827df9f3 | balrog | void (*unmap)(void *opaque), void *opaque); |
103 | 29885477 | balrog | |
104 | c3d2689d | balrog | /*
|
105 | c3d2689d | balrog | * Common IRQ numbers for level 1 interrupt handler
|
106 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
|
107 | c3d2689d | balrog | */
|
108 | c3d2689d | balrog | # define OMAP_INT_CAMERA 1 |
109 | c3d2689d | balrog | # define OMAP_INT_FIQ 3 |
110 | c3d2689d | balrog | # define OMAP_INT_RTDX 6 |
111 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU_ABORT 7 |
112 | c3d2689d | balrog | # define OMAP_INT_HOST 8 |
113 | c3d2689d | balrog | # define OMAP_INT_ABORT 9 |
114 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PRIV 13 |
115 | c3d2689d | balrog | # define OMAP_INT_GPIO_BANK1 14 |
116 | c3d2689d | balrog | # define OMAP_INT_UART3 15 |
117 | c3d2689d | balrog | # define OMAP_INT_TIMER3 16 |
118 | c3d2689d | balrog | # define OMAP_INT_DMA_CH0_6 19 |
119 | c3d2689d | balrog | # define OMAP_INT_DMA_CH1_7 20 |
120 | c3d2689d | balrog | # define OMAP_INT_DMA_CH2_8 21 |
121 | c3d2689d | balrog | # define OMAP_INT_DMA_CH3 22 |
122 | c3d2689d | balrog | # define OMAP_INT_DMA_CH4 23 |
123 | c3d2689d | balrog | # define OMAP_INT_DMA_CH5 24 |
124 | c3d2689d | balrog | # define OMAP_INT_DMA_LCD 25 |
125 | c3d2689d | balrog | # define OMAP_INT_TIMER1 26 |
126 | c3d2689d | balrog | # define OMAP_INT_WD_TIMER 27 |
127 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PUB 28 |
128 | c3d2689d | balrog | # define OMAP_INT_TIMER2 30 |
129 | c3d2689d | balrog | # define OMAP_INT_LCD_CTRL 31 |
130 | c3d2689d | balrog | |
131 | c3d2689d | balrog | /*
|
132 | c3d2689d | balrog | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
|
133 | c3d2689d | balrog | */
|
134 | c3d2689d | balrog | # define OMAP_INT_15XX_IH2_IRQ 0 |
135 | c3d2689d | balrog | # define OMAP_INT_15XX_LB_MMU 17 |
136 | c3d2689d | balrog | # define OMAP_INT_15XX_LOCAL_BUS 29 |
137 | c3d2689d | balrog | |
138 | c3d2689d | balrog | /*
|
139 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
|
140 | c3d2689d | balrog | */
|
141 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_TX 4 |
142 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_RX 5 |
143 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX1 10 |
144 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX2 11 |
145 | c3d2689d | balrog | |
146 | c3d2689d | balrog | /*
|
147 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 1 interrupt handler
|
148 | c3d2689d | balrog | */
|
149 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_TX 4 |
150 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_RX 5 |
151 | c3d2689d | balrog | # define OMAP_INT_310_HSB_MAILBOX1 12 |
152 | c3d2689d | balrog | # define OMAP_INT_310_HSAB_MMU 18 |
153 | c3d2689d | balrog | |
154 | c3d2689d | balrog | /*
|
155 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
|
156 | c3d2689d | balrog | */
|
157 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_IRQ 0 |
158 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_FIQ 2 |
159 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_TX 4 |
160 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_RX 5 |
161 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX1 10 |
162 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX2 11 |
163 | c3d2689d | balrog | # define OMAP_INT_1610_LCD_LINE 12 |
164 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER1 17 |
165 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER2 18 |
166 | c3d2689d | balrog | # define OMAP_INT_1610_SSR_FIFO_0 29 |
167 | c3d2689d | balrog | |
168 | c3d2689d | balrog | /*
|
169 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 1 interrupt handler
|
170 | c3d2689d | balrog | */
|
171 | c3d2689d | balrog | # define OMAP_INT_730_IH2_FIQ 0 |
172 | c3d2689d | balrog | # define OMAP_INT_730_IH2_IRQ 1 |
173 | c3d2689d | balrog | # define OMAP_INT_730_USB_NON_ISO 2 |
174 | c3d2689d | balrog | # define OMAP_INT_730_USB_ISO 3 |
175 | c3d2689d | balrog | # define OMAP_INT_730_ICR 4 |
176 | c3d2689d | balrog | # define OMAP_INT_730_EAC 5 |
177 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK1 6 |
178 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK2 7 |
179 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK3 8 |
180 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2TX 10 |
181 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX 11 |
182 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX_OVF 12 |
183 | c3d2689d | balrog | # define OMAP_INT_730_LCD_LINE 14 |
184 | c3d2689d | balrog | # define OMAP_INT_730_GSM_PROTECT 15 |
185 | c3d2689d | balrog | # define OMAP_INT_730_TIMER3 16 |
186 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK5 17 |
187 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK6 18 |
188 | c3d2689d | balrog | # define OMAP_INT_730_SPGIO_WR 29 |
189 | c3d2689d | balrog | |
190 | c3d2689d | balrog | /*
|
191 | c3d2689d | balrog | * Common IRQ numbers for level 2 interrupt handler
|
192 | c3d2689d | balrog | */
|
193 | c3d2689d | balrog | # define OMAP_INT_KEYBOARD 1 |
194 | c3d2689d | balrog | # define OMAP_INT_uWireTX 2 |
195 | c3d2689d | balrog | # define OMAP_INT_uWireRX 3 |
196 | c3d2689d | balrog | # define OMAP_INT_I2C 4 |
197 | c3d2689d | balrog | # define OMAP_INT_MPUIO 5 |
198 | c3d2689d | balrog | # define OMAP_INT_USB_HHC_1 6 |
199 | c3d2689d | balrog | # define OMAP_INT_McBSP3TX 10 |
200 | c3d2689d | balrog | # define OMAP_INT_McBSP3RX 11 |
201 | c3d2689d | balrog | # define OMAP_INT_McBSP1TX 12 |
202 | c3d2689d | balrog | # define OMAP_INT_McBSP1RX 13 |
203 | c3d2689d | balrog | # define OMAP_INT_UART1 14 |
204 | c3d2689d | balrog | # define OMAP_INT_UART2 15 |
205 | c3d2689d | balrog | # define OMAP_INT_USB_W2FC 20 |
206 | c3d2689d | balrog | # define OMAP_INT_1WIRE 21 |
207 | c3d2689d | balrog | # define OMAP_INT_OS_TIMER 22 |
208 | b30bb3a2 | balrog | # define OMAP_INT_OQN 23 |
209 | c3d2689d | balrog | # define OMAP_INT_GAUGE_32K 24 |
210 | c3d2689d | balrog | # define OMAP_INT_RTC_TIMER 25 |
211 | c3d2689d | balrog | # define OMAP_INT_RTC_ALARM 26 |
212 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU 28 |
213 | c3d2689d | balrog | |
214 | c3d2689d | balrog | /*
|
215 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
|
216 | c3d2689d | balrog | */
|
217 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1TX 16 |
218 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1RX 17 |
219 | c3d2689d | balrog | # define OMAP_INT_1510_SoSSI_MATCH 19 |
220 | c3d2689d | balrog | # define OMAP_INT_1510_MEM_STICK 27 |
221 | c3d2689d | balrog | # define OMAP_INT_1510_COM_SPI_RO 31 |
222 | c3d2689d | balrog | |
223 | c3d2689d | balrog | /*
|
224 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 2 interrupt handler
|
225 | c3d2689d | balrog | */
|
226 | c3d2689d | balrog | # define OMAP_INT_310_FAC 0 |
227 | c3d2689d | balrog | # define OMAP_INT_310_USB_HHC_2 7 |
228 | c3d2689d | balrog | # define OMAP_INT_310_MCSI1_FE 16 |
229 | c3d2689d | balrog | # define OMAP_INT_310_MCSI2_FE 17 |
230 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_ISO 29 |
231 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
232 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2RX_OF 31 |
233 | c3d2689d | balrog | |
234 | c3d2689d | balrog | /*
|
235 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
|
236 | c3d2689d | balrog | */
|
237 | c3d2689d | balrog | # define OMAP_INT_1610_FAC 0 |
238 | c3d2689d | balrog | # define OMAP_INT_1610_USB_HHC_2 7 |
239 | c3d2689d | balrog | # define OMAP_INT_1610_USB_OTG 8 |
240 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI 9 |
241 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1TX 16 |
242 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1RX 17 |
243 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI_MATCH 19 |
244 | c3d2689d | balrog | # define OMAP_INT_1610_MEM_STICK 27 |
245 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2RX_OF 31 |
246 | c3d2689d | balrog | # define OMAP_INT_1610_STI 32 |
247 | c3d2689d | balrog | # define OMAP_INT_1610_STI_WAKEUP 33 |
248 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER3 34 |
249 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER4 35 |
250 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER5 36 |
251 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER6 37 |
252 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER7 38 |
253 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER8 39 |
254 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK2 40 |
255 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK3 41 |
256 | c3d2689d | balrog | # define OMAP_INT_1610_MMC2 42 |
257 | c3d2689d | balrog | # define OMAP_INT_1610_CF 43 |
258 | c3d2689d | balrog | # define OMAP_INT_1610_WAKE_UP_REQ 46 |
259 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK4 48 |
260 | c3d2689d | balrog | # define OMAP_INT_1610_SPI 49 |
261 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH6 53 |
262 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH7 54 |
263 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH8 55 |
264 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH9 56 |
265 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH10 57 |
266 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH11 58 |
267 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH12 59 |
268 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH13 60 |
269 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH14 61 |
270 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH15 62 |
271 | c3d2689d | balrog | # define OMAP_INT_1610_NAND 63 |
272 | c3d2689d | balrog | |
273 | c3d2689d | balrog | /*
|
274 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 2 interrupt handler
|
275 | c3d2689d | balrog | */
|
276 | c3d2689d | balrog | # define OMAP_INT_730_HW_ERRORS 0 |
277 | c3d2689d | balrog | # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
278 | c3d2689d | balrog | # define OMAP_INT_730_CFCD 2 |
279 | c3d2689d | balrog | # define OMAP_INT_730_CFIREQ 3 |
280 | c3d2689d | balrog | # define OMAP_INT_730_I2C 4 |
281 | c3d2689d | balrog | # define OMAP_INT_730_PCC 5 |
282 | c3d2689d | balrog | # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
283 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_1 7 |
284 | c3d2689d | balrog | # define OMAP_INT_730_SYREN_SPI 8 |
285 | c3d2689d | balrog | # define OMAP_INT_730_VLYNQ 9 |
286 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK4 10 |
287 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1TX 11 |
288 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX 12 |
289 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX_OF 13 |
290 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
291 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_1 15 |
292 | c3d2689d | balrog | # define OMAP_INT_730_MCSI 16 |
293 | c3d2689d | balrog | # define OMAP_INT_730_uWireTX 17 |
294 | c3d2689d | balrog | # define OMAP_INT_730_uWireRX 18 |
295 | c3d2689d | balrog | # define OMAP_INT_730_SMC_CD 19 |
296 | c3d2689d | balrog | # define OMAP_INT_730_SMC_IREQ 20 |
297 | c3d2689d | balrog | # define OMAP_INT_730_HDQ_1WIRE 21 |
298 | c3d2689d | balrog | # define OMAP_INT_730_TIMER32K 22 |
299 | c3d2689d | balrog | # define OMAP_INT_730_MMC_SDIO 23 |
300 | c3d2689d | balrog | # define OMAP_INT_730_UPLD 24 |
301 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_1 27 |
302 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_2 28 |
303 | c3d2689d | balrog | # define OMAP_INT_730_USB_GENI 29 |
304 | c3d2689d | balrog | # define OMAP_INT_730_USB_OTG 30 |
305 | c3d2689d | balrog | # define OMAP_INT_730_CAMERA_IF 31 |
306 | c3d2689d | balrog | # define OMAP_INT_730_RNG 32 |
307 | c3d2689d | balrog | # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
308 | c3d2689d | balrog | # define OMAP_INT_730_DBB_RF_EN 34 |
309 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO_KEYPAD 35 |
310 | c3d2689d | balrog | # define OMAP_INT_730_SHA1_MD5 36 |
311 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_2 37 |
312 | c3d2689d | balrog | # define OMAP_INT_730_RNG_IDLE 38 |
313 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO 39 |
314 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
315 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_FALLING 41 |
316 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_RISING 42 |
317 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_VSYNC 43 |
318 | c3d2689d | balrog | # define OMAP_INT_730_WAKE_UP_REQ 46 |
319 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH6 53 |
320 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH7 54 |
321 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH8 55 |
322 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH9 56 |
323 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH10 57 |
324 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH11 58 |
325 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH12 59 |
326 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH13 60 |
327 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH14 61 |
328 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH15 62 |
329 | c3d2689d | balrog | # define OMAP_INT_730_NAND 63 |
330 | c3d2689d | balrog | |
331 | c3d2689d | balrog | /*
|
332 | c3d2689d | balrog | * OMAP-24xx common IRQ numbers
|
333 | c3d2689d | balrog | */
|
334 | 54585ffe | balrog | # define OMAP_INT_24XX_STI 4 |
335 | c3d2689d | balrog | # define OMAP_INT_24XX_SYS_NIRQ 7 |
336 | 827df9f3 | balrog | # define OMAP_INT_24XX_L3_IRQ 10 |
337 | 827df9f3 | balrog | # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
338 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ0 12 |
339 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ1 13 |
340 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ2 14 |
341 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ3 15 |
342 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP2_IRQ 16 |
343 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP3_IRQ 17 |
344 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP4_IRQ 18 |
345 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP5_IRQ 19 |
346 | 827df9f3 | balrog | # define OMAP_INT_24XX_GPMC_IRQ 20 |
347 | 827df9f3 | balrog | # define OMAP_INT_24XX_GUFFAW_IRQ 21 |
348 | 827df9f3 | balrog | # define OMAP_INT_24XX_IVA_IRQ 22 |
349 | 827df9f3 | balrog | # define OMAP_INT_24XX_EAC_IRQ 23 |
350 | c3d2689d | balrog | # define OMAP_INT_24XX_CAM_IRQ 24 |
351 | c3d2689d | balrog | # define OMAP_INT_24XX_DSS_IRQ 25 |
352 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
353 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_UMA 27 |
354 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_MMU 28 |
355 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK1 29 |
356 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK2 30 |
357 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK3 31 |
358 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK4 32 |
359 | 827df9f3 | balrog | # define OMAP_INT_243X_GPIO_BANK5 33 |
360 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
361 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT3 35 |
362 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT4 36 |
363 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER1 37 |
364 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER2 38 |
365 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER3 39 |
366 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER4 40 |
367 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER5 41 |
368 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER6 42 |
369 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER7 43 |
370 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER8 44 |
371 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER9 45 |
372 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER10 46 |
373 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER11 47 |
374 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER12 48 |
375 | 827df9f3 | balrog | # define OMAP_INT_24XX_PKA_IRQ 50 |
376 | 827df9f3 | balrog | # define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
377 | 827df9f3 | balrog | # define OMAP_INT_24XX_RNG_IRQ 52 |
378 | 827df9f3 | balrog | # define OMAP_INT_24XX_MG_IRQ 53 |
379 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C1_IRQ 56 |
380 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C2_IRQ 57 |
381 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
382 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
383 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
384 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
385 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP1_IRQ 64 |
386 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI1_IRQ 65 |
387 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI2_IRQ 66 |
388 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ0 67 |
389 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ1 68 |
390 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ0 69 |
391 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ1 70 |
392 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
393 | c3d2689d | balrog | # define OMAP_INT_24XX_UART1_IRQ 72 |
394 | c3d2689d | balrog | # define OMAP_INT_24XX_UART2_IRQ 73 |
395 | c3d2689d | balrog | # define OMAP_INT_24XX_UART3_IRQ 74 |
396 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
397 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
398 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
399 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
400 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
401 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
402 | 827df9f3 | balrog | # define OMAP_INT_24XX_VLYNQ_IRQ 81 |
403 | c3d2689d | balrog | # define OMAP_INT_24XX_MMC_IRQ 83 |
404 | 827df9f3 | balrog | # define OMAP_INT_24XX_MS_IRQ 84 |
405 | 827df9f3 | balrog | # define OMAP_INT_24XX_FAC_IRQ 85 |
406 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI3_IRQ 91 |
407 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_MC 92 |
408 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_DMA 93 |
409 | c3d2689d | balrog | # define OMAP_INT_243X_CARKIT 94 |
410 | 827df9f3 | balrog | # define OMAP_INT_34XX_GPTIMER12 95 |
411 | c3d2689d | balrog | |
412 | b4e3104b | balrog | /* omap_dma.c */
|
413 | 089b7c0a | balrog | enum omap_dma_model {
|
414 | b4e3104b | balrog | omap_dma_3_0, |
415 | b4e3104b | balrog | omap_dma_3_1, |
416 | b4e3104b | balrog | omap_dma_3_2, |
417 | b4e3104b | balrog | omap_dma_4, |
418 | 089b7c0a | balrog | }; |
419 | 089b7c0a | balrog | |
420 | c3d2689d | balrog | struct omap_dma_s;
|
421 | 089b7c0a | balrog | struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
422 | 089b7c0a | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
423 | 089b7c0a | balrog | enum omap_dma_model model);
|
424 | 827df9f3 | balrog | struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
|
425 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
426 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk);
|
427 | b4e3104b | balrog | void omap_dma_reset(struct omap_dma_s *s); |
428 | c3d2689d | balrog | |
429 | b4e3104b | balrog | struct dma_irq_map {
|
430 | b4e3104b | balrog | int ih;
|
431 | b4e3104b | balrog | int intr;
|
432 | b4e3104b | balrog | }; |
433 | b4e3104b | balrog | |
434 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
|
435 | c3d2689d | balrog | enum omap_dma_port {
|
436 | c3d2689d | balrog | emiff = 0,
|
437 | c3d2689d | balrog | emifs, |
438 | 089b7c0a | balrog | imif, /* omap16xx: ocp_t1 */
|
439 | c3d2689d | balrog | tipb, |
440 | 089b7c0a | balrog | local, /* omap16xx: ocp_t2 */
|
441 | c3d2689d | balrog | tipb_mpui, |
442 | 827df9f3 | balrog | __omap_dma_port_last, |
443 | c3d2689d | balrog | }; |
444 | c3d2689d | balrog | |
445 | 089b7c0a | balrog | typedef enum { |
446 | 089b7c0a | balrog | constant = 0,
|
447 | 089b7c0a | balrog | post_incremented, |
448 | 089b7c0a | balrog | single_index, |
449 | 089b7c0a | balrog | double_index, |
450 | 089b7c0a | balrog | } omap_dma_addressing_t; |
451 | 089b7c0a | balrog | |
452 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
|
453 | c3d2689d | balrog | struct omap_dma_lcd_channel_s {
|
454 | c3d2689d | balrog | enum omap_dma_port src;
|
455 | c3d2689d | balrog | target_phys_addr_t src_f1_top; |
456 | c3d2689d | balrog | target_phys_addr_t src_f1_bottom; |
457 | c3d2689d | balrog | target_phys_addr_t src_f2_top; |
458 | c3d2689d | balrog | target_phys_addr_t src_f2_bottom; |
459 | 089b7c0a | balrog | |
460 | 089b7c0a | balrog | /* Used in OMAP DMA 3.2 gigacell */
|
461 | 089b7c0a | balrog | unsigned char brust_f1; |
462 | 089b7c0a | balrog | unsigned char pack_f1; |
463 | 089b7c0a | balrog | unsigned char data_type_f1; |
464 | 089b7c0a | balrog | unsigned char brust_f2; |
465 | 089b7c0a | balrog | unsigned char pack_f2; |
466 | 089b7c0a | balrog | unsigned char data_type_f2; |
467 | 089b7c0a | balrog | unsigned char end_prog; |
468 | 089b7c0a | balrog | unsigned char repeat; |
469 | 089b7c0a | balrog | unsigned char auto_init; |
470 | 089b7c0a | balrog | unsigned char priority; |
471 | 089b7c0a | balrog | unsigned char fs; |
472 | 089b7c0a | balrog | unsigned char running; |
473 | 089b7c0a | balrog | unsigned char bs; |
474 | 089b7c0a | balrog | unsigned char omap_3_1_compatible_disable; |
475 | 089b7c0a | balrog | unsigned char dst; |
476 | 089b7c0a | balrog | unsigned char lch_type; |
477 | 089b7c0a | balrog | int16_t element_index_f1; |
478 | 089b7c0a | balrog | int16_t element_index_f2; |
479 | 089b7c0a | balrog | int32_t frame_index_f1; |
480 | 089b7c0a | balrog | int32_t frame_index_f2; |
481 | 089b7c0a | balrog | uint16_t elements_f1; |
482 | 089b7c0a | balrog | uint16_t frames_f1; |
483 | 089b7c0a | balrog | uint16_t elements_f2; |
484 | 089b7c0a | balrog | uint16_t frames_f2; |
485 | 089b7c0a | balrog | omap_dma_addressing_t mode_f1; |
486 | 089b7c0a | balrog | omap_dma_addressing_t mode_f2; |
487 | 089b7c0a | balrog | |
488 | c3d2689d | balrog | /* Destination port is fixed. */
|
489 | c3d2689d | balrog | int interrupts;
|
490 | c3d2689d | balrog | int condition;
|
491 | c3d2689d | balrog | int dual;
|
492 | c3d2689d | balrog | |
493 | c3d2689d | balrog | int current_frame;
|
494 | c3d2689d | balrog | ram_addr_t phys_framebuffer[2];
|
495 | c3d2689d | balrog | qemu_irq irq; |
496 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
497 | b4e3104b | balrog | } *omap_dma_get_lcdch(struct omap_dma_s *s);
|
498 | c3d2689d | balrog | |
499 | c3d2689d | balrog | /*
|
500 | c3d2689d | balrog | * DMA request numbers for OMAP1
|
501 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
502 | c3d2689d | balrog | */
|
503 | c3d2689d | balrog | # define OMAP_DMA_NO_DEVICE 0 |
504 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_TX 1 |
505 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_RX 2 |
506 | c3d2689d | balrog | # define OMAP_DMA_I2C_RX 3 |
507 | c3d2689d | balrog | # define OMAP_DMA_I2C_TX 4 |
508 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ0 5 |
509 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ1 6 |
510 | c3d2689d | balrog | # define OMAP_DMA_UWIRE_TX 7 |
511 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_TX 8 |
512 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_RX 9 |
513 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_TX 10 |
514 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_RX 11 |
515 | c3d2689d | balrog | # define OMAP_DMA_UART1_TX 12 |
516 | c3d2689d | balrog | # define OMAP_DMA_UART1_RX 13 |
517 | c3d2689d | balrog | # define OMAP_DMA_UART2_TX 14 |
518 | c3d2689d | balrog | # define OMAP_DMA_UART2_RX 15 |
519 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_TX 16 |
520 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_RX 17 |
521 | c3d2689d | balrog | # define OMAP_DMA_UART3_TX 18 |
522 | c3d2689d | balrog | # define OMAP_DMA_UART3_RX 19 |
523 | c3d2689d | balrog | # define OMAP_DMA_CAMERA_IF_RX 20 |
524 | c3d2689d | balrog | # define OMAP_DMA_MMC_TX 21 |
525 | c3d2689d | balrog | # define OMAP_DMA_MMC_RX 22 |
526 | c3d2689d | balrog | # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
527 | c3d2689d | balrog | # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
528 | c3d2689d | balrog | # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
529 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX0 26 |
530 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX1 27 |
531 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX2 28 |
532 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX0 29 |
533 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX1 30 |
534 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX2 31 |
535 | c3d2689d | balrog | |
536 | c3d2689d | balrog | /* These are only for 1610 */
|
537 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_IN 32 |
538 | c3d2689d | balrog | # define OMAP_DMA_SPI_TX 33 |
539 | c3d2689d | balrog | # define OMAP_DMA_SPI_RX 34 |
540 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_HASH 35 |
541 | c3d2689d | balrog | # define OMAP_DMA_CCP_ATTN 36 |
542 | c3d2689d | balrog | # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
543 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
544 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
545 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
546 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
547 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
548 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
549 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
550 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
551 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
552 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
553 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
554 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
555 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
556 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
557 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
558 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
559 | c3d2689d | balrog | # define OMAP_DMA_MMC2_TX 54 |
560 | c3d2689d | balrog | # define OMAP_DMA_MMC2_RX 55 |
561 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_OUT 56 |
562 | c3d2689d | balrog | |
563 | 827df9f3 | balrog | /*
|
564 | 827df9f3 | balrog | * DMA request numbers for the OMAP2
|
565 | 827df9f3 | balrog | */
|
566 | 827df9f3 | balrog | # define OMAP24XX_DMA_NO_DEVICE 0 |
567 | 827df9f3 | balrog | # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
568 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ0 2 |
569 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ1 3 |
570 | 827df9f3 | balrog | # define OMAP24XX_DMA_GPMC 4 |
571 | 827df9f3 | balrog | # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
572 | 827df9f3 | balrog | # define OMAP24XX_DMA_DSS 6 |
573 | 827df9f3 | balrog | # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
574 | 827df9f3 | balrog | # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
575 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
576 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
577 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
578 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
579 | 827df9f3 | balrog | # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
580 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ2 14 |
581 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ3 15 |
582 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ4 16 |
583 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_RD 17 |
584 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_WR 18 |
585 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
586 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
587 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
588 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
589 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
590 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
591 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
592 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
593 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_TX 27 |
594 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_RX 28 |
595 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_TX 29 |
596 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_RX 30 |
597 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_TX 31 |
598 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_RX 32 |
599 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_TX 33 |
600 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_RX 34 |
601 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX0 35 |
602 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX0 36 |
603 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX1 37 |
604 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX1 38 |
605 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX2 39 |
606 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX2 40 |
607 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX3 41 |
608 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX3 42 |
609 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX0 43 |
610 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX0 44 |
611 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX1 45 |
612 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX1 46 |
613 | 827df9f3 | balrog | |
614 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_TX 49 |
615 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_RX 50 |
616 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_TX 51 |
617 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_RX 52 |
618 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_TX 53 |
619 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_RX 54 |
620 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX0 55 |
621 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX0 56 |
622 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX1 57 |
623 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX1 58 |
624 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX2 59 |
625 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX2 60 |
626 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_TX 61 |
627 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_RX 62 |
628 | 827df9f3 | balrog | # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
629 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ5 64 |
630 | 827df9f3 | balrog | |
631 | b4e3104b | balrog | /* omap[123].c */
|
632 | c3d2689d | balrog | struct omap_mpu_timer_s;
|
633 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
634 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
635 | c3d2689d | balrog | |
636 | 827df9f3 | balrog | struct omap_gp_timer_s;
|
637 | 827df9f3 | balrog | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
638 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk); |
639 | 827df9f3 | balrog | |
640 | c3d2689d | balrog | struct omap_watchdog_timer_s;
|
641 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
642 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
643 | c3d2689d | balrog | |
644 | c3d2689d | balrog | struct omap_32khz_timer_s;
|
645 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
646 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
647 | c3d2689d | balrog | |
648 | 827df9f3 | balrog | void omap_synctimer_init(struct omap_target_agent_s *ta, |
649 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
|
650 | 827df9f3 | balrog | |
651 | c3d2689d | balrog | struct omap_tipb_bridge_s;
|
652 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
653 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk); |
654 | c3d2689d | balrog | |
655 | c3d2689d | balrog | struct omap_uart_s;
|
656 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
657 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
658 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
659 | 827df9f3 | balrog | struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
660 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
661 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
662 | 827df9f3 | balrog | void omap_uart_reset(struct omap_uart_s *s); |
663 | c3d2689d | balrog | |
664 | fe71e81a | balrog | struct omap_mpuio_s;
|
665 | fe71e81a | balrog | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
666 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
667 | fe71e81a | balrog | omap_clk clk); |
668 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
669 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
670 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
671 | fe71e81a | balrog | |
672 | 64330148 | balrog | struct omap_gpio_s;
|
673 | 64330148 | balrog | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
674 | 64330148 | balrog | qemu_irq irq, omap_clk clk); |
675 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
|
676 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
677 | 64330148 | balrog | |
678 | 827df9f3 | balrog | struct omap_gpif_s;
|
679 | 827df9f3 | balrog | struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
680 | 827df9f3 | balrog | qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
|
681 | 827df9f3 | balrog | qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); |
682 | 827df9f3 | balrog | void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); |
683 | 827df9f3 | balrog | |
684 | d951f6ff | balrog | struct uwire_slave_s {
|
685 | d951f6ff | balrog | uint16_t (*receive)(void *opaque);
|
686 | d951f6ff | balrog | void (*send)(void *opaque, uint16_t data); |
687 | d951f6ff | balrog | void *opaque;
|
688 | d951f6ff | balrog | }; |
689 | d951f6ff | balrog | struct omap_uwire_s;
|
690 | d951f6ff | balrog | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
691 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk); |
692 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
693 | d951f6ff | balrog | struct uwire_slave_s *slave, int chipselect); |
694 | d951f6ff | balrog | |
695 | 827df9f3 | balrog | struct omap_mcspi_s;
|
696 | 827df9f3 | balrog | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
697 | 827df9f3 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
698 | 827df9f3 | balrog | void omap_mcspi_attach(struct omap_mcspi_s *s, |
699 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
700 | 827df9f3 | balrog | int chipselect);
|
701 | 827df9f3 | balrog | |
702 | 5c1c390f | balrog | struct omap_rtc_s;
|
703 | 5c1c390f | balrog | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
704 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk); |
705 | 5c1c390f | balrog | |
706 | d8f699cb | balrog | struct i2s_codec_s {
|
707 | d8f699cb | balrog | void *opaque;
|
708 | d8f699cb | balrog | |
709 | d8f699cb | balrog | /* The CPU can call this if it is generating the clock signal on the
|
710 | d8f699cb | balrog | * i2s port. The CODEC can ignore it if it is set up as a clock
|
711 | d8f699cb | balrog | * master and generates its own clock. */
|
712 | d8f699cb | balrog | void (*set_rate)(void *opaque, int in, int out); |
713 | d8f699cb | balrog | |
714 | d8f699cb | balrog | void (*tx_swallow)(void *opaque); |
715 | d8f699cb | balrog | qemu_irq rx_swallow; |
716 | d8f699cb | balrog | qemu_irq tx_start; |
717 | d8f699cb | balrog | |
718 | 73560bc8 | balrog | int tx_rate;
|
719 | 73560bc8 | balrog | int cts;
|
720 | 73560bc8 | balrog | int rx_rate;
|
721 | 73560bc8 | balrog | int rts;
|
722 | 73560bc8 | balrog | |
723 | d8f699cb | balrog | struct i2s_fifo_s {
|
724 | d8f699cb | balrog | uint8_t *fifo; |
725 | d8f699cb | balrog | int len;
|
726 | d8f699cb | balrog | int start;
|
727 | d8f699cb | balrog | int size;
|
728 | d8f699cb | balrog | } in, out; |
729 | d8f699cb | balrog | }; |
730 | d8f699cb | balrog | struct omap_mcbsp_s;
|
731 | d8f699cb | balrog | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
732 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
733 | d8f699cb | balrog | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave); |
734 | d8f699cb | balrog | |
735 | f9d43072 | balrog | struct omap_lpg_s;
|
736 | f9d43072 | balrog | struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
|
737 | f9d43072 | balrog | |
738 | 827df9f3 | balrog | void omap_tap_init(struct omap_target_agent_s *ta, |
739 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu);
|
740 | 827df9f3 | balrog | |
741 | c3d2689d | balrog | /* omap_lcdc.c */
|
742 | c3d2689d | balrog | struct omap_lcd_panel_s;
|
743 | c3d2689d | balrog | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
744 | c3d2689d | balrog | struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
745 | c3d2689d | balrog | struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
|
746 | c3d2689d | balrog | ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
747 | c3d2689d | balrog | |
748 | 827df9f3 | balrog | /* omap_dss.c */
|
749 | 827df9f3 | balrog | struct rfbi_chip_s {
|
750 | 827df9f3 | balrog | void *opaque;
|
751 | 827df9f3 | balrog | void (*write)(void *opaque, int dc, uint16_t value); |
752 | 827df9f3 | balrog | void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
753 | 827df9f3 | balrog | uint16_t (*read)(void *opaque, int dc); |
754 | 827df9f3 | balrog | }; |
755 | 827df9f3 | balrog | struct omap_dss_s;
|
756 | 827df9f3 | balrog | void omap_dss_reset(struct omap_dss_s *s); |
757 | 827df9f3 | balrog | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
758 | 827df9f3 | balrog | target_phys_addr_t l3_base, DisplayState *ds, |
759 | 827df9f3 | balrog | qemu_irq irq, qemu_irq drq, |
760 | 827df9f3 | balrog | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
761 | 827df9f3 | balrog | omap_clk ick1, omap_clk ick2); |
762 | 827df9f3 | balrog | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
763 | 827df9f3 | balrog | |
764 | b30bb3a2 | balrog | /* omap_mmc.c */
|
765 | b30bb3a2 | balrog | struct omap_mmc_s;
|
766 | b30bb3a2 | balrog | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
767 | 87ecb68b | pbrook | BlockDriverState *bd, |
768 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
769 | 827df9f3 | balrog | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
770 | 827df9f3 | balrog | BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
771 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
772 | b30bb3a2 | balrog | void omap_mmc_reset(struct omap_mmc_s *s); |
773 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
774 | 827df9f3 | balrog | void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
775 | b30bb3a2 | balrog | |
776 | 02645926 | balrog | /* omap_i2c.c */
|
777 | 02645926 | balrog | struct omap_i2c_s;
|
778 | 02645926 | balrog | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
779 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk); |
780 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
781 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
782 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s); |
783 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
784 | 02645926 | balrog | |
785 | c3d2689d | balrog | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
786 | c3d2689d | balrog | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
787 | 827df9f3 | balrog | # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
|
788 | 827df9f3 | balrog | # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
|
789 | 827df9f3 | balrog | # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
|
790 | 827df9f3 | balrog | # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
|
791 | 827df9f3 | balrog | # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
|
792 | 827df9f3 | balrog | # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
|
793 | 827df9f3 | balrog | |
794 | c3d2689d | balrog | # define cpu_is_omap15xx(cpu) \
|
795 | c3d2689d | balrog | (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
796 | 827df9f3 | balrog | # define cpu_is_omap16xx(cpu) \
|
797 | 827df9f3 | balrog | (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
798 | 827df9f3 | balrog | # define cpu_is_omap24xx(cpu) \
|
799 | 827df9f3 | balrog | (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
800 | 827df9f3 | balrog | |
801 | 827df9f3 | balrog | # define cpu_class_omap1(cpu) \
|
802 | 827df9f3 | balrog | (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
803 | 827df9f3 | balrog | # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
|
804 | 827df9f3 | balrog | # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
|
805 | c3d2689d | balrog | |
806 | c3d2689d | balrog | struct omap_mpu_state_s {
|
807 | 827df9f3 | balrog | enum omap_mpu_model {
|
808 | c3d2689d | balrog | omap310, |
809 | c3d2689d | balrog | omap1510, |
810 | 827df9f3 | balrog | omap1610, |
811 | 827df9f3 | balrog | omap1710, |
812 | 827df9f3 | balrog | omap2410, |
813 | 827df9f3 | balrog | omap2420, |
814 | 827df9f3 | balrog | omap2422, |
815 | 827df9f3 | balrog | omap2423, |
816 | 827df9f3 | balrog | omap2430, |
817 | 827df9f3 | balrog | omap3430, |
818 | c3d2689d | balrog | } mpu_model; |
819 | c3d2689d | balrog | |
820 | c3d2689d | balrog | CPUState *env; |
821 | c3d2689d | balrog | |
822 | c3d2689d | balrog | qemu_irq *irq[2];
|
823 | c3d2689d | balrog | qemu_irq *drq; |
824 | c3d2689d | balrog | |
825 | c3d2689d | balrog | qemu_irq wakeup; |
826 | c3d2689d | balrog | |
827 | c3d2689d | balrog | struct omap_dma_port_if_s {
|
828 | 5fafdf24 | ths | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
829 | c3d2689d | balrog | target_phys_addr_t offset); |
830 | c3d2689d | balrog | void (*write[3])(struct omap_mpu_state_s *s, |
831 | c3d2689d | balrog | target_phys_addr_t offset, uint32_t value); |
832 | c3d2689d | balrog | int (*addr_valid)(struct omap_mpu_state_s *s, |
833 | c3d2689d | balrog | target_phys_addr_t addr); |
834 | 827df9f3 | balrog | } port[__omap_dma_port_last]; |
835 | c3d2689d | balrog | |
836 | c3d2689d | balrog | unsigned long sdram_size; |
837 | c3d2689d | balrog | unsigned long sram_size; |
838 | c3d2689d | balrog | |
839 | c3d2689d | balrog | /* MPUI-TIPB peripherals */
|
840 | d951f6ff | balrog | struct omap_uart_s *uart[3]; |
841 | d951f6ff | balrog | |
842 | d951f6ff | balrog | struct omap_gpio_s *gpio;
|
843 | c3d2689d | balrog | |
844 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp1;
|
845 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp3;
|
846 | d8f699cb | balrog | |
847 | c3d2689d | balrog | /* MPU public TIPB peripherals */
|
848 | c3d2689d | balrog | struct omap_32khz_timer_s *os_timer;
|
849 | c3d2689d | balrog | |
850 | b30bb3a2 | balrog | struct omap_mmc_s *mmc;
|
851 | b30bb3a2 | balrog | |
852 | d951f6ff | balrog | struct omap_mpuio_s *mpuio;
|
853 | d951f6ff | balrog | |
854 | d951f6ff | balrog | struct omap_uwire_s *microwire;
|
855 | d951f6ff | balrog | |
856 | 66450b15 | balrog | struct {
|
857 | 66450b15 | balrog | uint8_t output; |
858 | 66450b15 | balrog | uint8_t level; |
859 | 66450b15 | balrog | uint8_t enable; |
860 | 66450b15 | balrog | int clk;
|
861 | 66450b15 | balrog | } pwl; |
862 | 66450b15 | balrog | |
863 | f34c417b | balrog | struct {
|
864 | f34c417b | balrog | uint8_t frc; |
865 | f34c417b | balrog | uint8_t vrc; |
866 | f34c417b | balrog | uint8_t gcr; |
867 | f34c417b | balrog | omap_clk clk; |
868 | f34c417b | balrog | } pwt; |
869 | f34c417b | balrog | |
870 | 827df9f3 | balrog | struct omap_i2c_s *i2c[2]; |
871 | 4a2c8ac2 | balrog | |
872 | 02645926 | balrog | struct omap_rtc_s *rtc;
|
873 | 02645926 | balrog | |
874 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp2;
|
875 | d8f699cb | balrog | |
876 | f9d43072 | balrog | struct omap_lpg_s *led[2]; |
877 | f9d43072 | balrog | |
878 | c3d2689d | balrog | /* MPU private TIPB peripherals */
|
879 | c3d2689d | balrog | struct omap_intr_handler_s *ih[2]; |
880 | c3d2689d | balrog | |
881 | c3d2689d | balrog | struct omap_dma_s *dma;
|
882 | c3d2689d | balrog | |
883 | c3d2689d | balrog | struct omap_mpu_timer_s *timer[3]; |
884 | c3d2689d | balrog | struct omap_watchdog_timer_s *wdt;
|
885 | c3d2689d | balrog | |
886 | c3d2689d | balrog | struct omap_lcd_panel_s *lcd;
|
887 | c3d2689d | balrog | |
888 | c3d2689d | balrog | target_phys_addr_t ulpd_pm_base; |
889 | c3d2689d | balrog | uint32_t ulpd_pm_regs[21];
|
890 | c3d2689d | balrog | int64_t ulpd_gauge_start; |
891 | c3d2689d | balrog | |
892 | c3d2689d | balrog | target_phys_addr_t pin_cfg_base; |
893 | c3d2689d | balrog | uint32_t func_mux_ctrl[14];
|
894 | c3d2689d | balrog | uint32_t comp_mode_ctrl[1];
|
895 | c3d2689d | balrog | uint32_t pull_dwn_ctrl[4];
|
896 | c3d2689d | balrog | uint32_t gate_inh_ctrl[1];
|
897 | c3d2689d | balrog | uint32_t voltage_ctrl[1];
|
898 | c3d2689d | balrog | uint32_t test_dbg_ctrl[1];
|
899 | c3d2689d | balrog | uint32_t mod_conf_ctrl[1];
|
900 | c3d2689d | balrog | int compat1509;
|
901 | c3d2689d | balrog | |
902 | c3d2689d | balrog | uint32_t mpui_ctrl; |
903 | c3d2689d | balrog | target_phys_addr_t mpui_base; |
904 | c3d2689d | balrog | |
905 | c3d2689d | balrog | struct omap_tipb_bridge_s *private_tipb;
|
906 | c3d2689d | balrog | struct omap_tipb_bridge_s *public_tipb;
|
907 | c3d2689d | balrog | |
908 | c3d2689d | balrog | target_phys_addr_t tcmi_base; |
909 | c3d2689d | balrog | uint32_t tcmi_regs[17];
|
910 | c3d2689d | balrog | |
911 | c3d2689d | balrog | struct dpll_ctl_s {
|
912 | c3d2689d | balrog | target_phys_addr_t base; |
913 | c3d2689d | balrog | uint16_t mode; |
914 | c3d2689d | balrog | omap_clk dpll; |
915 | c3d2689d | balrog | } dpll[3];
|
916 | c3d2689d | balrog | |
917 | c3d2689d | balrog | omap_clk clks; |
918 | c3d2689d | balrog | struct {
|
919 | c3d2689d | balrog | target_phys_addr_t mpu_base; |
920 | c3d2689d | balrog | target_phys_addr_t dsp_base; |
921 | c3d2689d | balrog | |
922 | c3d2689d | balrog | int cold_start;
|
923 | c3d2689d | balrog | int clocking_scheme;
|
924 | c3d2689d | balrog | uint16_t arm_ckctl; |
925 | c3d2689d | balrog | uint16_t arm_idlect1; |
926 | c3d2689d | balrog | uint16_t arm_idlect2; |
927 | c3d2689d | balrog | uint16_t arm_ewupct; |
928 | c3d2689d | balrog | uint16_t arm_rstct1; |
929 | c3d2689d | balrog | uint16_t arm_rstct2; |
930 | c3d2689d | balrog | uint16_t arm_ckout1; |
931 | c3d2689d | balrog | int dpll1_mode;
|
932 | c3d2689d | balrog | uint16_t dsp_idlect1; |
933 | c3d2689d | balrog | uint16_t dsp_idlect2; |
934 | c3d2689d | balrog | uint16_t dsp_rstct2; |
935 | c3d2689d | balrog | } clkm; |
936 | 827df9f3 | balrog | |
937 | 827df9f3 | balrog | /* OMAP2-only peripherals */
|
938 | 827df9f3 | balrog | struct omap_l4_s *l4;
|
939 | 827df9f3 | balrog | |
940 | 827df9f3 | balrog | struct omap_gp_timer_s *gptimer[12]; |
941 | 827df9f3 | balrog | |
942 | 827df9f3 | balrog | target_phys_addr_t tap_base; |
943 | 827df9f3 | balrog | |
944 | 827df9f3 | balrog | struct omap_synctimer_s {
|
945 | 827df9f3 | balrog | target_phys_addr_t base; |
946 | 827df9f3 | balrog | uint32_t val; |
947 | 827df9f3 | balrog | uint16_t readh; |
948 | 827df9f3 | balrog | } synctimer; |
949 | 827df9f3 | balrog | |
950 | 827df9f3 | balrog | struct omap_prcm_s *prcm;
|
951 | 827df9f3 | balrog | struct omap_sdrc_s *sdrc;
|
952 | 827df9f3 | balrog | struct omap_gpmc_s *gpmc;
|
953 | 827df9f3 | balrog | struct omap_sysctl_s *sysc;
|
954 | 827df9f3 | balrog | |
955 | 827df9f3 | balrog | struct omap_gpif_s *gpif;
|
956 | 827df9f3 | balrog | |
957 | 827df9f3 | balrog | struct omap_mcspi_s *mcspi[2]; |
958 | 827df9f3 | balrog | |
959 | 827df9f3 | balrog | struct omap_dss_s *dss;
|
960 | 827df9f3 | balrog | }; |
961 | 827df9f3 | balrog | |
962 | 827df9f3 | balrog | /* omap1.c */
|
963 | 827df9f3 | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
964 | 827df9f3 | balrog | DisplayState *ds, const char *core); |
965 | 827df9f3 | balrog | |
966 | 827df9f3 | balrog | /* omap2.c */
|
967 | 827df9f3 | balrog | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
968 | c3d2689d | balrog | DisplayState *ds, const char *core); |
969 | c3d2689d | balrog | |
970 | c3d2689d | balrog | # if TARGET_PHYS_ADDR_BITS == 32 |
971 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08x" |
972 | c3d2689d | balrog | # elif TARGET_PHYS_ADDR_BITS == 64 |
973 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08" PRIx64 |
974 | c3d2689d | balrog | # else
|
975 | c3d2689d | balrog | # error TARGET_PHYS_ADDR_BITS undefined
|
976 | c3d2689d | balrog | # endif
|
977 | c3d2689d | balrog | |
978 | 9596ebb7 | pbrook | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
|
979 | 9596ebb7 | pbrook | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
980 | 9596ebb7 | pbrook | uint32_t value); |
981 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
982 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
983 | b30bb3a2 | balrog | uint32_t value); |
984 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
985 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
986 | b30bb3a2 | balrog | uint32_t value); |
987 | b30bb3a2 | balrog | |
988 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req); |
989 | 827df9f3 | balrog | |
990 | c3d2689d | balrog | # define OMAP_BAD_REG(paddr) \
|
991 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
992 | 827df9f3 | balrog | __FUNCTION__, paddr) |
993 | c3d2689d | balrog | # define OMAP_RO_REG(paddr) \
|
994 | 827df9f3 | balrog | fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ |
995 | c3d2689d | balrog | __FUNCTION__, paddr) |
996 | b854bc19 | balrog | |
997 | 827df9f3 | balrog | /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
|
998 | 827df9f3 | balrog | (Board-specifc tags are not here) */
|
999 | 827df9f3 | balrog | #define OMAP_TAG_CLOCK 0x4f01 |
1000 | 827df9f3 | balrog | #define OMAP_TAG_MMC 0x4f02 |
1001 | 827df9f3 | balrog | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
1002 | 827df9f3 | balrog | #define OMAP_TAG_USB 0x4f04 |
1003 | 827df9f3 | balrog | #define OMAP_TAG_LCD 0x4f05 |
1004 | 827df9f3 | balrog | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
1005 | 827df9f3 | balrog | #define OMAP_TAG_UART 0x4f07 |
1006 | 827df9f3 | balrog | #define OMAP_TAG_FBMEM 0x4f08 |
1007 | 827df9f3 | balrog | #define OMAP_TAG_STI_CONSOLE 0x4f09 |
1008 | 827df9f3 | balrog | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
1009 | 827df9f3 | balrog | #define OMAP_TAG_PARTITION 0x4f0b |
1010 | 827df9f3 | balrog | #define OMAP_TAG_TEA5761 0x4f10 |
1011 | 827df9f3 | balrog | #define OMAP_TAG_TMP105 0x4f11 |
1012 | 827df9f3 | balrog | #define OMAP_TAG_BOOT_REASON 0x4f80 |
1013 | 827df9f3 | balrog | #define OMAP_TAG_FLASH_PART_STR 0x4f81 |
1014 | 827df9f3 | balrog | #define OMAP_TAG_VERSION_STR 0x4f82 |
1015 | 827df9f3 | balrog | |
1016 | e927bb00 | balrog | enum {
|
1017 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
1018 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
1019 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
1020 | e927bb00 | balrog | }; |
1021 | e927bb00 | balrog | |
1022 | e927bb00 | balrog | #define OMAP_GPIOSW_INVERTED 0x0001 |
1023 | e927bb00 | balrog | #define OMAP_GPIOSW_OUTPUT 0x0002 |
1024 | e927bb00 | balrog | |
1025 | b854bc19 | balrog | # define TCMI_VERBOSE 1 |
1026 | d8f699cb | balrog | //# define MEM_VERBOSE 1
|
1027 | b854bc19 | balrog | |
1028 | b854bc19 | balrog | # ifdef TCMI_VERBOSE
|
1029 | b854bc19 | balrog | # define OMAP_8B_REG(paddr) \
|
1030 | 827df9f3 | balrog | fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ |
1031 | 66450b15 | balrog | __FUNCTION__, paddr) |
1032 | b854bc19 | balrog | # define OMAP_16B_REG(paddr) \
|
1033 | 827df9f3 | balrog | fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ |
1034 | c3d2689d | balrog | __FUNCTION__, paddr) |
1035 | b854bc19 | balrog | # define OMAP_32B_REG(paddr) \
|
1036 | 827df9f3 | balrog | fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ |
1037 | c3d2689d | balrog | __FUNCTION__, paddr) |
1038 | b854bc19 | balrog | # else
|
1039 | b854bc19 | balrog | # define OMAP_8B_REG(paddr)
|
1040 | b854bc19 | balrog | # define OMAP_16B_REG(paddr)
|
1041 | b854bc19 | balrog | # define OMAP_32B_REG(paddr)
|
1042 | b854bc19 | balrog | # endif
|
1043 | c3d2689d | balrog | |
1044 | cf965d24 | balrog | # define OMAP_MPUI_REG_MASK 0x000007ff |
1045 | cf965d24 | balrog | |
1046 | d8f699cb | balrog | # ifdef MEM_VERBOSE
|
1047 | d8f699cb | balrog | struct io_fn {
|
1048 | d8f699cb | balrog | CPUReadMemoryFunc **mem_read; |
1049 | d8f699cb | balrog | CPUWriteMemoryFunc **mem_write; |
1050 | d8f699cb | balrog | void *opaque;
|
1051 | d8f699cb | balrog | int in;
|
1052 | d8f699cb | balrog | }; |
1053 | d8f699cb | balrog | |
1054 | d8f699cb | balrog | static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
1055 | d8f699cb | balrog | { |
1056 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1057 | d8f699cb | balrog | uint32_t ret; |
1058 | d8f699cb | balrog | |
1059 | d8f699cb | balrog | s->in ++; |
1060 | d8f699cb | balrog | ret = s->mem_read[0](s->opaque, addr);
|
1061 | d8f699cb | balrog | s->in --; |
1062 | d8f699cb | balrog | if (!s->in)
|
1063 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
1064 | d8f699cb | balrog | return ret;
|
1065 | d8f699cb | balrog | } |
1066 | d8f699cb | balrog | static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
1067 | d8f699cb | balrog | { |
1068 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1069 | d8f699cb | balrog | uint32_t ret; |
1070 | d8f699cb | balrog | |
1071 | d8f699cb | balrog | s->in ++; |
1072 | d8f699cb | balrog | ret = s->mem_read[1](s->opaque, addr);
|
1073 | d8f699cb | balrog | s->in --; |
1074 | d8f699cb | balrog | if (!s->in)
|
1075 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
1076 | d8f699cb | balrog | return ret;
|
1077 | d8f699cb | balrog | } |
1078 | d8f699cb | balrog | static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
1079 | d8f699cb | balrog | { |
1080 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1081 | d8f699cb | balrog | uint32_t ret; |
1082 | d8f699cb | balrog | |
1083 | d8f699cb | balrog | s->in ++; |
1084 | d8f699cb | balrog | ret = s->mem_read[2](s->opaque, addr);
|
1085 | d8f699cb | balrog | s->in --; |
1086 | d8f699cb | balrog | if (!s->in)
|
1087 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
1088 | d8f699cb | balrog | return ret;
|
1089 | d8f699cb | balrog | } |
1090 | d8f699cb | balrog | static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
1091 | d8f699cb | balrog | { |
1092 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1093 | d8f699cb | balrog | |
1094 | d8f699cb | balrog | if (!s->in)
|
1095 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
1096 | d8f699cb | balrog | s->in ++; |
1097 | d8f699cb | balrog | s->mem_write[0](s->opaque, addr, value);
|
1098 | d8f699cb | balrog | s->in --; |
1099 | d8f699cb | balrog | } |
1100 | d8f699cb | balrog | static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
1101 | d8f699cb | balrog | { |
1102 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1103 | d8f699cb | balrog | |
1104 | d8f699cb | balrog | if (!s->in)
|
1105 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
1106 | d8f699cb | balrog | s->in ++; |
1107 | d8f699cb | balrog | s->mem_write[1](s->opaque, addr, value);
|
1108 | d8f699cb | balrog | s->in --; |
1109 | d8f699cb | balrog | } |
1110 | d8f699cb | balrog | static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
1111 | d8f699cb | balrog | { |
1112 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1113 | d8f699cb | balrog | |
1114 | d8f699cb | balrog | if (!s->in)
|
1115 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
1116 | d8f699cb | balrog | s->in ++; |
1117 | d8f699cb | balrog | s->mem_write[2](s->opaque, addr, value);
|
1118 | d8f699cb | balrog | s->in --; |
1119 | d8f699cb | balrog | } |
1120 | d8f699cb | balrog | |
1121 | d8f699cb | balrog | static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
|
1122 | d8f699cb | balrog | static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
|
1123 | d8f699cb | balrog | |
1124 | d8f699cb | balrog | inline static int debug_register_io_memory(int io_index, |
1125 | d8f699cb | balrog | CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, |
1126 | d8f699cb | balrog | void *opaque)
|
1127 | d8f699cb | balrog | { |
1128 | d8f699cb | balrog | struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
1129 | d8f699cb | balrog | |
1130 | d8f699cb | balrog | s->mem_read = mem_read; |
1131 | d8f699cb | balrog | s->mem_write = mem_write; |
1132 | d8f699cb | balrog | s->opaque = opaque; |
1133 | d8f699cb | balrog | s->in = 0;
|
1134 | d8f699cb | balrog | return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
|
1135 | d8f699cb | balrog | } |
1136 | d8f699cb | balrog | # define cpu_register_io_memory debug_register_io_memory
|
1137 | d8f699cb | balrog | # endif
|
1138 | d8f699cb | balrog | |
1139 | c66fb5bc | balrog | /* Define when we want to reduce the number of IO regions registered. */
|
1140 | c66fb5bc | balrog | # define L4_MUX_HACK
|
1141 | c66fb5bc | balrog | |
1142 | c66fb5bc | balrog | # ifdef L4_MUX_HACK
|
1143 | c66fb5bc | balrog | # undef l4_register_io_memory
|
1144 | c66fb5bc | balrog | int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, |
1145 | c66fb5bc | balrog | CPUWriteMemoryFunc **mem_write, void *opaque);
|
1146 | c66fb5bc | balrog | # endif
|
1147 | c66fb5bc | balrog | |
1148 | c3d2689d | balrog | #endif /* hw_omap_h */ |