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1 | 5fafdf24 | ths | /*
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2 | e69954b9 | pbrook | * Arm PrimeCell PL080/PL081 DMA controller
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3 | cdbdb648 | pbrook | *
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4 | cdbdb648 | pbrook | * Copyright (c) 2006 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "primecell.h" |
12 | cdbdb648 | pbrook | |
13 | e69954b9 | pbrook | #define PL080_MAX_CHANNELS 8 |
14 | cdbdb648 | pbrook | #define PL080_CONF_E 0x1 |
15 | cdbdb648 | pbrook | #define PL080_CONF_M1 0x2 |
16 | cdbdb648 | pbrook | #define PL080_CONF_M2 0x4 |
17 | cdbdb648 | pbrook | |
18 | cdbdb648 | pbrook | #define PL080_CCONF_H 0x40000 |
19 | cdbdb648 | pbrook | #define PL080_CCONF_A 0x20000 |
20 | cdbdb648 | pbrook | #define PL080_CCONF_L 0x10000 |
21 | cdbdb648 | pbrook | #define PL080_CCONF_ITC 0x08000 |
22 | cdbdb648 | pbrook | #define PL080_CCONF_IE 0x04000 |
23 | cdbdb648 | pbrook | #define PL080_CCONF_E 0x00001 |
24 | cdbdb648 | pbrook | |
25 | cdbdb648 | pbrook | #define PL080_CCTRL_I 0x80000000 |
26 | cdbdb648 | pbrook | #define PL080_CCTRL_DI 0x08000000 |
27 | cdbdb648 | pbrook | #define PL080_CCTRL_SI 0x04000000 |
28 | cdbdb648 | pbrook | #define PL080_CCTRL_D 0x02000000 |
29 | cdbdb648 | pbrook | #define PL080_CCTRL_S 0x01000000 |
30 | cdbdb648 | pbrook | |
31 | cdbdb648 | pbrook | typedef struct { |
32 | cdbdb648 | pbrook | uint32_t src; |
33 | cdbdb648 | pbrook | uint32_t dest; |
34 | cdbdb648 | pbrook | uint32_t lli; |
35 | cdbdb648 | pbrook | uint32_t ctrl; |
36 | cdbdb648 | pbrook | uint32_t conf; |
37 | cdbdb648 | pbrook | } pl080_channel; |
38 | cdbdb648 | pbrook | |
39 | cdbdb648 | pbrook | typedef struct { |
40 | cdbdb648 | pbrook | uint32_t base; |
41 | cdbdb648 | pbrook | uint8_t tc_int; |
42 | cdbdb648 | pbrook | uint8_t tc_mask; |
43 | cdbdb648 | pbrook | uint8_t err_int; |
44 | cdbdb648 | pbrook | uint8_t err_mask; |
45 | cdbdb648 | pbrook | uint32_t conf; |
46 | cdbdb648 | pbrook | uint32_t sync; |
47 | cdbdb648 | pbrook | uint32_t req_single; |
48 | cdbdb648 | pbrook | uint32_t req_burst; |
49 | e69954b9 | pbrook | pl080_channel chan[PL080_MAX_CHANNELS]; |
50 | e69954b9 | pbrook | int nchannels;
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51 | cdbdb648 | pbrook | /* Flag to avoid recursive DMA invocations. */
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52 | cdbdb648 | pbrook | int running;
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53 | d537cf6c | pbrook | qemu_irq irq; |
54 | cdbdb648 | pbrook | } pl080_state; |
55 | cdbdb648 | pbrook | |
56 | cdbdb648 | pbrook | static const unsigned char pl080_id[] = |
57 | cdbdb648 | pbrook | { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
58 | cdbdb648 | pbrook | |
59 | e69954b9 | pbrook | static const unsigned char pl081_id[] = |
60 | e69954b9 | pbrook | { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
61 | e69954b9 | pbrook | |
62 | cdbdb648 | pbrook | static void pl080_update(pl080_state *s) |
63 | cdbdb648 | pbrook | { |
64 | cdbdb648 | pbrook | if ((s->tc_int & s->tc_mask)
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65 | cdbdb648 | pbrook | || (s->err_int & s->err_mask)) |
66 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
67 | cdbdb648 | pbrook | else
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68 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
69 | cdbdb648 | pbrook | } |
70 | cdbdb648 | pbrook | |
71 | cdbdb648 | pbrook | static void pl080_run(pl080_state *s) |
72 | cdbdb648 | pbrook | { |
73 | cdbdb648 | pbrook | int c;
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74 | cdbdb648 | pbrook | int flow;
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75 | cdbdb648 | pbrook | pl080_channel *ch; |
76 | cdbdb648 | pbrook | int swidth;
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77 | cdbdb648 | pbrook | int dwidth;
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78 | cdbdb648 | pbrook | int xsize;
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79 | cdbdb648 | pbrook | int n;
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80 | cdbdb648 | pbrook | int src_id;
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81 | cdbdb648 | pbrook | int dest_id;
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82 | cdbdb648 | pbrook | int size;
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83 | cdbdb648 | pbrook | char buff[4]; |
84 | cdbdb648 | pbrook | uint32_t req; |
85 | cdbdb648 | pbrook | |
86 | cdbdb648 | pbrook | s->tc_mask = 0;
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87 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
88 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_ITC)
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89 | cdbdb648 | pbrook | s->tc_mask |= 1 << c;
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90 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_IE)
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91 | cdbdb648 | pbrook | s->err_mask |= 1 << c;
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92 | cdbdb648 | pbrook | } |
93 | cdbdb648 | pbrook | |
94 | cdbdb648 | pbrook | if ((s->conf & PL080_CONF_E) == 0) |
95 | cdbdb648 | pbrook | return;
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96 | cdbdb648 | pbrook | |
97 | cdbdb648 | pbrook | cpu_abort(cpu_single_env, "DMA active\n");
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98 | cdbdb648 | pbrook | /* If we are already in the middle of a DMA operation then indicate that
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99 | cdbdb648 | pbrook | there may be new DMA requests and return immediately. */
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100 | cdbdb648 | pbrook | if (s->running) {
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101 | cdbdb648 | pbrook | s->running++; |
102 | cdbdb648 | pbrook | return;
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103 | cdbdb648 | pbrook | } |
104 | cdbdb648 | pbrook | s->running = 1;
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105 | cdbdb648 | pbrook | while (s->running) {
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106 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
107 | cdbdb648 | pbrook | ch = &s->chan[c]; |
108 | cdbdb648 | pbrook | again:
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109 | cdbdb648 | pbrook | /* Test if thiws channel has any pending DMA requests. */
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110 | cdbdb648 | pbrook | if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
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111 | cdbdb648 | pbrook | != PL080_CCONF_E) |
112 | cdbdb648 | pbrook | continue;
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113 | cdbdb648 | pbrook | flow = (ch->conf >> 11) & 7; |
114 | cdbdb648 | pbrook | if (flow >= 4) { |
115 | 5fafdf24 | ths | cpu_abort(cpu_single_env, |
116 | cdbdb648 | pbrook | "pl080_run: Peripheral flow control not implemented\n");
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117 | cdbdb648 | pbrook | } |
118 | cdbdb648 | pbrook | src_id = (ch->conf >> 1) & 0x1f; |
119 | cdbdb648 | pbrook | dest_id = (ch->conf >> 6) & 0x1f; |
120 | cdbdb648 | pbrook | size = ch->ctrl & 0xfff;
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121 | cdbdb648 | pbrook | req = s->req_single | s->req_burst; |
122 | cdbdb648 | pbrook | switch (flow) {
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123 | cdbdb648 | pbrook | case 0: |
124 | cdbdb648 | pbrook | break;
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125 | cdbdb648 | pbrook | case 1: |
126 | cdbdb648 | pbrook | if ((req & (1u << dest_id)) == 0) |
127 | cdbdb648 | pbrook | size = 0;
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128 | cdbdb648 | pbrook | break;
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129 | cdbdb648 | pbrook | case 2: |
130 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0) |
131 | cdbdb648 | pbrook | size = 0;
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132 | cdbdb648 | pbrook | break;
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133 | cdbdb648 | pbrook | case 3: |
134 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0 |
135 | cdbdb648 | pbrook | || (req & (1u << dest_id)) == 0) |
136 | cdbdb648 | pbrook | size = 0;
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137 | cdbdb648 | pbrook | break;
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138 | cdbdb648 | pbrook | } |
139 | cdbdb648 | pbrook | if (!size)
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140 | cdbdb648 | pbrook | continue;
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141 | cdbdb648 | pbrook | |
142 | cdbdb648 | pbrook | /* Transfer one element. */
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143 | cdbdb648 | pbrook | /* ??? Should transfer multiple elements for a burst request. */
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144 | cdbdb648 | pbrook | /* ??? Unclear what the proper behavior is when source and
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145 | cdbdb648 | pbrook | destination widths are different. */
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146 | cdbdb648 | pbrook | swidth = 1 << ((ch->ctrl >> 18) & 7); |
147 | cdbdb648 | pbrook | dwidth = 1 << ((ch->ctrl >> 21) & 7); |
148 | cdbdb648 | pbrook | for (n = 0; n < dwidth; n+= swidth) { |
149 | cdbdb648 | pbrook | cpu_physical_memory_read(ch->src, buff + n, swidth); |
150 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_SI)
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151 | cdbdb648 | pbrook | ch->src += swidth; |
152 | cdbdb648 | pbrook | } |
153 | cdbdb648 | pbrook | xsize = (dwidth < swidth) ? swidth : dwidth; |
154 | cdbdb648 | pbrook | /* ??? This may pad the value incorrectly for dwidth < 32. */
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155 | cdbdb648 | pbrook | for (n = 0; n < xsize; n += dwidth) { |
156 | cdbdb648 | pbrook | cpu_physical_memory_write(ch->dest + n, buff + n, dwidth); |
157 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_DI)
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158 | cdbdb648 | pbrook | ch->dest += swidth; |
159 | cdbdb648 | pbrook | } |
160 | cdbdb648 | pbrook | |
161 | cdbdb648 | pbrook | size--; |
162 | cdbdb648 | pbrook | ch->ctrl = (ch->ctrl & 0xfffff000) | size;
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163 | cdbdb648 | pbrook | if (size == 0) { |
164 | cdbdb648 | pbrook | /* Transfer complete. */
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165 | cdbdb648 | pbrook | if (ch->lli) {
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166 | cdbdb648 | pbrook | ch->src = ldl_phys(ch->lli); |
167 | cdbdb648 | pbrook | ch->dest = ldl_phys(ch->lli + 4);
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168 | cdbdb648 | pbrook | ch->ctrl = ldl_phys(ch->lli + 12);
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169 | cdbdb648 | pbrook | ch->lli = ldl_phys(ch->lli + 8);
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170 | cdbdb648 | pbrook | } else {
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171 | cdbdb648 | pbrook | ch->conf &= ~PL080_CCONF_E; |
172 | cdbdb648 | pbrook | } |
173 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_I) {
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174 | cdbdb648 | pbrook | s->tc_int |= 1 << c;
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175 | cdbdb648 | pbrook | } |
176 | cdbdb648 | pbrook | } |
177 | cdbdb648 | pbrook | goto again;
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178 | cdbdb648 | pbrook | } |
179 | cdbdb648 | pbrook | if (--s->running)
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180 | cdbdb648 | pbrook | s->running = 1;
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181 | cdbdb648 | pbrook | } |
182 | cdbdb648 | pbrook | } |
183 | cdbdb648 | pbrook | |
184 | cdbdb648 | pbrook | static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) |
185 | cdbdb648 | pbrook | { |
186 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
187 | cdbdb648 | pbrook | uint32_t i; |
188 | cdbdb648 | pbrook | uint32_t mask; |
189 | cdbdb648 | pbrook | |
190 | cdbdb648 | pbrook | offset -= s->base; |
191 | cdbdb648 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) { |
192 | e69954b9 | pbrook | if (s->nchannels == 8) { |
193 | e69954b9 | pbrook | return pl080_id[(offset - 0xfe0) >> 2]; |
194 | e69954b9 | pbrook | } else {
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195 | e69954b9 | pbrook | return pl081_id[(offset - 0xfe0) >> 2]; |
196 | e69954b9 | pbrook | } |
197 | cdbdb648 | pbrook | } |
198 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
199 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
200 | e69954b9 | pbrook | if (i >= s->nchannels)
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201 | e69954b9 | pbrook | goto bad_offset;
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202 | cdbdb648 | pbrook | switch (offset >> 2) { |
203 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
204 | cdbdb648 | pbrook | return s->chan[i].src;
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205 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
206 | cdbdb648 | pbrook | return s->chan[i].dest;
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207 | cdbdb648 | pbrook | case 2: /* LLI */ |
208 | cdbdb648 | pbrook | return s->chan[i].lli;
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209 | cdbdb648 | pbrook | case 3: /* Control */ |
210 | cdbdb648 | pbrook | return s->chan[i].ctrl;
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211 | cdbdb648 | pbrook | case 4: /* Configuration */ |
212 | cdbdb648 | pbrook | return s->chan[i].conf;
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213 | cdbdb648 | pbrook | default:
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214 | cdbdb648 | pbrook | goto bad_offset;
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215 | cdbdb648 | pbrook | } |
216 | cdbdb648 | pbrook | } |
217 | cdbdb648 | pbrook | switch (offset >> 2) { |
218 | cdbdb648 | pbrook | case 0: /* IntStatus */ |
219 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
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220 | cdbdb648 | pbrook | case 1: /* IntTCStatus */ |
221 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask);
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222 | cdbdb648 | pbrook | case 3: /* IntErrorStatus */ |
223 | cdbdb648 | pbrook | return (s->err_int & s->err_mask);
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224 | cdbdb648 | pbrook | case 5: /* RawIntTCStatus */ |
225 | cdbdb648 | pbrook | return s->tc_int;
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226 | cdbdb648 | pbrook | case 6: /* RawIntErrorStatus */ |
227 | cdbdb648 | pbrook | return s->err_int;
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228 | cdbdb648 | pbrook | case 7: /* EnbldChns */ |
229 | cdbdb648 | pbrook | mask = 0;
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230 | e69954b9 | pbrook | for (i = 0; i < s->nchannels; i++) { |
231 | cdbdb648 | pbrook | if (s->chan[i].conf & PL080_CCONF_E)
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232 | cdbdb648 | pbrook | mask |= 1 << i;
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233 | cdbdb648 | pbrook | } |
234 | cdbdb648 | pbrook | return mask;
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235 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
236 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
237 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
238 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
239 | cdbdb648 | pbrook | /* ??? Implement these. */
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240 | cdbdb648 | pbrook | return 0; |
241 | cdbdb648 | pbrook | case 12: /* Configuration */ |
242 | cdbdb648 | pbrook | return s->conf;
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243 | cdbdb648 | pbrook | case 13: /* Sync */ |
244 | cdbdb648 | pbrook | return s->sync;
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245 | cdbdb648 | pbrook | default:
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246 | cdbdb648 | pbrook | bad_offset:
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247 | 4d1165fa | pbrook | cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset); |
248 | cdbdb648 | pbrook | return 0; |
249 | cdbdb648 | pbrook | } |
250 | cdbdb648 | pbrook | } |
251 | cdbdb648 | pbrook | |
252 | cdbdb648 | pbrook | static void pl080_write(void *opaque, target_phys_addr_t offset, |
253 | cdbdb648 | pbrook | uint32_t value) |
254 | cdbdb648 | pbrook | { |
255 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
256 | cdbdb648 | pbrook | int i;
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257 | cdbdb648 | pbrook | |
258 | cdbdb648 | pbrook | offset -= s->base; |
259 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
260 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
261 | e69954b9 | pbrook | if (i >= s->nchannels)
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262 | e69954b9 | pbrook | goto bad_offset;
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263 | cdbdb648 | pbrook | switch (offset >> 2) { |
264 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
265 | cdbdb648 | pbrook | s->chan[i].src = value; |
266 | cdbdb648 | pbrook | break;
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267 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
268 | cdbdb648 | pbrook | s->chan[i].dest = value; |
269 | cdbdb648 | pbrook | break;
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270 | cdbdb648 | pbrook | case 2: /* LLI */ |
271 | cdbdb648 | pbrook | s->chan[i].lli = value; |
272 | cdbdb648 | pbrook | break;
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273 | cdbdb648 | pbrook | case 3: /* Control */ |
274 | cdbdb648 | pbrook | s->chan[i].ctrl = value; |
275 | cdbdb648 | pbrook | break;
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276 | cdbdb648 | pbrook | case 4: /* Configuration */ |
277 | cdbdb648 | pbrook | s->chan[i].conf = value; |
278 | cdbdb648 | pbrook | pl080_run(s); |
279 | cdbdb648 | pbrook | break;
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280 | cdbdb648 | pbrook | } |
281 | cdbdb648 | pbrook | } |
282 | cdbdb648 | pbrook | switch (offset >> 2) { |
283 | cdbdb648 | pbrook | case 2: /* IntTCClear */ |
284 | cdbdb648 | pbrook | s->tc_int &= ~value; |
285 | cdbdb648 | pbrook | break;
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286 | cdbdb648 | pbrook | case 4: /* IntErrorClear */ |
287 | cdbdb648 | pbrook | s->err_int &= ~value; |
288 | cdbdb648 | pbrook | break;
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289 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
290 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
291 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
292 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
293 | cdbdb648 | pbrook | /* ??? Implement these. */
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294 | cdbdb648 | pbrook | cpu_abort(cpu_single_env, "pl080_write: Soft DMA not implemented\n");
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295 | cdbdb648 | pbrook | break;
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296 | cdbdb648 | pbrook | case 12: /* Configuration */ |
297 | cdbdb648 | pbrook | s->conf = value; |
298 | cdbdb648 | pbrook | if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
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299 | cdbdb648 | pbrook | cpu_abort(cpu_single_env, |
300 | cdbdb648 | pbrook | "pl080_write: Big-endian DMA not implemented\n");
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301 | cdbdb648 | pbrook | } |
302 | cdbdb648 | pbrook | pl080_run(s); |
303 | cdbdb648 | pbrook | break;
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304 | cdbdb648 | pbrook | case 13: /* Sync */ |
305 | cdbdb648 | pbrook | s->sync = value; |
306 | cdbdb648 | pbrook | break;
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307 | cdbdb648 | pbrook | default:
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308 | e69954b9 | pbrook | bad_offset:
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309 | 4d1165fa | pbrook | cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset); |
310 | cdbdb648 | pbrook | } |
311 | cdbdb648 | pbrook | pl080_update(s); |
312 | cdbdb648 | pbrook | } |
313 | cdbdb648 | pbrook | |
314 | cdbdb648 | pbrook | static CPUReadMemoryFunc *pl080_readfn[] = {
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315 | cdbdb648 | pbrook | pl080_read, |
316 | cdbdb648 | pbrook | pl080_read, |
317 | cdbdb648 | pbrook | pl080_read |
318 | cdbdb648 | pbrook | }; |
319 | cdbdb648 | pbrook | |
320 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *pl080_writefn[] = {
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321 | cdbdb648 | pbrook | pl080_write, |
322 | cdbdb648 | pbrook | pl080_write, |
323 | cdbdb648 | pbrook | pl080_write |
324 | cdbdb648 | pbrook | }; |
325 | cdbdb648 | pbrook | |
326 | e69954b9 | pbrook | /* The PL080 and PL081 are the same except for the number of channels
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327 | e69954b9 | pbrook | they implement (8 and 2 respectively). */
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328 | d537cf6c | pbrook | void *pl080_init(uint32_t base, qemu_irq irq, int nchannels) |
329 | cdbdb648 | pbrook | { |
330 | cdbdb648 | pbrook | int iomemtype;
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331 | cdbdb648 | pbrook | pl080_state *s; |
332 | cdbdb648 | pbrook | |
333 | cdbdb648 | pbrook | s = (pl080_state *)qemu_mallocz(sizeof(pl080_state));
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334 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, pl080_readfn,
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335 | cdbdb648 | pbrook | pl080_writefn, s); |
336 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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337 | cdbdb648 | pbrook | s->base = base; |
338 | cdbdb648 | pbrook | s->irq = irq; |
339 | e69954b9 | pbrook | s->nchannels = nchannels; |
340 | cdbdb648 | pbrook | /* ??? Save/restore. */
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341 | cdbdb648 | pbrook | return s;
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342 | cdbdb648 | pbrook | } |