root / hw / ppc / ppc_booke.c @ ab8131af
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1 | ddd1055b | Fabien Chouteau | /*
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2 | ddd1055b | Fabien Chouteau | * QEMU PowerPC Booke hardware System Emulator
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3 | ddd1055b | Fabien Chouteau | *
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4 | ddd1055b | Fabien Chouteau | * Copyright (c) 2011 AdaCore
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5 | ddd1055b | Fabien Chouteau | *
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6 | ddd1055b | Fabien Chouteau | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | ddd1055b | Fabien Chouteau | * of this software and associated documentation files (the "Software"), to deal
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8 | ddd1055b | Fabien Chouteau | * in the Software without restriction, including without limitation the rights
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9 | ddd1055b | Fabien Chouteau | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | ddd1055b | Fabien Chouteau | * copies of the Software, and to permit persons to whom the Software is
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11 | ddd1055b | Fabien Chouteau | * furnished to do so, subject to the following conditions:
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12 | ddd1055b | Fabien Chouteau | *
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13 | ddd1055b | Fabien Chouteau | * The above copyright notice and this permission notice shall be included in
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14 | ddd1055b | Fabien Chouteau | * all copies or substantial portions of the Software.
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15 | ddd1055b | Fabien Chouteau | *
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16 | ddd1055b | Fabien Chouteau | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | ddd1055b | Fabien Chouteau | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | ddd1055b | Fabien Chouteau | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | ddd1055b | Fabien Chouteau | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | ddd1055b | Fabien Chouteau | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | ddd1055b | Fabien Chouteau | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | ddd1055b | Fabien Chouteau | * THE SOFTWARE.
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23 | ddd1055b | Fabien Chouteau | */
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24 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
25 | 0d09e41a | Paolo Bonzini | #include "hw/ppc/ppc.h" |
26 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
27 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
28 | 0d09e41a | Paolo Bonzini | #include "hw/timer/m48t59.h" |
29 | 1de7afc9 | Paolo Bonzini | #include "qemu/log.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/loader.h" |
31 | 31f2cb8f | Bharat Bhushan | #include "kvm_ppc.h" |
32 | ddd1055b | Fabien Chouteau | |
33 | ddd1055b | Fabien Chouteau | |
34 | ddd1055b | Fabien Chouteau | /* Timer Control Register */
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35 | ddd1055b | Fabien Chouteau | |
36 | ddd1055b | Fabien Chouteau | #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ |
37 | ddd1055b | Fabien Chouteau | #define TCR_WP_MASK (0x3 << TCR_WP_SHIFT) |
38 | ddd1055b | Fabien Chouteau | #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ |
39 | ddd1055b | Fabien Chouteau | #define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT) |
40 | ddd1055b | Fabien Chouteau | #define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */ |
41 | ddd1055b | Fabien Chouteau | #define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */ |
42 | ddd1055b | Fabien Chouteau | #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ |
43 | ddd1055b | Fabien Chouteau | #define TCR_FP_MASK (0x3 << TCR_FP_SHIFT) |
44 | ddd1055b | Fabien Chouteau | #define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */ |
45 | ddd1055b | Fabien Chouteau | #define TCR_ARE (1 << 22) /* Auto-Reload Enable */ |
46 | ddd1055b | Fabien Chouteau | |
47 | ddd1055b | Fabien Chouteau | /* Timer Control Register (e500 specific fields) */
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48 | ddd1055b | Fabien Chouteau | |
49 | ddd1055b | Fabien Chouteau | #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ |
50 | ddd1055b | Fabien Chouteau | #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) |
51 | ddd1055b | Fabien Chouteau | #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ |
52 | ddd1055b | Fabien Chouteau | #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) |
53 | ddd1055b | Fabien Chouteau | |
54 | ddd1055b | Fabien Chouteau | /* Timer Status Register */
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55 | ddd1055b | Fabien Chouteau | |
56 | ddd1055b | Fabien Chouteau | #define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */ |
57 | ddd1055b | Fabien Chouteau | #define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */ |
58 | ddd1055b | Fabien Chouteau | #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ |
59 | ddd1055b | Fabien Chouteau | #define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT) |
60 | ddd1055b | Fabien Chouteau | #define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */ |
61 | ddd1055b | Fabien Chouteau | #define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */ |
62 | ddd1055b | Fabien Chouteau | |
63 | ddd1055b | Fabien Chouteau | typedef struct booke_timer_t booke_timer_t; |
64 | ddd1055b | Fabien Chouteau | struct booke_timer_t {
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65 | ddd1055b | Fabien Chouteau | |
66 | ddd1055b | Fabien Chouteau | uint64_t fit_next; |
67 | ddd1055b | Fabien Chouteau | struct QEMUTimer *fit_timer;
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68 | ddd1055b | Fabien Chouteau | |
69 | ddd1055b | Fabien Chouteau | uint64_t wdt_next; |
70 | ddd1055b | Fabien Chouteau | struct QEMUTimer *wdt_timer;
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71 | ddd1055b | Fabien Chouteau | |
72 | ddd1055b | Fabien Chouteau | uint32_t flags; |
73 | ddd1055b | Fabien Chouteau | }; |
74 | ddd1055b | Fabien Chouteau | |
75 | 7058581a | Andreas Färber | static void booke_update_irq(PowerPCCPU *cpu) |
76 | ddd1055b | Fabien Chouteau | { |
77 | 7058581a | Andreas Färber | CPUPPCState *env = &cpu->env; |
78 | 7058581a | Andreas Färber | |
79 | 7058581a | Andreas Färber | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, |
80 | ddd1055b | Fabien Chouteau | (env->spr[SPR_BOOKE_TSR] & TSR_DIS |
81 | ddd1055b | Fabien Chouteau | && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); |
82 | ddd1055b | Fabien Chouteau | |
83 | 7058581a | Andreas Färber | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, |
84 | ddd1055b | Fabien Chouteau | (env->spr[SPR_BOOKE_TSR] & TSR_WIS |
85 | ddd1055b | Fabien Chouteau | && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); |
86 | ddd1055b | Fabien Chouteau | |
87 | 7058581a | Andreas Färber | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, |
88 | ddd1055b | Fabien Chouteau | (env->spr[SPR_BOOKE_TSR] & TSR_FIS |
89 | ddd1055b | Fabien Chouteau | && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); |
90 | ddd1055b | Fabien Chouteau | } |
91 | ddd1055b | Fabien Chouteau | |
92 | ddd1055b | Fabien Chouteau | /* Return the location of the bit of time base at which the FIT will raise an
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93 | ddd1055b | Fabien Chouteau | interrupt */
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94 | e2684c0b | Andreas Färber | static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
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95 | ddd1055b | Fabien Chouteau | { |
96 | ddd1055b | Fabien Chouteau | uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; |
97 | ddd1055b | Fabien Chouteau | |
98 | ddd1055b | Fabien Chouteau | if (tb_env->flags & PPC_TIMER_E500) {
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99 | ddd1055b | Fabien Chouteau | /* e500 Fixed-interval timer period extension */
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100 | ddd1055b | Fabien Chouteau | uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) |
101 | ddd1055b | Fabien Chouteau | >> TCR_E500_FPEXT_SHIFT; |
102 | ddd1055b | Fabien Chouteau | fp = 63 - (fp | fpext << 2); |
103 | ddd1055b | Fabien Chouteau | } else {
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104 | ddd1055b | Fabien Chouteau | fp = env->fit_period[fp]; |
105 | ddd1055b | Fabien Chouteau | } |
106 | ddd1055b | Fabien Chouteau | |
107 | ddd1055b | Fabien Chouteau | return fp;
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108 | ddd1055b | Fabien Chouteau | } |
109 | ddd1055b | Fabien Chouteau | |
110 | ddd1055b | Fabien Chouteau | /* Return the location of the bit of time base at which the WDT will raise an
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111 | ddd1055b | Fabien Chouteau | interrupt */
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112 | e2684c0b | Andreas Färber | static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
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113 | ddd1055b | Fabien Chouteau | { |
114 | ddd1055b | Fabien Chouteau | uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; |
115 | ddd1055b | Fabien Chouteau | |
116 | ddd1055b | Fabien Chouteau | if (tb_env->flags & PPC_TIMER_E500) {
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117 | ddd1055b | Fabien Chouteau | /* e500 Watchdog timer period extension */
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118 | ddd1055b | Fabien Chouteau | uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) |
119 | ddd1055b | Fabien Chouteau | >> TCR_E500_WPEXT_SHIFT; |
120 | ddd1055b | Fabien Chouteau | wp = 63 - (wp | wpext << 2); |
121 | ddd1055b | Fabien Chouteau | } else {
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122 | ddd1055b | Fabien Chouteau | wp = env->wdt_period[wp]; |
123 | ddd1055b | Fabien Chouteau | } |
124 | ddd1055b | Fabien Chouteau | |
125 | ddd1055b | Fabien Chouteau | return wp;
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126 | ddd1055b | Fabien Chouteau | } |
127 | ddd1055b | Fabien Chouteau | |
128 | e2684c0b | Andreas Färber | static void booke_update_fixed_timer(CPUPPCState *env, |
129 | ddd1055b | Fabien Chouteau | uint8_t target_bit, |
130 | ddd1055b | Fabien Chouteau | uint64_t *next, |
131 | ddd1055b | Fabien Chouteau | struct QEMUTimer *timer)
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132 | ddd1055b | Fabien Chouteau | { |
133 | ddd1055b | Fabien Chouteau | ppc_tb_t *tb_env = env->tb_env; |
134 | ab8131af | Bharat Bhushan | uint64_t delta_tick, ticks = 0;
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135 | ddd1055b | Fabien Chouteau | uint64_t tb; |
136 | ab8131af | Bharat Bhushan | uint64_t period; |
137 | ddd1055b | Fabien Chouteau | uint64_t now; |
138 | ddd1055b | Fabien Chouteau | |
139 | ddd1055b | Fabien Chouteau | now = qemu_get_clock_ns(vm_clock); |
140 | ddd1055b | Fabien Chouteau | tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); |
141 | ab8131af | Bharat Bhushan | period = 1ULL << target_bit;
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142 | ab8131af | Bharat Bhushan | delta_tick = period - (tb & (period - 1));
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143 | ddd1055b | Fabien Chouteau | |
144 | ab8131af | Bharat Bhushan | /* the timer triggers only when the selected bit toggles from 0 to 1 */
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145 | ab8131af | Bharat Bhushan | if (tb & period) {
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146 | ab8131af | Bharat Bhushan | ticks = period; |
147 | ab8131af | Bharat Bhushan | } |
148 | ddd1055b | Fabien Chouteau | |
149 | ab8131af | Bharat Bhushan | if (ticks + delta_tick < ticks) {
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150 | ab8131af | Bharat Bhushan | /* Overflow, so assume the biggest number we can express. */
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151 | ab8131af | Bharat Bhushan | ticks = UINT64_MAX; |
152 | ab8131af | Bharat Bhushan | } else {
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153 | ab8131af | Bharat Bhushan | ticks += delta_tick; |
154 | ab8131af | Bharat Bhushan | } |
155 | ab8131af | Bharat Bhushan | |
156 | ab8131af | Bharat Bhushan | *next = now + muldiv64(ticks, get_ticks_per_sec(), tb_env->tb_freq); |
157 | ab8131af | Bharat Bhushan | if ((*next < now) || (*next > INT64_MAX)) {
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158 | ab8131af | Bharat Bhushan | /* Overflow, so assume the biggest number the qemu timer supports. */
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159 | ab8131af | Bharat Bhushan | *next = INT64_MAX; |
160 | ab8131af | Bharat Bhushan | } |
161 | ddd1055b | Fabien Chouteau | |
162 | ddd1055b | Fabien Chouteau | /* XXX: If expire time is now. We can't run the callback because we don't
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163 | ddd1055b | Fabien Chouteau | * have access to it. So we just set the timer one nanosecond later.
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164 | ddd1055b | Fabien Chouteau | */
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165 | ddd1055b | Fabien Chouteau | |
166 | ddd1055b | Fabien Chouteau | if (*next == now) {
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167 | ddd1055b | Fabien Chouteau | (*next)++; |
168 | ddd1055b | Fabien Chouteau | } |
169 | ddd1055b | Fabien Chouteau | |
170 | ddd1055b | Fabien Chouteau | qemu_mod_timer(timer, *next); |
171 | ddd1055b | Fabien Chouteau | } |
172 | ddd1055b | Fabien Chouteau | |
173 | ddd1055b | Fabien Chouteau | static void booke_decr_cb(void *opaque) |
174 | ddd1055b | Fabien Chouteau | { |
175 | ee0c98e6 | Andreas Färber | PowerPCCPU *cpu = opaque; |
176 | ee0c98e6 | Andreas Färber | CPUPPCState *env = &cpu->env; |
177 | ddd1055b | Fabien Chouteau | |
178 | ddd1055b | Fabien Chouteau | env->spr[SPR_BOOKE_TSR] |= TSR_DIS; |
179 | 7058581a | Andreas Färber | booke_update_irq(cpu); |
180 | ddd1055b | Fabien Chouteau | |
181 | ddd1055b | Fabien Chouteau | if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
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182 | ddd1055b | Fabien Chouteau | /* Auto Reload */
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183 | ddd1055b | Fabien Chouteau | cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); |
184 | ddd1055b | Fabien Chouteau | } |
185 | ddd1055b | Fabien Chouteau | } |
186 | ddd1055b | Fabien Chouteau | |
187 | ddd1055b | Fabien Chouteau | static void booke_fit_cb(void *opaque) |
188 | ddd1055b | Fabien Chouteau | { |
189 | ee0c98e6 | Andreas Färber | PowerPCCPU *cpu = opaque; |
190 | ee0c98e6 | Andreas Färber | CPUPPCState *env = &cpu->env; |
191 | ddd1055b | Fabien Chouteau | ppc_tb_t *tb_env; |
192 | ddd1055b | Fabien Chouteau | booke_timer_t *booke_timer; |
193 | ddd1055b | Fabien Chouteau | |
194 | ddd1055b | Fabien Chouteau | tb_env = env->tb_env; |
195 | ddd1055b | Fabien Chouteau | booke_timer = tb_env->opaque; |
196 | ddd1055b | Fabien Chouteau | env->spr[SPR_BOOKE_TSR] |= TSR_FIS; |
197 | ddd1055b | Fabien Chouteau | |
198 | 7058581a | Andreas Färber | booke_update_irq(cpu); |
199 | ddd1055b | Fabien Chouteau | |
200 | ddd1055b | Fabien Chouteau | booke_update_fixed_timer(env, |
201 | ddd1055b | Fabien Chouteau | booke_get_fit_target(env, tb_env), |
202 | ddd1055b | Fabien Chouteau | &booke_timer->fit_next, |
203 | ddd1055b | Fabien Chouteau | booke_timer->fit_timer); |
204 | ddd1055b | Fabien Chouteau | } |
205 | ddd1055b | Fabien Chouteau | |
206 | ddd1055b | Fabien Chouteau | static void booke_wdt_cb(void *opaque) |
207 | ddd1055b | Fabien Chouteau | { |
208 | ee0c98e6 | Andreas Färber | PowerPCCPU *cpu = opaque; |
209 | ee0c98e6 | Andreas Färber | CPUPPCState *env = &cpu->env; |
210 | ddd1055b | Fabien Chouteau | ppc_tb_t *tb_env; |
211 | ddd1055b | Fabien Chouteau | booke_timer_t *booke_timer; |
212 | ddd1055b | Fabien Chouteau | |
213 | ddd1055b | Fabien Chouteau | tb_env = env->tb_env; |
214 | ddd1055b | Fabien Chouteau | booke_timer = tb_env->opaque; |
215 | ddd1055b | Fabien Chouteau | |
216 | ddd1055b | Fabien Chouteau | /* TODO: There's lots of complicated stuff to do here */
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217 | ddd1055b | Fabien Chouteau | |
218 | 7058581a | Andreas Färber | booke_update_irq(cpu); |
219 | ddd1055b | Fabien Chouteau | |
220 | ddd1055b | Fabien Chouteau | booke_update_fixed_timer(env, |
221 | ddd1055b | Fabien Chouteau | booke_get_wdt_target(env, tb_env), |
222 | ddd1055b | Fabien Chouteau | &booke_timer->wdt_next, |
223 | ddd1055b | Fabien Chouteau | booke_timer->wdt_timer); |
224 | ddd1055b | Fabien Chouteau | } |
225 | ddd1055b | Fabien Chouteau | |
226 | e2684c0b | Andreas Färber | void store_booke_tsr(CPUPPCState *env, target_ulong val)
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227 | ddd1055b | Fabien Chouteau | { |
228 | 7058581a | Andreas Färber | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
229 | 7058581a | Andreas Färber | |
230 | ddd1055b | Fabien Chouteau | env->spr[SPR_BOOKE_TSR] &= ~val; |
231 | 31f2cb8f | Bharat Bhushan | kvmppc_clear_tsr_bits(cpu, val); |
232 | 7058581a | Andreas Färber | booke_update_irq(cpu); |
233 | ddd1055b | Fabien Chouteau | } |
234 | ddd1055b | Fabien Chouteau | |
235 | e2684c0b | Andreas Färber | void store_booke_tcr(CPUPPCState *env, target_ulong val)
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236 | ddd1055b | Fabien Chouteau | { |
237 | 7058581a | Andreas Färber | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
238 | ddd1055b | Fabien Chouteau | ppc_tb_t *tb_env = env->tb_env; |
239 | ddd1055b | Fabien Chouteau | booke_timer_t *booke_timer = tb_env->opaque; |
240 | ddd1055b | Fabien Chouteau | |
241 | ddd1055b | Fabien Chouteau | tb_env = env->tb_env; |
242 | ddd1055b | Fabien Chouteau | env->spr[SPR_BOOKE_TCR] = val; |
243 | 31f2cb8f | Bharat Bhushan | kvmppc_set_tcr(cpu); |
244 | ddd1055b | Fabien Chouteau | |
245 | 7058581a | Andreas Färber | booke_update_irq(cpu); |
246 | ddd1055b | Fabien Chouteau | |
247 | ddd1055b | Fabien Chouteau | booke_update_fixed_timer(env, |
248 | ddd1055b | Fabien Chouteau | booke_get_fit_target(env, tb_env), |
249 | ddd1055b | Fabien Chouteau | &booke_timer->fit_next, |
250 | ddd1055b | Fabien Chouteau | booke_timer->fit_timer); |
251 | ddd1055b | Fabien Chouteau | |
252 | ddd1055b | Fabien Chouteau | booke_update_fixed_timer(env, |
253 | ddd1055b | Fabien Chouteau | booke_get_wdt_target(env, tb_env), |
254 | ddd1055b | Fabien Chouteau | &booke_timer->wdt_next, |
255 | ddd1055b | Fabien Chouteau | booke_timer->wdt_timer); |
256 | ddd1055b | Fabien Chouteau | } |
257 | ddd1055b | Fabien Chouteau | |
258 | 88a78d90 | Bharat Bhushan | static void ppc_booke_timer_reset_handle(void *opaque) |
259 | 88a78d90 | Bharat Bhushan | { |
260 | 88a78d90 | Bharat Bhushan | PowerPCCPU *cpu = opaque; |
261 | 88a78d90 | Bharat Bhushan | CPUPPCState *env = &cpu->env; |
262 | 88a78d90 | Bharat Bhushan | |
263 | 31f2cb8f | Bharat Bhushan | store_booke_tcr(env, 0);
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264 | 31f2cb8f | Bharat Bhushan | store_booke_tsr(env, -1);
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265 | 31f2cb8f | Bharat Bhushan | } |
266 | 88a78d90 | Bharat Bhushan | |
267 | 31f2cb8f | Bharat Bhushan | /*
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268 | 31f2cb8f | Bharat Bhushan | * This function will be called whenever the CPU state changes.
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269 | 31f2cb8f | Bharat Bhushan | * CPU states are defined "typedef enum RunState".
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270 | 31f2cb8f | Bharat Bhushan | * Regarding timer, When CPU state changes to running after debug halt
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271 | 31f2cb8f | Bharat Bhushan | * or similar cases which takes time then in between final watchdog
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272 | 31f2cb8f | Bharat Bhushan | * expiry happenes. This will cause exit to QEMU and configured watchdog
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273 | 31f2cb8f | Bharat Bhushan | * action will be taken. To avoid this we always clear the watchdog state when
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274 | 31f2cb8f | Bharat Bhushan | * state changes to running.
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275 | 31f2cb8f | Bharat Bhushan | */
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276 | 31f2cb8f | Bharat Bhushan | static void cpu_state_change_handler(void *opaque, int running, RunState state) |
277 | 31f2cb8f | Bharat Bhushan | { |
278 | 31f2cb8f | Bharat Bhushan | PowerPCCPU *cpu = opaque; |
279 | 31f2cb8f | Bharat Bhushan | CPUPPCState *env = &cpu->env; |
280 | 31f2cb8f | Bharat Bhushan | |
281 | 31f2cb8f | Bharat Bhushan | if (!running) {
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282 | 31f2cb8f | Bharat Bhushan | return;
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283 | 31f2cb8f | Bharat Bhushan | } |
284 | 31f2cb8f | Bharat Bhushan | |
285 | 31f2cb8f | Bharat Bhushan | /*
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286 | 31f2cb8f | Bharat Bhushan | * Clear watchdog interrupt condition by clearing TSR.
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287 | 31f2cb8f | Bharat Bhushan | */
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288 | 31f2cb8f | Bharat Bhushan | store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); |
289 | 88a78d90 | Bharat Bhushan | } |
290 | 88a78d90 | Bharat Bhushan | |
291 | a34a92b9 | Andreas Färber | void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
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292 | ddd1055b | Fabien Chouteau | { |
293 | ddd1055b | Fabien Chouteau | ppc_tb_t *tb_env; |
294 | ddd1055b | Fabien Chouteau | booke_timer_t *booke_timer; |
295 | 31f2cb8f | Bharat Bhushan | int ret = 0; |
296 | ddd1055b | Fabien Chouteau | |
297 | ddd1055b | Fabien Chouteau | tb_env = g_malloc0(sizeof(ppc_tb_t));
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298 | ddd1055b | Fabien Chouteau | booke_timer = g_malloc0(sizeof(booke_timer_t));
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299 | ddd1055b | Fabien Chouteau | |
300 | a34a92b9 | Andreas Färber | cpu->env.tb_env = tb_env; |
301 | ddd1055b | Fabien Chouteau | tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; |
302 | ddd1055b | Fabien Chouteau | |
303 | ddd1055b | Fabien Chouteau | tb_env->tb_freq = freq; |
304 | ddd1055b | Fabien Chouteau | tb_env->decr_freq = freq; |
305 | ddd1055b | Fabien Chouteau | tb_env->opaque = booke_timer; |
306 | ee0c98e6 | Andreas Färber | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu); |
307 | ddd1055b | Fabien Chouteau | |
308 | ddd1055b | Fabien Chouteau | booke_timer->fit_timer = |
309 | ee0c98e6 | Andreas Färber | qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu); |
310 | ddd1055b | Fabien Chouteau | booke_timer->wdt_timer = |
311 | ee0c98e6 | Andreas Färber | qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu); |
312 | 88a78d90 | Bharat Bhushan | |
313 | 31f2cb8f | Bharat Bhushan | ret = kvmppc_booke_watchdog_enable(cpu); |
314 | 31f2cb8f | Bharat Bhushan | |
315 | 31f2cb8f | Bharat Bhushan | if (ret) {
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316 | 31f2cb8f | Bharat Bhushan | /* TODO: Start the QEMU emulated watchdog if not running on KVM.
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317 | 31f2cb8f | Bharat Bhushan | * Also start the QEMU emulated watchdog if KVM does not support
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318 | 31f2cb8f | Bharat Bhushan | * emulated watchdog or somehow it is not enabled (supported but
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319 | 31f2cb8f | Bharat Bhushan | * not enabled is though some bug and requires debugging :)).
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320 | 31f2cb8f | Bharat Bhushan | */
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321 | 31f2cb8f | Bharat Bhushan | } |
322 | 31f2cb8f | Bharat Bhushan | |
323 | 31f2cb8f | Bharat Bhushan | qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); |
324 | 31f2cb8f | Bharat Bhushan | |
325 | 88a78d90 | Bharat Bhushan | qemu_register_reset(ppc_booke_timer_reset_handle, cpu); |
326 | ddd1055b | Fabien Chouteau | } |