root / hw / omap_sdrc.c @ ab9adc88
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1 | 0bf43016 | cmchao | /*
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2 | 0bf43016 | cmchao | * TI OMAP SDRAM controller emulation.
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3 | 0bf43016 | cmchao | *
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4 | 0bf43016 | cmchao | * Copyright (C) 2007-2008 Nokia Corporation
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5 | 0bf43016 | cmchao | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 0bf43016 | cmchao | *
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7 | 0bf43016 | cmchao | * This program is free software; you can redistribute it and/or
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8 | 0bf43016 | cmchao | * modify it under the terms of the GNU General Public License as
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9 | 0bf43016 | cmchao | * published by the Free Software Foundation; either version 2 or
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10 | 0bf43016 | cmchao | * (at your option) any later version of the License.
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11 | 0bf43016 | cmchao | *
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12 | 0bf43016 | cmchao | * This program is distributed in the hope that it will be useful,
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13 | 0bf43016 | cmchao | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 0bf43016 | cmchao | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 0bf43016 | cmchao | * GNU General Public License for more details.
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16 | 0bf43016 | cmchao | *
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17 | 0bf43016 | cmchao | * You should have received a copy of the GNU General Public License along
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18 | 0bf43016 | cmchao | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 0bf43016 | cmchao | */
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20 | 0bf43016 | cmchao | #include "hw.h" |
21 | 0bf43016 | cmchao | #include "omap.h" |
22 | 0bf43016 | cmchao | |
23 | 0bf43016 | cmchao | /* SDRAM Controller Subsystem */
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24 | 0bf43016 | cmchao | struct omap_sdrc_s {
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25 | 0bf43016 | cmchao | uint8_t config; |
26 | 0bf43016 | cmchao | }; |
27 | 0bf43016 | cmchao | |
28 | 0bf43016 | cmchao | void omap_sdrc_reset(struct omap_sdrc_s *s) |
29 | 0bf43016 | cmchao | { |
30 | 0bf43016 | cmchao | s->config = 0x10;
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31 | 0bf43016 | cmchao | } |
32 | 0bf43016 | cmchao | |
33 | 0bf43016 | cmchao | static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) |
34 | 0bf43016 | cmchao | { |
35 | 0bf43016 | cmchao | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
36 | 0bf43016 | cmchao | |
37 | 0bf43016 | cmchao | switch (addr) {
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38 | 0bf43016 | cmchao | case 0x00: /* SDRC_REVISION */ |
39 | 0bf43016 | cmchao | return 0x20; |
40 | 0bf43016 | cmchao | |
41 | 0bf43016 | cmchao | case 0x10: /* SDRC_SYSCONFIG */ |
42 | 0bf43016 | cmchao | return s->config;
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43 | 0bf43016 | cmchao | |
44 | 0bf43016 | cmchao | case 0x14: /* SDRC_SYSSTATUS */ |
45 | 0bf43016 | cmchao | return 1; /* RESETDONE */ |
46 | 0bf43016 | cmchao | |
47 | 0bf43016 | cmchao | case 0x40: /* SDRC_CS_CFG */ |
48 | 0bf43016 | cmchao | case 0x44: /* SDRC_SHARING */ |
49 | 0bf43016 | cmchao | case 0x48: /* SDRC_ERR_ADDR */ |
50 | 0bf43016 | cmchao | case 0x4c: /* SDRC_ERR_TYPE */ |
51 | 0bf43016 | cmchao | case 0x60: /* SDRC_DLLA_SCTRL */ |
52 | 0bf43016 | cmchao | case 0x64: /* SDRC_DLLA_STATUS */ |
53 | 0bf43016 | cmchao | case 0x68: /* SDRC_DLLB_CTRL */ |
54 | 0bf43016 | cmchao | case 0x6c: /* SDRC_DLLB_STATUS */ |
55 | 0bf43016 | cmchao | case 0x70: /* SDRC_POWER */ |
56 | 0bf43016 | cmchao | case 0x80: /* SDRC_MCFG_0 */ |
57 | 0bf43016 | cmchao | case 0x84: /* SDRC_MR_0 */ |
58 | 0bf43016 | cmchao | case 0x88: /* SDRC_EMR1_0 */ |
59 | 0bf43016 | cmchao | case 0x8c: /* SDRC_EMR2_0 */ |
60 | 0bf43016 | cmchao | case 0x90: /* SDRC_EMR3_0 */ |
61 | 0bf43016 | cmchao | case 0x94: /* SDRC_DCDL1_CTRL */ |
62 | 0bf43016 | cmchao | case 0x98: /* SDRC_DCDL2_CTRL */ |
63 | 0bf43016 | cmchao | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
64 | 0bf43016 | cmchao | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
65 | 0bf43016 | cmchao | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
66 | 0bf43016 | cmchao | case 0xa8: /* SDRC_MANUAL_0 */ |
67 | 0bf43016 | cmchao | case 0xb0: /* SDRC_MCFG_1 */ |
68 | 0bf43016 | cmchao | case 0xb4: /* SDRC_MR_1 */ |
69 | 0bf43016 | cmchao | case 0xb8: /* SDRC_EMR1_1 */ |
70 | 0bf43016 | cmchao | case 0xbc: /* SDRC_EMR2_1 */ |
71 | 0bf43016 | cmchao | case 0xc0: /* SDRC_EMR3_1 */ |
72 | 0bf43016 | cmchao | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
73 | 0bf43016 | cmchao | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
74 | 0bf43016 | cmchao | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
75 | 0bf43016 | cmchao | case 0xd8: /* SDRC_MANUAL_1 */ |
76 | 0bf43016 | cmchao | return 0x00; |
77 | 0bf43016 | cmchao | } |
78 | 0bf43016 | cmchao | |
79 | 0bf43016 | cmchao | OMAP_BAD_REG(addr); |
80 | 0bf43016 | cmchao | return 0; |
81 | 0bf43016 | cmchao | } |
82 | 0bf43016 | cmchao | |
83 | 0bf43016 | cmchao | static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, |
84 | 0bf43016 | cmchao | uint32_t value) |
85 | 0bf43016 | cmchao | { |
86 | 0bf43016 | cmchao | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
87 | 0bf43016 | cmchao | |
88 | 0bf43016 | cmchao | switch (addr) {
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89 | 0bf43016 | cmchao | case 0x00: /* SDRC_REVISION */ |
90 | 0bf43016 | cmchao | case 0x14: /* SDRC_SYSSTATUS */ |
91 | 0bf43016 | cmchao | case 0x48: /* SDRC_ERR_ADDR */ |
92 | 0bf43016 | cmchao | case 0x64: /* SDRC_DLLA_STATUS */ |
93 | 0bf43016 | cmchao | case 0x6c: /* SDRC_DLLB_STATUS */ |
94 | 0bf43016 | cmchao | OMAP_RO_REG(addr); |
95 | 0bf43016 | cmchao | return;
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96 | 0bf43016 | cmchao | |
97 | 0bf43016 | cmchao | case 0x10: /* SDRC_SYSCONFIG */ |
98 | 0bf43016 | cmchao | if ((value >> 3) != 0x2) |
99 | 0bf43016 | cmchao | fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
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100 | 0bf43016 | cmchao | __FUNCTION__, value >> 3);
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101 | 0bf43016 | cmchao | if (value & 2) |
102 | 0bf43016 | cmchao | omap_sdrc_reset(s); |
103 | 0bf43016 | cmchao | s->config = value & 0x18;
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104 | 0bf43016 | cmchao | break;
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105 | 0bf43016 | cmchao | |
106 | 0bf43016 | cmchao | case 0x40: /* SDRC_CS_CFG */ |
107 | 0bf43016 | cmchao | case 0x44: /* SDRC_SHARING */ |
108 | 0bf43016 | cmchao | case 0x4c: /* SDRC_ERR_TYPE */ |
109 | 0bf43016 | cmchao | case 0x60: /* SDRC_DLLA_SCTRL */ |
110 | 0bf43016 | cmchao | case 0x68: /* SDRC_DLLB_CTRL */ |
111 | 0bf43016 | cmchao | case 0x70: /* SDRC_POWER */ |
112 | 0bf43016 | cmchao | case 0x80: /* SDRC_MCFG_0 */ |
113 | 0bf43016 | cmchao | case 0x84: /* SDRC_MR_0 */ |
114 | 0bf43016 | cmchao | case 0x88: /* SDRC_EMR1_0 */ |
115 | 0bf43016 | cmchao | case 0x8c: /* SDRC_EMR2_0 */ |
116 | 0bf43016 | cmchao | case 0x90: /* SDRC_EMR3_0 */ |
117 | 0bf43016 | cmchao | case 0x94: /* SDRC_DCDL1_CTRL */ |
118 | 0bf43016 | cmchao | case 0x98: /* SDRC_DCDL2_CTRL */ |
119 | 0bf43016 | cmchao | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
120 | 0bf43016 | cmchao | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
121 | 0bf43016 | cmchao | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
122 | 0bf43016 | cmchao | case 0xa8: /* SDRC_MANUAL_0 */ |
123 | 0bf43016 | cmchao | case 0xb0: /* SDRC_MCFG_1 */ |
124 | 0bf43016 | cmchao | case 0xb4: /* SDRC_MR_1 */ |
125 | 0bf43016 | cmchao | case 0xb8: /* SDRC_EMR1_1 */ |
126 | 0bf43016 | cmchao | case 0xbc: /* SDRC_EMR2_1 */ |
127 | 0bf43016 | cmchao | case 0xc0: /* SDRC_EMR3_1 */ |
128 | 0bf43016 | cmchao | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
129 | 0bf43016 | cmchao | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
130 | 0bf43016 | cmchao | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
131 | 0bf43016 | cmchao | case 0xd8: /* SDRC_MANUAL_1 */ |
132 | 0bf43016 | cmchao | break;
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133 | 0bf43016 | cmchao | |
134 | 0bf43016 | cmchao | default:
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135 | 0bf43016 | cmchao | OMAP_BAD_REG(addr); |
136 | 0bf43016 | cmchao | return;
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137 | 0bf43016 | cmchao | } |
138 | 0bf43016 | cmchao | } |
139 | 0bf43016 | cmchao | |
140 | 0bf43016 | cmchao | static CPUReadMemoryFunc * const omap_sdrc_readfn[] = { |
141 | 0bf43016 | cmchao | omap_badwidth_read32, |
142 | 0bf43016 | cmchao | omap_badwidth_read32, |
143 | 0bf43016 | cmchao | omap_sdrc_read, |
144 | 0bf43016 | cmchao | }; |
145 | 0bf43016 | cmchao | |
146 | 0bf43016 | cmchao | static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = { |
147 | 0bf43016 | cmchao | omap_badwidth_write32, |
148 | 0bf43016 | cmchao | omap_badwidth_write32, |
149 | 0bf43016 | cmchao | omap_sdrc_write, |
150 | 0bf43016 | cmchao | }; |
151 | 0bf43016 | cmchao | |
152 | 0bf43016 | cmchao | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
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153 | 0bf43016 | cmchao | { |
154 | 0bf43016 | cmchao | int iomemtype;
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155 | 0bf43016 | cmchao | struct omap_sdrc_s *s = (struct omap_sdrc_s *) |
156 | 0bf43016 | cmchao | qemu_mallocz(sizeof(struct omap_sdrc_s)); |
157 | 0bf43016 | cmchao | |
158 | 0bf43016 | cmchao | omap_sdrc_reset(s); |
159 | 0bf43016 | cmchao | |
160 | 0bf43016 | cmchao | iomemtype = cpu_register_io_memory(omap_sdrc_readfn, |
161 | 2507c12a | Alexander Graf | omap_sdrc_writefn, s, DEVICE_NATIVE_ENDIAN); |
162 | 0bf43016 | cmchao | cpu_register_physical_memory(base, 0x1000, iomemtype);
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163 | 0bf43016 | cmchao | |
164 | 0bf43016 | cmchao | return s;
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165 | 0bf43016 | cmchao | } |