root / m68k-dis.c @ abb6ae2c
History | View | Annotate | Download (211.6 kB)
1 | 48024e4a | bellard | /* This file is composed of several different files from the upstream
|
---|---|---|---|
2 | 48024e4a | bellard | sourceware.org CVS. Original file boundaries marked with **** */
|
3 | 48024e4a | bellard | |
4 | 48024e4a | bellard | #include <string.h> |
5 | 48024e4a | bellard | #include <math.h> |
6 | 48024e4a | bellard | #include <stdio.h> |
7 | 48024e4a | bellard | |
8 | 48024e4a | bellard | #include "dis-asm.h" |
9 | 48024e4a | bellard | |
10 | 1addc7c5 | aurel32 | /* **** floatformat.h from sourceware.org CVS 2005-08-14. */
|
11 | 48024e4a | bellard | /* IEEE floating point support declarations, for GDB, the GNU Debugger.
|
12 | 48024e4a | bellard | Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.
|
13 | 48024e4a | bellard | |
14 | 48024e4a | bellard | This file is part of GDB.
|
15 | 48024e4a | bellard | |
16 | 48024e4a | bellard | This program is free software; you can redistribute it and/or modify
|
17 | 48024e4a | bellard | it under the terms of the GNU General Public License as published by
|
18 | 48024e4a | bellard | the Free Software Foundation; either version 2 of the License, or
|
19 | 48024e4a | bellard | (at your option) any later version.
|
20 | 48024e4a | bellard | |
21 | 48024e4a | bellard | This program is distributed in the hope that it will be useful,
|
22 | 48024e4a | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
23 | 48024e4a | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
24 | 48024e4a | bellard | GNU General Public License for more details.
|
25 | 48024e4a | bellard | |
26 | 48024e4a | bellard | You should have received a copy of the GNU General Public License
|
27 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
28 | 48024e4a | bellard | |
29 | 48024e4a | bellard | #if !defined (FLOATFORMAT_H)
|
30 | 48024e4a | bellard | #define FLOATFORMAT_H 1 |
31 | 48024e4a | bellard | |
32 | 48024e4a | bellard | /*#include "ansidecl.h" */
|
33 | 48024e4a | bellard | |
34 | 48024e4a | bellard | /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
|
35 | 48024e4a | bellard | bytes are concatenated according to the byteorder flag, then each of those
|
36 | 48024e4a | bellard | fields is contiguous. We number the bits with 0 being the most significant
|
37 | 48024e4a | bellard | (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
|
38 | 48024e4a | bellard | contains with the *_start and *_len fields. */
|
39 | 48024e4a | bellard | |
40 | 48024e4a | bellard | /* What is the order of the bytes. */
|
41 | 48024e4a | bellard | |
42 | 48024e4a | bellard | enum floatformat_byteorders {
|
43 | 48024e4a | bellard | |
44 | 48024e4a | bellard | /* Standard little endian byte order.
|
45 | 48024e4a | bellard | EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
|
46 | 48024e4a | bellard | |
47 | 48024e4a | bellard | floatformat_little, |
48 | 48024e4a | bellard | |
49 | 48024e4a | bellard | /* Standard big endian byte order.
|
50 | 48024e4a | bellard | EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
|
51 | 48024e4a | bellard | |
52 | 48024e4a | bellard | floatformat_big, |
53 | 48024e4a | bellard | |
54 | 48024e4a | bellard | /* Little endian byte order but big endian word order.
|
55 | 48024e4a | bellard | EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
|
56 | 48024e4a | bellard | |
57 | 48024e4a | bellard | floatformat_littlebyte_bigword |
58 | 48024e4a | bellard | |
59 | 48024e4a | bellard | }; |
60 | 48024e4a | bellard | |
61 | 48024e4a | bellard | enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
|
62 | 48024e4a | bellard | |
63 | 48024e4a | bellard | struct floatformat
|
64 | 48024e4a | bellard | { |
65 | 48024e4a | bellard | enum floatformat_byteorders byteorder;
|
66 | 48024e4a | bellard | unsigned int totalsize; /* Total size of number in bits */ |
67 | 48024e4a | bellard | |
68 | 48024e4a | bellard | /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
|
69 | 48024e4a | bellard | unsigned int sign_start; |
70 | 48024e4a | bellard | |
71 | 48024e4a | bellard | unsigned int exp_start; |
72 | 48024e4a | bellard | unsigned int exp_len; |
73 | 48024e4a | bellard | /* Bias added to a "true" exponent to form the biased exponent. It
|
74 | 48024e4a | bellard | is intentionally signed as, otherwize, -exp_bias can turn into a
|
75 | 48024e4a | bellard | very large number (e.g., given the exp_bias of 0x3fff and a 64
|
76 | 48024e4a | bellard | bit long, the equation (long)(1 - exp_bias) evaluates to
|
77 | 48024e4a | bellard | 4294950914) instead of -16382). */
|
78 | 48024e4a | bellard | int exp_bias;
|
79 | 48024e4a | bellard | /* Exponent value which indicates NaN. This is the actual value stored in
|
80 | 48024e4a | bellard | the float, not adjusted by the exp_bias. This usually consists of all
|
81 | 48024e4a | bellard | one bits. */
|
82 | 48024e4a | bellard | unsigned int exp_nan; |
83 | 48024e4a | bellard | |
84 | 48024e4a | bellard | unsigned int man_start; |
85 | 48024e4a | bellard | unsigned int man_len; |
86 | 48024e4a | bellard | |
87 | 48024e4a | bellard | /* Is the integer bit explicit or implicit? */
|
88 | 48024e4a | bellard | enum floatformat_intbit intbit;
|
89 | 48024e4a | bellard | |
90 | 48024e4a | bellard | /* Internal name for debugging. */
|
91 | 48024e4a | bellard | const char *name; |
92 | 48024e4a | bellard | |
93 | 48024e4a | bellard | /* Validator method. */
|
94 | 48024e4a | bellard | int (*is_valid) (const struct floatformat *fmt, const char *from); |
95 | 48024e4a | bellard | }; |
96 | 48024e4a | bellard | |
97 | 48024e4a | bellard | /* floatformats for IEEE single and double, big and little endian. */
|
98 | 48024e4a | bellard | |
99 | 48024e4a | bellard | extern const struct floatformat floatformat_ieee_single_big; |
100 | 48024e4a | bellard | extern const struct floatformat floatformat_ieee_single_little; |
101 | 48024e4a | bellard | extern const struct floatformat floatformat_ieee_double_big; |
102 | 48024e4a | bellard | extern const struct floatformat floatformat_ieee_double_little; |
103 | 48024e4a | bellard | |
104 | 48024e4a | bellard | /* floatformat for ARM IEEE double, little endian bytes and big endian words */
|
105 | 48024e4a | bellard | |
106 | 48024e4a | bellard | extern const struct floatformat floatformat_ieee_double_littlebyte_bigword; |
107 | 48024e4a | bellard | |
108 | 48024e4a | bellard | /* floatformats for various extendeds. */
|
109 | 48024e4a | bellard | |
110 | 48024e4a | bellard | extern const struct floatformat floatformat_i387_ext; |
111 | 48024e4a | bellard | extern const struct floatformat floatformat_m68881_ext; |
112 | 48024e4a | bellard | extern const struct floatformat floatformat_i960_ext; |
113 | 48024e4a | bellard | extern const struct floatformat floatformat_m88110_ext; |
114 | 48024e4a | bellard | extern const struct floatformat floatformat_m88110_harris_ext; |
115 | 48024e4a | bellard | extern const struct floatformat floatformat_arm_ext_big; |
116 | 48024e4a | bellard | extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; |
117 | 48024e4a | bellard | /* IA-64 Floating Point register spilt into memory. */
|
118 | 48024e4a | bellard | extern const struct floatformat floatformat_ia64_spill_big; |
119 | 48024e4a | bellard | extern const struct floatformat floatformat_ia64_spill_little; |
120 | 48024e4a | bellard | extern const struct floatformat floatformat_ia64_quad_big; |
121 | 48024e4a | bellard | extern const struct floatformat floatformat_ia64_quad_little; |
122 | 48024e4a | bellard | |
123 | 48024e4a | bellard | /* Convert from FMT to a double.
|
124 | 48024e4a | bellard | FROM is the address of the extended float.
|
125 | 48024e4a | bellard | Store the double in *TO. */
|
126 | 48024e4a | bellard | |
127 | 48024e4a | bellard | extern void |
128 | 48024e4a | bellard | floatformat_to_double (const struct floatformat *, const char *, double *); |
129 | 48024e4a | bellard | |
130 | 48024e4a | bellard | /* The converse: convert the double *FROM to FMT
|
131 | 48024e4a | bellard | and store where TO points. */
|
132 | 48024e4a | bellard | |
133 | 48024e4a | bellard | extern void |
134 | 48024e4a | bellard | floatformat_from_double (const struct floatformat *, const double *, char *); |
135 | 48024e4a | bellard | |
136 | 48024e4a | bellard | /* Return non-zero iff the data at FROM is a valid number in format FMT. */
|
137 | 48024e4a | bellard | |
138 | 48024e4a | bellard | extern int |
139 | 48024e4a | bellard | floatformat_is_valid (const struct floatformat *fmt, const char *from); |
140 | 48024e4a | bellard | |
141 | 48024e4a | bellard | #endif /* defined (FLOATFORMAT_H) */ |
142 | 48024e4a | bellard | /* **** End of floatformat.h */
|
143 | 48024e4a | bellard | /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */
|
144 | 48024e4a | bellard | /* Opcode table header for m680[01234]0/m6888[12]/m68851.
|
145 | 48024e4a | bellard | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
|
146 | 48024e4a | bellard | 2003, 2004 Free Software Foundation, Inc.
|
147 | 48024e4a | bellard | |
148 | 48024e4a | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
149 | 48024e4a | bellard | |
150 | 48024e4a | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
151 | 48024e4a | bellard | them and/or modify them under the terms of the GNU General Public
|
152 | 48024e4a | bellard | License as published by the Free Software Foundation; either version
|
153 | 48024e4a | bellard | 1, or (at your option) any later version.
|
154 | 48024e4a | bellard | |
155 | 48024e4a | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
156 | 48024e4a | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
157 | 48024e4a | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
158 | 48024e4a | bellard | the GNU General Public License for more details.
|
159 | 48024e4a | bellard | |
160 | 48024e4a | bellard | You should have received a copy of the GNU General Public License
|
161 | 8167ee88 | Blue Swirl | along with this file; see the file COPYING. If not,
|
162 | 8167ee88 | Blue Swirl | see <http://www.gnu.org/licenses/>. */
|
163 | 48024e4a | bellard | |
164 | 48024e4a | bellard | /* These are used as bit flags for the arch field in the m68k_opcode
|
165 | 48024e4a | bellard | structure. */
|
166 | 48024e4a | bellard | #define _m68k_undef 0 |
167 | 48024e4a | bellard | #define m68000 0x001 |
168 | 48024e4a | bellard | #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ |
169 | 48024e4a | bellard | #define m68010 0x002 |
170 | 48024e4a | bellard | #define m68020 0x004 |
171 | 48024e4a | bellard | #define m68030 0x008 |
172 | 48024e4a | bellard | #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; |
173 | 48024e4a | bellard | gas will deal with the few differences. */
|
174 | 48024e4a | bellard | #define m68040 0x010 |
175 | 48024e4a | bellard | /* There is no 68050. */
|
176 | 48024e4a | bellard | #define m68060 0x020 |
177 | 48024e4a | bellard | #define m68881 0x040 |
178 | 48024e4a | bellard | #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ |
179 | 48024e4a | bellard | #define m68851 0x080 |
180 | 48024e4a | bellard | #define cpu32 0x100 /* e.g., 68332 */ |
181 | 48024e4a | bellard | |
182 | 48024e4a | bellard | #define mcfmac 0x200 /* ColdFire MAC. */ |
183 | 48024e4a | bellard | #define mcfemac 0x400 /* ColdFire EMAC. */ |
184 | 48024e4a | bellard | #define cfloat 0x800 /* ColdFire FPU. */ |
185 | 48024e4a | bellard | #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ |
186 | 48024e4a | bellard | |
187 | 48024e4a | bellard | #define mcfisa_a 0x2000 /* ColdFire ISA_A. */ |
188 | 48024e4a | bellard | #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ |
189 | 48024e4a | bellard | #define mcfisa_b 0x8000 /* ColdFire ISA_B. */ |
190 | 48024e4a | bellard | #define mcfusp 0x10000 /* ColdFire USP instructions. */ |
191 | 48024e4a | bellard | |
192 | 48024e4a | bellard | #define mcf5200 0x20000 |
193 | 48024e4a | bellard | #define mcf5206e 0x40000 |
194 | 48024e4a | bellard | #define mcf521x 0x80000 |
195 | 48024e4a | bellard | #define mcf5249 0x100000 |
196 | 48024e4a | bellard | #define mcf528x 0x200000 |
197 | 48024e4a | bellard | #define mcf5307 0x400000 |
198 | 48024e4a | bellard | #define mcf5407 0x800000 |
199 | 48024e4a | bellard | #define mcf5470 0x1000000 |
200 | 48024e4a | bellard | #define mcf5480 0x2000000 |
201 | 48024e4a | bellard | |
202 | 48024e4a | bellard | /* Handy aliases. */
|
203 | 48024e4a | bellard | #define m68040up (m68040 | m68060)
|
204 | 48024e4a | bellard | #define m68030up (m68030 | m68040up)
|
205 | 48024e4a | bellard | #define m68020up (m68020 | m68030up)
|
206 | 48024e4a | bellard | #define m68010up (m68010 | cpu32 | m68020up)
|
207 | 48024e4a | bellard | #define m68000up (m68000 | m68010up)
|
208 | 48024e4a | bellard | |
209 | 48024e4a | bellard | #define mfloat (m68881 | m68882 | m68040 | m68060)
|
210 | 48024e4a | bellard | #define mmmu (m68851 | m68030 | m68040 | m68060)
|
211 | 48024e4a | bellard | |
212 | 48024e4a | bellard | /* The structure used to hold information for an opcode. */
|
213 | 48024e4a | bellard | |
214 | 48024e4a | bellard | struct m68k_opcode
|
215 | 48024e4a | bellard | { |
216 | 48024e4a | bellard | /* The opcode name. */
|
217 | 48024e4a | bellard | const char *name; |
218 | 48024e4a | bellard | /* The pseudo-size of the instruction(in bytes). Used to determine
|
219 | 48024e4a | bellard | number of bytes necessary to disassemble the instruction. */
|
220 | 48024e4a | bellard | unsigned int size; |
221 | 48024e4a | bellard | /* The opcode itself. */
|
222 | 48024e4a | bellard | unsigned long opcode; |
223 | 48024e4a | bellard | /* The mask used by the disassembler. */
|
224 | 48024e4a | bellard | unsigned long match; |
225 | 48024e4a | bellard | /* The arguments. */
|
226 | 48024e4a | bellard | const char *args; |
227 | 48024e4a | bellard | /* The architectures which support this opcode. */
|
228 | 48024e4a | bellard | unsigned int arch; |
229 | 48024e4a | bellard | }; |
230 | 48024e4a | bellard | |
231 | 48024e4a | bellard | /* The structure used to hold information for an opcode alias. */
|
232 | 48024e4a | bellard | |
233 | 48024e4a | bellard | struct m68k_opcode_alias
|
234 | 48024e4a | bellard | { |
235 | 48024e4a | bellard | /* The alias name. */
|
236 | 48024e4a | bellard | const char *alias; |
237 | 48024e4a | bellard | /* The instruction for which this is an alias. */
|
238 | 48024e4a | bellard | const char *primary; |
239 | 48024e4a | bellard | }; |
240 | 48024e4a | bellard | |
241 | 48024e4a | bellard | /* We store four bytes of opcode for all opcodes because that is the
|
242 | 48024e4a | bellard | most any of them need. The actual length of an instruction is
|
243 | 48024e4a | bellard | always at least 2 bytes, and is as much longer as necessary to hold
|
244 | 48024e4a | bellard | the operands it has.
|
245 | 48024e4a | bellard | |
246 | 48024e4a | bellard | The match field is a mask saying which bits must match particular
|
247 | 48024e4a | bellard | opcode in order for an instruction to be an instance of that
|
248 | 48024e4a | bellard | opcode.
|
249 | 48024e4a | bellard | |
250 | 48024e4a | bellard | The args field is a string containing two characters for each
|
251 | 48024e4a | bellard | operand of the instruction. The first specifies the kind of
|
252 | 48024e4a | bellard | operand; the second, the place it is stored. */
|
253 | 48024e4a | bellard | |
254 | 48024e4a | bellard | /* Kinds of operands:
|
255 | 48024e4a | bellard | Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
|
256 | 48024e4a | bellard | |
257 | 48024e4a | bellard | D data register only. Stored as 3 bits.
|
258 | 48024e4a | bellard | A address register only. Stored as 3 bits.
|
259 | 48024e4a | bellard | a address register indirect only. Stored as 3 bits.
|
260 | 48024e4a | bellard | R either kind of register. Stored as 4 bits.
|
261 | 48024e4a | bellard | r either kind of register indirect only. Stored as 4 bits.
|
262 | 48024e4a | bellard | At the moment, used only for cas2 instruction.
|
263 | 48024e4a | bellard | F floating point coprocessor register only. Stored as 3 bits.
|
264 | 48024e4a | bellard | O an offset (or width): immediate data 0-31 or data register.
|
265 | 48024e4a | bellard | Stored as 6 bits in special format for BF... insns.
|
266 | 48024e4a | bellard | + autoincrement only. Stored as 3 bits (number of the address register).
|
267 | 48024e4a | bellard | - autodecrement only. Stored as 3 bits (number of the address register).
|
268 | 48024e4a | bellard | Q quick immediate data. Stored as 3 bits.
|
269 | 48024e4a | bellard | This matches an immediate operand only when value is in range 1 .. 8.
|
270 | 48024e4a | bellard | M moveq immediate data. Stored as 8 bits.
|
271 | 48024e4a | bellard | This matches an immediate operand only when value is in range -128..127
|
272 | 48024e4a | bellard | T trap vector immediate data. Stored as 4 bits.
|
273 | 48024e4a | bellard | |
274 | 48024e4a | bellard | k K-factor for fmove.p instruction. Stored as a 7-bit constant or
|
275 | 48024e4a | bellard | a three bit register offset, depending on the field type.
|
276 | 48024e4a | bellard | |
277 | 48024e4a | bellard | # immediate data. Stored in special places (b, w or l)
|
278 | 48024e4a | bellard | which say how many bits to store.
|
279 | 48024e4a | bellard | ^ immediate data for floating point instructions. Special places
|
280 | 48024e4a | bellard | are offset by 2 bytes from '#'...
|
281 | 48024e4a | bellard | B pc-relative address, converted to an offset
|
282 | 48024e4a | bellard | that is treated as immediate data.
|
283 | 48024e4a | bellard | d displacement and register. Stores the register as 3 bits
|
284 | 48024e4a | bellard | and stores the displacement in the entire second word.
|
285 | 48024e4a | bellard | |
286 | 48024e4a | bellard | C the CCR. No need to store it; this is just for filtering validity.
|
287 | 48024e4a | bellard | S the SR. No need to store, just as with CCR.
|
288 | 48024e4a | bellard | U the USP. No need to store, just as with CCR.
|
289 | 48024e4a | bellard | E the MAC ACC. No need to store, just as with CCR.
|
290 | 48024e4a | bellard | e the EMAC ACC[0123].
|
291 | 48024e4a | bellard | G the MAC/EMAC MACSR. No need to store, just as with CCR.
|
292 | 48024e4a | bellard | g the EMAC ACCEXT{01,23}.
|
293 | 48024e4a | bellard | H the MASK. No need to store, just as with CCR.
|
294 | 48024e4a | bellard | i the MAC/EMAC scale factor.
|
295 | 48024e4a | bellard | |
296 | 48024e4a | bellard | I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
|
297 | 48024e4a | bellard | extracted from the 'd' field of word one, which means that an extended
|
298 | 48024e4a | bellard | coprocessor opcode can be skipped using the 'i' place, if needed.
|
299 | 48024e4a | bellard | |
300 | 48024e4a | bellard | s System Control register for the floating point coprocessor.
|
301 | 48024e4a | bellard | |
302 | 48024e4a | bellard | J Misc register for movec instruction, stored in 'j' format.
|
303 | 48024e4a | bellard | Possible values:
|
304 | 48024e4a | bellard | 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
|
305 | 48024e4a | bellard | 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
|
306 | 48024e4a | bellard | 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
|
307 | 48024e4a | bellard | 0x003 TC MMU Translation Control [60, 40]
|
308 | 48024e4a | bellard | 0x004 ITT0 Instruction Transparent
|
309 | 48024e4a | bellard | Translation reg 0 [60, 40]
|
310 | 48024e4a | bellard | 0x005 ITT1 Instruction Transparent
|
311 | 48024e4a | bellard | Translation reg 1 [60, 40]
|
312 | 48024e4a | bellard | 0x006 DTT0 Data Transparent
|
313 | 48024e4a | bellard | Translation reg 0 [60, 40]
|
314 | 48024e4a | bellard | 0x007 DTT1 Data Transparent
|
315 | 48024e4a | bellard | Translation reg 1 [60, 40]
|
316 | 48024e4a | bellard | 0x008 BUSCR Bus Control Register [60]
|
317 | 48024e4a | bellard | 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
|
318 | 48024e4a | bellard | 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
|
319 | 48024e4a | bellard | 0x802 CAAR Cache Address Register [ 30, 20]
|
320 | 48024e4a | bellard | 0x803 MSP Master Stack Pointer [ 40, 30, 20]
|
321 | 48024e4a | bellard | 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
|
322 | 48024e4a | bellard | 0x805 MMUSR MMU Status reg [ 40]
|
323 | 48024e4a | bellard | 0x806 URP User Root Pointer [60, 40]
|
324 | 48024e4a | bellard | 0x807 SRP Supervisor Root Pointer [60, 40]
|
325 | 48024e4a | bellard | 0x808 PCR Processor Configuration reg [60]
|
326 | 48024e4a | bellard | 0xC00 ROMBAR ROM Base Address Register [520X]
|
327 | 48024e4a | bellard | 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
|
328 | 48024e4a | bellard | 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
|
329 | 48024e4a | bellard | 0xC0F MBAR0 RAM Base Address Register 0 [520X]
|
330 | 48024e4a | bellard | 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
|
331 | 48024e4a | bellard | 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
|
332 | 48024e4a | bellard | |
333 | 48024e4a | bellard | L Register list of the type d0-d7/a0-a7 etc.
|
334 | 48024e4a | bellard | (New! Improved! Can also hold fp0-fp7, as well!)
|
335 | 48024e4a | bellard | The assembler tries to see if the registers match the insn by
|
336 | 48024e4a | bellard | looking at where the insn wants them stored.
|
337 | 48024e4a | bellard | |
338 | 48024e4a | bellard | l Register list like L, but with all the bits reversed.
|
339 | 48024e4a | bellard | Used for going the other way. . .
|
340 | 48024e4a | bellard | |
341 | 48024e4a | bellard | c cache identifier which may be "nc" for no cache, "ic"
|
342 | 48024e4a | bellard | for instruction cache, "dc" for data cache, or "bc"
|
343 | 48024e4a | bellard | for both caches. Used in cinv and cpush. Always
|
344 | 48024e4a | bellard | stored in position "d".
|
345 | 48024e4a | bellard | |
346 | 48024e4a | bellard | u Any register, with ``upper'' or ``lower'' specification. Used
|
347 | 48024e4a | bellard | in the mac instructions with size word.
|
348 | 48024e4a | bellard | |
349 | 48024e4a | bellard | The remainder are all stored as 6 bits using an address mode and a
|
350 | 48024e4a | bellard | register number; they differ in which addressing modes they match.
|
351 | 48024e4a | bellard | |
352 | 48024e4a | bellard | * all (modes 0-6,7.0-4)
|
353 | 48024e4a | bellard | ~ alterable memory (modes 2-6,7.0,7.1)
|
354 | 48024e4a | bellard | (not 0,1,7.2-4)
|
355 | 48024e4a | bellard | % alterable (modes 0-6,7.0,7.1)
|
356 | 48024e4a | bellard | (not 7.2-4)
|
357 | 48024e4a | bellard | ; data (modes 0,2-6,7.0-4)
|
358 | 48024e4a | bellard | (not 1)
|
359 | 48024e4a | bellard | @ data, but not immediate (modes 0,2-6,7.0-3)
|
360 | 48024e4a | bellard | (not 1,7.4)
|
361 | 48024e4a | bellard | ! control (modes 2,5,6,7.0-3)
|
362 | 48024e4a | bellard | (not 0,1,3,4,7.4)
|
363 | 48024e4a | bellard | & alterable control (modes 2,5,6,7.0,7.1)
|
364 | 48024e4a | bellard | (not 0,1,3,4,7.2-4)
|
365 | 48024e4a | bellard | $ alterable data (modes 0,2-6,7.0,7.1)
|
366 | 48024e4a | bellard | (not 1,7.2-4)
|
367 | 48024e4a | bellard | ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
|
368 | 48024e4a | bellard | (not 1,3,4,7.2-4)
|
369 | 48024e4a | bellard | / control, or data register (modes 0,2,5,6,7.0-3)
|
370 | 48024e4a | bellard | (not 1,3,4,7.4)
|
371 | 48024e4a | bellard | > *save operands (modes 2,4,5,6,7.0,7.1)
|
372 | 48024e4a | bellard | (not 0,1,3,7.2-4)
|
373 | 48024e4a | bellard | < *restore operands (modes 2,3,5,6,7.0-3)
|
374 | 48024e4a | bellard | (not 0,1,4,7.4)
|
375 | 48024e4a | bellard | |
376 | 48024e4a | bellard | coldfire move operands:
|
377 | 48024e4a | bellard | m (modes 0-4)
|
378 | 48024e4a | bellard | n (modes 5,7.2)
|
379 | 48024e4a | bellard | o (modes 6,7.0,7.1,7.3,7.4)
|
380 | 48024e4a | bellard | p (modes 0-5)
|
381 | 48024e4a | bellard | |
382 | 48024e4a | bellard | coldfire bset/bclr/btst/mulsl/mulul operands:
|
383 | 48024e4a | bellard | q (modes 0,2-5)
|
384 | 48024e4a | bellard | v (modes 0,2-5,7.0,7.1)
|
385 | 48024e4a | bellard | b (modes 0,2-5,7.2)
|
386 | 48024e4a | bellard | w (modes 2-5,7.2)
|
387 | 48024e4a | bellard | y (modes 2,5)
|
388 | 48024e4a | bellard | z (modes 2,5,7.2)
|
389 | 48024e4a | bellard | x mov3q immediate operand.
|
390 | 48024e4a | bellard | 4 (modes 2,3,4,5)
|
391 | 48024e4a | bellard | */
|
392 | 48024e4a | bellard | |
393 | 48024e4a | bellard | /* For the 68851: */
|
394 | 48024e4a | bellard | /* I didn't use much imagination in choosing the
|
395 | 48024e4a | bellard | following codes, so many of them aren't very
|
396 | 48024e4a | bellard | mnemonic. -rab
|
397 | 48024e4a | bellard | |
398 | 48024e4a | bellard | 0 32 bit pmmu register
|
399 | 48024e4a | bellard | Possible values:
|
400 | 48024e4a | bellard | 000 TC Translation Control Register (68030, 68851)
|
401 | 48024e4a | bellard | |
402 | 48024e4a | bellard | 1 16 bit pmmu register
|
403 | 48024e4a | bellard | 111 AC Access Control (68851)
|
404 | 48024e4a | bellard | |
405 | 48024e4a | bellard | 2 8 bit pmmu register
|
406 | 48024e4a | bellard | 100 CAL Current Access Level (68851)
|
407 | 48024e4a | bellard | 101 VAL Validate Access Level (68851)
|
408 | 48024e4a | bellard | 110 SCC Stack Change Control (68851)
|
409 | 48024e4a | bellard | |
410 | 48024e4a | bellard | 3 68030-only pmmu registers (32 bit)
|
411 | 48024e4a | bellard | 010 TT0 Transparent Translation reg 0
|
412 | 48024e4a | bellard | (aka Access Control reg 0 -- AC0 -- on 68ec030)
|
413 | 48024e4a | bellard | 011 TT1 Transparent Translation reg 1
|
414 | 48024e4a | bellard | (aka Access Control reg 1 -- AC1 -- on 68ec030)
|
415 | 48024e4a | bellard | |
416 | 48024e4a | bellard | W wide pmmu registers
|
417 | 48024e4a | bellard | Possible values:
|
418 | 48024e4a | bellard | 001 DRP Dma Root Pointer (68851)
|
419 | 48024e4a | bellard | 010 SRP Supervisor Root Pointer (68030, 68851)
|
420 | 48024e4a | bellard | 011 CRP Cpu Root Pointer (68030, 68851)
|
421 | 48024e4a | bellard | |
422 | 48024e4a | bellard | f function code register (68030, 68851)
|
423 | 48024e4a | bellard | 0 SFC
|
424 | 48024e4a | bellard | 1 DFC
|
425 | 48024e4a | bellard | |
426 | 48024e4a | bellard | V VAL register only (68851)
|
427 | 48024e4a | bellard | |
428 | 48024e4a | bellard | X BADx, BACx (16 bit)
|
429 | 48024e4a | bellard | 100 BAD Breakpoint Acknowledge Data (68851)
|
430 | 48024e4a | bellard | 101 BAC Breakpoint Acknowledge Control (68851)
|
431 | 48024e4a | bellard | |
432 | 48024e4a | bellard | Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
|
433 | 48024e4a | bellard | Z PCSR (68851)
|
434 | 48024e4a | bellard | |
435 | 48024e4a | bellard | | memory (modes 2-6, 7.*)
|
436 | 48024e4a | bellard | |
437 | 48024e4a | bellard | t address test level (68030 only)
|
438 | 48024e4a | bellard | Stored as 3 bits, range 0-7.
|
439 | 48024e4a | bellard | Also used for breakpoint instruction now.
|
440 | 48024e4a | bellard | |
441 | 48024e4a | bellard | */
|
442 | 48024e4a | bellard | |
443 | 48024e4a | bellard | /* Places to put an operand, for non-general operands:
|
444 | 48024e4a | bellard | Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
|
445 | 48024e4a | bellard | |
446 | 48024e4a | bellard | s source, low bits of first word.
|
447 | 48024e4a | bellard | d dest, shifted 9 in first word
|
448 | 48024e4a | bellard | 1 second word, shifted 12
|
449 | 48024e4a | bellard | 2 second word, shifted 6
|
450 | 48024e4a | bellard | 3 second word, shifted 0
|
451 | 48024e4a | bellard | 4 third word, shifted 12
|
452 | 48024e4a | bellard | 5 third word, shifted 6
|
453 | 48024e4a | bellard | 6 third word, shifted 0
|
454 | 48024e4a | bellard | 7 second word, shifted 7
|
455 | 48024e4a | bellard | 8 second word, shifted 10
|
456 | 48024e4a | bellard | 9 second word, shifted 5
|
457 | 48024e4a | bellard | D store in both place 1 and place 3; for divul and divsl.
|
458 | 48024e4a | bellard | B first word, low byte, for branch displacements
|
459 | 48024e4a | bellard | W second word (entire), for branch displacements
|
460 | 48024e4a | bellard | L second and third words (entire), for branch displacements
|
461 | 48024e4a | bellard | (also overloaded for move16)
|
462 | 48024e4a | bellard | b second word, low byte
|
463 | 48024e4a | bellard | w second word (entire) [variable word/long branch offset for dbra]
|
464 | 48024e4a | bellard | W second word (entire) (must be signed 16 bit value)
|
465 | 48024e4a | bellard | l second and third word (entire)
|
466 | 48024e4a | bellard | g variable branch offset for bra and similar instructions.
|
467 | 48024e4a | bellard | The place to store depends on the magnitude of offset.
|
468 | 48024e4a | bellard | t store in both place 7 and place 8; for floating point operations
|
469 | 48024e4a | bellard | c branch offset for cpBcc operations.
|
470 | 48024e4a | bellard | The place to store is word two if bit six of word one is zero,
|
471 | 48024e4a | bellard | and words two and three if bit six of word one is one.
|
472 | 48024e4a | bellard | i Increment by two, to skip over coprocessor extended operands. Only
|
473 | 48024e4a | bellard | works with the 'I' format.
|
474 | 48024e4a | bellard | k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
|
475 | 48024e4a | bellard | Also used for dynamic fmovem instruction.
|
476 | 48024e4a | bellard | C floating point coprocessor constant - 7 bits. Also used for static
|
477 | 48024e4a | bellard | K-factors...
|
478 | 48024e4a | bellard | j Movec register #, stored in 12 low bits of second word.
|
479 | 48024e4a | bellard | m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
|
480 | 48024e4a | bellard | and remaining 3 bits of register shifted 9 bits in first word.
|
481 | 48024e4a | bellard | Indicate upper/lower in 1 bit shifted 7 bits in second word.
|
482 | 48024e4a | bellard | Use with `R' or `u' format.
|
483 | 48024e4a | bellard | n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
|
484 | 48024e4a | bellard | with MSB shifted 6 bits in first word and remaining 3 bits of
|
485 | 48024e4a | bellard | register shifted 9 bits in first word. No upper/lower
|
486 | 48024e4a | bellard | indication is done.) Use with `R' or `u' format.
|
487 | 48024e4a | bellard | o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
|
488 | 48024e4a | bellard | Indicate upper/lower in 1 bit shifted 7 bits in second word.
|
489 | 48024e4a | bellard | Use with `R' or `u' format.
|
490 | 48024e4a | bellard | M For M[S]ACw; 4 bits in low bits of first word. Indicate
|
491 | 48024e4a | bellard | upper/lower in 1 bit shifted 6 bits in second word. Use with
|
492 | 48024e4a | bellard | `R' or `u' format.
|
493 | 48024e4a | bellard | N For M[S]ACw; 4 bits in low bits of second word. Indicate
|
494 | 48024e4a | bellard | upper/lower in 1 bit shifted 6 bits in second word. Use with
|
495 | 48024e4a | bellard | `R' or `u' format.
|
496 | 48024e4a | bellard | h shift indicator (scale factor), 1 bit shifted 10 in second word
|
497 | 48024e4a | bellard | |
498 | 48024e4a | bellard | Places to put operand, for general operands:
|
499 | 48024e4a | bellard | d destination, shifted 6 bits in first word
|
500 | 48024e4a | bellard | b source, at low bit of first word, and immediate uses one byte
|
501 | 48024e4a | bellard | w source, at low bit of first word, and immediate uses two bytes
|
502 | 48024e4a | bellard | l source, at low bit of first word, and immediate uses four bytes
|
503 | 48024e4a | bellard | s source, at low bit of first word.
|
504 | 48024e4a | bellard | Used sometimes in contexts where immediate is not allowed anyway.
|
505 | 48024e4a | bellard | f single precision float, low bit of 1st word, immediate uses 4 bytes
|
506 | 48024e4a | bellard | F double precision float, low bit of 1st word, immediate uses 8 bytes
|
507 | 48024e4a | bellard | x extended precision float, low bit of 1st word, immediate uses 12 bytes
|
508 | 48024e4a | bellard | p packed float, low bit of 1st word, immediate uses 12 bytes
|
509 | 48024e4a | bellard | G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
|
510 | 48024e4a | bellard | H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
|
511 | 48024e4a | bellard | F EMAC ACCx
|
512 | 48024e4a | bellard | f EMAC ACCy
|
513 | 48024e4a | bellard | I MAC/EMAC scale factor
|
514 | 48024e4a | bellard | / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
|
515 | 48024e4a | bellard | ] first word, bit 10
|
516 | 48024e4a | bellard | */
|
517 | 48024e4a | bellard | |
518 | 48024e4a | bellard | extern const struct m68k_opcode m68k_opcodes[]; |
519 | 48024e4a | bellard | extern const struct m68k_opcode_alias m68k_opcode_aliases[]; |
520 | 48024e4a | bellard | |
521 | 48024e4a | bellard | extern const int m68k_numopcodes, m68k_numaliases; |
522 | 48024e4a | bellard | |
523 | 48024e4a | bellard | /* **** End of m68k-opcode.h */
|
524 | 48024e4a | bellard | /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */
|
525 | 48024e4a | bellard | /* Print Motorola 68k instructions.
|
526 | 48024e4a | bellard | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
|
527 | 48024e4a | bellard | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
|
528 | 48024e4a | bellard | Free Software Foundation, Inc.
|
529 | 48024e4a | bellard | |
530 | 48024e4a | bellard | This file is free software; you can redistribute it and/or modify
|
531 | 48024e4a | bellard | it under the terms of the GNU General Public License as published by
|
532 | 48024e4a | bellard | the Free Software Foundation; either version 2 of the License, or
|
533 | 48024e4a | bellard | (at your option) any later version.
|
534 | 48024e4a | bellard | |
535 | 48024e4a | bellard | This program is distributed in the hope that it will be useful,
|
536 | 48024e4a | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
537 | 48024e4a | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
538 | 48024e4a | bellard | GNU General Public License for more details.
|
539 | 48024e4a | bellard | |
540 | 48024e4a | bellard | You should have received a copy of the GNU General Public License
|
541 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
542 | 48024e4a | bellard | |
543 | 48024e4a | bellard | /* Local function prototypes. */
|
544 | 48024e4a | bellard | |
545 | 7ccfb2eb | blueswir1 | static const char * const fpcr_names[] = |
546 | 48024e4a | bellard | { |
547 | 48024e4a | bellard | "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", |
548 | 48024e4a | bellard | "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" |
549 | 48024e4a | bellard | }; |
550 | 48024e4a | bellard | |
551 | 7ccfb2eb | blueswir1 | static const char *const reg_names[] = |
552 | 48024e4a | bellard | { |
553 | 48024e4a | bellard | "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", |
554 | 48024e4a | bellard | "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", |
555 | 48024e4a | bellard | "%ps", "%pc" |
556 | 48024e4a | bellard | }; |
557 | 48024e4a | bellard | |
558 | 48024e4a | bellard | /* Name of register halves for MAC/EMAC.
|
559 | aa1f17c1 | ths | Separate from reg_names since 'spu', 'fpl' look weird. */
|
560 | 7ccfb2eb | blueswir1 | static const char *const reg_half_names[] = |
561 | 48024e4a | bellard | { |
562 | 48024e4a | bellard | "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", |
563 | 48024e4a | bellard | "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", |
564 | 48024e4a | bellard | "%ps", "%pc" |
565 | 48024e4a | bellard | }; |
566 | 48024e4a | bellard | |
567 | 48024e4a | bellard | /* Sign-extend an (unsigned char). */
|
568 | 48024e4a | bellard | #if __STDC__ == 1 |
569 | 48024e4a | bellard | #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) |
570 | 48024e4a | bellard | #else
|
571 | 48024e4a | bellard | #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) |
572 | 48024e4a | bellard | #endif
|
573 | 48024e4a | bellard | |
574 | 48024e4a | bellard | /* Get a 1 byte signed integer. */
|
575 | 48024e4a | bellard | #define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1])) |
576 | 48024e4a | bellard | |
577 | 48024e4a | bellard | /* Get a 2 byte signed integer. */
|
578 | 48024e4a | bellard | #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) |
579 | 48024e4a | bellard | #define NEXTWORD(p) \
|
580 | 48024e4a | bellard | (p += 2, FETCH_DATA (info, p), \
|
581 | 48024e4a | bellard | COERCE16 ((p[-2] << 8) + p[-1])) |
582 | 48024e4a | bellard | |
583 | 48024e4a | bellard | /* Get a 4 byte signed integer. */
|
584 | 48024e4a | bellard | #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000) |
585 | 48024e4a | bellard | #define NEXTLONG(p) \
|
586 | 48024e4a | bellard | (p += 4, FETCH_DATA (info, p), \
|
587 | 48024e4a | bellard | (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))) |
588 | 48024e4a | bellard | |
589 | 48024e4a | bellard | /* Get a 4 byte unsigned integer. */
|
590 | 48024e4a | bellard | #define NEXTULONG(p) \
|
591 | 48024e4a | bellard | (p += 4, FETCH_DATA (info, p), \
|
592 | 48024e4a | bellard | (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])) |
593 | 48024e4a | bellard | |
594 | 48024e4a | bellard | /* Get a single precision float. */
|
595 | 48024e4a | bellard | #define NEXTSINGLE(val, p) \
|
596 | 48024e4a | bellard | (p += 4, FETCH_DATA (info, p), \
|
597 | 48024e4a | bellard | floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val)) |
598 | 48024e4a | bellard | |
599 | 48024e4a | bellard | /* Get a double precision float. */
|
600 | 48024e4a | bellard | #define NEXTDOUBLE(val, p) \
|
601 | 48024e4a | bellard | (p += 8, FETCH_DATA (info, p), \
|
602 | 48024e4a | bellard | floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val)) |
603 | 48024e4a | bellard | |
604 | 48024e4a | bellard | /* Get an extended precision float. */
|
605 | 48024e4a | bellard | #define NEXTEXTEND(val, p) \
|
606 | 48024e4a | bellard | (p += 12, FETCH_DATA (info, p), \
|
607 | 48024e4a | bellard | floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val)) |
608 | 48024e4a | bellard | |
609 | 48024e4a | bellard | /* Need a function to convert from packed to double
|
610 | 48024e4a | bellard | precision. Actually, it's easier to print a
|
611 | 48024e4a | bellard | packed number than a double anyway, so maybe
|
612 | 48024e4a | bellard | there should be a special case to handle this... */
|
613 | 48024e4a | bellard | #define NEXTPACKED(p) \
|
614 | 48024e4a | bellard | (p += 12, FETCH_DATA (info, p), 0.0) |
615 | 48024e4a | bellard | |
616 | 48024e4a | bellard | /* Maximum length of an instruction. */
|
617 | 48024e4a | bellard | #define MAXLEN 22 |
618 | 48024e4a | bellard | |
619 | 48024e4a | bellard | #include <setjmp.h> |
620 | 48024e4a | bellard | |
621 | 48024e4a | bellard | struct private
|
622 | 48024e4a | bellard | { |
623 | 48024e4a | bellard | /* Points to first byte not fetched. */
|
624 | 48024e4a | bellard | bfd_byte *max_fetched; |
625 | 48024e4a | bellard | bfd_byte the_buffer[MAXLEN]; |
626 | 48024e4a | bellard | bfd_vma insn_start; |
627 | 48024e4a | bellard | jmp_buf bailout; |
628 | 48024e4a | bellard | }; |
629 | 48024e4a | bellard | |
630 | 48024e4a | bellard | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
|
631 | 48024e4a | bellard | to ADDR (exclusive) are valid. Returns 1 for success, longjmps
|
632 | 48024e4a | bellard | on error. */
|
633 | 48024e4a | bellard | #define FETCH_DATA(info, addr) \
|
634 | 48024e4a | bellard | ((addr) <= ((struct private *) (info->private_data))->max_fetched \
|
635 | 48024e4a | bellard | ? 1 : fetch_data ((info), (addr)))
|
636 | 48024e4a | bellard | |
637 | 48024e4a | bellard | static int |
638 | 48024e4a | bellard | fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
639 | 48024e4a | bellard | { |
640 | 48024e4a | bellard | int status;
|
641 | 48024e4a | bellard | struct private *priv = (struct private *)info->private_data; |
642 | 48024e4a | bellard | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
643 | 48024e4a | bellard | |
644 | 48024e4a | bellard | status = (*info->read_memory_func) (start, |
645 | 48024e4a | bellard | priv->max_fetched, |
646 | 48024e4a | bellard | addr - priv->max_fetched, |
647 | 48024e4a | bellard | info); |
648 | 48024e4a | bellard | if (status != 0) |
649 | 48024e4a | bellard | { |
650 | 48024e4a | bellard | (*info->memory_error_func) (status, start, info); |
651 | 48024e4a | bellard | longjmp (priv->bailout, 1);
|
652 | 48024e4a | bellard | } |
653 | 48024e4a | bellard | else
|
654 | 48024e4a | bellard | priv->max_fetched = addr; |
655 | 48024e4a | bellard | return 1; |
656 | 48024e4a | bellard | } |
657 | 48024e4a | bellard | |
658 | 48024e4a | bellard | /* This function is used to print to the bit-bucket. */
|
659 | 48024e4a | bellard | static int |
660 | 48024e4a | bellard | dummy_printer (FILE *file ATTRIBUTE_UNUSED, |
661 | 48024e4a | bellard | const char *format ATTRIBUTE_UNUSED, |
662 | 48024e4a | bellard | ...) |
663 | 48024e4a | bellard | { |
664 | 48024e4a | bellard | return 0; |
665 | 48024e4a | bellard | } |
666 | 48024e4a | bellard | |
667 | 48024e4a | bellard | static void |
668 | 48024e4a | bellard | dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, |
669 | 48024e4a | bellard | struct disassemble_info *info ATTRIBUTE_UNUSED)
|
670 | 48024e4a | bellard | { |
671 | 48024e4a | bellard | } |
672 | 48024e4a | bellard | |
673 | 48024e4a | bellard | /* Fetch BITS bits from a position in the instruction specified by CODE.
|
674 | 48024e4a | bellard | CODE is a "place to put an argument", or 'x' for a destination
|
675 | 48024e4a | bellard | that is a general address (mode and register).
|
676 | 48024e4a | bellard | BUFFER contains the instruction. */
|
677 | 48024e4a | bellard | |
678 | 48024e4a | bellard | static int |
679 | 48024e4a | bellard | fetch_arg (unsigned char *buffer, |
680 | 48024e4a | bellard | int code,
|
681 | 48024e4a | bellard | int bits,
|
682 | 48024e4a | bellard | disassemble_info *info) |
683 | 48024e4a | bellard | { |
684 | 48024e4a | bellard | int val = 0; |
685 | 48024e4a | bellard | |
686 | 48024e4a | bellard | switch (code)
|
687 | 48024e4a | bellard | { |
688 | 48024e4a | bellard | case '/': /* MAC/EMAC mask bit. */ |
689 | 48024e4a | bellard | val = buffer[3] >> 5; |
690 | 48024e4a | bellard | break;
|
691 | 48024e4a | bellard | |
692 | 48024e4a | bellard | case 'G': /* EMAC ACC load. */ |
693 | 48024e4a | bellard | val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); |
694 | 48024e4a | bellard | break;
|
695 | 48024e4a | bellard | |
696 | 48024e4a | bellard | case 'H': /* EMAC ACC !load. */ |
697 | 48024e4a | bellard | val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); |
698 | 48024e4a | bellard | break;
|
699 | 48024e4a | bellard | |
700 | 48024e4a | bellard | case ']': /* EMAC ACCEXT bit. */ |
701 | 48024e4a | bellard | val = buffer[0] >> 2; |
702 | 48024e4a | bellard | break;
|
703 | 48024e4a | bellard | |
704 | 48024e4a | bellard | case 'I': /* MAC/EMAC scale factor. */ |
705 | 48024e4a | bellard | val = buffer[2] >> 1; |
706 | 48024e4a | bellard | break;
|
707 | 48024e4a | bellard | |
708 | 48024e4a | bellard | case 'F': /* EMAC ACCx. */ |
709 | 48024e4a | bellard | val = buffer[0] >> 1; |
710 | 48024e4a | bellard | break;
|
711 | 48024e4a | bellard | |
712 | 48024e4a | bellard | case 'f': |
713 | 48024e4a | bellard | val = buffer[1];
|
714 | 48024e4a | bellard | break;
|
715 | 48024e4a | bellard | |
716 | 48024e4a | bellard | case 's': |
717 | 48024e4a | bellard | val = buffer[1];
|
718 | 48024e4a | bellard | break;
|
719 | 48024e4a | bellard | |
720 | 48024e4a | bellard | case 'd': /* Destination, for register or quick. */ |
721 | 48024e4a | bellard | val = (buffer[0] << 8) + buffer[1]; |
722 | 48024e4a | bellard | val >>= 9;
|
723 | 48024e4a | bellard | break;
|
724 | 48024e4a | bellard | |
725 | 48024e4a | bellard | case 'x': /* Destination, for general arg. */ |
726 | 48024e4a | bellard | val = (buffer[0] << 8) + buffer[1]; |
727 | 48024e4a | bellard | val >>= 6;
|
728 | 48024e4a | bellard | break;
|
729 | 48024e4a | bellard | |
730 | 48024e4a | bellard | case 'k': |
731 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
732 | 48024e4a | bellard | val = (buffer[3] >> 4); |
733 | 48024e4a | bellard | break;
|
734 | 48024e4a | bellard | |
735 | 48024e4a | bellard | case 'C': |
736 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
737 | 48024e4a | bellard | val = buffer[3];
|
738 | 48024e4a | bellard | break;
|
739 | 48024e4a | bellard | |
740 | 48024e4a | bellard | case '1': |
741 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
742 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
743 | 48024e4a | bellard | val >>= 12;
|
744 | 48024e4a | bellard | break;
|
745 | 48024e4a | bellard | |
746 | 48024e4a | bellard | case '2': |
747 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
748 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
749 | 48024e4a | bellard | val >>= 6;
|
750 | 48024e4a | bellard | break;
|
751 | 48024e4a | bellard | |
752 | 48024e4a | bellard | case '3': |
753 | 48024e4a | bellard | case 'j': |
754 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
755 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
756 | 48024e4a | bellard | break;
|
757 | 48024e4a | bellard | |
758 | 48024e4a | bellard | case '4': |
759 | 48024e4a | bellard | FETCH_DATA (info, buffer + 5);
|
760 | 48024e4a | bellard | val = (buffer[4] << 8) + buffer[5]; |
761 | 48024e4a | bellard | val >>= 12;
|
762 | 48024e4a | bellard | break;
|
763 | 48024e4a | bellard | |
764 | 48024e4a | bellard | case '5': |
765 | 48024e4a | bellard | FETCH_DATA (info, buffer + 5);
|
766 | 48024e4a | bellard | val = (buffer[4] << 8) + buffer[5]; |
767 | 48024e4a | bellard | val >>= 6;
|
768 | 48024e4a | bellard | break;
|
769 | 48024e4a | bellard | |
770 | 48024e4a | bellard | case '6': |
771 | 48024e4a | bellard | FETCH_DATA (info, buffer + 5);
|
772 | 48024e4a | bellard | val = (buffer[4] << 8) + buffer[5]; |
773 | 48024e4a | bellard | break;
|
774 | 48024e4a | bellard | |
775 | 48024e4a | bellard | case '7': |
776 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
777 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
778 | 48024e4a | bellard | val >>= 7;
|
779 | 48024e4a | bellard | break;
|
780 | 48024e4a | bellard | |
781 | 48024e4a | bellard | case '8': |
782 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
783 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
784 | 48024e4a | bellard | val >>= 10;
|
785 | 48024e4a | bellard | break;
|
786 | 48024e4a | bellard | |
787 | 48024e4a | bellard | case '9': |
788 | 48024e4a | bellard | FETCH_DATA (info, buffer + 3);
|
789 | 48024e4a | bellard | val = (buffer[2] << 8) + buffer[3]; |
790 | 48024e4a | bellard | val >>= 5;
|
791 | 48024e4a | bellard | break;
|
792 | 48024e4a | bellard | |
793 | 48024e4a | bellard | case 'e': |
794 | 48024e4a | bellard | val = (buffer[1] >> 6); |
795 | 48024e4a | bellard | break;
|
796 | 48024e4a | bellard | |
797 | 48024e4a | bellard | case 'm': |
798 | 48024e4a | bellard | val = (buffer[1] & 0x40 ? 0x8 : 0) |
799 | 48024e4a | bellard | | ((buffer[0] >> 1) & 0x7) |
800 | 48024e4a | bellard | | (buffer[3] & 0x80 ? 0x10 : 0); |
801 | 48024e4a | bellard | break;
|
802 | 48024e4a | bellard | |
803 | 48024e4a | bellard | case 'n': |
804 | 48024e4a | bellard | val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); |
805 | 48024e4a | bellard | break;
|
806 | 48024e4a | bellard | |
807 | 48024e4a | bellard | case 'o': |
808 | 48024e4a | bellard | val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); |
809 | 48024e4a | bellard | break;
|
810 | 48024e4a | bellard | |
811 | 48024e4a | bellard | case 'M': |
812 | 48024e4a | bellard | val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); |
813 | 48024e4a | bellard | break;
|
814 | 48024e4a | bellard | |
815 | 48024e4a | bellard | case 'N': |
816 | 48024e4a | bellard | val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); |
817 | 48024e4a | bellard | break;
|
818 | 48024e4a | bellard | |
819 | 48024e4a | bellard | case 'h': |
820 | 48024e4a | bellard | val = buffer[2] >> 2; |
821 | 48024e4a | bellard | break;
|
822 | 48024e4a | bellard | |
823 | 48024e4a | bellard | default:
|
824 | 48024e4a | bellard | abort (); |
825 | 48024e4a | bellard | } |
826 | 48024e4a | bellard | |
827 | 48024e4a | bellard | switch (bits)
|
828 | 48024e4a | bellard | { |
829 | 48024e4a | bellard | case 1: |
830 | 48024e4a | bellard | return val & 1; |
831 | 48024e4a | bellard | case 2: |
832 | 48024e4a | bellard | return val & 3; |
833 | 48024e4a | bellard | case 3: |
834 | 48024e4a | bellard | return val & 7; |
835 | 48024e4a | bellard | case 4: |
836 | 48024e4a | bellard | return val & 017; |
837 | 48024e4a | bellard | case 5: |
838 | 48024e4a | bellard | return val & 037; |
839 | 48024e4a | bellard | case 6: |
840 | 48024e4a | bellard | return val & 077; |
841 | 48024e4a | bellard | case 7: |
842 | 48024e4a | bellard | return val & 0177; |
843 | 48024e4a | bellard | case 8: |
844 | 48024e4a | bellard | return val & 0377; |
845 | 48024e4a | bellard | case 12: |
846 | 48024e4a | bellard | return val & 07777; |
847 | 48024e4a | bellard | default:
|
848 | 48024e4a | bellard | abort (); |
849 | 48024e4a | bellard | } |
850 | 48024e4a | bellard | } |
851 | 48024e4a | bellard | |
852 | 48024e4a | bellard | /* Check if an EA is valid for a particular code. This is required
|
853 | 48024e4a | bellard | for the EMAC instructions since the type of source address determines
|
854 | 48024e4a | bellard | if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
|
855 | 48024e4a | bellard | is a non-load EMAC instruction and the bits mean register Ry.
|
856 | 48024e4a | bellard | A similar case exists for the movem instructions where the register
|
857 | 48024e4a | bellard | mask is interpreted differently for different EAs. */
|
858 | 48024e4a | bellard | |
859 | 48024e4a | bellard | static bfd_boolean
|
860 | 48024e4a | bellard | m68k_valid_ea (char code, int val) |
861 | 48024e4a | bellard | { |
862 | 48024e4a | bellard | int mode, mask;
|
863 | 48024e4a | bellard | #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
|
864 | 48024e4a | bellard | (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ |
865 | 48024e4a | bellard | | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) |
866 | 48024e4a | bellard | |
867 | 48024e4a | bellard | switch (code)
|
868 | 48024e4a | bellard | { |
869 | 48024e4a | bellard | case '*': |
870 | 48024e4a | bellard | mask = M (1,1,1,1,1,1,1,1,1,1,1,1); |
871 | 48024e4a | bellard | break;
|
872 | 48024e4a | bellard | case '~': |
873 | 48024e4a | bellard | mask = M (0,0,1,1,1,1,1,1,1,0,0,0); |
874 | 48024e4a | bellard | break;
|
875 | 48024e4a | bellard | case '%': |
876 | 48024e4a | bellard | mask = M (1,1,1,1,1,1,1,1,1,0,0,0); |
877 | 48024e4a | bellard | break;
|
878 | 48024e4a | bellard | case ';': |
879 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,1,1,1,1,1,1); |
880 | 48024e4a | bellard | break;
|
881 | 48024e4a | bellard | case '@': |
882 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,1,1,1,1,1,0); |
883 | 48024e4a | bellard | break;
|
884 | 48024e4a | bellard | case '!': |
885 | 48024e4a | bellard | mask = M (0,0,1,0,0,1,1,1,1,1,1,0); |
886 | 48024e4a | bellard | break;
|
887 | 48024e4a | bellard | case '&': |
888 | 48024e4a | bellard | mask = M (0,0,1,0,0,1,1,1,1,0,0,0); |
889 | 48024e4a | bellard | break;
|
890 | 48024e4a | bellard | case '$': |
891 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,1,1,1,0,0,0); |
892 | 48024e4a | bellard | break;
|
893 | 48024e4a | bellard | case '?': |
894 | 48024e4a | bellard | mask = M (1,0,1,0,0,1,1,1,1,0,0,0); |
895 | 48024e4a | bellard | break;
|
896 | 48024e4a | bellard | case '/': |
897 | 48024e4a | bellard | mask = M (1,0,1,0,0,1,1,1,1,1,1,0); |
898 | 48024e4a | bellard | break;
|
899 | 48024e4a | bellard | case '|': |
900 | 48024e4a | bellard | mask = M (0,0,1,0,0,1,1,1,1,1,1,0); |
901 | 48024e4a | bellard | break;
|
902 | 48024e4a | bellard | case '>': |
903 | 48024e4a | bellard | mask = M (0,0,1,0,1,1,1,1,1,0,0,0); |
904 | 48024e4a | bellard | break;
|
905 | 48024e4a | bellard | case '<': |
906 | 48024e4a | bellard | mask = M (0,0,1,1,0,1,1,1,1,1,1,0); |
907 | 48024e4a | bellard | break;
|
908 | 48024e4a | bellard | case 'm': |
909 | 48024e4a | bellard | mask = M (1,1,1,1,1,0,0,0,0,0,0,0); |
910 | 48024e4a | bellard | break;
|
911 | 48024e4a | bellard | case 'n': |
912 | 48024e4a | bellard | mask = M (0,0,0,0,0,1,0,0,0,1,0,0); |
913 | 48024e4a | bellard | break;
|
914 | 48024e4a | bellard | case 'o': |
915 | 48024e4a | bellard | mask = M (0,0,0,0,0,0,1,1,1,0,1,1); |
916 | 48024e4a | bellard | break;
|
917 | 48024e4a | bellard | case 'p': |
918 | 48024e4a | bellard | mask = M (1,1,1,1,1,1,0,0,0,0,0,0); |
919 | 48024e4a | bellard | break;
|
920 | 48024e4a | bellard | case 'q': |
921 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,0,0,0,0,0,0); |
922 | 48024e4a | bellard | break;
|
923 | 48024e4a | bellard | case 'v': |
924 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,0,1,1,0,0,0); |
925 | 48024e4a | bellard | break;
|
926 | 48024e4a | bellard | case 'b': |
927 | 48024e4a | bellard | mask = M (1,0,1,1,1,1,0,0,0,1,0,0); |
928 | 48024e4a | bellard | break;
|
929 | 48024e4a | bellard | case 'w': |
930 | 48024e4a | bellard | mask = M (0,0,1,1,1,1,0,0,0,1,0,0); |
931 | 48024e4a | bellard | break;
|
932 | 48024e4a | bellard | case 'y': |
933 | 48024e4a | bellard | mask = M (0,0,1,0,0,1,0,0,0,0,0,0); |
934 | 48024e4a | bellard | break;
|
935 | 48024e4a | bellard | case 'z': |
936 | 48024e4a | bellard | mask = M (0,0,1,0,0,1,0,0,0,1,0,0); |
937 | 48024e4a | bellard | break;
|
938 | 48024e4a | bellard | case '4': |
939 | 48024e4a | bellard | mask = M (0,0,1,1,1,1,0,0,0,0,0,0); |
940 | 48024e4a | bellard | break;
|
941 | 48024e4a | bellard | default:
|
942 | 48024e4a | bellard | abort (); |
943 | 48024e4a | bellard | } |
944 | 48024e4a | bellard | #undef M
|
945 | 48024e4a | bellard | |
946 | 48024e4a | bellard | mode = (val >> 3) & 7; |
947 | 48024e4a | bellard | if (mode == 7) |
948 | 48024e4a | bellard | mode += val & 7;
|
949 | 48024e4a | bellard | return (mask & (1 << mode)) != 0; |
950 | 48024e4a | bellard | } |
951 | 48024e4a | bellard | |
952 | 48024e4a | bellard | /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
|
953 | 48024e4a | bellard | REGNO = -1 for pc, -2 for none (suppressed). */
|
954 | 48024e4a | bellard | |
955 | 48024e4a | bellard | static void |
956 | 48024e4a | bellard | print_base (int regno, bfd_vma disp, disassemble_info *info)
|
957 | 48024e4a | bellard | { |
958 | 48024e4a | bellard | if (regno == -1) |
959 | 48024e4a | bellard | { |
960 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%pc@(");
|
961 | 48024e4a | bellard | (*info->print_address_func) (disp, info); |
962 | 48024e4a | bellard | } |
963 | 48024e4a | bellard | else
|
964 | 48024e4a | bellard | { |
965 | 48024e4a | bellard | char buf[50]; |
966 | 48024e4a | bellard | |
967 | 48024e4a | bellard | if (regno == -2) |
968 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "@(");
|
969 | 48024e4a | bellard | else if (regno == -3) |
970 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%zpc@(");
|
971 | 48024e4a | bellard | else
|
972 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
|
973 | 48024e4a | bellard | |
974 | 48024e4a | bellard | sprintf_vma (buf, disp); |
975 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", buf);
|
976 | 48024e4a | bellard | } |
977 | 48024e4a | bellard | } |
978 | 48024e4a | bellard | |
979 | 48024e4a | bellard | /* Print an indexed argument. The base register is BASEREG (-1 for pc).
|
980 | 48024e4a | bellard | P points to extension word, in buffer.
|
981 | 48024e4a | bellard | ADDR is the nominal core address of that extension word. */
|
982 | 48024e4a | bellard | |
983 | 48024e4a | bellard | static unsigned char * |
984 | 48024e4a | bellard | print_indexed (int basereg,
|
985 | 48024e4a | bellard | unsigned char *p, |
986 | 48024e4a | bellard | bfd_vma addr, |
987 | 48024e4a | bellard | disassemble_info *info) |
988 | 48024e4a | bellard | { |
989 | 48024e4a | bellard | int word;
|
990 | 7ccfb2eb | blueswir1 | static const char *const scales[] = { "", ":2", ":4", ":8" }; |
991 | 48024e4a | bellard | bfd_vma base_disp; |
992 | 48024e4a | bellard | bfd_vma outer_disp; |
993 | 48024e4a | bellard | char buf[40]; |
994 | 48024e4a | bellard | char vmabuf[50]; |
995 | 48024e4a | bellard | |
996 | 48024e4a | bellard | word = NEXTWORD (p); |
997 | 48024e4a | bellard | |
998 | 48024e4a | bellard | /* Generate the text for the index register.
|
999 | 48024e4a | bellard | Where this will be output is not yet determined. */
|
1000 | 48024e4a | bellard | sprintf (buf, "%s:%c%s",
|
1001 | 48024e4a | bellard | reg_names[(word >> 12) & 0xf], |
1002 | 48024e4a | bellard | (word & 0x800) ? 'l' : 'w', |
1003 | 48024e4a | bellard | scales[(word >> 9) & 3]); |
1004 | 48024e4a | bellard | |
1005 | 48024e4a | bellard | /* Handle the 68000 style of indexing. */
|
1006 | 48024e4a | bellard | |
1007 | 48024e4a | bellard | if ((word & 0x100) == 0) |
1008 | 48024e4a | bellard | { |
1009 | 48024e4a | bellard | base_disp = word & 0xff;
|
1010 | 48024e4a | bellard | if ((base_disp & 0x80) != 0) |
1011 | 48024e4a | bellard | base_disp -= 0x100;
|
1012 | 48024e4a | bellard | if (basereg == -1) |
1013 | 48024e4a | bellard | base_disp += addr; |
1014 | 48024e4a | bellard | print_base (basereg, base_disp, info); |
1015 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ",%s)", buf);
|
1016 | 48024e4a | bellard | return p;
|
1017 | 48024e4a | bellard | } |
1018 | 48024e4a | bellard | |
1019 | 48024e4a | bellard | /* Handle the generalized kind. */
|
1020 | 48024e4a | bellard | /* First, compute the displacement to add to the base register. */
|
1021 | 48024e4a | bellard | if (word & 0200) |
1022 | 48024e4a | bellard | { |
1023 | 48024e4a | bellard | if (basereg == -1) |
1024 | 48024e4a | bellard | basereg = -3;
|
1025 | 48024e4a | bellard | else
|
1026 | 48024e4a | bellard | basereg = -2;
|
1027 | 48024e4a | bellard | } |
1028 | 48024e4a | bellard | if (word & 0100) |
1029 | 48024e4a | bellard | buf[0] = '\0'; |
1030 | 48024e4a | bellard | base_disp = 0;
|
1031 | 48024e4a | bellard | switch ((word >> 4) & 3) |
1032 | 48024e4a | bellard | { |
1033 | 48024e4a | bellard | case 2: |
1034 | 48024e4a | bellard | base_disp = NEXTWORD (p); |
1035 | 48024e4a | bellard | break;
|
1036 | 48024e4a | bellard | case 3: |
1037 | 48024e4a | bellard | base_disp = NEXTLONG (p); |
1038 | 48024e4a | bellard | } |
1039 | 48024e4a | bellard | if (basereg == -1) |
1040 | 48024e4a | bellard | base_disp += addr; |
1041 | 48024e4a | bellard | |
1042 | 48024e4a | bellard | /* Handle single-level case (not indirect). */
|
1043 | 48024e4a | bellard | if ((word & 7) == 0) |
1044 | 48024e4a | bellard | { |
1045 | 48024e4a | bellard | print_base (basereg, base_disp, info); |
1046 | 48024e4a | bellard | if (buf[0] != '\0') |
1047 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ",%s", buf);
|
1048 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ")");
|
1049 | 48024e4a | bellard | return p;
|
1050 | 48024e4a | bellard | } |
1051 | 48024e4a | bellard | |
1052 | 48024e4a | bellard | /* Two level. Compute displacement to add after indirection. */
|
1053 | 48024e4a | bellard | outer_disp = 0;
|
1054 | 48024e4a | bellard | switch (word & 3) |
1055 | 48024e4a | bellard | { |
1056 | 48024e4a | bellard | case 2: |
1057 | 48024e4a | bellard | outer_disp = NEXTWORD (p); |
1058 | 48024e4a | bellard | break;
|
1059 | 48024e4a | bellard | case 3: |
1060 | 48024e4a | bellard | outer_disp = NEXTLONG (p); |
1061 | 48024e4a | bellard | } |
1062 | 48024e4a | bellard | |
1063 | 48024e4a | bellard | print_base (basereg, base_disp, info); |
1064 | 48024e4a | bellard | if ((word & 4) == 0 && buf[0] != '\0') |
1065 | 48024e4a | bellard | { |
1066 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ",%s", buf);
|
1067 | 48024e4a | bellard | buf[0] = '\0'; |
1068 | 48024e4a | bellard | } |
1069 | 48024e4a | bellard | sprintf_vma (vmabuf, outer_disp); |
1070 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
|
1071 | 48024e4a | bellard | if (buf[0] != '\0') |
1072 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ",%s", buf);
|
1073 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ")");
|
1074 | 48024e4a | bellard | |
1075 | 48024e4a | bellard | return p;
|
1076 | 48024e4a | bellard | } |
1077 | 48024e4a | bellard | |
1078 | 48024e4a | bellard | /* Returns number of bytes "eaten" by the operand, or
|
1079 | 48024e4a | bellard | return -1 if an invalid operand was found, or -2 if
|
1080 | 48024e4a | bellard | an opcode tabe error was found.
|
1081 | 48024e4a | bellard | ADDR is the pc for this arg to be relative to. */
|
1082 | 48024e4a | bellard | |
1083 | 48024e4a | bellard | static int |
1084 | 48024e4a | bellard | print_insn_arg (const char *d, |
1085 | 48024e4a | bellard | unsigned char *buffer, |
1086 | 48024e4a | bellard | unsigned char *p0, |
1087 | 48024e4a | bellard | bfd_vma addr, |
1088 | 48024e4a | bellard | disassemble_info *info) |
1089 | 48024e4a | bellard | { |
1090 | 48024e4a | bellard | int val = 0; |
1091 | 48024e4a | bellard | int place = d[1]; |
1092 | 48024e4a | bellard | unsigned char *p = p0; |
1093 | 48024e4a | bellard | int regno;
|
1094 | 48024e4a | bellard | const char *regname; |
1095 | 48024e4a | bellard | unsigned char *p1; |
1096 | 48024e4a | bellard | double flval;
|
1097 | 48024e4a | bellard | int flt_p;
|
1098 | 48024e4a | bellard | bfd_signed_vma disp; |
1099 | 48024e4a | bellard | unsigned int uval; |
1100 | 48024e4a | bellard | |
1101 | 48024e4a | bellard | switch (*d)
|
1102 | 48024e4a | bellard | { |
1103 | 48024e4a | bellard | case 'c': /* Cache identifier. */ |
1104 | 48024e4a | bellard | { |
1105 | 7ccfb2eb | blueswir1 | static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; |
1106 | 48024e4a | bellard | val = fetch_arg (buffer, place, 2, info);
|
1107 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, cacheFieldName[val]); |
1108 | 48024e4a | bellard | break;
|
1109 | 48024e4a | bellard | } |
1110 | 48024e4a | bellard | |
1111 | 48024e4a | bellard | case 'a': /* Address register indirect only. Cf. case '+'. */ |
1112 | 48024e4a | bellard | { |
1113 | 48024e4a | bellard | (*info->fprintf_func) |
1114 | 48024e4a | bellard | (info->stream, |
1115 | 48024e4a | bellard | "%s@",
|
1116 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info) + 8]); |
1117 | 48024e4a | bellard | break;
|
1118 | 48024e4a | bellard | } |
1119 | 48024e4a | bellard | |
1120 | 48024e4a | bellard | case '_': /* 32-bit absolute address for move16. */ |
1121 | 48024e4a | bellard | { |
1122 | 48024e4a | bellard | uval = NEXTULONG (p); |
1123 | 48024e4a | bellard | (*info->print_address_func) (uval, info); |
1124 | 48024e4a | bellard | break;
|
1125 | 48024e4a | bellard | } |
1126 | 48024e4a | bellard | |
1127 | 48024e4a | bellard | case 'C': |
1128 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%ccr");
|
1129 | 48024e4a | bellard | break;
|
1130 | 48024e4a | bellard | |
1131 | 48024e4a | bellard | case 'S': |
1132 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%sr");
|
1133 | 48024e4a | bellard | break;
|
1134 | 48024e4a | bellard | |
1135 | 48024e4a | bellard | case 'U': |
1136 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%usp");
|
1137 | 48024e4a | bellard | break;
|
1138 | 48024e4a | bellard | |
1139 | 48024e4a | bellard | case 'E': |
1140 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%acc");
|
1141 | 48024e4a | bellard | break;
|
1142 | 48024e4a | bellard | |
1143 | 48024e4a | bellard | case 'G': |
1144 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%macsr");
|
1145 | 48024e4a | bellard | break;
|
1146 | 48024e4a | bellard | |
1147 | 48024e4a | bellard | case 'H': |
1148 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%mask");
|
1149 | 48024e4a | bellard | break;
|
1150 | 48024e4a | bellard | |
1151 | 48024e4a | bellard | case 'J': |
1152 | 48024e4a | bellard | { |
1153 | 48024e4a | bellard | /* FIXME: There's a problem here, different m68k processors call the
|
1154 | 48024e4a | bellard | same address different names. This table can't get it right
|
1155 | 48024e4a | bellard | because it doesn't know which processor it's disassembling for. */
|
1156 | 7ccfb2eb | blueswir1 | static const struct { const char *name; int value; } names[] |
1157 | 48024e4a | bellard | = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, |
1158 | 48024e4a | bellard | {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, |
1159 | 48024e4a | bellard | {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, |
1160 | 48024e4a | bellard | {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, |
1161 | 48024e4a | bellard | {"%msp", 0x803}, {"%isp", 0x804}, |
1162 | 48024e4a | bellard | {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */ |
1163 | 48024e4a | bellard | |
1164 | 48024e4a | bellard | /* Should we be calling this psr like we do in case 'Y'? */
|
1165 | 48024e4a | bellard | {"%mmusr",0x805}, |
1166 | 48024e4a | bellard | |
1167 | 48024e4a | bellard | {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}}; |
1168 | 48024e4a | bellard | |
1169 | 48024e4a | bellard | val = fetch_arg (buffer, place, 12, info);
|
1170 | 48024e4a | bellard | for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) |
1171 | 48024e4a | bellard | if (names[regno].value == val)
|
1172 | 48024e4a | bellard | { |
1173 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", names[regno].name);
|
1174 | 48024e4a | bellard | break;
|
1175 | 48024e4a | bellard | } |
1176 | 48024e4a | bellard | if (regno < 0) |
1177 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%d", val);
|
1178 | 48024e4a | bellard | } |
1179 | 48024e4a | bellard | break;
|
1180 | 48024e4a | bellard | |
1181 | 48024e4a | bellard | case 'Q': |
1182 | 48024e4a | bellard | val = fetch_arg (buffer, place, 3, info);
|
1183 | 48024e4a | bellard | /* 0 means 8, except for the bkpt instruction... */
|
1184 | 48024e4a | bellard | if (val == 0 && d[1] != 's') |
1185 | 48024e4a | bellard | val = 8;
|
1186 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1187 | 48024e4a | bellard | break;
|
1188 | 48024e4a | bellard | |
1189 | 48024e4a | bellard | case 'x': |
1190 | 48024e4a | bellard | val = fetch_arg (buffer, place, 3, info);
|
1191 | 48024e4a | bellard | /* 0 means -1. */
|
1192 | 48024e4a | bellard | if (val == 0) |
1193 | 48024e4a | bellard | val = -1;
|
1194 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1195 | 48024e4a | bellard | break;
|
1196 | 48024e4a | bellard | |
1197 | 48024e4a | bellard | case 'M': |
1198 | 48024e4a | bellard | if (place == 'h') |
1199 | 48024e4a | bellard | { |
1200 | 7ccfb2eb | blueswir1 | static const char *const scalefactor_name[] = { "<<", ">>" }; |
1201 | 48024e4a | bellard | val = fetch_arg (buffer, place, 1, info);
|
1202 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, scalefactor_name[val]); |
1203 | 48024e4a | bellard | } |
1204 | 48024e4a | bellard | else
|
1205 | 48024e4a | bellard | { |
1206 | 48024e4a | bellard | val = fetch_arg (buffer, place, 8, info);
|
1207 | 48024e4a | bellard | if (val & 0x80) |
1208 | 48024e4a | bellard | val = val - 0x100;
|
1209 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1210 | 48024e4a | bellard | } |
1211 | 48024e4a | bellard | break;
|
1212 | 48024e4a | bellard | |
1213 | 48024e4a | bellard | case 'T': |
1214 | 48024e4a | bellard | val = fetch_arg (buffer, place, 4, info);
|
1215 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1216 | 48024e4a | bellard | break;
|
1217 | 48024e4a | bellard | |
1218 | 48024e4a | bellard | case 'D': |
1219 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s",
|
1220 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info)]);
|
1221 | 48024e4a | bellard | break;
|
1222 | 48024e4a | bellard | |
1223 | 48024e4a | bellard | case 'A': |
1224 | 48024e4a | bellard | (*info->fprintf_func) |
1225 | 48024e4a | bellard | (info->stream, "%s",
|
1226 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info) + 010]); |
1227 | 48024e4a | bellard | break;
|
1228 | 48024e4a | bellard | |
1229 | 48024e4a | bellard | case 'R': |
1230 | 48024e4a | bellard | (*info->fprintf_func) |
1231 | 48024e4a | bellard | (info->stream, "%s",
|
1232 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 4, info)]);
|
1233 | 48024e4a | bellard | break;
|
1234 | 48024e4a | bellard | |
1235 | 48024e4a | bellard | case 'r': |
1236 | 48024e4a | bellard | regno = fetch_arg (buffer, place, 4, info);
|
1237 | 48024e4a | bellard | if (regno > 7) |
1238 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
|
1239 | 48024e4a | bellard | else
|
1240 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
|
1241 | 48024e4a | bellard | break;
|
1242 | 48024e4a | bellard | |
1243 | 48024e4a | bellard | case 'F': |
1244 | 48024e4a | bellard | (*info->fprintf_func) |
1245 | 48024e4a | bellard | (info->stream, "%%fp%d",
|
1246 | 48024e4a | bellard | fetch_arg (buffer, place, 3, info));
|
1247 | 48024e4a | bellard | break;
|
1248 | 48024e4a | bellard | |
1249 | 48024e4a | bellard | case 'O': |
1250 | 48024e4a | bellard | val = fetch_arg (buffer, place, 6, info);
|
1251 | 48024e4a | bellard | if (val & 0x20) |
1252 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); |
1253 | 48024e4a | bellard | else
|
1254 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%d", val);
|
1255 | 48024e4a | bellard | break;
|
1256 | 48024e4a | bellard | |
1257 | 48024e4a | bellard | case '+': |
1258 | 48024e4a | bellard | (*info->fprintf_func) |
1259 | 48024e4a | bellard | (info->stream, "%s@+",
|
1260 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info) + 8]); |
1261 | 48024e4a | bellard | break;
|
1262 | 48024e4a | bellard | |
1263 | 48024e4a | bellard | case '-': |
1264 | 48024e4a | bellard | (*info->fprintf_func) |
1265 | 48024e4a | bellard | (info->stream, "%s@-",
|
1266 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info) + 8]); |
1267 | 48024e4a | bellard | break;
|
1268 | 48024e4a | bellard | |
1269 | 48024e4a | bellard | case 'k': |
1270 | 48024e4a | bellard | if (place == 'k') |
1271 | 48024e4a | bellard | (*info->fprintf_func) |
1272 | 48024e4a | bellard | (info->stream, "{%s}",
|
1273 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info)]);
|
1274 | 48024e4a | bellard | else if (place == 'C') |
1275 | 48024e4a | bellard | { |
1276 | 48024e4a | bellard | val = fetch_arg (buffer, place, 7, info);
|
1277 | 48024e4a | bellard | if (val > 63) /* This is a signed constant. */ |
1278 | 48024e4a | bellard | val -= 128;
|
1279 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "{#%d}", val);
|
1280 | 48024e4a | bellard | } |
1281 | 48024e4a | bellard | else
|
1282 | 48024e4a | bellard | return -2; |
1283 | 48024e4a | bellard | break;
|
1284 | 48024e4a | bellard | |
1285 | 48024e4a | bellard | case '#': |
1286 | 48024e4a | bellard | case '^': |
1287 | 48024e4a | bellard | p1 = buffer + (*d == '#' ? 2 : 4); |
1288 | 48024e4a | bellard | if (place == 's') |
1289 | 48024e4a | bellard | val = fetch_arg (buffer, place, 4, info);
|
1290 | 48024e4a | bellard | else if (place == 'C') |
1291 | 48024e4a | bellard | val = fetch_arg (buffer, place, 7, info);
|
1292 | 48024e4a | bellard | else if (place == '8') |
1293 | 48024e4a | bellard | val = fetch_arg (buffer, place, 3, info);
|
1294 | 48024e4a | bellard | else if (place == '3') |
1295 | 48024e4a | bellard | val = fetch_arg (buffer, place, 8, info);
|
1296 | 48024e4a | bellard | else if (place == 'b') |
1297 | 48024e4a | bellard | val = NEXTBYTE (p1); |
1298 | 48024e4a | bellard | else if (place == 'w' || place == 'W') |
1299 | 48024e4a | bellard | val = NEXTWORD (p1); |
1300 | 48024e4a | bellard | else if (place == 'l') |
1301 | 48024e4a | bellard | val = NEXTLONG (p1); |
1302 | 48024e4a | bellard | else
|
1303 | 48024e4a | bellard | return -2; |
1304 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1305 | 48024e4a | bellard | break;
|
1306 | 48024e4a | bellard | |
1307 | 48024e4a | bellard | case 'B': |
1308 | 48024e4a | bellard | if (place == 'b') |
1309 | 48024e4a | bellard | disp = NEXTBYTE (p); |
1310 | 48024e4a | bellard | else if (place == 'B') |
1311 | 48024e4a | bellard | disp = COERCE_SIGNED_CHAR (buffer[1]);
|
1312 | 48024e4a | bellard | else if (place == 'w' || place == 'W') |
1313 | 48024e4a | bellard | disp = NEXTWORD (p); |
1314 | 48024e4a | bellard | else if (place == 'l' || place == 'L' || place == 'C') |
1315 | 48024e4a | bellard | disp = NEXTLONG (p); |
1316 | 48024e4a | bellard | else if (place == 'g') |
1317 | 48024e4a | bellard | { |
1318 | 48024e4a | bellard | disp = NEXTBYTE (buffer); |
1319 | 48024e4a | bellard | if (disp == 0) |
1320 | 48024e4a | bellard | disp = NEXTWORD (p); |
1321 | 48024e4a | bellard | else if (disp == -1) |
1322 | 48024e4a | bellard | disp = NEXTLONG (p); |
1323 | 48024e4a | bellard | } |
1324 | 48024e4a | bellard | else if (place == 'c') |
1325 | 48024e4a | bellard | { |
1326 | 48024e4a | bellard | if (buffer[1] & 0x40) /* If bit six is one, long offset. */ |
1327 | 48024e4a | bellard | disp = NEXTLONG (p); |
1328 | 48024e4a | bellard | else
|
1329 | 48024e4a | bellard | disp = NEXTWORD (p); |
1330 | 48024e4a | bellard | } |
1331 | 48024e4a | bellard | else
|
1332 | 48024e4a | bellard | return -2; |
1333 | 48024e4a | bellard | |
1334 | 48024e4a | bellard | (*info->print_address_func) (addr + disp, info); |
1335 | 48024e4a | bellard | break;
|
1336 | 48024e4a | bellard | |
1337 | 48024e4a | bellard | case 'd': |
1338 | 48024e4a | bellard | val = NEXTWORD (p); |
1339 | 48024e4a | bellard | (*info->fprintf_func) |
1340 | 48024e4a | bellard | (info->stream, "%s@(%d)",
|
1341 | 48024e4a | bellard | reg_names[fetch_arg (buffer, place, 3, info) + 8], val); |
1342 | 48024e4a | bellard | break;
|
1343 | 48024e4a | bellard | |
1344 | 48024e4a | bellard | case 's': |
1345 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s",
|
1346 | 48024e4a | bellard | fpcr_names[fetch_arg (buffer, place, 3, info)]);
|
1347 | 48024e4a | bellard | break;
|
1348 | 48024e4a | bellard | |
1349 | 48024e4a | bellard | case 'e': |
1350 | 48024e4a | bellard | val = fetch_arg(buffer, place, 2, info);
|
1351 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%acc%d", val);
|
1352 | 48024e4a | bellard | break;
|
1353 | 48024e4a | bellard | |
1354 | 48024e4a | bellard | case 'g': |
1355 | 48024e4a | bellard | val = fetch_arg(buffer, place, 1, info);
|
1356 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23"); |
1357 | 48024e4a | bellard | break;
|
1358 | 48024e4a | bellard | |
1359 | 48024e4a | bellard | case 'i': |
1360 | 48024e4a | bellard | val = fetch_arg(buffer, place, 2, info);
|
1361 | 48024e4a | bellard | if (val == 1) |
1362 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "<<");
|
1363 | 48024e4a | bellard | else if (val == 3) |
1364 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ">>");
|
1365 | 48024e4a | bellard | else
|
1366 | 48024e4a | bellard | return -1; |
1367 | 48024e4a | bellard | break;
|
1368 | 48024e4a | bellard | |
1369 | 48024e4a | bellard | case 'I': |
1370 | 48024e4a | bellard | /* Get coprocessor ID... */
|
1371 | 48024e4a | bellard | val = fetch_arg (buffer, 'd', 3, info); |
1372 | 48024e4a | bellard | |
1373 | 48024e4a | bellard | if (val != 1) /* Unusual coprocessor ID? */ |
1374 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
|
1375 | 48024e4a | bellard | break;
|
1376 | 48024e4a | bellard | |
1377 | 48024e4a | bellard | case '4': |
1378 | 48024e4a | bellard | case '*': |
1379 | 48024e4a | bellard | case '~': |
1380 | 48024e4a | bellard | case '%': |
1381 | 48024e4a | bellard | case ';': |
1382 | 48024e4a | bellard | case '@': |
1383 | 48024e4a | bellard | case '!': |
1384 | 48024e4a | bellard | case '$': |
1385 | 48024e4a | bellard | case '?': |
1386 | 48024e4a | bellard | case '/': |
1387 | 48024e4a | bellard | case '&': |
1388 | 48024e4a | bellard | case '|': |
1389 | 48024e4a | bellard | case '<': |
1390 | 48024e4a | bellard | case '>': |
1391 | 48024e4a | bellard | case 'm': |
1392 | 48024e4a | bellard | case 'n': |
1393 | 48024e4a | bellard | case 'o': |
1394 | 48024e4a | bellard | case 'p': |
1395 | 48024e4a | bellard | case 'q': |
1396 | 48024e4a | bellard | case 'v': |
1397 | 48024e4a | bellard | case 'b': |
1398 | 48024e4a | bellard | case 'w': |
1399 | 48024e4a | bellard | case 'y': |
1400 | 48024e4a | bellard | case 'z': |
1401 | 48024e4a | bellard | if (place == 'd') |
1402 | 48024e4a | bellard | { |
1403 | 48024e4a | bellard | val = fetch_arg (buffer, 'x', 6, info); |
1404 | 48024e4a | bellard | val = ((val & 7) << 3) + ((val >> 3) & 7); |
1405 | 48024e4a | bellard | } |
1406 | 48024e4a | bellard | else
|
1407 | 48024e4a | bellard | val = fetch_arg (buffer, 's', 6, info); |
1408 | 48024e4a | bellard | |
1409 | 48024e4a | bellard | /* If the <ea> is invalid for *d, then reject this match. */
|
1410 | 48024e4a | bellard | if (!m68k_valid_ea (*d, val))
|
1411 | 48024e4a | bellard | return -1; |
1412 | 48024e4a | bellard | |
1413 | 48024e4a | bellard | /* Get register number assuming address register. */
|
1414 | 48024e4a | bellard | regno = (val & 7) + 8; |
1415 | 48024e4a | bellard | regname = reg_names[regno]; |
1416 | 48024e4a | bellard | switch (val >> 3) |
1417 | 48024e4a | bellard | { |
1418 | 48024e4a | bellard | case 0: |
1419 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
|
1420 | 48024e4a | bellard | break;
|
1421 | 48024e4a | bellard | |
1422 | 48024e4a | bellard | case 1: |
1423 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", regname);
|
1424 | 48024e4a | bellard | break;
|
1425 | 48024e4a | bellard | |
1426 | 48024e4a | bellard | case 2: |
1427 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@", regname);
|
1428 | 48024e4a | bellard | break;
|
1429 | 48024e4a | bellard | |
1430 | 48024e4a | bellard | case 3: |
1431 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@+", regname);
|
1432 | 48024e4a | bellard | break;
|
1433 | 48024e4a | bellard | |
1434 | 48024e4a | bellard | case 4: |
1435 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@-", regname);
|
1436 | 48024e4a | bellard | break;
|
1437 | 48024e4a | bellard | |
1438 | 48024e4a | bellard | case 5: |
1439 | 48024e4a | bellard | val = NEXTWORD (p); |
1440 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
|
1441 | 48024e4a | bellard | break;
|
1442 | 48024e4a | bellard | |
1443 | 48024e4a | bellard | case 6: |
1444 | 48024e4a | bellard | p = print_indexed (regno, p, addr, info); |
1445 | 48024e4a | bellard | break;
|
1446 | 48024e4a | bellard | |
1447 | 48024e4a | bellard | case 7: |
1448 | 48024e4a | bellard | switch (val & 7) |
1449 | 48024e4a | bellard | { |
1450 | 48024e4a | bellard | case 0: |
1451 | 48024e4a | bellard | val = NEXTWORD (p); |
1452 | 48024e4a | bellard | (*info->print_address_func) (val, info); |
1453 | 48024e4a | bellard | break;
|
1454 | 48024e4a | bellard | |
1455 | 48024e4a | bellard | case 1: |
1456 | 48024e4a | bellard | uval = NEXTULONG (p); |
1457 | 48024e4a | bellard | (*info->print_address_func) (uval, info); |
1458 | 48024e4a | bellard | break;
|
1459 | 48024e4a | bellard | |
1460 | 48024e4a | bellard | case 2: |
1461 | 48024e4a | bellard | val = NEXTWORD (p); |
1462 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%pc@(");
|
1463 | 48024e4a | bellard | (*info->print_address_func) (addr + val, info); |
1464 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, ")");
|
1465 | 48024e4a | bellard | break;
|
1466 | 48024e4a | bellard | |
1467 | 48024e4a | bellard | case 3: |
1468 | 48024e4a | bellard | p = print_indexed (-1, p, addr, info);
|
1469 | 48024e4a | bellard | break;
|
1470 | 48024e4a | bellard | |
1471 | 48024e4a | bellard | case 4: |
1472 | 48024e4a | bellard | flt_p = 1; /* Assume it's a float... */ |
1473 | 48024e4a | bellard | switch (place)
|
1474 | 48024e4a | bellard | { |
1475 | 48024e4a | bellard | case 'b': |
1476 | 48024e4a | bellard | val = NEXTBYTE (p); |
1477 | 48024e4a | bellard | flt_p = 0;
|
1478 | 48024e4a | bellard | break;
|
1479 | 48024e4a | bellard | |
1480 | 48024e4a | bellard | case 'w': |
1481 | 48024e4a | bellard | val = NEXTWORD (p); |
1482 | 48024e4a | bellard | flt_p = 0;
|
1483 | 48024e4a | bellard | break;
|
1484 | 48024e4a | bellard | |
1485 | 48024e4a | bellard | case 'l': |
1486 | 48024e4a | bellard | val = NEXTLONG (p); |
1487 | 48024e4a | bellard | flt_p = 0;
|
1488 | 48024e4a | bellard | break;
|
1489 | 48024e4a | bellard | |
1490 | 48024e4a | bellard | case 'f': |
1491 | 48024e4a | bellard | NEXTSINGLE (flval, p); |
1492 | 48024e4a | bellard | break;
|
1493 | 48024e4a | bellard | |
1494 | 48024e4a | bellard | case 'F': |
1495 | 48024e4a | bellard | NEXTDOUBLE (flval, p); |
1496 | 48024e4a | bellard | break;
|
1497 | 48024e4a | bellard | |
1498 | 48024e4a | bellard | case 'x': |
1499 | 48024e4a | bellard | NEXTEXTEND (flval, p); |
1500 | 48024e4a | bellard | break;
|
1501 | 48024e4a | bellard | |
1502 | 48024e4a | bellard | case 'p': |
1503 | 48024e4a | bellard | flval = NEXTPACKED (p); |
1504 | 48024e4a | bellard | break;
|
1505 | 48024e4a | bellard | |
1506 | 48024e4a | bellard | default:
|
1507 | 48024e4a | bellard | return -1; |
1508 | 48024e4a | bellard | } |
1509 | 48024e4a | bellard | if (flt_p) /* Print a float? */ |
1510 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%g", flval);
|
1511 | 48024e4a | bellard | else
|
1512 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#%d", val);
|
1513 | 48024e4a | bellard | break;
|
1514 | 48024e4a | bellard | |
1515 | 48024e4a | bellard | default:
|
1516 | 48024e4a | bellard | return -1; |
1517 | 48024e4a | bellard | } |
1518 | 48024e4a | bellard | } |
1519 | 48024e4a | bellard | |
1520 | 48024e4a | bellard | /* If place is '/', then this is the case of the mask bit for
|
1521 | 48024e4a | bellard | mac/emac loads. Now that the arg has been printed, grab the
|
1522 | 48024e4a | bellard | mask bit and if set, add a '&' to the arg. */
|
1523 | 48024e4a | bellard | if (place == '/') |
1524 | 48024e4a | bellard | { |
1525 | 48024e4a | bellard | val = fetch_arg (buffer, place, 1, info);
|
1526 | 48024e4a | bellard | if (val)
|
1527 | 48024e4a | bellard | info->fprintf_func (info->stream, "&");
|
1528 | 48024e4a | bellard | } |
1529 | 48024e4a | bellard | break;
|
1530 | 48024e4a | bellard | |
1531 | 48024e4a | bellard | case 'L': |
1532 | 48024e4a | bellard | case 'l': |
1533 | 48024e4a | bellard | if (place == 'w') |
1534 | 48024e4a | bellard | { |
1535 | 48024e4a | bellard | char doneany;
|
1536 | 48024e4a | bellard | p1 = buffer + 2;
|
1537 | 48024e4a | bellard | val = NEXTWORD (p1); |
1538 | 48024e4a | bellard | /* Move the pointer ahead if this point is farther ahead
|
1539 | 48024e4a | bellard | than the last. */
|
1540 | 48024e4a | bellard | p = p1 > p ? p1 : p; |
1541 | 48024e4a | bellard | if (val == 0) |
1542 | 48024e4a | bellard | { |
1543 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#0");
|
1544 | 48024e4a | bellard | break;
|
1545 | 48024e4a | bellard | } |
1546 | 48024e4a | bellard | if (*d == 'l') |
1547 | 48024e4a | bellard | { |
1548 | 48024e4a | bellard | int newval = 0; |
1549 | 48024e4a | bellard | |
1550 | 48024e4a | bellard | for (regno = 0; regno < 16; ++regno) |
1551 | 48024e4a | bellard | if (val & (0x8000 >> regno)) |
1552 | 48024e4a | bellard | newval |= 1 << regno;
|
1553 | 48024e4a | bellard | val = newval; |
1554 | 48024e4a | bellard | } |
1555 | 48024e4a | bellard | val &= 0xffff;
|
1556 | 48024e4a | bellard | doneany = 0;
|
1557 | 48024e4a | bellard | for (regno = 0; regno < 16; ++regno) |
1558 | 48024e4a | bellard | if (val & (1 << regno)) |
1559 | 48024e4a | bellard | { |
1560 | 48024e4a | bellard | int first_regno;
|
1561 | 48024e4a | bellard | |
1562 | 48024e4a | bellard | if (doneany)
|
1563 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "/");
|
1564 | 48024e4a | bellard | doneany = 1;
|
1565 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
|
1566 | 48024e4a | bellard | first_regno = regno; |
1567 | 48024e4a | bellard | while (val & (1 << (regno + 1))) |
1568 | 48024e4a | bellard | ++regno; |
1569 | 48024e4a | bellard | if (regno > first_regno)
|
1570 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "-%s",
|
1571 | 48024e4a | bellard | reg_names[regno]); |
1572 | 48024e4a | bellard | } |
1573 | 48024e4a | bellard | } |
1574 | 48024e4a | bellard | else if (place == '3') |
1575 | 48024e4a | bellard | { |
1576 | 48024e4a | bellard | /* `fmovem' insn. */
|
1577 | 48024e4a | bellard | char doneany;
|
1578 | 48024e4a | bellard | val = fetch_arg (buffer, place, 8, info);
|
1579 | 48024e4a | bellard | if (val == 0) |
1580 | 48024e4a | bellard | { |
1581 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "#0");
|
1582 | 48024e4a | bellard | break;
|
1583 | 48024e4a | bellard | } |
1584 | 48024e4a | bellard | if (*d == 'l') |
1585 | 48024e4a | bellard | { |
1586 | 48024e4a | bellard | int newval = 0; |
1587 | 48024e4a | bellard | |
1588 | 48024e4a | bellard | for (regno = 0; regno < 8; ++regno) |
1589 | 48024e4a | bellard | if (val & (0x80 >> regno)) |
1590 | 48024e4a | bellard | newval |= 1 << regno;
|
1591 | 48024e4a | bellard | val = newval; |
1592 | 48024e4a | bellard | } |
1593 | 48024e4a | bellard | val &= 0xff;
|
1594 | 48024e4a | bellard | doneany = 0;
|
1595 | 48024e4a | bellard | for (regno = 0; regno < 8; ++regno) |
1596 | 48024e4a | bellard | if (val & (1 << regno)) |
1597 | 48024e4a | bellard | { |
1598 | 48024e4a | bellard | int first_regno;
|
1599 | 48024e4a | bellard | if (doneany)
|
1600 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "/");
|
1601 | 48024e4a | bellard | doneany = 1;
|
1602 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%fp%d", regno);
|
1603 | 48024e4a | bellard | first_regno = regno; |
1604 | 48024e4a | bellard | while (val & (1 << (regno + 1))) |
1605 | 48024e4a | bellard | ++regno; |
1606 | 48024e4a | bellard | if (regno > first_regno)
|
1607 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
|
1608 | 48024e4a | bellard | } |
1609 | 48024e4a | bellard | } |
1610 | 48024e4a | bellard | else if (place == '8') |
1611 | 48024e4a | bellard | { |
1612 | 48024e4a | bellard | /* fmoveml for FP status registers. */
|
1613 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s",
|
1614 | 48024e4a | bellard | fpcr_names[fetch_arg (buffer, place, 3,
|
1615 | 48024e4a | bellard | info)]); |
1616 | 48024e4a | bellard | } |
1617 | 48024e4a | bellard | else
|
1618 | 48024e4a | bellard | return -2; |
1619 | 48024e4a | bellard | break;
|
1620 | 48024e4a | bellard | |
1621 | 48024e4a | bellard | case 'X': |
1622 | 48024e4a | bellard | place = '8';
|
1623 | 48024e4a | bellard | case 'Y': |
1624 | 48024e4a | bellard | case 'Z': |
1625 | 48024e4a | bellard | case 'W': |
1626 | 48024e4a | bellard | case '0': |
1627 | 48024e4a | bellard | case '1': |
1628 | 48024e4a | bellard | case '2': |
1629 | 48024e4a | bellard | case '3': |
1630 | 48024e4a | bellard | { |
1631 | 48024e4a | bellard | int val = fetch_arg (buffer, place, 5, info); |
1632 | 7ccfb2eb | blueswir1 | const char *name = 0; |
1633 | 48024e4a | bellard | |
1634 | 48024e4a | bellard | switch (val)
|
1635 | 48024e4a | bellard | { |
1636 | 48024e4a | bellard | case 2: name = "%tt0"; break; |
1637 | 48024e4a | bellard | case 3: name = "%tt1"; break; |
1638 | 48024e4a | bellard | case 0x10: name = "%tc"; break; |
1639 | 48024e4a | bellard | case 0x11: name = "%drp"; break; |
1640 | 48024e4a | bellard | case 0x12: name = "%srp"; break; |
1641 | 48024e4a | bellard | case 0x13: name = "%crp"; break; |
1642 | 48024e4a | bellard | case 0x14: name = "%cal"; break; |
1643 | 48024e4a | bellard | case 0x15: name = "%val"; break; |
1644 | 48024e4a | bellard | case 0x16: name = "%scc"; break; |
1645 | 48024e4a | bellard | case 0x17: name = "%ac"; break; |
1646 | 48024e4a | bellard | case 0x18: name = "%psr"; break; |
1647 | 48024e4a | bellard | case 0x19: name = "%pcsr"; break; |
1648 | 48024e4a | bellard | case 0x1c: |
1649 | 48024e4a | bellard | case 0x1d: |
1650 | 48024e4a | bellard | { |
1651 | 48024e4a | bellard | int break_reg = ((buffer[3] >> 2) & 7); |
1652 | 48024e4a | bellard | |
1653 | 48024e4a | bellard | (*info->fprintf_func) |
1654 | 48024e4a | bellard | (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", |
1655 | 48024e4a | bellard | break_reg); |
1656 | 48024e4a | bellard | } |
1657 | 48024e4a | bellard | break;
|
1658 | 48024e4a | bellard | default:
|
1659 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
|
1660 | 48024e4a | bellard | } |
1661 | 48024e4a | bellard | if (name)
|
1662 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s", name);
|
1663 | 48024e4a | bellard | } |
1664 | 48024e4a | bellard | break;
|
1665 | 48024e4a | bellard | |
1666 | 48024e4a | bellard | case 'f': |
1667 | 48024e4a | bellard | { |
1668 | 48024e4a | bellard | int fc = fetch_arg (buffer, place, 5, info); |
1669 | 48024e4a | bellard | |
1670 | 48024e4a | bellard | if (fc == 1) |
1671 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%dfc");
|
1672 | 48024e4a | bellard | else if (fc == 0) |
1673 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%sfc");
|
1674 | 48024e4a | bellard | else
|
1675 | 48024e4a | bellard | /* xgettext:c-format */
|
1676 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
|
1677 | 48024e4a | bellard | } |
1678 | 48024e4a | bellard | break;
|
1679 | 48024e4a | bellard | |
1680 | 48024e4a | bellard | case 'V': |
1681 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%%val");
|
1682 | 48024e4a | bellard | break;
|
1683 | 48024e4a | bellard | |
1684 | 48024e4a | bellard | case 't': |
1685 | 48024e4a | bellard | { |
1686 | 48024e4a | bellard | int level = fetch_arg (buffer, place, 3, info); |
1687 | 48024e4a | bellard | |
1688 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%d", level);
|
1689 | 48024e4a | bellard | } |
1690 | 48024e4a | bellard | break;
|
1691 | 48024e4a | bellard | |
1692 | 48024e4a | bellard | case 'u': |
1693 | 48024e4a | bellard | { |
1694 | 48024e4a | bellard | short is_upper = 0; |
1695 | 48024e4a | bellard | int reg = fetch_arg (buffer, place, 5, info); |
1696 | 48024e4a | bellard | |
1697 | 48024e4a | bellard | if (reg & 0x10) |
1698 | 48024e4a | bellard | { |
1699 | 48024e4a | bellard | is_upper = 1;
|
1700 | 48024e4a | bellard | reg &= 0xf;
|
1701 | 48024e4a | bellard | } |
1702 | 48024e4a | bellard | (*info->fprintf_func) (info->stream, "%s%s",
|
1703 | 48024e4a | bellard | reg_half_names[reg], |
1704 | 48024e4a | bellard | is_upper ? "u" : "l"); |
1705 | 48024e4a | bellard | } |
1706 | 48024e4a | bellard | break;
|
1707 | 48024e4a | bellard | |
1708 | 48024e4a | bellard | default:
|
1709 | 48024e4a | bellard | return -2; |
1710 | 48024e4a | bellard | } |
1711 | 48024e4a | bellard | |
1712 | 48024e4a | bellard | return p - p0;
|
1713 | 48024e4a | bellard | } |
1714 | 48024e4a | bellard | |
1715 | 48024e4a | bellard | /* Try to match the current instruction to best and if so, return the
|
1716 | 48024e4a | bellard | number of bytes consumed from the instruction stream, else zero. */
|
1717 | 48024e4a | bellard | |
1718 | 48024e4a | bellard | static int |
1719 | 48024e4a | bellard | match_insn_m68k (bfd_vma memaddr, |
1720 | 48024e4a | bellard | disassemble_info * info, |
1721 | 48024e4a | bellard | const struct m68k_opcode * best, |
1722 | 48024e4a | bellard | struct private * priv)
|
1723 | 48024e4a | bellard | { |
1724 | 48024e4a | bellard | unsigned char *save_p; |
1725 | 48024e4a | bellard | unsigned char *p; |
1726 | 48024e4a | bellard | const char *d; |
1727 | 48024e4a | bellard | |
1728 | 48024e4a | bellard | bfd_byte *buffer = priv->the_buffer; |
1729 | 48024e4a | bellard | fprintf_ftype save_printer = info->fprintf_func; |
1730 | 48024e4a | bellard | void (* save_print_address) (bfd_vma, struct disassemble_info *) |
1731 | 48024e4a | bellard | = info->print_address_func; |
1732 | 48024e4a | bellard | |
1733 | 48024e4a | bellard | /* Point at first word of argument data,
|
1734 | 48024e4a | bellard | and at descriptor for first argument. */
|
1735 | 48024e4a | bellard | p = buffer + 2;
|
1736 | 48024e4a | bellard | |
1737 | 48024e4a | bellard | /* Figure out how long the fixed-size portion of the instruction is.
|
1738 | 48024e4a | bellard | The only place this is stored in the opcode table is
|
1739 | 48024e4a | bellard | in the arguments--look for arguments which specify fields in the 2nd
|
1740 | 48024e4a | bellard | or 3rd words of the instruction. */
|
1741 | 48024e4a | bellard | for (d = best->args; *d; d += 2) |
1742 | 48024e4a | bellard | { |
1743 | 48024e4a | bellard | /* I don't think it is necessary to be checking d[0] here;
|
1744 | 48024e4a | bellard | I suspect all this could be moved to the case statement below. */
|
1745 | 48024e4a | bellard | if (d[0] == '#') |
1746 | 48024e4a | bellard | { |
1747 | 48024e4a | bellard | if (d[1] == 'l' && p - buffer < 6) |
1748 | 48024e4a | bellard | p = buffer + 6;
|
1749 | 48024e4a | bellard | else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') |
1750 | 48024e4a | bellard | p = buffer + 4;
|
1751 | 48024e4a | bellard | } |
1752 | 48024e4a | bellard | |
1753 | 48024e4a | bellard | if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) |
1754 | 48024e4a | bellard | p = buffer + 4;
|
1755 | 48024e4a | bellard | |
1756 | 48024e4a | bellard | switch (d[1]) |
1757 | 48024e4a | bellard | { |
1758 | 48024e4a | bellard | case '1': |
1759 | 48024e4a | bellard | case '2': |
1760 | 48024e4a | bellard | case '3': |
1761 | 48024e4a | bellard | case '7': |
1762 | 48024e4a | bellard | case '8': |
1763 | 48024e4a | bellard | case '9': |
1764 | 48024e4a | bellard | case 'i': |
1765 | 48024e4a | bellard | if (p - buffer < 4) |
1766 | 48024e4a | bellard | p = buffer + 4;
|
1767 | 48024e4a | bellard | break;
|
1768 | 48024e4a | bellard | case '4': |
1769 | 48024e4a | bellard | case '5': |
1770 | 48024e4a | bellard | case '6': |
1771 | 48024e4a | bellard | if (p - buffer < 6) |
1772 | 48024e4a | bellard | p = buffer + 6;
|
1773 | 48024e4a | bellard | break;
|
1774 | 48024e4a | bellard | default:
|
1775 | 48024e4a | bellard | break;
|
1776 | 48024e4a | bellard | } |
1777 | 48024e4a | bellard | } |
1778 | 48024e4a | bellard | |
1779 | 48024e4a | bellard | /* pflusha is an exceptions. It takes no arguments but is two words
|
1780 | 48024e4a | bellard | long. Recognize it by looking at the lower 16 bits of the mask. */
|
1781 | 48024e4a | bellard | if (p - buffer < 4 && (best->match & 0xFFFF) != 0) |
1782 | 48024e4a | bellard | p = buffer + 4;
|
1783 | 48024e4a | bellard | |
1784 | 48024e4a | bellard | /* lpstop is another exception. It takes a one word argument but is
|
1785 | 48024e4a | bellard | three words long. */
|
1786 | 48024e4a | bellard | if (p - buffer < 6 |
1787 | 48024e4a | bellard | && (best->match & 0xffff) == 0xffff |
1788 | 48024e4a | bellard | && best->args[0] == '#' |
1789 | 48024e4a | bellard | && best->args[1] == 'w') |
1790 | 48024e4a | bellard | { |
1791 | 48024e4a | bellard | /* Copy the one word argument into the usual location for a one
|
1792 | 48024e4a | bellard | word argument, to simplify printing it. We can get away with
|
1793 | 48024e4a | bellard | this because we know exactly what the second word is, and we
|
1794 | 48024e4a | bellard | aren't going to print anything based on it. */
|
1795 | 48024e4a | bellard | p = buffer + 6;
|
1796 | 48024e4a | bellard | FETCH_DATA (info, p); |
1797 | 48024e4a | bellard | buffer[2] = buffer[4]; |
1798 | 48024e4a | bellard | buffer[3] = buffer[5]; |
1799 | 48024e4a | bellard | } |
1800 | 48024e4a | bellard | |
1801 | 48024e4a | bellard | FETCH_DATA (info, p); |
1802 | 48024e4a | bellard | |
1803 | 48024e4a | bellard | d = best->args; |
1804 | 48024e4a | bellard | |
1805 | 48024e4a | bellard | save_p = p; |
1806 | 48024e4a | bellard | info->print_address_func = dummy_print_address; |
1807 | 48024e4a | bellard | info->fprintf_func = (fprintf_ftype) dummy_printer; |
1808 | 48024e4a | bellard | |
1809 | 48024e4a | bellard | /* We scan the operands twice. The first time we don't print anything,
|
1810 | 48024e4a | bellard | but look for errors. */
|
1811 | 48024e4a | bellard | for (; *d; d += 2) |
1812 | 48024e4a | bellard | { |
1813 | 48024e4a | bellard | int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
|
1814 | 48024e4a | bellard | |
1815 | 48024e4a | bellard | if (eaten >= 0) |
1816 | 48024e4a | bellard | p += eaten; |
1817 | 48024e4a | bellard | else if (eaten == -1) |
1818 | 48024e4a | bellard | { |
1819 | 48024e4a | bellard | info->fprintf_func = save_printer; |
1820 | 48024e4a | bellard | info->print_address_func = save_print_address; |
1821 | 48024e4a | bellard | return 0; |
1822 | 48024e4a | bellard | } |
1823 | 48024e4a | bellard | else
|
1824 | 48024e4a | bellard | { |
1825 | 48024e4a | bellard | info->fprintf_func (info->stream, |
1826 | 48024e4a | bellard | /* xgettext:c-format */
|
1827 | 48024e4a | bellard | _("<internal error in opcode table: %s %s>\n"),
|
1828 | 48024e4a | bellard | best->name, best->args); |
1829 | 48024e4a | bellard | info->fprintf_func = save_printer; |
1830 | 48024e4a | bellard | info->print_address_func = save_print_address; |
1831 | 48024e4a | bellard | return 2; |
1832 | 48024e4a | bellard | } |
1833 | 48024e4a | bellard | } |
1834 | 48024e4a | bellard | |
1835 | 48024e4a | bellard | p = save_p; |
1836 | 48024e4a | bellard | info->fprintf_func = save_printer; |
1837 | 48024e4a | bellard | info->print_address_func = save_print_address; |
1838 | 48024e4a | bellard | |
1839 | 48024e4a | bellard | d = best->args; |
1840 | 48024e4a | bellard | |
1841 | 48024e4a | bellard | info->fprintf_func (info->stream, "%s", best->name);
|
1842 | 48024e4a | bellard | |
1843 | 48024e4a | bellard | if (*d)
|
1844 | 48024e4a | bellard | info->fprintf_func (info->stream, " ");
|
1845 | 48024e4a | bellard | |
1846 | 48024e4a | bellard | while (*d)
|
1847 | 48024e4a | bellard | { |
1848 | 48024e4a | bellard | p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); |
1849 | 48024e4a | bellard | d += 2;
|
1850 | 48024e4a | bellard | |
1851 | 48024e4a | bellard | if (*d && *(d - 2) != 'I' && *d != 'k') |
1852 | 48024e4a | bellard | info->fprintf_func (info->stream, ",");
|
1853 | 48024e4a | bellard | } |
1854 | 48024e4a | bellard | |
1855 | 48024e4a | bellard | return p - buffer;
|
1856 | 48024e4a | bellard | } |
1857 | 48024e4a | bellard | |
1858 | 48024e4a | bellard | /* Print the m68k instruction at address MEMADDR in debugged memory,
|
1859 | 48024e4a | bellard | on INFO->STREAM. Returns length of the instruction, in bytes. */
|
1860 | 48024e4a | bellard | |
1861 | 48024e4a | bellard | int
|
1862 | 48024e4a | bellard | print_insn_m68k (bfd_vma memaddr, disassemble_info *info) |
1863 | 48024e4a | bellard | { |
1864 | 48024e4a | bellard | int i;
|
1865 | 48024e4a | bellard | const char *d; |
1866 | 48024e4a | bellard | unsigned int arch_mask; |
1867 | 48024e4a | bellard | struct private priv;
|
1868 | 48024e4a | bellard | bfd_byte *buffer = priv.the_buffer; |
1869 | 48024e4a | bellard | int major_opcode;
|
1870 | 48024e4a | bellard | static int numopcodes[16]; |
1871 | 48024e4a | bellard | static const struct m68k_opcode **opcodes[16]; |
1872 | 48024e4a | bellard | int val;
|
1873 | 48024e4a | bellard | |
1874 | 48024e4a | bellard | if (!opcodes[0]) |
1875 | 48024e4a | bellard | { |
1876 | 48024e4a | bellard | /* Speed up the matching by sorting the opcode
|
1877 | 48024e4a | bellard | table on the upper four bits of the opcode. */
|
1878 | 48024e4a | bellard | const struct m68k_opcode **opc_pointer[16]; |
1879 | 48024e4a | bellard | |
1880 | 48024e4a | bellard | /* First count how many opcodes are in each of the sixteen buckets. */
|
1881 | 48024e4a | bellard | for (i = 0; i < m68k_numopcodes; i++) |
1882 | 48024e4a | bellard | numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; |
1883 | 48024e4a | bellard | |
1884 | 48024e4a | bellard | /* Then create a sorted table of pointers
|
1885 | 48024e4a | bellard | that point into the unsorted table. */
|
1886 | 48024e4a | bellard | opc_pointer[0] = malloc (sizeof (struct m68k_opcode *) |
1887 | 48024e4a | bellard | * m68k_numopcodes); |
1888 | 48024e4a | bellard | opcodes[0] = opc_pointer[0]; |
1889 | 48024e4a | bellard | |
1890 | 48024e4a | bellard | for (i = 1; i < 16; i++) |
1891 | 48024e4a | bellard | { |
1892 | 48024e4a | bellard | opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; |
1893 | 48024e4a | bellard | opcodes[i] = opc_pointer[i]; |
1894 | 48024e4a | bellard | } |
1895 | 48024e4a | bellard | |
1896 | 48024e4a | bellard | for (i = 0; i < m68k_numopcodes; i++) |
1897 | 48024e4a | bellard | *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; |
1898 | 48024e4a | bellard | } |
1899 | 48024e4a | bellard | |
1900 | 48024e4a | bellard | info->private_data = (PTR) &priv; |
1901 | 48024e4a | bellard | /* Tell objdump to use two bytes per chunk
|
1902 | 48024e4a | bellard | and six bytes per line for displaying raw data. */
|
1903 | 48024e4a | bellard | info->bytes_per_chunk = 2;
|
1904 | 48024e4a | bellard | info->bytes_per_line = 6;
|
1905 | 48024e4a | bellard | info->display_endian = BFD_ENDIAN_BIG; |
1906 | 48024e4a | bellard | priv.max_fetched = priv.the_buffer; |
1907 | 48024e4a | bellard | priv.insn_start = memaddr; |
1908 | 48024e4a | bellard | |
1909 | 48024e4a | bellard | if (setjmp (priv.bailout) != 0) |
1910 | 48024e4a | bellard | /* Error return. */
|
1911 | 48024e4a | bellard | return -1; |
1912 | 48024e4a | bellard | |
1913 | 48024e4a | bellard | switch (info->mach)
|
1914 | 48024e4a | bellard | { |
1915 | 48024e4a | bellard | default:
|
1916 | 48024e4a | bellard | case 0: |
1917 | 48024e4a | bellard | arch_mask = (unsigned int) -1; |
1918 | 48024e4a | bellard | break;
|
1919 | 48024e4a | bellard | case bfd_mach_m68000:
|
1920 | 48024e4a | bellard | arch_mask = m68000|m68881|m68851; |
1921 | 48024e4a | bellard | break;
|
1922 | 48024e4a | bellard | case bfd_mach_m68008:
|
1923 | 48024e4a | bellard | arch_mask = m68008|m68881|m68851; |
1924 | 48024e4a | bellard | break;
|
1925 | 48024e4a | bellard | case bfd_mach_m68010:
|
1926 | 48024e4a | bellard | arch_mask = m68010|m68881|m68851; |
1927 | 48024e4a | bellard | break;
|
1928 | 48024e4a | bellard | case bfd_mach_m68020:
|
1929 | 48024e4a | bellard | arch_mask = m68020|m68881|m68851; |
1930 | 48024e4a | bellard | break;
|
1931 | 48024e4a | bellard | case bfd_mach_m68030:
|
1932 | 48024e4a | bellard | arch_mask = m68030|m68881|m68851; |
1933 | 48024e4a | bellard | break;
|
1934 | 48024e4a | bellard | case bfd_mach_m68040:
|
1935 | 48024e4a | bellard | arch_mask = m68040|m68881|m68851; |
1936 | 48024e4a | bellard | break;
|
1937 | 48024e4a | bellard | case bfd_mach_m68060:
|
1938 | 48024e4a | bellard | arch_mask = m68060|m68881|m68851; |
1939 | 48024e4a | bellard | break;
|
1940 | 48024e4a | bellard | case bfd_mach_mcf5200:
|
1941 | 48024e4a | bellard | arch_mask = mcfisa_a; |
1942 | 48024e4a | bellard | break;
|
1943 | 48024e4a | bellard | case bfd_mach_mcf521x:
|
1944 | 48024e4a | bellard | case bfd_mach_mcf528x:
|
1945 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; |
1946 | 48024e4a | bellard | break;
|
1947 | 48024e4a | bellard | case bfd_mach_mcf5206e:
|
1948 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfmac; |
1949 | 48024e4a | bellard | break;
|
1950 | 48024e4a | bellard | case bfd_mach_mcf5249:
|
1951 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfemac; |
1952 | 48024e4a | bellard | break;
|
1953 | 48024e4a | bellard | case bfd_mach_mcf5307:
|
1954 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfmac; |
1955 | 48024e4a | bellard | break;
|
1956 | 48024e4a | bellard | case bfd_mach_mcf5407:
|
1957 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; |
1958 | 48024e4a | bellard | break;
|
1959 | 48024e4a | bellard | case bfd_mach_mcf547x:
|
1960 | 48024e4a | bellard | case bfd_mach_mcf548x:
|
1961 | 48024e4a | bellard | case bfd_mach_mcfv4e:
|
1962 | 48024e4a | bellard | arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; |
1963 | 48024e4a | bellard | break;
|
1964 | 48024e4a | bellard | } |
1965 | 48024e4a | bellard | |
1966 | 48024e4a | bellard | FETCH_DATA (info, buffer + 2);
|
1967 | 48024e4a | bellard | major_opcode = (buffer[0] >> 4) & 15; |
1968 | 48024e4a | bellard | |
1969 | 48024e4a | bellard | for (i = 0; i < numopcodes[major_opcode]; i++) |
1970 | 48024e4a | bellard | { |
1971 | 48024e4a | bellard | const struct m68k_opcode *opc = opcodes[major_opcode][i]; |
1972 | 48024e4a | bellard | unsigned long opcode = opc->opcode; |
1973 | 48024e4a | bellard | unsigned long match = opc->match; |
1974 | 48024e4a | bellard | |
1975 | 48024e4a | bellard | if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) |
1976 | 48024e4a | bellard | && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) |
1977 | 48024e4a | bellard | /* Only fetch the next two bytes if we need to. */
|
1978 | 48024e4a | bellard | && (((0xffff & match) == 0) |
1979 | 48024e4a | bellard | || |
1980 | 48024e4a | bellard | (FETCH_DATA (info, buffer + 4)
|
1981 | 48024e4a | bellard | && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) |
1982 | 48024e4a | bellard | && ((0xff & buffer[3] & match) == (0xff & opcode))) |
1983 | 48024e4a | bellard | ) |
1984 | 48024e4a | bellard | && (opc->arch & arch_mask) != 0)
|
1985 | 48024e4a | bellard | { |
1986 | 48024e4a | bellard | /* Don't use for printout the variants of divul and divsl
|
1987 | 48024e4a | bellard | that have the same register number in two places.
|
1988 | 48024e4a | bellard | The more general variants will match instead. */
|
1989 | 48024e4a | bellard | for (d = opc->args; *d; d += 2) |
1990 | 48024e4a | bellard | if (d[1] == 'D') |
1991 | 48024e4a | bellard | break;
|
1992 | 48024e4a | bellard | |
1993 | 48024e4a | bellard | /* Don't use for printout the variants of most floating
|
1994 | 48024e4a | bellard | point coprocessor instructions which use the same
|
1995 | 48024e4a | bellard | register number in two places, as above. */
|
1996 | 48024e4a | bellard | if (*d == '\0') |
1997 | 48024e4a | bellard | for (d = opc->args; *d; d += 2) |
1998 | 48024e4a | bellard | if (d[1] == 't') |
1999 | 48024e4a | bellard | break;
|
2000 | 48024e4a | bellard | |
2001 | 48024e4a | bellard | /* Don't match fmovel with more than one register;
|
2002 | 48024e4a | bellard | wait for fmoveml. */
|
2003 | 48024e4a | bellard | if (*d == '\0') |
2004 | 48024e4a | bellard | { |
2005 | 48024e4a | bellard | for (d = opc->args; *d; d += 2) |
2006 | 48024e4a | bellard | { |
2007 | 48024e4a | bellard | if (d[0] == 's' && d[1] == '8') |
2008 | 48024e4a | bellard | { |
2009 | 48024e4a | bellard | val = fetch_arg (buffer, d[1], 3, info); |
2010 | 48024e4a | bellard | if ((val & (val - 1)) != 0) |
2011 | 48024e4a | bellard | break;
|
2012 | 48024e4a | bellard | } |
2013 | 48024e4a | bellard | } |
2014 | 48024e4a | bellard | } |
2015 | 48024e4a | bellard | |
2016 | 48024e4a | bellard | if (*d == '\0') |
2017 | 48024e4a | bellard | if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
|
2018 | 48024e4a | bellard | return val;
|
2019 | 48024e4a | bellard | } |
2020 | 48024e4a | bellard | } |
2021 | 48024e4a | bellard | |
2022 | 48024e4a | bellard | /* Handle undefined instructions. */
|
2023 | 48024e4a | bellard | info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]); |
2024 | 48024e4a | bellard | return 2; |
2025 | 48024e4a | bellard | } |
2026 | 48024e4a | bellard | /* **** End of m68k-dis.c */
|
2027 | 48024e4a | bellard | /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */
|
2028 | 48024e4a | bellard | /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
|
2029 | 48024e4a | bellard | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
|
2030 | 48024e4a | bellard | 2000, 2001, 2003, 2004, 2005
|
2031 | 48024e4a | bellard | Free Software Foundation, Inc.
|
2032 | 48024e4a | bellard | |
2033 | 48024e4a | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
2034 | 48024e4a | bellard | |
2035 | 48024e4a | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
2036 | 48024e4a | bellard | them and/or modify them under the terms of the GNU General Public
|
2037 | 48024e4a | bellard | License as published by the Free Software Foundation; either version
|
2038 | 48024e4a | bellard | 1, or (at your option) any later version.
|
2039 | 48024e4a | bellard | |
2040 | 48024e4a | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
2041 | 48024e4a | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
2042 | 48024e4a | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
2043 | 48024e4a | bellard | the GNU General Public License for more details.
|
2044 | 48024e4a | bellard | |
2045 | 48024e4a | bellard | You should have received a copy of the GNU General Public License
|
2046 | 8167ee88 | Blue Swirl | along with this file; see the file COPYING. If not,
|
2047 | 8167ee88 | Blue Swirl | see <http://www.gnu.org/licenses/>. */
|
2048 | 48024e4a | bellard | |
2049 | 48024e4a | bellard | #define one(x) ((unsigned int) (x) << 16) |
2050 | 48024e4a | bellard | #define two(x, y) (((unsigned int) (x) << 16) + (y)) |
2051 | 48024e4a | bellard | |
2052 | 48024e4a | bellard | /* The assembler requires that all instances of the same mnemonic must
|
2053 | 48024e4a | bellard | be consecutive. If they aren't, the assembler will bomb at
|
2054 | 48024e4a | bellard | runtime. */
|
2055 | 48024e4a | bellard | |
2056 | 48024e4a | bellard | const struct m68k_opcode m68k_opcodes[] = |
2057 | 48024e4a | bellard | { |
2058 | 48024e4a | bellard | {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, |
2059 | 48024e4a | bellard | {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, |
2060 | 48024e4a | bellard | |
2061 | 48024e4a | bellard | {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, |
2062 | 48024e4a | bellard | {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
2063 | 48024e4a | bellard | |
2064 | 48024e4a | bellard | {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, |
2065 | 48024e4a | bellard | {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, |
2066 | 48024e4a | bellard | {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, |
2067 | 48024e4a | bellard | {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, |
2068 | 48024e4a | bellard | |
2069 | 48024e4a | bellard | {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, |
2070 | 48024e4a | bellard | {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, |
2071 | 48024e4a | bellard | {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, |
2072 | 48024e4a | bellard | |
2073 | 48024e4a | bellard | /* The add opcode can generate the adda, addi, and addq instructions. */
|
2074 | 48024e4a | bellard | {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, |
2075 | 48024e4a | bellard | {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, |
2076 | 48024e4a | bellard | {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, |
2077 | 48024e4a | bellard | {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, |
2078 | 48024e4a | bellard | {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, |
2079 | 48024e4a | bellard | {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, |
2080 | 48024e4a | bellard | {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, |
2081 | 48024e4a | bellard | {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, |
2082 | 48024e4a | bellard | {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, |
2083 | 48024e4a | bellard | {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, |
2084 | 48024e4a | bellard | {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, |
2085 | 48024e4a | bellard | {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, |
2086 | 48024e4a | bellard | {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
2087 | 48024e4a | bellard | {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, |
2088 | 48024e4a | bellard | {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, |
2089 | 48024e4a | bellard | |
2090 | 48024e4a | bellard | {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, |
2091 | 48024e4a | bellard | {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, |
2092 | 48024e4a | bellard | {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, |
2093 | 48024e4a | bellard | {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, |
2094 | 48024e4a | bellard | {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, |
2095 | 48024e4a | bellard | {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, |
2096 | 48024e4a | bellard | |
2097 | 48024e4a | bellard | {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, |
2098 | 48024e4a | bellard | {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, |
2099 | 48024e4a | bellard | {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, |
2100 | 48024e4a | bellard | {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, |
2101 | 48024e4a | bellard | {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, |
2102 | 48024e4a | bellard | {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, |
2103 | 48024e4a | bellard | {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, |
2104 | 48024e4a | bellard | {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, |
2105 | 48024e4a | bellard | {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, |
2106 | 48024e4a | bellard | |
2107 | 48024e4a | bellard | /* The and opcode can generate the andi instruction. */
|
2108 | 48024e4a | bellard | {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, |
2109 | 48024e4a | bellard | {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, |
2110 | 48024e4a | bellard | {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, |
2111 | 48024e4a | bellard | {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, |
2112 | 48024e4a | bellard | {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, |
2113 | 48024e4a | bellard | {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, |
2114 | 48024e4a | bellard | {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, |
2115 | 48024e4a | bellard | {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, |
2116 | 48024e4a | bellard | {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, |
2117 | 48024e4a | bellard | {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, |
2118 | 48024e4a | bellard | {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, |
2119 | 48024e4a | bellard | {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, |
2120 | 48024e4a | bellard | {"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, |
2121 | 48024e4a | bellard | {"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, |
2122 | 48024e4a | bellard | {"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, |
2123 | 48024e4a | bellard | {"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, |
2124 | 48024e4a | bellard | {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, |
2125 | 48024e4a | bellard | |
2126 | 48024e4a | bellard | {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, |
2127 | 48024e4a | bellard | {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, |
2128 | 48024e4a | bellard | {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, |
2129 | 48024e4a | bellard | {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, |
2130 | 48024e4a | bellard | {"aslw", 2, one(0160700), one(0177700), "~s", m68000up }, |
2131 | 48024e4a | bellard | {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, |
2132 | 48024e4a | bellard | {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, |
2133 | 48024e4a | bellard | |
2134 | 48024e4a | bellard | {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, |
2135 | 48024e4a | bellard | {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, |
2136 | 48024e4a | bellard | {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, |
2137 | 48024e4a | bellard | {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, |
2138 | 48024e4a | bellard | {"asrw", 2, one(0160300), one(0177700), "~s", m68000up }, |
2139 | 48024e4a | bellard | {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, |
2140 | 48024e4a | bellard | {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, |
2141 | 48024e4a | bellard | |
2142 | 48024e4a | bellard | {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, |
2143 | 48024e4a | bellard | {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, |
2144 | 48024e4a | bellard | {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, |
2145 | 48024e4a | bellard | {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, |
2146 | 48024e4a | bellard | {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, |
2147 | 48024e4a | bellard | {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, |
2148 | 48024e4a | bellard | {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, |
2149 | 48024e4a | bellard | {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, |
2150 | 48024e4a | bellard | {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, |
2151 | 48024e4a | bellard | {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, |
2152 | 48024e4a | bellard | {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, |
2153 | 48024e4a | bellard | {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, |
2154 | 48024e4a | bellard | {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, |
2155 | 48024e4a | bellard | {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, |
2156 | 48024e4a | bellard | |
2157 | 48024e4a | bellard | {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2158 | 48024e4a | bellard | {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2159 | 48024e4a | bellard | {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2160 | 48024e4a | bellard | {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2161 | 48024e4a | bellard | {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2162 | 48024e4a | bellard | {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2163 | 48024e4a | bellard | {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2164 | 48024e4a | bellard | {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2165 | 48024e4a | bellard | {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2166 | 48024e4a | bellard | {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2167 | 48024e4a | bellard | {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2168 | 48024e4a | bellard | {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2169 | 48024e4a | bellard | {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2170 | 48024e4a | bellard | {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2171 | 48024e4a | bellard | |
2172 | 48024e4a | bellard | {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, |
2173 | 48024e4a | bellard | {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, |
2174 | 48024e4a | bellard | {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, |
2175 | 48024e4a | bellard | {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, |
2176 | 48024e4a | bellard | {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, |
2177 | 48024e4a | bellard | {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, |
2178 | 48024e4a | bellard | {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, |
2179 | 48024e4a | bellard | {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, |
2180 | 48024e4a | bellard | {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, |
2181 | 48024e4a | bellard | {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, |
2182 | 48024e4a | bellard | {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, |
2183 | 48024e4a | bellard | {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, |
2184 | 48024e4a | bellard | {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, |
2185 | 48024e4a | bellard | {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, |
2186 | 48024e4a | bellard | |
2187 | 48024e4a | bellard | {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2188 | 48024e4a | bellard | {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2189 | 48024e4a | bellard | {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2190 | 48024e4a | bellard | {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2191 | 48024e4a | bellard | {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2192 | 48024e4a | bellard | {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2193 | 48024e4a | bellard | {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2194 | 48024e4a | bellard | {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2195 | 48024e4a | bellard | {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2196 | 48024e4a | bellard | {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2197 | 48024e4a | bellard | {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2198 | 48024e4a | bellard | {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2199 | 48024e4a | bellard | {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, |
2200 | 48024e4a | bellard | {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, |
2201 | 48024e4a | bellard | |
2202 | 48024e4a | bellard | {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, |
2203 | 48024e4a | bellard | {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, |
2204 | 48024e4a | bellard | {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, |
2205 | 48024e4a | bellard | |
2206 | 48024e4a | bellard | {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, |
2207 | 48024e4a | bellard | {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, |
2208 | 48024e4a | bellard | {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, |
2209 | 48024e4a | bellard | |
2210 | 48024e4a | bellard | {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, |
2211 | 48024e4a | bellard | {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, |
2212 | 48024e4a | bellard | {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, |
2213 | 48024e4a | bellard | {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, |
2214 | 48024e4a | bellard | {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, |
2215 | 48024e4a | bellard | {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, |
2216 | 48024e4a | bellard | {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, |
2217 | 48024e4a | bellard | {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, |
2218 | 48024e4a | bellard | |
2219 | 48024e4a | bellard | {"bgnd", 2, one(0045372), one(0177777), "", cpu32 }, |
2220 | 48024e4a | bellard | |
2221 | 48024e4a | bellard | {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa}, |
2222 | 48024e4a | bellard | |
2223 | 48024e4a | bellard | {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, |
2224 | 48024e4a | bellard | |
2225 | 48024e4a | bellard | {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, |
2226 | 48024e4a | bellard | {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2227 | 48024e4a | bellard | {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, |
2228 | 48024e4a | bellard | |
2229 | 48024e4a | bellard | {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, |
2230 | 48024e4a | bellard | {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, |
2231 | 48024e4a | bellard | {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, |
2232 | 48024e4a | bellard | {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, |
2233 | 48024e4a | bellard | |
2234 | 48024e4a | bellard | {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, |
2235 | 48024e4a | bellard | {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, |
2236 | 48024e4a | bellard | {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, |
2237 | 48024e4a | bellard | |
2238 | 48024e4a | bellard | {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, |
2239 | 48024e4a | bellard | {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, |
2240 | 48024e4a | bellard | {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, |
2241 | 48024e4a | bellard | |
2242 | 48024e4a | bellard | {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa}, |
2243 | 48024e4a | bellard | |
2244 | 48024e4a | bellard | {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, |
2245 | 48024e4a | bellard | |
2246 | 48024e4a | bellard | {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, |
2247 | 48024e4a | bellard | {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, |
2248 | 48024e4a | bellard | {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, |
2249 | 48024e4a | bellard | {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, |
2250 | 48024e4a | bellard | |
2251 | 48024e4a | bellard | {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, |
2252 | 48024e4a | bellard | {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, |
2253 | 48024e4a | bellard | {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, |
2254 | 48024e4a | bellard | |
2255 | 48024e4a | bellard | {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2256 | 48024e4a | bellard | {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2257 | 48024e4a | bellard | {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2258 | 48024e4a | bellard | |
2259 | 48024e4a | bellard | {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up }, |
2260 | 48024e4a | bellard | {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, |
2261 | 48024e4a | bellard | |
2262 | 48024e4a | bellard | #define SCOPE_LINE (0x1 << 3) |
2263 | 48024e4a | bellard | #define SCOPE_PAGE (0x2 << 3) |
2264 | 48024e4a | bellard | #define SCOPE_ALL (0x3 << 3) |
2265 | 48024e4a | bellard | |
2266 | 48024e4a | bellard | {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, |
2267 | 48024e4a | bellard | {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, |
2268 | 48024e4a | bellard | {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, |
2269 | 48024e4a | bellard | |
2270 | 48024e4a | bellard | {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, |
2271 | 48024e4a | bellard | {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, |
2272 | 48024e4a | bellard | {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, |
2273 | 48024e4a | bellard | |
2274 | 48024e4a | bellard | #undef SCOPE_LINE
|
2275 | 48024e4a | bellard | #undef SCOPE_PAGE
|
2276 | 48024e4a | bellard | #undef SCOPE_ALL
|
2277 | 48024e4a | bellard | |
2278 | 48024e4a | bellard | {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, |
2279 | 48024e4a | bellard | {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, |
2280 | 48024e4a | bellard | {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, |
2281 | 48024e4a | bellard | |
2282 | 48024e4a | bellard | {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2283 | 48024e4a | bellard | {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2284 | 48024e4a | bellard | {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, |
2285 | 48024e4a | bellard | |
2286 | 48024e4a | bellard | {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, |
2287 | 48024e4a | bellard | {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
2288 | 48024e4a | bellard | |
2289 | 48024e4a | bellard | {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up }, |
2290 | 48024e4a | bellard | {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, |
2291 | 48024e4a | bellard | {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up }, |
2292 | 48024e4a | bellard | {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, |
2293 | 48024e4a | bellard | {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up }, |
2294 | 48024e4a | bellard | {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, |
2295 | 48024e4a | bellard | |
2296 | 48024e4a | bellard | {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, |
2297 | 48024e4a | bellard | {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, |
2298 | 48024e4a | bellard | {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, |
2299 | 48024e4a | bellard | |
2300 | 48024e4a | bellard | /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
|
2301 | 48024e4a | bellard | {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up }, |
2302 | 48024e4a | bellard | {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, |
2303 | 48024e4a | bellard | {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, |
2304 | 48024e4a | bellard | {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, |
2305 | 48024e4a | bellard | {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b }, |
2306 | 48024e4a | bellard | {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, |
2307 | 48024e4a | bellard | {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up }, |
2308 | 48024e4a | bellard | {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, |
2309 | 48024e4a | bellard | {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, |
2310 | 48024e4a | bellard | {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b }, |
2311 | 48024e4a | bellard | {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
2312 | 48024e4a | bellard | {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up }, |
2313 | 48024e4a | bellard | {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, |
2314 | 48024e4a | bellard | {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, |
2315 | 48024e4a | bellard | {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, |
2316 | 48024e4a | bellard | |
2317 | 48024e4a | bellard | {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, |
2318 | 48024e4a | bellard | {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, |
2319 | 48024e4a | bellard | {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, |
2320 | 48024e4a | bellard | {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, |
2321 | 48024e4a | bellard | {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, |
2322 | 48024e4a | bellard | {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, |
2323 | 48024e4a | bellard | {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, |
2324 | 48024e4a | bellard | {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, |
2325 | 48024e4a | bellard | {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, |
2326 | 48024e4a | bellard | {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, |
2327 | 48024e4a | bellard | {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, |
2328 | 48024e4a | bellard | {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, |
2329 | 48024e4a | bellard | {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, |
2330 | 48024e4a | bellard | {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, |
2331 | 48024e4a | bellard | {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, |
2332 | 48024e4a | bellard | {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, |
2333 | 48024e4a | bellard | |
2334 | 48024e4a | bellard | {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, |
2335 | 48024e4a | bellard | |
2336 | 48024e4a | bellard | {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, |
2337 | 48024e4a | bellard | {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, |
2338 | 48024e4a | bellard | {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, |
2339 | 48024e4a | bellard | |
2340 | 48024e4a | bellard | {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, |
2341 | 48024e4a | bellard | {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, |
2342 | 48024e4a | bellard | |
2343 | 48024e4a | bellard | {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, |
2344 | 48024e4a | bellard | |
2345 | 48024e4a | bellard | {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, |
2346 | 48024e4a | bellard | {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, |
2347 | 48024e4a | bellard | {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, |
2348 | 48024e4a | bellard | |
2349 | 48024e4a | bellard | {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, |
2350 | 48024e4a | bellard | {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, |
2351 | 48024e4a | bellard | |
2352 | 48024e4a | bellard | {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, |
2353 | 48024e4a | bellard | {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, |
2354 | 48024e4a | bellard | {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, |
2355 | 48024e4a | bellard | {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, |
2356 | 48024e4a | bellard | {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, |
2357 | 48024e4a | bellard | {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, |
2358 | 48024e4a | bellard | {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, |
2359 | 48024e4a | bellard | {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, |
2360 | 48024e4a | bellard | {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, |
2361 | 48024e4a | bellard | |
2362 | 48024e4a | bellard | /* The eor opcode can generate the eori instruction. */
|
2363 | 48024e4a | bellard | {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, |
2364 | 48024e4a | bellard | {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, |
2365 | 48024e4a | bellard | {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, |
2366 | 48024e4a | bellard | {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, |
2367 | 48024e4a | bellard | {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, |
2368 | 48024e4a | bellard | {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, |
2369 | 48024e4a | bellard | {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, |
2370 | 48024e4a | bellard | {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, |
2371 | 48024e4a | bellard | {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, |
2372 | 48024e4a | bellard | {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, |
2373 | 48024e4a | bellard | {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, |
2374 | 48024e4a | bellard | {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, |
2375 | 48024e4a | bellard | {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, |
2376 | 3b46e624 | ths | |
2377 | 48024e4a | bellard | {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, |
2378 | 48024e4a | bellard | {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, |
2379 | 48024e4a | bellard | {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, |
2380 | 48024e4a | bellard | {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, |
2381 | 48024e4a | bellard | |
2382 | 48024e4a | bellard | {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, |
2383 | 48024e4a | bellard | {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, |
2384 | 48024e4a | bellard | {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a }, |
2385 | 48024e4a | bellard | |
2386 | 48024e4a | bellard | {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa}, |
2387 | 48024e4a | bellard | |
2388 | 48024e4a | bellard | /* float stuff starts here */
|
2389 | 48024e4a | bellard | |
2390 | 48024e4a | bellard | {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2391 | 48024e4a | bellard | {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2392 | 48024e4a | bellard | {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2393 | 48024e4a | bellard | {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
2394 | 48024e4a | bellard | {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2395 | 48024e4a | bellard | {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2396 | 48024e4a | bellard | {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2397 | 48024e4a | bellard | {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2398 | 48024e4a | bellard | {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2399 | 48024e4a | bellard | {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, |
2400 | 48024e4a | bellard | {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2401 | 48024e4a | bellard | {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2402 | 48024e4a | bellard | {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2403 | 48024e4a | bellard | {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2404 | 48024e4a | bellard | {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2405 | 48024e4a | bellard | {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2406 | 48024e4a | bellard | |
2407 | 48024e4a | bellard | {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2408 | 48024e4a | bellard | {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2409 | 48024e4a | bellard | {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2410 | 48024e4a | bellard | {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
2411 | 48024e4a | bellard | {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2412 | 48024e4a | bellard | {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2413 | 48024e4a | bellard | {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2414 | 48024e4a | bellard | {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2415 | 48024e4a | bellard | {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2416 | 48024e4a | bellard | {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2417 | 48024e4a | bellard | {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2418 | 48024e4a | bellard | {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2419 | 48024e4a | bellard | {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2420 | 48024e4a | bellard | {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2421 | 48024e4a | bellard | {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2422 | 48024e4a | bellard | {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
2423 | 48024e4a | bellard | |
2424 | 48024e4a | bellard | {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2425 | 48024e4a | bellard | {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, |
2426 | 48024e4a | bellard | {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2427 | 48024e4a | bellard | {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
2428 | 48024e4a | bellard | {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2429 | 48024e4a | bellard | {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, |
2430 | 48024e4a | bellard | {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2431 | 48024e4a | bellard | {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, |
2432 | 48024e4a | bellard | {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, |
2433 | 48024e4a | bellard | {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2434 | 48024e4a | bellard | {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, |
2435 | 48024e4a | bellard | {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2436 | 48024e4a | bellard | {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, |
2437 | 48024e4a | bellard | {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, |
2438 | 48024e4a | bellard | {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, |
2439 | 48024e4a | bellard | {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, |
2440 | 48024e4a | bellard | |
2441 | 48024e4a | bellard | {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2442 | 48024e4a | bellard | {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2443 | 48024e4a | bellard | {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2444 | 48024e4a | bellard | {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2445 | 48024e4a | bellard | {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2446 | 48024e4a | bellard | {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2447 | 48024e4a | bellard | {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2448 | 48024e4a | bellard | {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2449 | 48024e4a | bellard | {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2450 | 48024e4a | bellard | |
2451 | 48024e4a | bellard | {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2452 | 48024e4a | bellard | {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2453 | 48024e4a | bellard | {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2454 | 48024e4a | bellard | {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2455 | 48024e4a | bellard | {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2456 | 48024e4a | bellard | {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2457 | 48024e4a | bellard | {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2458 | 48024e4a | bellard | {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2459 | 48024e4a | bellard | {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2460 | 48024e4a | bellard | {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2461 | 48024e4a | bellard | {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2462 | 48024e4a | bellard | {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2463 | 48024e4a | bellard | {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2464 | 48024e4a | bellard | {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2465 | 48024e4a | bellard | {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2466 | 48024e4a | bellard | |
2467 | 48024e4a | bellard | {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2468 | 48024e4a | bellard | {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2469 | 48024e4a | bellard | {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2470 | 48024e4a | bellard | {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2471 | 48024e4a | bellard | {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2472 | 48024e4a | bellard | {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2473 | 48024e4a | bellard | {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2474 | 48024e4a | bellard | {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2475 | 48024e4a | bellard | {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2476 | 48024e4a | bellard | {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2477 | 48024e4a | bellard | {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2478 | 48024e4a | bellard | {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2479 | 48024e4a | bellard | {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2480 | 48024e4a | bellard | {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2481 | 48024e4a | bellard | |
2482 | 48024e4a | bellard | {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2483 | 48024e4a | bellard | {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2484 | 48024e4a | bellard | {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2485 | 48024e4a | bellard | {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2486 | 48024e4a | bellard | {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2487 | 48024e4a | bellard | {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2488 | 48024e4a | bellard | {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2489 | 48024e4a | bellard | {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2490 | 48024e4a | bellard | {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2491 | 48024e4a | bellard | {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2492 | 48024e4a | bellard | {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2493 | 48024e4a | bellard | {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2494 | 48024e4a | bellard | {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2495 | 48024e4a | bellard | {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2496 | 48024e4a | bellard | |
2497 | 48024e4a | bellard | {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2498 | 48024e4a | bellard | {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2499 | 48024e4a | bellard | {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2500 | 48024e4a | bellard | {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2501 | 48024e4a | bellard | {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2502 | 48024e4a | bellard | {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2503 | 48024e4a | bellard | {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2504 | 48024e4a | bellard | {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2505 | 48024e4a | bellard | {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2506 | 48024e4a | bellard | |
2507 | 48024e4a | bellard | {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2508 | 48024e4a | bellard | {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2509 | 48024e4a | bellard | {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2510 | 48024e4a | bellard | {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2511 | 48024e4a | bellard | {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2512 | 48024e4a | bellard | {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2513 | 48024e4a | bellard | {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2514 | 48024e4a | bellard | {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2515 | 48024e4a | bellard | {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2516 | 48024e4a | bellard | |
2517 | 48024e4a | bellard | {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2518 | 48024e4a | bellard | {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2519 | 48024e4a | bellard | {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2520 | 48024e4a | bellard | {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2521 | 48024e4a | bellard | {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2522 | 48024e4a | bellard | {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2523 | 48024e4a | bellard | {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2524 | 48024e4a | bellard | {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2525 | 48024e4a | bellard | {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2526 | 48024e4a | bellard | |
2527 | 48024e4a | bellard | {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2528 | 48024e4a | bellard | {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2529 | 48024e4a | bellard | {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2530 | 48024e4a | bellard | {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2531 | 48024e4a | bellard | {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2532 | 48024e4a | bellard | {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2533 | 48024e4a | bellard | {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2534 | 48024e4a | bellard | {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2535 | 48024e4a | bellard | {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2536 | 48024e4a | bellard | {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2537 | 48024e4a | bellard | {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2538 | 48024e4a | bellard | {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2539 | 48024e4a | bellard | {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2540 | 48024e4a | bellard | {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2541 | 48024e4a | bellard | {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2542 | 48024e4a | bellard | {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2543 | 48024e4a | bellard | {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2544 | 48024e4a | bellard | {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2545 | 48024e4a | bellard | {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2546 | 48024e4a | bellard | {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2547 | 48024e4a | bellard | {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2548 | 48024e4a | bellard | {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2549 | 48024e4a | bellard | {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2550 | 48024e4a | bellard | {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2551 | 48024e4a | bellard | {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2552 | 48024e4a | bellard | {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2553 | 48024e4a | bellard | {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2554 | 48024e4a | bellard | {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2555 | 48024e4a | bellard | {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2556 | 48024e4a | bellard | {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2557 | 48024e4a | bellard | {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2558 | 48024e4a | bellard | {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, |
2559 | 48024e4a | bellard | |
2560 | 48024e4a | bellard | {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2561 | 48024e4a | bellard | {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2562 | 48024e4a | bellard | {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2563 | 48024e4a | bellard | {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2564 | 48024e4a | bellard | {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2565 | 48024e4a | bellard | {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2566 | 48024e4a | bellard | {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2567 | 48024e4a | bellard | {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2568 | 48024e4a | bellard | {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2569 | 48024e4a | bellard | {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2570 | 48024e4a | bellard | {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2571 | 48024e4a | bellard | {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2572 | 48024e4a | bellard | {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2573 | 48024e4a | bellard | {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2574 | 48024e4a | bellard | {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2575 | 48024e4a | bellard | {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2576 | 48024e4a | bellard | {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2577 | 48024e4a | bellard | {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2578 | 48024e4a | bellard | {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2579 | 48024e4a | bellard | {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2580 | 48024e4a | bellard | {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2581 | 48024e4a | bellard | {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2582 | 48024e4a | bellard | {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2583 | 48024e4a | bellard | {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2584 | 48024e4a | bellard | {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2585 | 48024e4a | bellard | {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2586 | 48024e4a | bellard | {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2587 | 48024e4a | bellard | {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2588 | 48024e4a | bellard | {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2589 | 48024e4a | bellard | {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2590 | 48024e4a | bellard | {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2591 | 48024e4a | bellard | {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, |
2592 | 48024e4a | bellard | |
2593 | 48024e4a | bellard | {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2594 | 48024e4a | bellard | {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2595 | 48024e4a | bellard | {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2596 | 48024e4a | bellard | {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2597 | 48024e4a | bellard | {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2598 | 48024e4a | bellard | {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2599 | 48024e4a | bellard | {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2600 | 48024e4a | bellard | {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2601 | 48024e4a | bellard | {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2602 | 48024e4a | bellard | {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2603 | 48024e4a | bellard | {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2604 | 48024e4a | bellard | {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2605 | 48024e4a | bellard | {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2606 | 48024e4a | bellard | {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2607 | 48024e4a | bellard | {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2608 | 48024e4a | bellard | {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2609 | 48024e4a | bellard | {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2610 | 48024e4a | bellard | {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2611 | 48024e4a | bellard | {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2612 | 48024e4a | bellard | {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2613 | 48024e4a | bellard | {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2614 | 48024e4a | bellard | {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2615 | 48024e4a | bellard | {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2616 | 48024e4a | bellard | {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2617 | 48024e4a | bellard | {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2618 | 48024e4a | bellard | {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2619 | 48024e4a | bellard | {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2620 | 48024e4a | bellard | {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2621 | 48024e4a | bellard | {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2622 | 48024e4a | bellard | {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2623 | 48024e4a | bellard | {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2624 | 48024e4a | bellard | {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, |
2625 | 48024e4a | bellard | |
2626 | 48024e4a | bellard | {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2627 | 48024e4a | bellard | {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2628 | 48024e4a | bellard | {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2629 | 48024e4a | bellard | {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2630 | 48024e4a | bellard | {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2631 | 48024e4a | bellard | {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2632 | 48024e4a | bellard | {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2633 | 48024e4a | bellard | {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2634 | 48024e4a | bellard | {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2635 | 48024e4a | bellard | {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2636 | 48024e4a | bellard | {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2637 | 48024e4a | bellard | {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2638 | 48024e4a | bellard | {"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2639 | 48024e4a | bellard | {"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2640 | 48024e4a | bellard | |
2641 | 48024e4a | bellard | {"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2642 | 48024e4a | bellard | {"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2643 | 48024e4a | bellard | {"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2644 | 48024e4a | bellard | {"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2645 | 48024e4a | bellard | {"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2646 | 48024e4a | bellard | {"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2647 | 48024e4a | bellard | {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2648 | 48024e4a | bellard | {"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2649 | 48024e4a | bellard | {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2650 | 48024e4a | bellard | |
2651 | 48024e4a | bellard | {"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2652 | 48024e4a | bellard | {"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2653 | 48024e4a | bellard | {"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2654 | 48024e4a | bellard | {"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2655 | 48024e4a | bellard | {"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2656 | 48024e4a | bellard | {"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2657 | 48024e4a | bellard | {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2658 | 48024e4a | bellard | {"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2659 | 48024e4a | bellard | {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2660 | 48024e4a | bellard | |
2661 | 48024e4a | bellard | {"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2662 | 48024e4a | bellard | {"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2663 | 48024e4a | bellard | {"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2664 | 48024e4a | bellard | {"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2665 | 48024e4a | bellard | {"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2666 | 48024e4a | bellard | {"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2667 | 48024e4a | bellard | {"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2668 | 48024e4a | bellard | {"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2669 | 48024e4a | bellard | {"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2670 | 48024e4a | bellard | {"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2671 | 48024e4a | bellard | {"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2672 | 48024e4a | bellard | {"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2673 | 48024e4a | bellard | {"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2674 | 48024e4a | bellard | {"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2675 | 48024e4a | bellard | {"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2676 | 48024e4a | bellard | {"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2677 | 48024e4a | bellard | {"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2678 | 48024e4a | bellard | {"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2679 | 48024e4a | bellard | {"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2680 | 48024e4a | bellard | {"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2681 | 48024e4a | bellard | {"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2682 | 48024e4a | bellard | {"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2683 | 48024e4a | bellard | {"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2684 | 48024e4a | bellard | {"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2685 | 48024e4a | bellard | {"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2686 | 48024e4a | bellard | {"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2687 | 48024e4a | bellard | {"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2688 | 48024e4a | bellard | {"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2689 | 48024e4a | bellard | {"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2690 | 48024e4a | bellard | {"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2691 | 48024e4a | bellard | {"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2692 | 48024e4a | bellard | {"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, |
2693 | 48024e4a | bellard | |
2694 | 48024e4a | bellard | {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2695 | 48024e4a | bellard | {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2696 | 48024e4a | bellard | {"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2697 | 48024e4a | bellard | {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2698 | 48024e4a | bellard | {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2699 | 48024e4a | bellard | {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2700 | 48024e4a | bellard | {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2701 | 48024e4a | bellard | {"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2702 | 48024e4a | bellard | {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2703 | 48024e4a | bellard | {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2704 | 48024e4a | bellard | {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2705 | 48024e4a | bellard | {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2706 | 48024e4a | bellard | {"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2707 | 48024e4a | bellard | {"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2708 | 48024e4a | bellard | |
2709 | 48024e4a | bellard | {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2710 | 48024e4a | bellard | {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2711 | 48024e4a | bellard | {"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2712 | 48024e4a | bellard | {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2713 | 48024e4a | bellard | {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2714 | 48024e4a | bellard | {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2715 | 48024e4a | bellard | {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2716 | 48024e4a | bellard | {"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2717 | 48024e4a | bellard | {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2718 | 48024e4a | bellard | {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2719 | 48024e4a | bellard | {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2720 | 48024e4a | bellard | {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2721 | 48024e4a | bellard | {"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2722 | 48024e4a | bellard | {"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2723 | 48024e4a | bellard | |
2724 | 48024e4a | bellard | {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2725 | 48024e4a | bellard | {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2726 | 48024e4a | bellard | {"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2727 | 48024e4a | bellard | {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2728 | 48024e4a | bellard | {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2729 | 48024e4a | bellard | {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2730 | 48024e4a | bellard | {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2731 | 48024e4a | bellard | {"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2732 | 48024e4a | bellard | {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2733 | 48024e4a | bellard | {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2734 | 48024e4a | bellard | {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2735 | 48024e4a | bellard | {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2736 | 48024e4a | bellard | {"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2737 | 48024e4a | bellard | {"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2738 | 48024e4a | bellard | |
2739 | 48024e4a | bellard | {"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2740 | 48024e4a | bellard | {"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2741 | 48024e4a | bellard | {"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2742 | 48024e4a | bellard | {"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2743 | 48024e4a | bellard | {"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2744 | 48024e4a | bellard | {"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2745 | 48024e4a | bellard | {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2746 | 48024e4a | bellard | {"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2747 | 48024e4a | bellard | {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2748 | 48024e4a | bellard | |
2749 | 48024e4a | bellard | {"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2750 | 48024e4a | bellard | {"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2751 | 48024e4a | bellard | {"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2752 | 48024e4a | bellard | {"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2753 | 48024e4a | bellard | {"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2754 | 48024e4a | bellard | {"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2755 | 48024e4a | bellard | {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2756 | 48024e4a | bellard | {"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2757 | 48024e4a | bellard | {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2758 | 48024e4a | bellard | |
2759 | 48024e4a | bellard | {"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2760 | 48024e4a | bellard | {"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2761 | 48024e4a | bellard | {"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2762 | 48024e4a | bellard | {"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2763 | 48024e4a | bellard | {"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2764 | 48024e4a | bellard | {"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2765 | 48024e4a | bellard | {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2766 | 48024e4a | bellard | {"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2767 | 48024e4a | bellard | {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2768 | 48024e4a | bellard | |
2769 | 48024e4a | bellard | {"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2770 | 48024e4a | bellard | {"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2771 | 48024e4a | bellard | {"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2772 | 48024e4a | bellard | {"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2773 | 48024e4a | bellard | {"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2774 | 48024e4a | bellard | {"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2775 | 48024e4a | bellard | {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2776 | 48024e4a | bellard | {"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2777 | 48024e4a | bellard | {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2778 | 48024e4a | bellard | |
2779 | 48024e4a | bellard | {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2780 | 48024e4a | bellard | {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2781 | 48024e4a | bellard | {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2782 | 48024e4a | bellard | {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
2783 | 48024e4a | bellard | {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2784 | 48024e4a | bellard | {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2785 | 48024e4a | bellard | {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2786 | 48024e4a | bellard | {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2787 | 48024e4a | bellard | {"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2788 | 48024e4a | bellard | {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2789 | 48024e4a | bellard | {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2790 | 48024e4a | bellard | {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2791 | 48024e4a | bellard | {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2792 | 48024e4a | bellard | {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2793 | 48024e4a | bellard | {"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2794 | 48024e4a | bellard | {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2795 | 48024e4a | bellard | |
2796 | 48024e4a | bellard | {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2797 | 48024e4a | bellard | {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2798 | 48024e4a | bellard | {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2799 | 48024e4a | bellard | {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
2800 | 48024e4a | bellard | {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2801 | 48024e4a | bellard | {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2802 | 48024e4a | bellard | {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2803 | 48024e4a | bellard | {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2804 | 48024e4a | bellard | {"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2805 | 48024e4a | bellard | {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2806 | 48024e4a | bellard | {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2807 | 48024e4a | bellard | {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2808 | 48024e4a | bellard | {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2809 | 48024e4a | bellard | {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2810 | 48024e4a | bellard | {"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2811 | 48024e4a | bellard | {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2812 | 48024e4a | bellard | |
2813 | 48024e4a | bellard | {"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2814 | 48024e4a | bellard | {"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2815 | 48024e4a | bellard | {"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2816 | 48024e4a | bellard | {"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2817 | 48024e4a | bellard | {"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2818 | 48024e4a | bellard | {"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2819 | 48024e4a | bellard | {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2820 | 48024e4a | bellard | {"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2821 | 48024e4a | bellard | {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2822 | 48024e4a | bellard | |
2823 | 48024e4a | bellard | {"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2824 | 48024e4a | bellard | {"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2825 | 48024e4a | bellard | {"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2826 | 48024e4a | bellard | {"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2827 | 48024e4a | bellard | {"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2828 | 48024e4a | bellard | {"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2829 | 48024e4a | bellard | {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2830 | 48024e4a | bellard | {"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2831 | 48024e4a | bellard | {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2832 | 48024e4a | bellard | |
2833 | 48024e4a | bellard | {"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2834 | 48024e4a | bellard | {"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2835 | 48024e4a | bellard | {"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2836 | 48024e4a | bellard | {"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2837 | 48024e4a | bellard | {"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2838 | 48024e4a | bellard | {"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2839 | 48024e4a | bellard | {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2840 | 48024e4a | bellard | {"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2841 | 48024e4a | bellard | {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2842 | 48024e4a | bellard | |
2843 | 48024e4a | bellard | {"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2844 | 48024e4a | bellard | {"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2845 | 48024e4a | bellard | {"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2846 | 48024e4a | bellard | {"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2847 | 48024e4a | bellard | {"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2848 | 48024e4a | bellard | {"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2849 | 48024e4a | bellard | {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2850 | 48024e4a | bellard | {"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2851 | 48024e4a | bellard | {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
2852 | 48024e4a | bellard | |
2853 | 48024e4a | bellard | {"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2854 | 48024e4a | bellard | {"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2855 | 48024e4a | bellard | {"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2856 | 48024e4a | bellard | {"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2857 | 48024e4a | bellard | {"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2858 | 48024e4a | bellard | {"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2859 | 48024e4a | bellard | {"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2860 | 48024e4a | bellard | {"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2861 | 48024e4a | bellard | |
2862 | 48024e4a | bellard | {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2863 | 48024e4a | bellard | {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, |
2864 | 48024e4a | bellard | {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2865 | 48024e4a | bellard | {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, |
2866 | 48024e4a | bellard | {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2867 | 48024e4a | bellard | {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, |
2868 | 48024e4a | bellard | {"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2869 | 48024e4a | bellard | {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2870 | 48024e4a | bellard | {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, |
2871 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2872 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, |
2873 | 48024e4a | bellard | /* FIXME: the next two variants should not permit moving an address
|
2874 | 48024e4a | bellard | register to anything but the floating point instruction register. */
|
2875 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, |
2876 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, |
2877 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2878 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, |
2879 | 48024e4a | bellard | /* Move the FP control registers. */
|
2880 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, |
2881 | 48024e4a | bellard | {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, |
2882 | 48024e4a | bellard | {"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2883 | 48024e4a | bellard | {"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, |
2884 | 48024e4a | bellard | {"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, |
2885 | 48024e4a | bellard | {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2886 | 48024e4a | bellard | {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, |
2887 | 48024e4a | bellard | {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2888 | 48024e4a | bellard | {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2889 | 48024e4a | bellard | {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2890 | 48024e4a | bellard | {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, |
2891 | 48024e4a | bellard | {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2892 | 48024e4a | bellard | {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2893 | 48024e4a | bellard | {"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, |
2894 | 48024e4a | bellard | {"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
2895 | 48024e4a | bellard | {"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, |
2896 | 48024e4a | bellard | |
2897 | 48024e4a | bellard | {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2898 | 48024e4a | bellard | {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2899 | 48024e4a | bellard | {"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2900 | 48024e4a | bellard | {"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2901 | 48024e4a | bellard | {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2902 | 48024e4a | bellard | {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2903 | 48024e4a | bellard | {"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, |
2904 | 48024e4a | bellard | {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2905 | 48024e4a | bellard | {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2906 | 48024e4a | bellard | {"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2907 | 48024e4a | bellard | {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2908 | 48024e4a | bellard | {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2909 | 48024e4a | bellard | {"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2910 | 48024e4a | bellard | {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2911 | 48024e4a | bellard | {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2912 | 48024e4a | bellard | {"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2913 | 48024e4a | bellard | {"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2914 | 48024e4a | bellard | {"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2915 | 48024e4a | bellard | {"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2916 | 48024e4a | bellard | |
2917 | 48024e4a | bellard | {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
2918 | 48024e4a | bellard | {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2919 | 48024e4a | bellard | {"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2920 | 48024e4a | bellard | {"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2921 | 48024e4a | bellard | {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
2922 | 48024e4a | bellard | {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2923 | 48024e4a | bellard | {"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2924 | 48024e4a | bellard | {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
2925 | 48024e4a | bellard | {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2926 | 48024e4a | bellard | {"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2927 | 48024e4a | bellard | {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
2928 | 48024e4a | bellard | {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2929 | 48024e4a | bellard | {"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2930 | 48024e4a | bellard | {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
2931 | 48024e4a | bellard | {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2932 | 48024e4a | bellard | {"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, |
2933 | 48024e4a | bellard | {"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
2934 | 48024e4a | bellard | {"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
2935 | 48024e4a | bellard | {"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
2936 | 48024e4a | bellard | |
2937 | 48024e4a | bellard | {"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, |
2938 | 48024e4a | bellard | |
2939 | 48024e4a | bellard | {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat }, |
2940 | 48024e4a | bellard | {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat }, |
2941 | 48024e4a | bellard | {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat }, |
2942 | 48024e4a | bellard | {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat }, |
2943 | 48024e4a | bellard | |
2944 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, |
2945 | 48024e4a | bellard | {"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, |
2946 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, |
2947 | 48024e4a | bellard | {"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, |
2948 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, |
2949 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, |
2950 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, |
2951 | 48024e4a | bellard | {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, |
2952 | 48024e4a | bellard | {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, |
2953 | 48024e4a | bellard | {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, |
2954 | 48024e4a | bellard | {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, |
2955 | 48024e4a | bellard | {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, |
2956 | 48024e4a | bellard | |
2957 | 48024e4a | bellard | {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, |
2958 | 48024e4a | bellard | {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, |
2959 | 48024e4a | bellard | /* FIXME: In the next instruction, we should only permit %dn if the
|
2960 | 48024e4a | bellard | target is a single register. We should only permit %an if the
|
2961 | 48024e4a | bellard | target is a single %fpiar. */
|
2962 | 48024e4a | bellard | {"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, |
2963 | 48024e4a | bellard | |
2964 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat }, |
2965 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat }, |
2966 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat }, |
2967 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat }, |
2968 | 48024e4a | bellard | |
2969 | 48024e4a | bellard | {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, |
2970 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, |
2971 | 48024e4a | bellard | {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, |
2972 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, |
2973 | 48024e4a | bellard | {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, |
2974 | 48024e4a | bellard | {"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, |
2975 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, |
2976 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, |
2977 | 48024e4a | bellard | {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, |
2978 | 48024e4a | bellard | {"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, |
2979 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, |
2980 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, |
2981 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, |
2982 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, |
2983 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, |
2984 | 48024e4a | bellard | {"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, |
2985 | 48024e4a | bellard | |
2986 | 48024e4a | bellard | {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
2987 | 48024e4a | bellard | {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2988 | 48024e4a | bellard | {"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
2989 | 48024e4a | bellard | {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
2990 | 48024e4a | bellard | {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
2991 | 48024e4a | bellard | {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
2992 | 48024e4a | bellard | {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2993 | 48024e4a | bellard | {"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
2994 | 48024e4a | bellard | {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
2995 | 48024e4a | bellard | {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2996 | 48024e4a | bellard | {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
2997 | 48024e4a | bellard | {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
2998 | 48024e4a | bellard | {"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
2999 | 48024e4a | bellard | {"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3000 | 48024e4a | bellard | |
3001 | 48024e4a | bellard | {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3002 | 48024e4a | bellard | {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3003 | 48024e4a | bellard | {"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3004 | 48024e4a | bellard | {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3005 | 48024e4a | bellard | {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3006 | 48024e4a | bellard | {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3007 | 48024e4a | bellard | {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3008 | 48024e4a | bellard | {"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3009 | 48024e4a | bellard | {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3010 | 48024e4a | bellard | {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3011 | 48024e4a | bellard | {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3012 | 48024e4a | bellard | {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3013 | 48024e4a | bellard | {"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3014 | 48024e4a | bellard | {"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3015 | 48024e4a | bellard | |
3016 | 48024e4a | bellard | {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3017 | 48024e4a | bellard | {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3018 | 48024e4a | bellard | {"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3019 | 48024e4a | bellard | {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3020 | 48024e4a | bellard | {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3021 | 48024e4a | bellard | {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3022 | 48024e4a | bellard | {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3023 | 48024e4a | bellard | {"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3024 | 48024e4a | bellard | {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3025 | 48024e4a | bellard | {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3026 | 48024e4a | bellard | {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3027 | 48024e4a | bellard | {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3028 | 48024e4a | bellard | {"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3029 | 48024e4a | bellard | {"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3030 | 48024e4a | bellard | |
3031 | 48024e4a | bellard | {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3032 | 48024e4a | bellard | {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3033 | 48024e4a | bellard | {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3034 | 48024e4a | bellard | {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3035 | 48024e4a | bellard | {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3036 | 48024e4a | bellard | {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3037 | 48024e4a | bellard | {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3038 | 48024e4a | bellard | {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3039 | 48024e4a | bellard | {"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3040 | 48024e4a | bellard | {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3041 | 48024e4a | bellard | {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3042 | 48024e4a | bellard | {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3043 | 48024e4a | bellard | {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3044 | 48024e4a | bellard | {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3045 | 48024e4a | bellard | {"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3046 | 48024e4a | bellard | {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3047 | 48024e4a | bellard | |
3048 | 48024e4a | bellard | {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3049 | 48024e4a | bellard | {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3050 | 48024e4a | bellard | {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3051 | 48024e4a | bellard | {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3052 | 48024e4a | bellard | {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3053 | 48024e4a | bellard | {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3054 | 48024e4a | bellard | {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3055 | 48024e4a | bellard | {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3056 | 48024e4a | bellard | {"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3057 | 48024e4a | bellard | {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3058 | 48024e4a | bellard | {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3059 | 48024e4a | bellard | {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3060 | 48024e4a | bellard | {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3061 | 48024e4a | bellard | {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3062 | 48024e4a | bellard | {"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3063 | 48024e4a | bellard | {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3064 | 48024e4a | bellard | |
3065 | 48024e4a | bellard | {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3066 | 48024e4a | bellard | {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3067 | 48024e4a | bellard | {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3068 | 48024e4a | bellard | {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3069 | 48024e4a | bellard | {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3070 | 48024e4a | bellard | {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3071 | 48024e4a | bellard | {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3072 | 48024e4a | bellard | {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3073 | 48024e4a | bellard | {"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3074 | 48024e4a | bellard | {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3075 | 48024e4a | bellard | {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3076 | 48024e4a | bellard | {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3077 | 48024e4a | bellard | {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3078 | 48024e4a | bellard | {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3079 | 48024e4a | bellard | {"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3080 | 48024e4a | bellard | {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3081 | 48024e4a | bellard | |
3082 | 48024e4a | bellard | {"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat }, |
3083 | 48024e4a | bellard | |
3084 | 48024e4a | bellard | {"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3085 | 48024e4a | bellard | {"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3086 | 48024e4a | bellard | {"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3087 | 48024e4a | bellard | {"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3088 | 48024e4a | bellard | {"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3089 | 48024e4a | bellard | {"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3090 | 48024e4a | bellard | {"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3091 | 48024e4a | bellard | {"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3092 | 48024e4a | bellard | |
3093 | 48024e4a | bellard | {"frestore", 2, one(0xF140), one(0xF1C0), "Id<s", mfloat }, |
3094 | 48024e4a | bellard | {"frestore", 2, one(0xF140), one(0xF1C0), "Idys", cfloat }, |
3095 | 48024e4a | bellard | |
3096 | 48024e4a | bellard | {"fsave", 2, one(0xF100), one(0xF1C0), "Id>s", mfloat }, |
3097 | 48024e4a | bellard | {"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat }, |
3098 | 48024e4a | bellard | |
3099 | 48024e4a | bellard | {"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3100 | 48024e4a | bellard | {"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3101 | 48024e4a | bellard | {"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3102 | 48024e4a | bellard | {"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3103 | 48024e4a | bellard | {"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3104 | 48024e4a | bellard | {"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3105 | 48024e4a | bellard | {"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3106 | 48024e4a | bellard | {"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3107 | 48024e4a | bellard | |
3108 | 48024e4a | bellard | /* $ is necessary to prevent the assembler from using PC-relative.
|
3109 | 48024e4a | bellard | If @ were used, "label: fseq label" could produce "ftrapeq", 2,
|
3110 | 48024e4a | bellard | because "label" became "pc@label". */
|
3111 | 48024e4a | bellard | {"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3112 | 48024e4a | bellard | {"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3113 | 48024e4a | bellard | {"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3114 | 48024e4a | bellard | {"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3115 | 48024e4a | bellard | {"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3116 | 48024e4a | bellard | {"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3117 | 48024e4a | bellard | {"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3118 | 48024e4a | bellard | {"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3119 | 48024e4a | bellard | {"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3120 | 48024e4a | bellard | {"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3121 | 48024e4a | bellard | {"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3122 | 48024e4a | bellard | {"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3123 | 48024e4a | bellard | {"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3124 | 48024e4a | bellard | {"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3125 | 48024e4a | bellard | {"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3126 | 48024e4a | bellard | {"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3127 | 48024e4a | bellard | {"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3128 | 48024e4a | bellard | {"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3129 | 48024e4a | bellard | {"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3130 | 48024e4a | bellard | {"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3131 | 48024e4a | bellard | {"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3132 | 48024e4a | bellard | {"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3133 | 48024e4a | bellard | {"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3134 | 48024e4a | bellard | {"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3135 | 48024e4a | bellard | {"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3136 | 48024e4a | bellard | {"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3137 | 48024e4a | bellard | {"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3138 | 48024e4a | bellard | {"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3139 | 48024e4a | bellard | {"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3140 | 48024e4a | bellard | {"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3141 | 48024e4a | bellard | {"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3142 | 48024e4a | bellard | {"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, |
3143 | 48024e4a | bellard | |
3144 | 48024e4a | bellard | {"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3145 | 48024e4a | bellard | {"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3146 | 48024e4a | bellard | {"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3147 | 48024e4a | bellard | {"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3148 | 48024e4a | bellard | {"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3149 | 48024e4a | bellard | {"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3150 | 48024e4a | bellard | {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3151 | 48024e4a | bellard | {"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3152 | 48024e4a | bellard | {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3153 | 48024e4a | bellard | |
3154 | 48024e4a | bellard | {"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3155 | 48024e4a | bellard | {"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3156 | 48024e4a | bellard | {"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3157 | 48024e4a | bellard | {"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3158 | 48024e4a | bellard | {"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3159 | 48024e4a | bellard | {"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3160 | 48024e4a | bellard | {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3161 | 48024e4a | bellard | {"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3162 | 48024e4a | bellard | {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3163 | 48024e4a | bellard | |
3164 | 48024e4a | bellard | {"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3165 | 48024e4a | bellard | {"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3166 | 48024e4a | bellard | {"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3167 | 48024e4a | bellard | {"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3168 | 48024e4a | bellard | {"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3169 | 48024e4a | bellard | {"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3170 | 48024e4a | bellard | {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3171 | 48024e4a | bellard | {"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3172 | 48024e4a | bellard | {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3173 | 48024e4a | bellard | |
3174 | 48024e4a | bellard | {"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, |
3175 | 48024e4a | bellard | {"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, |
3176 | 48024e4a | bellard | {"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, |
3177 | 48024e4a | bellard | {"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, |
3178 | 48024e4a | bellard | {"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, |
3179 | 48024e4a | bellard | {"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, |
3180 | 48024e4a | bellard | {"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, |
3181 | 48024e4a | bellard | {"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, |
3182 | 48024e4a | bellard | |
3183 | 48024e4a | bellard | {"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3184 | 48024e4a | bellard | {"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3185 | 48024e4a | bellard | {"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3186 | 48024e4a | bellard | {"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3187 | 48024e4a | bellard | {"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3188 | 48024e4a | bellard | {"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3189 | 48024e4a | bellard | {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3190 | 48024e4a | bellard | {"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3191 | 48024e4a | bellard | {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3192 | 48024e4a | bellard | |
3193 | 48024e4a | bellard | {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3194 | 48024e4a | bellard | {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3195 | 48024e4a | bellard | {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3196 | 48024e4a | bellard | {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3197 | 48024e4a | bellard | {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3198 | 48024e4a | bellard | {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3199 | 48024e4a | bellard | {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3200 | 48024e4a | bellard | {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3201 | 48024e4a | bellard | {"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3202 | 48024e4a | bellard | {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3203 | 48024e4a | bellard | {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3204 | 48024e4a | bellard | {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3205 | 48024e4a | bellard | {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3206 | 48024e4a | bellard | {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3207 | 48024e4a | bellard | {"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3208 | 48024e4a | bellard | {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3209 | 48024e4a | bellard | |
3210 | 48024e4a | bellard | {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3211 | 48024e4a | bellard | {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3212 | 48024e4a | bellard | {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3213 | 48024e4a | bellard | {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3214 | 48024e4a | bellard | {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3215 | 48024e4a | bellard | {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3216 | 48024e4a | bellard | {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3217 | 48024e4a | bellard | {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3218 | 48024e4a | bellard | {"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3219 | 48024e4a | bellard | {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3220 | 48024e4a | bellard | {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3221 | 48024e4a | bellard | {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3222 | 48024e4a | bellard | {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3223 | 48024e4a | bellard | {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3224 | 48024e4a | bellard | {"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3225 | 48024e4a | bellard | {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3226 | 48024e4a | bellard | |
3227 | 48024e4a | bellard | {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3228 | 48024e4a | bellard | {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3229 | 48024e4a | bellard | {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3230 | 48024e4a | bellard | {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat }, |
3231 | 48024e4a | bellard | {"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3232 | 48024e4a | bellard | {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3233 | 48024e4a | bellard | {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3234 | 48024e4a | bellard | {"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3235 | 48024e4a | bellard | {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3236 | 48024e4a | bellard | {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3237 | 48024e4a | bellard | {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3238 | 48024e4a | bellard | {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3239 | 48024e4a | bellard | {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3240 | 48024e4a | bellard | {"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3241 | 48024e4a | bellard | {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3242 | 48024e4a | bellard | |
3243 | 48024e4a | bellard | {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3244 | 48024e4a | bellard | {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3245 | 48024e4a | bellard | {"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3246 | 48024e4a | bellard | {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3247 | 48024e4a | bellard | {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3248 | 48024e4a | bellard | {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3249 | 48024e4a | bellard | {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3250 | 48024e4a | bellard | {"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3251 | 48024e4a | bellard | {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3252 | 48024e4a | bellard | {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3253 | 48024e4a | bellard | {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3254 | 48024e4a | bellard | {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3255 | 48024e4a | bellard | {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3256 | 48024e4a | bellard | {"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3257 | 48024e4a | bellard | {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3258 | 48024e4a | bellard | |
3259 | 48024e4a | bellard | {"fssubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3260 | 48024e4a | bellard | {"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3261 | 48024e4a | bellard | {"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3262 | 48024e4a | bellard | {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3263 | 48024e4a | bellard | {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3264 | 48024e4a | bellard | {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3265 | 48024e4a | bellard | {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3266 | 48024e4a | bellard | {"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3267 | 48024e4a | bellard | {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3268 | 48024e4a | bellard | {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3269 | 48024e4a | bellard | {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3270 | 48024e4a | bellard | {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3271 | 48024e4a | bellard | {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3272 | 48024e4a | bellard | {"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3273 | 48024e4a | bellard | {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3274 | 48024e4a | bellard | |
3275 | 48024e4a | bellard | {"fdsubb", 4, two(0xF000, 0x586A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3276 | 48024e4a | bellard | {"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, |
3277 | 48024e4a | bellard | {"fdsubd", 4, two(0xF000, 0x006A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, |
3278 | 48024e4a | bellard | {"fdsubd", 4, two(0xF000, 0x546A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, |
3279 | 48024e4a | bellard | {"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, |
3280 | 48024e4a | bellard | {"fdsubl", 4, two(0xF000, 0x406A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3281 | 48024e4a | bellard | {"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, |
3282 | 48024e4a | bellard | {"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, |
3283 | 48024e4a | bellard | {"fdsubs", 4, two(0xF000, 0x446A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3284 | 48024e4a | bellard | {"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, |
3285 | 48024e4a | bellard | {"fdsubw", 4, two(0xF000, 0x506A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, |
3286 | 48024e4a | bellard | {"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, |
3287 | 48024e4a | bellard | {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, |
3288 | 48024e4a | bellard | {"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, |
3289 | 48024e4a | bellard | {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, |
3290 | 48024e4a | bellard | |
3291 | 48024e4a | bellard | {"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3292 | 48024e4a | bellard | {"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3293 | 48024e4a | bellard | {"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3294 | 48024e4a | bellard | {"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3295 | 48024e4a | bellard | {"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3296 | 48024e4a | bellard | {"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3297 | 48024e4a | bellard | {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3298 | 48024e4a | bellard | {"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3299 | 48024e4a | bellard | {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3300 | 48024e4a | bellard | |
3301 | 48024e4a | bellard | {"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3302 | 48024e4a | bellard | {"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3303 | 48024e4a | bellard | {"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3304 | 48024e4a | bellard | {"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3305 | 48024e4a | bellard | {"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3306 | 48024e4a | bellard | {"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3307 | 48024e4a | bellard | {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3308 | 48024e4a | bellard | {"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3309 | 48024e4a | bellard | {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3310 | 48024e4a | bellard | |
3311 | 48024e4a | bellard | {"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3312 | 48024e4a | bellard | {"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3313 | 48024e4a | bellard | {"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3314 | 48024e4a | bellard | {"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3315 | 48024e4a | bellard | {"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3316 | 48024e4a | bellard | {"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3317 | 48024e4a | bellard | {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3318 | 48024e4a | bellard | {"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3319 | 48024e4a | bellard | {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3320 | 48024e4a | bellard | |
3321 | 48024e4a | bellard | {"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3322 | 48024e4a | bellard | {"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3323 | 48024e4a | bellard | {"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3324 | 48024e4a | bellard | {"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3325 | 48024e4a | bellard | {"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3326 | 48024e4a | bellard | {"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3327 | 48024e4a | bellard | {"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3328 | 48024e4a | bellard | {"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3329 | 48024e4a | bellard | {"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3330 | 48024e4a | bellard | {"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3331 | 48024e4a | bellard | {"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3332 | 48024e4a | bellard | {"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3333 | 48024e4a | bellard | {"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3334 | 48024e4a | bellard | {"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3335 | 48024e4a | bellard | {"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3336 | 48024e4a | bellard | {"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3337 | 48024e4a | bellard | {"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3338 | 48024e4a | bellard | {"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3339 | 48024e4a | bellard | {"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3340 | 48024e4a | bellard | {"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3341 | 48024e4a | bellard | {"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3342 | 48024e4a | bellard | {"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3343 | 48024e4a | bellard | {"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3344 | 48024e4a | bellard | {"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3345 | 48024e4a | bellard | {"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3346 | 48024e4a | bellard | {"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3347 | 48024e4a | bellard | {"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3348 | 48024e4a | bellard | {"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3349 | 48024e4a | bellard | {"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3350 | 48024e4a | bellard | {"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3351 | 48024e4a | bellard | {"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3352 | 48024e4a | bellard | {"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, |
3353 | 48024e4a | bellard | |
3354 | 48024e4a | bellard | {"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3355 | 48024e4a | bellard | {"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3356 | 48024e4a | bellard | {"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3357 | 48024e4a | bellard | {"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3358 | 48024e4a | bellard | {"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3359 | 48024e4a | bellard | {"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3360 | 48024e4a | bellard | {"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3361 | 48024e4a | bellard | {"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3362 | 48024e4a | bellard | {"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3363 | 48024e4a | bellard | {"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3364 | 48024e4a | bellard | {"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3365 | 48024e4a | bellard | {"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3366 | 48024e4a | bellard | {"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3367 | 48024e4a | bellard | {"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3368 | 48024e4a | bellard | {"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3369 | 48024e4a | bellard | {"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3370 | 48024e4a | bellard | {"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3371 | 48024e4a | bellard | {"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3372 | 48024e4a | bellard | {"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3373 | 48024e4a | bellard | {"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3374 | 48024e4a | bellard | {"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3375 | 48024e4a | bellard | {"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3376 | 48024e4a | bellard | {"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3377 | 48024e4a | bellard | {"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3378 | 48024e4a | bellard | {"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3379 | 48024e4a | bellard | {"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3380 | 48024e4a | bellard | {"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3381 | 48024e4a | bellard | {"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3382 | 48024e4a | bellard | {"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3383 | 48024e4a | bellard | {"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3384 | 48024e4a | bellard | {"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3385 | 48024e4a | bellard | {"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, |
3386 | 48024e4a | bellard | |
3387 | 48024e4a | bellard | {"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3388 | 48024e4a | bellard | {"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3389 | 48024e4a | bellard | {"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3390 | 48024e4a | bellard | {"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3391 | 48024e4a | bellard | {"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3392 | 48024e4a | bellard | {"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3393 | 48024e4a | bellard | {"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3394 | 48024e4a | bellard | {"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3395 | 48024e4a | bellard | {"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3396 | 48024e4a | bellard | {"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3397 | 48024e4a | bellard | {"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3398 | 48024e4a | bellard | {"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3399 | 48024e4a | bellard | {"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3400 | 48024e4a | bellard | {"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3401 | 48024e4a | bellard | {"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3402 | 48024e4a | bellard | {"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3403 | 48024e4a | bellard | {"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3404 | 48024e4a | bellard | {"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3405 | 48024e4a | bellard | {"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3406 | 48024e4a | bellard | {"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3407 | 48024e4a | bellard | {"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3408 | 48024e4a | bellard | {"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3409 | 48024e4a | bellard | {"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3410 | 48024e4a | bellard | {"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3411 | 48024e4a | bellard | {"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3412 | 48024e4a | bellard | {"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3413 | 48024e4a | bellard | {"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3414 | 48024e4a | bellard | {"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3415 | 48024e4a | bellard | {"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3416 | 48024e4a | bellard | {"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3417 | 48024e4a | bellard | {"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3418 | 48024e4a | bellard | {"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, |
3419 | 48024e4a | bellard | |
3420 | 48024e4a | bellard | {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, |
3421 | 48024e4a | bellard | {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, |
3422 | 48024e4a | bellard | {"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat }, |
3423 | 48024e4a | bellard | {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, |
3424 | 48024e4a | bellard | {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, |
3425 | 48024e4a | bellard | {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, |
3426 | 48024e4a | bellard | {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, |
3427 | 48024e4a | bellard | {"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, |
3428 | 48024e4a | bellard | {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, |
3429 | 48024e4a | bellard | {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, |
3430 | 48024e4a | bellard | {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, |
3431 | 48024e4a | bellard | {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, |
3432 | 48024e4a | bellard | {"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, |
3433 | 48024e4a | bellard | {"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, |
3434 | 48024e4a | bellard | |
3435 | 48024e4a | bellard | {"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, |
3436 | 48024e4a | bellard | {"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, |
3437 | 48024e4a | bellard | {"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, |
3438 | 48024e4a | bellard | {"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, |
3439 | 48024e4a | bellard | {"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, |
3440 | 48024e4a | bellard | {"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, |
3441 | 48024e4a | bellard | {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, |
3442 | 48024e4a | bellard | {"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, |
3443 | 48024e4a | bellard | {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, |
3444 | 48024e4a | bellard | |
3445 | 48024e4a | bellard | {"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, |
3446 | 48024e4a | bellard | |
3447 | 48024e4a | bellard | {"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, |
3448 | 48024e4a | bellard | {"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b }, |
3449 | 48024e4a | bellard | |
3450 | 48024e4a | bellard | {"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, |
3451 | 48024e4a | bellard | |
3452 | 48024e4a | bellard | {"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a }, |
3453 | 48024e4a | bellard | {"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, |
3454 | 48024e4a | bellard | |
3455 | 48024e4a | bellard | {"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, |
3456 | 48024e4a | bellard | |
3457 | 48024e4a | bellard | {"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a }, |
3458 | 48024e4a | bellard | {"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, |
3459 | 48024e4a | bellard | |
3460 | 48024e4a | bellard | {"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, |
3461 | 48024e4a | bellard | |
3462 | 48024e4a | bellard | {"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 }, |
3463 | 48024e4a | bellard | |
3464 | 48024e4a | bellard | {"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, |
3465 | 48024e4a | bellard | {"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 }, |
3466 | 48024e4a | bellard | {"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, |
3467 | 48024e4a | bellard | {"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 }, |
3468 | 48024e4a | bellard | |
3469 | 48024e4a | bellard | {"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up }, |
3470 | 48024e4a | bellard | {"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up }, |
3471 | 48024e4a | bellard | {"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up }, |
3472 | 48024e4a | bellard | {"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up }, |
3473 | 48024e4a | bellard | {"lslw", 2, one(0161700), one(0177700), "~s", m68000up }, |
3474 | 48024e4a | bellard | {"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, |
3475 | 48024e4a | bellard | {"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, |
3476 | 48024e4a | bellard | |
3477 | 48024e4a | bellard | {"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up }, |
3478 | 48024e4a | bellard | {"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up }, |
3479 | 48024e4a | bellard | {"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up }, |
3480 | 48024e4a | bellard | {"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up }, |
3481 | 48024e4a | bellard | {"lsrw", 2, one(0161300), one(0177700), "~s", m68000up }, |
3482 | 48024e4a | bellard | {"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, |
3483 | 48024e4a | bellard | {"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, |
3484 | 48024e4a | bellard | |
3485 | 48024e4a | bellard | {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, |
3486 | 48024e4a | bellard | {"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, |
3487 | 48024e4a | bellard | {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, |
3488 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, |
3489 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, |
3490 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac }, |
3491 | 48024e4a | bellard | |
3492 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */ |
3493 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */ |
3494 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */ |
3495 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ |
3496 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ |
3497 | 48024e4a | bellard | {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ |
3498 | 48024e4a | bellard | |
3499 | 48024e4a | bellard | {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, |
3500 | 48024e4a | bellard | {"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, |
3501 | 48024e4a | bellard | {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, |
3502 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, |
3503 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, |
3504 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac }, |
3505 | 48024e4a | bellard | |
3506 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, |
3507 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, |
3508 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, |
3509 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, |
3510 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, |
3511 | 48024e4a | bellard | {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, |
3512 | 48024e4a | bellard | |
3513 | 48024e4a | bellard | /* NOTE: The mcf5200 family programmer's reference manual does not
|
3514 | 48024e4a | bellard | indicate the byte form of the movea instruction is invalid (as it
|
3515 | 48024e4a | bellard | is on 68000 family cpus). However, experiments on the 5202 yeild
|
3516 | 48024e4a | bellard | unexpected results. The value is copied, but it is not sign extended
|
3517 | 48024e4a | bellard | (as is done with movea.w) and the top three bytes in the address
|
3518 | 48024e4a | bellard | register are not disturbed. I don't know if this is the intended
|
3519 | 48024e4a | bellard | behavior --- it could be a hole in instruction decoding (Motorola
|
3520 | 48024e4a | bellard | decided not to trap all invalid instructions for performance reasons)
|
3521 | 48024e4a | bellard | --- but I suspect that it is not.
|
3522 | 48024e4a | bellard | |
3523 | 48024e4a | bellard | I reported this to Motorola ISD Technical Communications Support,
|
3524 | 48024e4a | bellard | which replied that other coldfire assemblers reject movea.b. For
|
3525 | 48024e4a | bellard | this reason I've decided to not allow moveab.
|
3526 | 48024e4a | bellard | |
3527 | 48024e4a | bellard | jtc@cygnus.com - 97/01/24. */
|
3528 | 48024e4a | bellard | |
3529 | 48024e4a | bellard | {"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, |
3530 | 48024e4a | bellard | {"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, |
3531 | 48024e4a | bellard | |
3532 | 48024e4a | bellard | {"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, |
3533 | 48024e4a | bellard | |
3534 | 48024e4a | bellard | {"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, |
3535 | 48024e4a | bellard | {"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, |
3536 | 48024e4a | bellard | {"movec", 4, one(0047172), one(0177777), "JjR1", m68010up }, |
3537 | 48024e4a | bellard | {"movec", 4, one(0047172), one(0177777), "#jR1", m68010up }, |
3538 | 48024e4a | bellard | |
3539 | 48024e4a | bellard | {"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up }, |
3540 | 48024e4a | bellard | {"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up }, |
3541 | 48024e4a | bellard | {"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up }, |
3542 | 48024e4a | bellard | {"movemw", 4, one(0046200), one(0177700), "<sLw", m68000up }, |
3543 | 48024e4a | bellard | {"movemw", 4, one(0046200), one(0177700), "<s#w", m68000up }, |
3544 | 48024e4a | bellard | {"moveml", 4, one(0044300), one(0177700), "Lw&s", m68000up }, |
3545 | 48024e4a | bellard | {"moveml", 4, one(0044340), one(0177770), "lw-s", m68000up }, |
3546 | 48024e4a | bellard | {"moveml", 4, one(0044300), one(0177700), "#w>s", m68000up }, |
3547 | 48024e4a | bellard | {"moveml", 4, one(0046300), one(0177700), "<sLw", m68000up }, |
3548 | 48024e4a | bellard | {"moveml", 4, one(0046300), one(0177700), "<s#w", m68000up }, |
3549 | 48024e4a | bellard | /* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns. */
|
3550 | 48024e4a | bellard | {"moveml", 4, one(0044320), one(0177770), "Lwas", mcfisa_a }, |
3551 | 48024e4a | bellard | {"moveml", 4, one(0044320), one(0177770), "#was", mcfisa_a }, |
3552 | 48024e4a | bellard | {"moveml", 4, one(0044350), one(0177770), "Lwds", mcfisa_a }, |
3553 | 48024e4a | bellard | {"moveml", 4, one(0044350), one(0177770), "#wds", mcfisa_a }, |
3554 | 48024e4a | bellard | {"moveml", 4, one(0046320), one(0177770), "asLw", mcfisa_a }, |
3555 | 48024e4a | bellard | {"moveml", 4, one(0046320), one(0177770), "as#w", mcfisa_a }, |
3556 | 48024e4a | bellard | {"moveml", 4, one(0046350), one(0177770), "dsLw", mcfisa_a }, |
3557 | 48024e4a | bellard | {"moveml", 4, one(0046350), one(0177770), "ds#w", mcfisa_a }, |
3558 | 48024e4a | bellard | |
3559 | 48024e4a | bellard | {"movepw", 2, one(0000410), one(0170770), "dsDd", m68000up }, |
3560 | 48024e4a | bellard | {"movepw", 2, one(0000610), one(0170770), "Ddds", m68000up }, |
3561 | 48024e4a | bellard | {"movepl", 2, one(0000510), one(0170770), "dsDd", m68000up }, |
3562 | 48024e4a | bellard | {"movepl", 2, one(0000710), one(0170770), "Ddds", m68000up }, |
3563 | 48024e4a | bellard | |
3564 | 48024e4a | bellard | {"moveq", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a }, |
3565 | 48024e4a | bellard | {"moveq", 2, one(0070000), one(0170400), "#BDd", m68000up | mcfisa_a }, |
3566 | 48024e4a | bellard | |
3567 | 48024e4a | bellard | /* The move opcode can generate the movea and moveq instructions. */
|
3568 | 48024e4a | bellard | {"moveb", 2, one(0010000), one(0170000), ";b$d", m68000up }, |
3569 | 48024e4a | bellard | {"moveb", 2, one(0010000), one(0170070), "Ds$d", mcfisa_a }, |
3570 | 48024e4a | bellard | {"moveb", 2, one(0010020), one(0170070), "as$d", mcfisa_a }, |
3571 | 48024e4a | bellard | {"moveb", 2, one(0010030), one(0170070), "+s$d", mcfisa_a }, |
3572 | 48024e4a | bellard | {"moveb", 2, one(0010040), one(0170070), "-s$d", mcfisa_a }, |
3573 | 48024e4a | bellard | {"moveb", 2, one(0010000), one(0170000), "nsqd", mcfisa_a }, |
3574 | 48024e4a | bellard | {"moveb", 2, one(0010000), one(0170700), "obDd", mcfisa_a }, |
3575 | 48024e4a | bellard | {"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a }, |
3576 | 48024e4a | bellard | {"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a }, |
3577 | 48024e4a | bellard | {"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a }, |
3578 | 48024e4a | bellard | {"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b }, |
3579 | 48024e4a | bellard | |
3580 | 48024e4a | bellard | {"movew", 2, one(0030000), one(0170000), "*w%d", m68000up }, |
3581 | 48024e4a | bellard | {"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, |
3582 | 48024e4a | bellard | {"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, |
3583 | 48024e4a | bellard | {"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, |
3584 | 48024e4a | bellard | {"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, |
3585 | 48024e4a | bellard | {"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up }, |
3586 | 48024e4a | bellard | {"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, |
3587 | 48024e4a | bellard | {"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up }, |
3588 | 48024e4a | bellard | {"movew", 2, one(0041300), one(0177770), "CsDs", mcfisa_a }, |
3589 | 48024e4a | bellard | {"movew", 2, one(0042300), one(0177700), ";wCd", m68000up }, |
3590 | 48024e4a | bellard | {"movew", 2, one(0042300), one(0177700), "DsCd", mcfisa_a }, |
3591 | 48024e4a | bellard | {"movew", 4, one(0042374), one(0177777), "#wCd", mcfisa_a }, |
3592 | 48024e4a | bellard | {"movew", 2, one(0043300), one(0177700), ";wSd", m68000up }, |
3593 | 48024e4a | bellard | {"movew", 2, one(0043300), one(0177700), "DsSd", mcfisa_a }, |
3594 | 48024e4a | bellard | {"movew", 4, one(0043374), one(0177777), "#wSd", mcfisa_a }, |
3595 | 48024e4a | bellard | |
3596 | 48024e4a | bellard | {"movel", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a }, |
3597 | 48024e4a | bellard | {"movel", 2, one(0020000), one(0170000), "*l%d", m68000up }, |
3598 | 48024e4a | bellard | {"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a }, |
3599 | 48024e4a | bellard | {"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a }, |
3600 | 48024e4a | bellard | {"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a }, |
3601 | 48024e4a | bellard | {"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b }, |
3602 | 48024e4a | bellard | {"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp }, |
3603 | 48024e4a | bellard | {"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp }, |
3604 | 48024e4a | bellard | {"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac }, |
3605 | 48024e4a | bellard | {"movel", 2, one(0120400), one(0177760), "RsEs", mcfmac }, |
3606 | 48024e4a | bellard | {"movel", 6, one(0120474), one(0177777), "#lEs", mcfmac }, |
3607 | 48024e4a | bellard | {"movel", 2, one(0124600), one(0177760), "GsRs", mcfmac }, |
3608 | 48024e4a | bellard | {"movel", 2, one(0124400), one(0177760), "RsGs", mcfmac }, |
3609 | 48024e4a | bellard | {"movel", 6, one(0124474), one(0177777), "#lGs", mcfmac }, |
3610 | 48024e4a | bellard | {"movel", 2, one(0126600), one(0177760), "HsRs", mcfmac }, |
3611 | 48024e4a | bellard | {"movel", 2, one(0126400), one(0177760), "RsHs", mcfmac }, |
3612 | 48024e4a | bellard | {"movel", 6, one(0126474), one(0177777), "#lHs", mcfmac }, |
3613 | 48024e4a | bellard | {"movel", 2, one(0124700), one(0177777), "GsCs", mcfmac }, |
3614 | 48024e4a | bellard | |
3615 | 48024e4a | bellard | {"movel", 2, one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx. */ |
3616 | 48024e4a | bellard | {"movel", 2, one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx. */ |
3617 | 48024e4a | bellard | {"movel", 2, one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx. */ |
3618 | 48024e4a | bellard | {"movel", 2, one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx. */ |
3619 | 48024e4a | bellard | {"movel", 2, one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx. */ |
3620 | 48024e4a | bellard | {"movel", 2, one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr. */ |
3621 | 48024e4a | bellard | {"movel", 2, one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx. */ |
3622 | 48024e4a | bellard | {"movel", 6, one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,ACCx. */ |
3623 | 48024e4a | bellard | {"movel", 2, one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx. */ |
3624 | 48024e4a | bellard | {"movel", 6, one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx. */ |
3625 | 48024e4a | bellard | {"movel", 2, one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr. */ |
3626 | 48024e4a | bellard | {"movel", 6, one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr. */ |
3627 | 48024e4a | bellard | {"movel", 2, one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask. */ |
3628 | 48024e4a | bellard | {"movel", 6, one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask. */ |
3629 | 48024e4a | bellard | |
3630 | 48024e4a | bellard | {"move", 2, one(0030000), one(0170000), "*w%d", m68000up }, |
3631 | 48024e4a | bellard | {"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, |
3632 | 48024e4a | bellard | {"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, |
3633 | 48024e4a | bellard | {"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, |
3634 | 48024e4a | bellard | {"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, |
3635 | 48024e4a | bellard | {"move", 2, one(0040300), one(0177700), "Ss$s", m68000up }, |
3636 | 48024e4a | bellard | {"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, |
3637 | 48024e4a | bellard | {"move", 2, one(0041300), one(0177700), "Cs$s", m68010up }, |
3638 | 48024e4a | bellard | {"move", 2, one(0041300), one(0177770), "CsDs", mcfisa_a }, |
3639 | 48024e4a | bellard | {"move", 2, one(0042300), one(0177700), ";wCd", m68000up }, |
3640 | 48024e4a | bellard | {"move", 2, one(0042300), one(0177700), "DsCd", mcfisa_a }, |
3641 | 48024e4a | bellard | {"move", 4, one(0042374), one(0177777), "#wCd", mcfisa_a }, |
3642 | 48024e4a | bellard | {"move", 2, one(0043300), one(0177700), ";wSd", m68000up }, |
3643 | 48024e4a | bellard | {"move", 2, one(0043300), one(0177700), "DsSd", mcfisa_a }, |
3644 | 48024e4a | bellard | {"move", 4, one(0043374), one(0177777), "#wSd", mcfisa_a }, |
3645 | 48024e4a | bellard | |
3646 | 48024e4a | bellard | {"move", 2, one(0047140), one(0177770), "AsUd", m68000up }, |
3647 | 48024e4a | bellard | {"move", 2, one(0047150), one(0177770), "UdAs", m68000up }, |
3648 | 48024e4a | bellard | |
3649 | 48024e4a | bellard | {"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b }, |
3650 | 48024e4a | bellard | {"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b }, |
3651 | 48024e4a | bellard | {"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b }, |
3652 | 48024e4a | bellard | {"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b }, |
3653 | 48024e4a | bellard | {"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b }, |
3654 | 48024e4a | bellard | |
3655 | 48024e4a | bellard | {"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up }, |
3656 | 48024e4a | bellard | {"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up }, |
3657 | 48024e4a | bellard | {"movesw", 4, two(0007100, 0), two(0177700, 07777), "~sR1", m68010up }, |
3658 | 48024e4a | bellard | {"movesw", 4, two(0007100, 04000), two(0177700, 07777), "R1~s", m68010up }, |
3659 | 48024e4a | bellard | {"movesl", 4, two(0007200, 0), two(0177700, 07777), "~sR1", m68010up }, |
3660 | 48024e4a | bellard | {"movesl", 4, two(0007200, 04000), two(0177700, 07777), "R1~s", m68010up }, |
3661 | 48024e4a | bellard | |
3662 | 48024e4a | bellard | {"move16", 4, two(0xf620, 0x8000), two(0xfff8, 0x8fff), "+s+1", m68040up }, |
3663 | 48024e4a | bellard | {"move16", 2, one(0xf600), one(0xfff8), "+s_L", m68040up }, |
3664 | 48024e4a | bellard | {"move16", 2, one(0xf608), one(0xfff8), "_L+s", m68040up }, |
3665 | 48024e4a | bellard | {"move16", 2, one(0xf610), one(0xfff8), "as_L", m68040up }, |
3666 | 48024e4a | bellard | {"move16", 2, one(0xf618), one(0xfff8), "_Las", m68040up }, |
3667 | 48024e4a | bellard | |
3668 | 48024e4a | bellard | {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, |
3669 | 48024e4a | bellard | {"msacw", 4, two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, |
3670 | 48024e4a | bellard | {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, |
3671 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, |
3672 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0300), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, |
3673 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0f00), "uMum", mcfmac }, |
3674 | 48024e4a | bellard | |
3675 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */ |
3676 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */ |
3677 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */ |
3678 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ |
3679 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ |
3680 | 48024e4a | bellard | {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ |
3681 | 48024e4a | bellard | |
3682 | 48024e4a | bellard | {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, |
3683 | 48024e4a | bellard | {"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, |
3684 | 48024e4a | bellard | {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, |
3685 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, |
3686 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, |
3687 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac }, |
3688 | 48024e4a | bellard | |
3689 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, |
3690 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, |
3691 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, |
3692 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, |
3693 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, |
3694 | 48024e4a | bellard | {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, |
3695 | 48024e4a | bellard | |
3696 | 48024e4a | bellard | {"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a }, |
3697 | 48024e4a | bellard | {"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, |
3698 | 48024e4a | bellard | {"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a }, |
3699 | 48024e4a | bellard | {"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, |
3700 | 48024e4a | bellard | |
3701 | 48024e4a | bellard | {"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a }, |
3702 | 48024e4a | bellard | {"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, |
3703 | 48024e4a | bellard | {"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a }, |
3704 | 48024e4a | bellard | {"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, |
3705 | 48024e4a | bellard | |
3706 | 48024e4a | bellard | {"nbcd", 2, one(0044000), one(0177700), "$s", m68000up }, |
3707 | 48024e4a | bellard | |
3708 | 48024e4a | bellard | {"negb", 2, one(0042000), one(0177700), "$s", m68000up }, |
3709 | 48024e4a | bellard | {"negw", 2, one(0042100), one(0177700), "$s", m68000up }, |
3710 | 48024e4a | bellard | {"negl", 2, one(0042200), one(0177700), "$s", m68000up }, |
3711 | 48024e4a | bellard | {"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a}, |
3712 | 48024e4a | bellard | |
3713 | 48024e4a | bellard | {"negxb", 2, one(0040000), one(0177700), "$s", m68000up }, |
3714 | 48024e4a | bellard | {"negxw", 2, one(0040100), one(0177700), "$s", m68000up }, |
3715 | 48024e4a | bellard | {"negxl", 2, one(0040200), one(0177700), "$s", m68000up }, |
3716 | 48024e4a | bellard | {"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a}, |
3717 | 48024e4a | bellard | |
3718 | 48024e4a | bellard | {"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a}, |
3719 | 48024e4a | bellard | |
3720 | 48024e4a | bellard | {"notb", 2, one(0043000), one(0177700), "$s", m68000up }, |
3721 | 48024e4a | bellard | {"notw", 2, one(0043100), one(0177700), "$s", m68000up }, |
3722 | 48024e4a | bellard | {"notl", 2, one(0043200), one(0177700), "$s", m68000up }, |
3723 | 48024e4a | bellard | {"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a}, |
3724 | 48024e4a | bellard | |
3725 | 48024e4a | bellard | {"orib", 4, one(0000000), one(0177700), "#b$s", m68000up }, |
3726 | 48024e4a | bellard | {"orib", 4, one(0000074), one(0177777), "#bCs", m68000up }, |
3727 | 48024e4a | bellard | {"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up }, |
3728 | 48024e4a | bellard | {"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up }, |
3729 | 48024e4a | bellard | {"oril", 6, one(0000200), one(0177700), "#l$s", m68000up }, |
3730 | 48024e4a | bellard | {"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, |
3731 | 48024e4a | bellard | {"ori", 4, one(0000074), one(0177777), "#bCs", m68000up }, |
3732 | 48024e4a | bellard | {"ori", 4, one(0000100), one(0177700), "#w$s", m68000up }, |
3733 | 48024e4a | bellard | {"ori", 4, one(0000174), one(0177777), "#wSs", m68000up }, |
3734 | 48024e4a | bellard | |
3735 | 48024e4a | bellard | /* The or opcode can generate the ori instruction. */
|
3736 | 48024e4a | bellard | {"orb", 4, one(0000000), one(0177700), "#b$s", m68000up }, |
3737 | 48024e4a | bellard | {"orb", 4, one(0000074), one(0177777), "#bCs", m68000up }, |
3738 | 48024e4a | bellard | {"orb", 2, one(0100000), one(0170700), ";bDd", m68000up }, |
3739 | 48024e4a | bellard | {"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up }, |
3740 | 48024e4a | bellard | {"orw", 4, one(0000100), one(0177700), "#w$s", m68000up }, |
3741 | 48024e4a | bellard | {"orw", 4, one(0000174), one(0177777), "#wSs", m68000up }, |
3742 | 48024e4a | bellard | {"orw", 2, one(0100100), one(0170700), ";wDd", m68000up }, |
3743 | 48024e4a | bellard | {"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up }, |
3744 | 48024e4a | bellard | {"orl", 6, one(0000200), one(0177700), "#l$s", m68000up }, |
3745 | 48024e4a | bellard | {"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, |
3746 | 48024e4a | bellard | {"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a }, |
3747 | 48024e4a | bellard | {"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a }, |
3748 | 48024e4a | bellard | {"or", 4, one(0000074), one(0177777), "#bCs", m68000up }, |
3749 | 48024e4a | bellard | {"or", 4, one(0000100), one(0177700), "#w$s", m68000up }, |
3750 | 48024e4a | bellard | {"or", 4, one(0000174), one(0177777), "#wSs", m68000up }, |
3751 | 48024e4a | bellard | {"or", 2, one(0100100), one(0170700), ";wDd", m68000up }, |
3752 | 48024e4a | bellard | {"or", 2, one(0100500), one(0170700), "Dd~s", m68000up }, |
3753 | 48024e4a | bellard | |
3754 | 48024e4a | bellard | {"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up }, |
3755 | 48024e4a | bellard | {"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up }, |
3756 | 48024e4a | bellard | |
3757 | 48024e4a | bellard | {"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 }, |
3758 | 48024e4a | bellard | {"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 }, |
3759 | 48024e4a | bellard | {"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 }, |
3760 | 48024e4a | bellard | {"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 }, |
3761 | 48024e4a | bellard | {"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 }, |
3762 | 48024e4a | bellard | {"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 }, |
3763 | 48024e4a | bellard | {"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 }, |
3764 | 48024e4a | bellard | {"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 }, |
3765 | 48024e4a | bellard | {"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 }, |
3766 | 48024e4a | bellard | {"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 }, |
3767 | 48024e4a | bellard | {"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 }, |
3768 | 48024e4a | bellard | {"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 }, |
3769 | 48024e4a | bellard | {"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 }, |
3770 | 48024e4a | bellard | {"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 }, |
3771 | 48024e4a | bellard | {"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 }, |
3772 | 48024e4a | bellard | {"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 }, |
3773 | 48024e4a | bellard | {"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 }, |
3774 | 48024e4a | bellard | {"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 }, |
3775 | 48024e4a | bellard | {"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 }, |
3776 | 48024e4a | bellard | {"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 }, |
3777 | 48024e4a | bellard | {"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 }, |
3778 | 48024e4a | bellard | {"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 }, |
3779 | 48024e4a | bellard | {"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 }, |
3780 | 48024e4a | bellard | {"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 }, |
3781 | 48024e4a | bellard | {"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 }, |
3782 | 48024e4a | bellard | {"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 }, |
3783 | 48024e4a | bellard | {"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 }, |
3784 | 48024e4a | bellard | {"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 }, |
3785 | 48024e4a | bellard | {"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 }, |
3786 | 48024e4a | bellard | {"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 }, |
3787 | 48024e4a | bellard | {"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 }, |
3788 | 48024e4a | bellard | {"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 }, |
3789 | 48024e4a | bellard | |
3790 | 48024e4a | bellard | {"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3791 | 48024e4a | bellard | {"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3792 | 48024e4a | bellard | {"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3793 | 48024e4a | bellard | {"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3794 | 48024e4a | bellard | {"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3795 | 48024e4a | bellard | {"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3796 | 48024e4a | bellard | {"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3797 | 48024e4a | bellard | {"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3798 | 48024e4a | bellard | {"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3799 | 48024e4a | bellard | {"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3800 | 48024e4a | bellard | {"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3801 | 48024e4a | bellard | {"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3802 | 48024e4a | bellard | {"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3803 | 48024e4a | bellard | {"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3804 | 48024e4a | bellard | {"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3805 | 48024e4a | bellard | {"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, |
3806 | 48024e4a | bellard | |
3807 | 48024e4a | bellard | {"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a }, |
3808 | 48024e4a | bellard | |
3809 | 48024e4a | bellard | {"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up }, |
3810 | 48024e4a | bellard | {"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, |
3811 | 48024e4a | bellard | |
3812 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, |
3813 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, |
3814 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, |
3815 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, |
3816 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, |
3817 | 48024e4a | bellard | {"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, |
3818 | 48024e4a | bellard | {"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up }, |
3819 | 48024e4a | bellard | {"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up }, |
3820 | 48024e4a | bellard | |
3821 | 48024e4a | bellard | {"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up }, |
3822 | 48024e4a | bellard | {"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up }, |
3823 | 48024e4a | bellard | {"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up }, |
3824 | 48024e4a | bellard | |
3825 | 48024e4a | bellard | {"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, |
3826 | 48024e4a | bellard | |
3827 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, |
3828 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, |
3829 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, |
3830 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, |
3831 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, |
3832 | 48024e4a | bellard | {"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, |
3833 | 48024e4a | bellard | |
3834 | 48024e4a | bellard | {"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, |
3835 | 48024e4a | bellard | {"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, |
3836 | 48024e4a | bellard | {"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, |
3837 | 48024e4a | bellard | {"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, |
3838 | 48024e4a | bellard | {"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, |
3839 | 48024e4a | bellard | {"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, |
3840 | 48024e4a | bellard | |
3841 | 48024e4a | bellard | {"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 }, |
3842 | 48024e4a | bellard | {"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 }, |
3843 | 48024e4a | bellard | |
3844 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, |
3845 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, |
3846 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, |
3847 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, |
3848 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, |
3849 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, |
3850 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, |
3851 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, |
3852 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 }, |
3853 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 }, |
3854 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, |
3855 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, |
3856 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, |
3857 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, |
3858 | 48024e4a | bellard | {"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, |
3859 | 48024e4a | bellard | |
3860 | 48024e4a | bellard | {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, |
3861 | 48024e4a | bellard | {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, |
3862 | 48024e4a | bellard | {"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, |
3863 | 48024e4a | bellard | |
3864 | 48024e4a | bellard | {"prestore", 2, one(0xf140), one(0xffc0), "<s", m68851 }, |
3865 | 48024e4a | bellard | |
3866 | 48024e4a | bellard | {"psave", 2, one(0xf100), one(0xffc0), ">s", m68851 }, |
3867 | 48024e4a | bellard | |
3868 | 48024e4a | bellard | {"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, |
3869 | 48024e4a | bellard | {"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, |
3870 | 48024e4a | bellard | {"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, |
3871 | 48024e4a | bellard | {"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, |
3872 | 48024e4a | bellard | {"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, |
3873 | 48024e4a | bellard | {"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, |
3874 | 48024e4a | bellard | {"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, |
3875 | 48024e4a | bellard | {"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, |
3876 | 48024e4a | bellard | {"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, |
3877 | 48024e4a | bellard | {"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, |
3878 | 48024e4a | bellard | {"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, |
3879 | 48024e4a | bellard | {"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, |
3880 | 48024e4a | bellard | {"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, |
3881 | 48024e4a | bellard | {"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, |
3882 | 48024e4a | bellard | {"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, |
3883 | 48024e4a | bellard | {"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, |
3884 | 48024e4a | bellard | |
3885 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, |
3886 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, |
3887 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, |
3888 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, |
3889 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, |
3890 | 48024e4a | bellard | {"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, |
3891 | 48024e4a | bellard | {"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 }, |
3892 | 48024e4a | bellard | |
3893 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, |
3894 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, |
3895 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, |
3896 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, |
3897 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, |
3898 | 48024e4a | bellard | {"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, |
3899 | 48024e4a | bellard | {"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 }, |
3900 | 48024e4a | bellard | |
3901 | 48024e4a | bellard | {"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, |
3902 | 48024e4a | bellard | {"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, |
3903 | 48024e4a | bellard | {"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, |
3904 | 48024e4a | bellard | |
3905 | 48024e4a | bellard | {"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, |
3906 | 48024e4a | bellard | {"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, |
3907 | 48024e4a | bellard | {"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, |
3908 | 48024e4a | bellard | |
3909 | 48024e4a | bellard | {"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, |
3910 | 48024e4a | bellard | {"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, |
3911 | 48024e4a | bellard | {"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, |
3912 | 48024e4a | bellard | |
3913 | 48024e4a | bellard | {"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, |
3914 | 48024e4a | bellard | {"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, |
3915 | 48024e4a | bellard | {"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, |
3916 | 48024e4a | bellard | |
3917 | 48024e4a | bellard | {"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, |
3918 | 48024e4a | bellard | {"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, |
3919 | 48024e4a | bellard | {"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, |
3920 | 48024e4a | bellard | |
3921 | 48024e4a | bellard | {"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, |
3922 | 48024e4a | bellard | {"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, |
3923 | 48024e4a | bellard | {"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, |
3924 | 48024e4a | bellard | |
3925 | 48024e4a | bellard | {"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, |
3926 | 48024e4a | bellard | {"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, |
3927 | 48024e4a | bellard | {"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, |
3928 | 48024e4a | bellard | |
3929 | 48024e4a | bellard | {"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, |
3930 | 48024e4a | bellard | {"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, |
3931 | 48024e4a | bellard | {"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, |
3932 | 48024e4a | bellard | |
3933 | 48024e4a | bellard | {"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, |
3934 | 48024e4a | bellard | {"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, |
3935 | 48024e4a | bellard | {"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, |
3936 | 48024e4a | bellard | |
3937 | 48024e4a | bellard | {"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, |
3938 | 48024e4a | bellard | {"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, |
3939 | 48024e4a | bellard | {"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, |
3940 | 48024e4a | bellard | |
3941 | 48024e4a | bellard | {"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, |
3942 | 48024e4a | bellard | {"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, |
3943 | 48024e4a | bellard | {"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, |
3944 | 48024e4a | bellard | |
3945 | 48024e4a | bellard | {"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, |
3946 | 48024e4a | bellard | {"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, |
3947 | 48024e4a | bellard | {"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, |
3948 | 48024e4a | bellard | |
3949 | 48024e4a | bellard | {"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, |
3950 | 48024e4a | bellard | {"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, |
3951 | 48024e4a | bellard | {"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, |
3952 | 48024e4a | bellard | |
3953 | 48024e4a | bellard | {"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, |
3954 | 48024e4a | bellard | {"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, |
3955 | 48024e4a | bellard | {"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, |
3956 | 48024e4a | bellard | |
3957 | 48024e4a | bellard | {"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, |
3958 | 48024e4a | bellard | {"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, |
3959 | 48024e4a | bellard | {"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, |
3960 | 48024e4a | bellard | |
3961 | 48024e4a | bellard | {"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, |
3962 | 48024e4a | bellard | {"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, |
3963 | 48024e4a | bellard | {"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, |
3964 | 48024e4a | bellard | |
3965 | 48024e4a | bellard | {"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a }, |
3966 | 48024e4a | bellard | |
3967 | 48024e4a | bellard | {"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, |
3968 | 48024e4a | bellard | {"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, |
3969 | 48024e4a | bellard | |
3970 | 48024e4a | bellard | /* FIXME: don't allow Dw==Dx. */
|
3971 | 48024e4a | bellard | {"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, |
3972 | 48024e4a | bellard | {"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, |
3973 | 48024e4a | bellard | |
3974 | 48024e4a | bellard | {"reset", 2, one(0047160), one(0177777), "", m68000up }, |
3975 | 48024e4a | bellard | |
3976 | 48024e4a | bellard | {"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up }, |
3977 | 48024e4a | bellard | {"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up }, |
3978 | 48024e4a | bellard | {"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up }, |
3979 | 48024e4a | bellard | {"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up }, |
3980 | 48024e4a | bellard | {"rolw", 2, one(0163700), one(0177700), "~s", m68000up }, |
3981 | 48024e4a | bellard | {"roll", 2, one(0160630), one(0170770), "QdDs", m68000up }, |
3982 | 48024e4a | bellard | {"roll", 2, one(0160670), one(0170770), "DdDs", m68000up }, |
3983 | 48024e4a | bellard | |
3984 | 48024e4a | bellard | {"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up }, |
3985 | 48024e4a | bellard | {"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up }, |
3986 | 48024e4a | bellard | {"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up }, |
3987 | 48024e4a | bellard | {"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up }, |
3988 | 48024e4a | bellard | {"rorw", 2, one(0163300), one(0177700), "~s", m68000up }, |
3989 | 48024e4a | bellard | {"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up }, |
3990 | 48024e4a | bellard | {"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up }, |
3991 | 48024e4a | bellard | |
3992 | 48024e4a | bellard | {"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up }, |
3993 | 48024e4a | bellard | {"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up }, |
3994 | 48024e4a | bellard | {"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up }, |
3995 | 48024e4a | bellard | {"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up }, |
3996 | 48024e4a | bellard | {"roxlw", 2, one(0162700), one(0177700), "~s", m68000up }, |
3997 | 48024e4a | bellard | {"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up }, |
3998 | 48024e4a | bellard | {"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up }, |
3999 | 48024e4a | bellard | |
4000 | 48024e4a | bellard | {"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up }, |
4001 | 48024e4a | bellard | {"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up }, |
4002 | 48024e4a | bellard | {"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up }, |
4003 | 48024e4a | bellard | {"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up }, |
4004 | 48024e4a | bellard | {"roxrw", 2, one(0162300), one(0177700), "~s", m68000up }, |
4005 | 48024e4a | bellard | {"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up }, |
4006 | 48024e4a | bellard | {"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up }, |
4007 | 48024e4a | bellard | |
4008 | 48024e4a | bellard | {"rtd", 4, one(0047164), one(0177777), "#w", m68010up }, |
4009 | 3b46e624 | ths | |
4010 | 48024e4a | bellard | {"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a }, |
4011 | 3b46e624 | ths | |
4012 | 48024e4a | bellard | {"rtm", 2, one(0003300), one(0177760), "Rs", m68020 }, |
4013 | 3b46e624 | ths | |
4014 | 48024e4a | bellard | {"rtr", 2, one(0047167), one(0177777), "", m68000up }, |
4015 | 3b46e624 | ths | |
4016 | 48024e4a | bellard | {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, |
4017 | 48024e4a | bellard | |
4018 | 48024e4a | bellard | {"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b }, |
4019 | 48024e4a | bellard | |
4020 | 48024e4a | bellard | {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, |
4021 | 48024e4a | bellard | {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, |
4022 | 48024e4a | bellard | |
4023 | 48024e4a | bellard | {"scc", 2, one(0052300), one(0177700), "$s", m68000up }, |
4024 | 48024e4a | bellard | {"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a }, |
4025 | 48024e4a | bellard | {"scs", 2, one(0052700), one(0177700), "$s", m68000up }, |
4026 | 48024e4a | bellard | {"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a }, |
4027 | 48024e4a | bellard | {"seq", 2, one(0053700), one(0177700), "$s", m68000up }, |
4028 | 48024e4a | bellard | {"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a }, |
4029 | 48024e4a | bellard | {"sf", 2, one(0050700), one(0177700), "$s", m68000up }, |
4030 | 48024e4a | bellard | {"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a }, |
4031 | 48024e4a | bellard | {"sge", 2, one(0056300), one(0177700), "$s", m68000up }, |
4032 | 48024e4a | bellard | {"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a }, |
4033 | 48024e4a | bellard | {"sgt", 2, one(0057300), one(0177700), "$s", m68000up }, |
4034 | 48024e4a | bellard | {"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a }, |
4035 | 48024e4a | bellard | {"shi", 2, one(0051300), one(0177700), "$s", m68000up }, |
4036 | 48024e4a | bellard | {"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a }, |
4037 | 48024e4a | bellard | {"sle", 2, one(0057700), one(0177700), "$s", m68000up }, |
4038 | 48024e4a | bellard | {"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a }, |
4039 | 48024e4a | bellard | {"sls", 2, one(0051700), one(0177700), "$s", m68000up }, |
4040 | 48024e4a | bellard | {"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a }, |
4041 | 48024e4a | bellard | {"slt", 2, one(0056700), one(0177700), "$s", m68000up }, |
4042 | 48024e4a | bellard | {"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a }, |
4043 | 48024e4a | bellard | {"smi", 2, one(0055700), one(0177700), "$s", m68000up }, |
4044 | 48024e4a | bellard | {"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a }, |
4045 | 48024e4a | bellard | {"sne", 2, one(0053300), one(0177700), "$s", m68000up }, |
4046 | 48024e4a | bellard | {"sne", 2, one(0053300), one(0177700), "Ds", mcfisa_a }, |
4047 | 48024e4a | bellard | {"spl", 2, one(0055300), one(0177700), "$s", m68000up }, |
4048 | 48024e4a | bellard | {"spl", 2, one(0055300), one(0177700), "Ds", mcfisa_a }, |
4049 | 48024e4a | bellard | {"st", 2, one(0050300), one(0177700), "$s", m68000up }, |
4050 | 48024e4a | bellard | {"st", 2, one(0050300), one(0177700), "Ds", mcfisa_a }, |
4051 | 48024e4a | bellard | {"svc", 2, one(0054300), one(0177700), "$s", m68000up }, |
4052 | 48024e4a | bellard | {"svc", 2, one(0054300), one(0177700), "Ds", mcfisa_a }, |
4053 | 48024e4a | bellard | {"svs", 2, one(0054700), one(0177700), "$s", m68000up }, |
4054 | 48024e4a | bellard | {"svs", 2, one(0054700), one(0177700), "Ds", mcfisa_a }, |
4055 | 48024e4a | bellard | |
4056 | 48024e4a | bellard | {"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a }, |
4057 | 48024e4a | bellard | |
4058 | 48024e4a | bellard | {"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa}, |
4059 | 48024e4a | bellard | |
4060 | 48024e4a | bellard | {"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
4061 | 48024e4a | bellard | {"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up }, |
4062 | 48024e4a | bellard | |
4063 | 48024e4a | bellard | {"subib", 4, one(0002000), one(0177700), "#b$s", m68000up }, |
4064 | 48024e4a | bellard | {"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up }, |
4065 | 48024e4a | bellard | {"subil", 6, one(0002200), one(0177700), "#l$s", m68000up }, |
4066 | 48024e4a | bellard | {"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, |
4067 | 48024e4a | bellard | |
4068 | 48024e4a | bellard | {"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, |
4069 | 48024e4a | bellard | {"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, |
4070 | 48024e4a | bellard | {"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, |
4071 | 48024e4a | bellard | |
4072 | 48024e4a | bellard | /* The sub opcode can generate the suba, subi, and subq instructions. */
|
4073 | 48024e4a | bellard | {"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, |
4074 | 48024e4a | bellard | {"subb", 4, one(0002000), one(0177700), "#b$s", m68000up }, |
4075 | 48024e4a | bellard | {"subb", 2, one(0110000), one(0170700), ";bDd", m68000up }, |
4076 | 48024e4a | bellard | {"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up }, |
4077 | 48024e4a | bellard | {"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, |
4078 | 48024e4a | bellard | {"subw", 4, one(0002100), one(0177700), "#w$s", m68000up }, |
4079 | 48024e4a | bellard | {"subw", 2, one(0110300), one(0170700), "*wAd", m68000up }, |
4080 | 48024e4a | bellard | {"subw", 2, one(0110100), one(0170700), "*wDd", m68000up }, |
4081 | 48024e4a | bellard | {"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up }, |
4082 | 48024e4a | bellard | {"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, |
4083 | 48024e4a | bellard | {"subl", 6, one(0002200), one(0177700), "#l$s", m68000up }, |
4084 | 48024e4a | bellard | {"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, |
4085 | 48024e4a | bellard | {"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, |
4086 | 48024e4a | bellard | {"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a }, |
4087 | 48024e4a | bellard | {"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a }, |
4088 | 48024e4a | bellard | |
4089 | 48024e4a | bellard | {"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up }, |
4090 | 48024e4a | bellard | {"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up }, |
4091 | 48024e4a | bellard | {"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up }, |
4092 | 48024e4a | bellard | {"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up }, |
4093 | 48024e4a | bellard | {"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a }, |
4094 | 48024e4a | bellard | {"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up }, |
4095 | 48024e4a | bellard | |
4096 | 48024e4a | bellard | {"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a }, |
4097 | 48024e4a | bellard | |
4098 | 48024e4a | bellard | /* swbeg and swbegl are magic constants used on sysV68. The compiler
|
4099 | 48024e4a | bellard | generates them before a switch table. They tell the debugger and
|
4100 | 48024e4a | bellard | disassembler that a switch table follows. The parameter is the
|
4101 | 48024e4a | bellard | number of elements in the table. swbeg means that the entries in
|
4102 | 48024e4a | bellard | the table are word (2 byte) sized, and swbegl means that the
|
4103 | 48024e4a | bellard | entries in the table are longword (4 byte) sized. */
|
4104 | 48024e4a | bellard | {"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, |
4105 | 48024e4a | bellard | {"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, |
4106 | 48024e4a | bellard | |
4107 | 48024e4a | bellard | {"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b}, |
4108 | 48024e4a | bellard | |
4109 | 48024e4a | bellard | #define TBL1(name,insn_size,signed,round,size) \ |
4110 | 48024e4a | bellard | {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ |
4111 | 48024e4a | bellard | two(0177700,0107777), "!sD1", cpu32 }, \ |
4112 | 48024e4a | bellard | {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \ |
4113 | 48024e4a | bellard | two(0177770,0107770), "DsD3D1", cpu32 } |
4114 | 48024e4a | bellard | #define TBL(name1, name2, name3, s, r) \
|
4115 | 48024e4a | bellard | TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2) |
4116 | 48024e4a | bellard | TBL("tblsb", "tblsw", "tblsl", 2, 1), |
4117 | 48024e4a | bellard | TBL("tblsnb", "tblsnw", "tblsnl", 2, 0), |
4118 | 48024e4a | bellard | TBL("tblub", "tbluw", "tblul", 0, 1), |
4119 | 48024e4a | bellard | TBL("tblunb", "tblunw", "tblunl", 0, 0), |
4120 | 48024e4a | bellard | |
4121 | 48024e4a | bellard | {"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a }, |
4122 | 48024e4a | bellard | |
4123 | 48024e4a | bellard | {"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 }, |
4124 | 48024e4a | bellard | {"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 }, |
4125 | 48024e4a | bellard | {"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 }, |
4126 | 48024e4a | bellard | {"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | mcfisa_a }, |
4127 | 48024e4a | bellard | {"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 }, |
4128 | 48024e4a | bellard | {"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 }, |
4129 | 48024e4a | bellard | {"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 }, |
4130 | 48024e4a | bellard | {"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 }, |
4131 | 48024e4a | bellard | {"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 }, |
4132 | 48024e4a | bellard | {"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 }, |
4133 | 48024e4a | bellard | {"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 }, |
4134 | 48024e4a | bellard | {"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 }, |
4135 | 48024e4a | bellard | {"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 }, |
4136 | 48024e4a | bellard | {"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 }, |
4137 | 48024e4a | bellard | {"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 }, |
4138 | 48024e4a | bellard | {"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 }, |
4139 | 48024e4a | bellard | |
4140 | 48024e4a | bellard | {"trapccw", 4, one(0052372), one(0177777), "#w", m68020up|cpu32 }, |
4141 | 48024e4a | bellard | {"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up|cpu32 }, |
4142 | 48024e4a | bellard | {"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up|cpu32 }, |
4143 | 48024e4a | bellard | {"trapfw", 4, one(0050772), one(0177777), "#w", m68020up|cpu32|mcfisa_a}, |
4144 | 48024e4a | bellard | {"trapgew", 4, one(0056372), one(0177777), "#w", m68020up|cpu32 }, |
4145 | 48024e4a | bellard | {"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up|cpu32 }, |
4146 | 48024e4a | bellard | {"traphiw", 4, one(0051372), one(0177777), "#w", m68020up|cpu32 }, |
4147 | 48024e4a | bellard | {"traplew", 4, one(0057772), one(0177777), "#w", m68020up|cpu32 }, |
4148 | 48024e4a | bellard | {"traplsw", 4, one(0051772), one(0177777), "#w", m68020up|cpu32 }, |
4149 | 48024e4a | bellard | {"trapltw", 4, one(0056772), one(0177777), "#w", m68020up|cpu32 }, |
4150 | 48024e4a | bellard | {"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up|cpu32 }, |
4151 | 48024e4a | bellard | {"trapnew", 4, one(0053372), one(0177777), "#w", m68020up|cpu32 }, |
4152 | 48024e4a | bellard | {"trapplw", 4, one(0055372), one(0177777), "#w", m68020up|cpu32 }, |
4153 | 48024e4a | bellard | {"traptw", 4, one(0050372), one(0177777), "#w", m68020up|cpu32 }, |
4154 | 48024e4a | bellard | {"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up|cpu32 }, |
4155 | 48024e4a | bellard | {"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up|cpu32 }, |
4156 | 48024e4a | bellard | |
4157 | 48024e4a | bellard | {"trapccl", 6, one(0052373), one(0177777), "#l", m68020up|cpu32 }, |
4158 | 48024e4a | bellard | {"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up|cpu32 }, |
4159 | 48024e4a | bellard | {"trapeql", 6, one(0053773), one(0177777), "#l", m68020up|cpu32 }, |
4160 | 48024e4a | bellard | {"trapfl", 6, one(0050773), one(0177777), "#l", m68020up|cpu32|mcfisa_a}, |
4161 | 48024e4a | bellard | {"trapgel", 6, one(0056373), one(0177777), "#l", m68020up|cpu32 }, |
4162 | 48024e4a | bellard | {"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up|cpu32 }, |
4163 | 48024e4a | bellard | {"traphil", 6, one(0051373), one(0177777), "#l", m68020up|cpu32 }, |
4164 | 48024e4a | bellard | {"traplel", 6, one(0057773), one(0177777), "#l", m68020up|cpu32 }, |
4165 | 48024e4a | bellard | {"traplsl", 6, one(0051773), one(0177777), "#l", m68020up|cpu32 }, |
4166 | 48024e4a | bellard | {"trapltl", 6, one(0056773), one(0177777), "#l", m68020up|cpu32 }, |
4167 | 48024e4a | bellard | {"trapmil", 6, one(0055773), one(0177777), "#l", m68020up|cpu32 }, |
4168 | 48024e4a | bellard | {"trapnel", 6, one(0053373), one(0177777), "#l", m68020up|cpu32 }, |
4169 | 48024e4a | bellard | {"trappll", 6, one(0055373), one(0177777), "#l", m68020up|cpu32 }, |
4170 | 48024e4a | bellard | {"traptl", 6, one(0050373), one(0177777), "#l", m68020up|cpu32 }, |
4171 | 48024e4a | bellard | {"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up|cpu32 }, |
4172 | 48024e4a | bellard | {"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up|cpu32 }, |
4173 | 48024e4a | bellard | |
4174 | 48024e4a | bellard | {"trapv", 2, one(0047166), one(0177777), "", m68000up }, |
4175 | 48024e4a | bellard | |
4176 | 48024e4a | bellard | {"tstb", 2, one(0045000), one(0177700), ";b", m68020up|cpu32|mcfisa_a }, |
4177 | 48024e4a | bellard | {"tstb", 2, one(0045000), one(0177700), "$b", m68000up }, |
4178 | 48024e4a | bellard | {"tstw", 2, one(0045100), one(0177700), "*w", m68020up|cpu32|mcfisa_a }, |
4179 | 48024e4a | bellard | {"tstw", 2, one(0045100), one(0177700), "$w", m68000up }, |
4180 | 48024e4a | bellard | {"tstl", 2, one(0045200), one(0177700), "*l", m68020up|cpu32|mcfisa_a }, |
4181 | 48024e4a | bellard | {"tstl", 2, one(0045200), one(0177700), "$l", m68000up }, |
4182 | 48024e4a | bellard | |
4183 | 48024e4a | bellard | {"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a }, |
4184 | 48024e4a | bellard | |
4185 | 48024e4a | bellard | {"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up }, |
4186 | 48024e4a | bellard | {"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up }, |
4187 | 48024e4a | bellard | |
4188 | 48024e4a | bellard | {"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a }, |
4189 | 48024e4a | bellard | {"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a }, |
4190 | 48024e4a | bellard | {"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a }, |
4191 | 48024e4a | bellard | |
4192 | 48024e4a | bellard | {"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, |
4193 | 48024e4a | bellard | {"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, |
4194 | 48024e4a | bellard | }; |
4195 | 48024e4a | bellard | |
4196 | 48024e4a | bellard | const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; |
4197 | 48024e4a | bellard | |
4198 | 48024e4a | bellard | /* These aliases used to be in the above table, each one duplicating
|
4199 | 48024e4a | bellard | all of the entries for its primary exactly. This table was
|
4200 | 48024e4a | bellard | constructed by mechanical processing of the opcode table, with a
|
4201 | 48024e4a | bellard | small number of tweaks done by hand. There are probably a lot more
|
4202 | 48024e4a | bellard | aliases above that could be moved down here, except for very minor
|
4203 | 48024e4a | bellard | differences. */
|
4204 | 48024e4a | bellard | |
4205 | 48024e4a | bellard | const struct m68k_opcode_alias m68k_opcode_aliases[] = |
4206 | 48024e4a | bellard | { |
4207 | 48024e4a | bellard | { "add", "addw", }, |
4208 | 48024e4a | bellard | { "adda", "addaw", }, |
4209 | 48024e4a | bellard | { "addi", "addiw", }, |
4210 | 48024e4a | bellard | { "addq", "addqw", }, |
4211 | 48024e4a | bellard | { "addx", "addxw", }, |
4212 | 48024e4a | bellard | { "asl", "aslw", }, |
4213 | 48024e4a | bellard | { "asr", "asrw", }, |
4214 | 48024e4a | bellard | { "bhi", "bhiw", }, |
4215 | 48024e4a | bellard | { "bls", "blsw", }, |
4216 | 48024e4a | bellard | { "bcc", "bccw", }, |
4217 | 48024e4a | bellard | { "bcs", "bcsw", }, |
4218 | 48024e4a | bellard | { "bne", "bnew", }, |
4219 | 48024e4a | bellard | { "beq", "beqw", }, |
4220 | 48024e4a | bellard | { "bvc", "bvcw", }, |
4221 | 48024e4a | bellard | { "bvs", "bvsw", }, |
4222 | 48024e4a | bellard | { "bpl", "bplw", }, |
4223 | 48024e4a | bellard | { "bmi", "bmiw", }, |
4224 | 48024e4a | bellard | { "bge", "bgew", }, |
4225 | 48024e4a | bellard | { "blt", "bltw", }, |
4226 | 48024e4a | bellard | { "bgt", "bgtw", }, |
4227 | 48024e4a | bellard | { "ble", "blew", }, |
4228 | 48024e4a | bellard | { "bra", "braw", }, |
4229 | 48024e4a | bellard | { "bsr", "bsrw", }, |
4230 | 48024e4a | bellard | { "bhib", "bhis", }, |
4231 | 48024e4a | bellard | { "blsb", "blss", }, |
4232 | 48024e4a | bellard | { "bccb", "bccs", }, |
4233 | 48024e4a | bellard | { "bcsb", "bcss", }, |
4234 | 48024e4a | bellard | { "bneb", "bnes", }, |
4235 | 48024e4a | bellard | { "beqb", "beqs", }, |
4236 | 48024e4a | bellard | { "bvcb", "bvcs", }, |
4237 | 48024e4a | bellard | { "bvsb", "bvss", }, |
4238 | 48024e4a | bellard | { "bplb", "bpls", }, |
4239 | 48024e4a | bellard | { "bmib", "bmis", }, |
4240 | 48024e4a | bellard | { "bgeb", "bges", }, |
4241 | 48024e4a | bellard | { "bltb", "blts", }, |
4242 | 48024e4a | bellard | { "bgtb", "bgts", }, |
4243 | 48024e4a | bellard | { "bleb", "bles", }, |
4244 | 48024e4a | bellard | { "brab", "bras", }, |
4245 | 48024e4a | bellard | { "bsrb", "bsrs", }, |
4246 | 48024e4a | bellard | { "bhs", "bccw" }, |
4247 | 48024e4a | bellard | { "bhss", "bccs" }, |
4248 | 48024e4a | bellard | { "bhsb", "bccs" }, |
4249 | 48024e4a | bellard | { "bhsw", "bccw" }, |
4250 | 48024e4a | bellard | { "bhsl", "bccl" }, |
4251 | 48024e4a | bellard | { "blo", "bcsw" }, |
4252 | 48024e4a | bellard | { "blos", "bcss" }, |
4253 | 48024e4a | bellard | { "blob", "bcss" }, |
4254 | 48024e4a | bellard | { "blow", "bcsw" }, |
4255 | 48024e4a | bellard | { "blol", "bcsl" }, |
4256 | 48024e4a | bellard | { "br", "braw", }, |
4257 | 48024e4a | bellard | { "brs", "bras", }, |
4258 | 48024e4a | bellard | { "brb", "bras", }, |
4259 | 48024e4a | bellard | { "brw", "braw", }, |
4260 | 48024e4a | bellard | { "brl", "bral", }, |
4261 | 48024e4a | bellard | { "jfnlt", "bcc", }, /* Apparently a sun alias. */ |
4262 | 48024e4a | bellard | { "jfngt", "ble", }, /* Apparently a sun alias. */ |
4263 | 48024e4a | bellard | { "jfeq", "beqs", }, /* Apparently a sun alias. */ |
4264 | 48024e4a | bellard | { "bchgb", "bchg", }, |
4265 | 48024e4a | bellard | { "bchgl", "bchg", }, |
4266 | 48024e4a | bellard | { "bclrb", "bclr", }, |
4267 | 48024e4a | bellard | { "bclrl", "bclr", }, |
4268 | 48024e4a | bellard | { "bsetb", "bset", }, |
4269 | 48024e4a | bellard | { "bsetl", "bset", }, |
4270 | 48024e4a | bellard | { "btstb", "btst", }, |
4271 | 48024e4a | bellard | { "btstl", "btst", }, |
4272 | 48024e4a | bellard | { "cas2", "cas2w", }, |
4273 | 48024e4a | bellard | { "cas", "casw", }, |
4274 | 48024e4a | bellard | { "chk2", "chk2w", }, |
4275 | 48024e4a | bellard | { "chk", "chkw", }, |
4276 | 48024e4a | bellard | { "clr", "clrw", }, |
4277 | 48024e4a | bellard | { "cmp2", "cmp2w", }, |
4278 | 48024e4a | bellard | { "cmpa", "cmpaw", }, |
4279 | 48024e4a | bellard | { "cmpi", "cmpiw", }, |
4280 | 48024e4a | bellard | { "cmpm", "cmpmw", }, |
4281 | 48024e4a | bellard | { "cmp", "cmpw", }, |
4282 | 48024e4a | bellard | { "dbccw", "dbcc", }, |
4283 | 48024e4a | bellard | { "dbcsw", "dbcs", }, |
4284 | 48024e4a | bellard | { "dbeqw", "dbeq", }, |
4285 | 48024e4a | bellard | { "dbfw", "dbf", }, |
4286 | 48024e4a | bellard | { "dbgew", "dbge", }, |
4287 | 48024e4a | bellard | { "dbgtw", "dbgt", }, |
4288 | 48024e4a | bellard | { "dbhiw", "dbhi", }, |
4289 | 48024e4a | bellard | { "dblew", "dble", }, |
4290 | 48024e4a | bellard | { "dblsw", "dbls", }, |
4291 | 48024e4a | bellard | { "dbltw", "dblt", }, |
4292 | 48024e4a | bellard | { "dbmiw", "dbmi", }, |
4293 | 48024e4a | bellard | { "dbnew", "dbne", }, |
4294 | 48024e4a | bellard | { "dbplw", "dbpl", }, |
4295 | 48024e4a | bellard | { "dbtw", "dbt", }, |
4296 | 48024e4a | bellard | { "dbvcw", "dbvc", }, |
4297 | 48024e4a | bellard | { "dbvsw", "dbvs", }, |
4298 | 48024e4a | bellard | { "dbhs", "dbcc", }, |
4299 | 48024e4a | bellard | { "dbhsw", "dbcc", }, |
4300 | 48024e4a | bellard | { "dbra", "dbf", }, |
4301 | 48024e4a | bellard | { "dbraw", "dbf", }, |
4302 | 48024e4a | bellard | { "tdivsl", "divsl", }, |
4303 | 48024e4a | bellard | { "divs", "divsw", }, |
4304 | 48024e4a | bellard | { "divu", "divuw", }, |
4305 | 48024e4a | bellard | { "ext", "extw", }, |
4306 | 48024e4a | bellard | { "extbw", "extw", }, |
4307 | 48024e4a | bellard | { "extwl", "extl", }, |
4308 | 48024e4a | bellard | { "fbneq", "fbne", }, |
4309 | 48024e4a | bellard | { "fbsneq", "fbsne", }, |
4310 | 48024e4a | bellard | { "fdbneq", "fdbne", }, |
4311 | 48024e4a | bellard | { "fdbsneq", "fdbsne", }, |
4312 | 48024e4a | bellard | { "fmovecr", "fmovecrx", }, |
4313 | 48024e4a | bellard | { "fmovm", "fmovem", }, |
4314 | 48024e4a | bellard | { "fsneq", "fsne", }, |
4315 | 48024e4a | bellard | { "fssneq", "fssne", }, |
4316 | 48024e4a | bellard | { "ftrapneq", "ftrapne", }, |
4317 | 48024e4a | bellard | { "ftrapsneq", "ftrapsne", }, |
4318 | 48024e4a | bellard | { "fjneq", "fjne", }, |
4319 | 48024e4a | bellard | { "fjsneq", "fjsne", }, |
4320 | 48024e4a | bellard | { "jmpl", "jmp", }, |
4321 | 48024e4a | bellard | { "jmps", "jmp", }, |
4322 | 48024e4a | bellard | { "jsrl", "jsr", }, |
4323 | 48024e4a | bellard | { "jsrs", "jsr", }, |
4324 | 48024e4a | bellard | { "leal", "lea", }, |
4325 | 48024e4a | bellard | { "lsl", "lslw", }, |
4326 | 48024e4a | bellard | { "lsr", "lsrw", }, |
4327 | 48024e4a | bellard | { "mac", "macw" }, |
4328 | 48024e4a | bellard | { "movea", "moveaw", }, |
4329 | 48024e4a | bellard | { "movem", "movemw", }, |
4330 | 48024e4a | bellard | { "movml", "moveml", }, |
4331 | 48024e4a | bellard | { "movmw", "movemw", }, |
4332 | 48024e4a | bellard | { "movm", "movemw", }, |
4333 | 48024e4a | bellard | { "movep", "movepw", }, |
4334 | 48024e4a | bellard | { "movpw", "movepw", }, |
4335 | 48024e4a | bellard | { "moves", "movesw" }, |
4336 | 48024e4a | bellard | { "muls", "mulsw", }, |
4337 | 48024e4a | bellard | { "mulu", "muluw", }, |
4338 | 48024e4a | bellard | { "msac", "msacw" }, |
4339 | 48024e4a | bellard | { "nbcdb", "nbcd" }, |
4340 | 48024e4a | bellard | { "neg", "negw", }, |
4341 | 48024e4a | bellard | { "negx", "negxw", }, |
4342 | 48024e4a | bellard | { "not", "notw", }, |
4343 | 48024e4a | bellard | { "peal", "pea", }, |
4344 | 48024e4a | bellard | { "rol", "rolw", }, |
4345 | 48024e4a | bellard | { "ror", "rorw", }, |
4346 | 48024e4a | bellard | { "roxl", "roxlw", }, |
4347 | 48024e4a | bellard | { "roxr", "roxrw", }, |
4348 | 48024e4a | bellard | { "sats", "satsl", }, |
4349 | 48024e4a | bellard | { "sbcdb", "sbcd", }, |
4350 | 48024e4a | bellard | { "sccb", "scc", }, |
4351 | 48024e4a | bellard | { "scsb", "scs", }, |
4352 | 48024e4a | bellard | { "seqb", "seq", }, |
4353 | 48024e4a | bellard | { "sfb", "sf", }, |
4354 | 48024e4a | bellard | { "sgeb", "sge", }, |
4355 | 48024e4a | bellard | { "sgtb", "sgt", }, |
4356 | 48024e4a | bellard | { "shib", "shi", }, |
4357 | 48024e4a | bellard | { "sleb", "sle", }, |
4358 | 48024e4a | bellard | { "slsb", "sls", }, |
4359 | 48024e4a | bellard | { "sltb", "slt", }, |
4360 | 48024e4a | bellard | { "smib", "smi", }, |
4361 | 48024e4a | bellard | { "sneb", "sne", }, |
4362 | 48024e4a | bellard | { "splb", "spl", }, |
4363 | 48024e4a | bellard | { "stb", "st", }, |
4364 | 48024e4a | bellard | { "svcb", "svc", }, |
4365 | 48024e4a | bellard | { "svsb", "svs", }, |
4366 | 48024e4a | bellard | { "sfge", "sge", }, |
4367 | 48024e4a | bellard | { "sfgt", "sgt", }, |
4368 | 48024e4a | bellard | { "sfle", "sle", }, |
4369 | 48024e4a | bellard | { "sflt", "slt", }, |
4370 | 48024e4a | bellard | { "sfneq", "sne", }, |
4371 | 48024e4a | bellard | { "suba", "subaw", }, |
4372 | 48024e4a | bellard | { "subi", "subiw", }, |
4373 | 48024e4a | bellard | { "subq", "subqw", }, |
4374 | 48024e4a | bellard | { "sub", "subw", }, |
4375 | 48024e4a | bellard | { "subx", "subxw", }, |
4376 | 48024e4a | bellard | { "swapw", "swap", }, |
4377 | 48024e4a | bellard | { "tasb", "tas", }, |
4378 | 48024e4a | bellard | { "tpcc", "trapcc", }, |
4379 | 48024e4a | bellard | { "tcc", "trapcc", }, |
4380 | 48024e4a | bellard | { "tst", "tstw", }, |
4381 | 48024e4a | bellard | { "jbra", "jra", }, |
4382 | 48024e4a | bellard | { "jbhi", "jhi", }, |
4383 | 48024e4a | bellard | { "jbls", "jls", }, |
4384 | 48024e4a | bellard | { "jbcc", "jcc", }, |
4385 | 48024e4a | bellard | { "jbcs", "jcs", }, |
4386 | 48024e4a | bellard | { "jbne", "jne", }, |
4387 | 48024e4a | bellard | { "jbeq", "jeq", }, |
4388 | 48024e4a | bellard | { "jbvc", "jvc", }, |
4389 | 48024e4a | bellard | { "jbvs", "jvs", }, |
4390 | 48024e4a | bellard | { "jbpl", "jpl", }, |
4391 | 48024e4a | bellard | { "jbmi", "jmi", }, |
4392 | 48024e4a | bellard | { "jbge", "jge", }, |
4393 | 48024e4a | bellard | { "jblt", "jlt", }, |
4394 | 48024e4a | bellard | { "jbgt", "jgt", }, |
4395 | 48024e4a | bellard | { "jble", "jle", }, |
4396 | 48024e4a | bellard | { "movql", "moveq", }, |
4397 | 48024e4a | bellard | { "moveql", "moveq", }, |
4398 | 48024e4a | bellard | { "movl", "movel", }, |
4399 | 48024e4a | bellard | { "movq", "moveq", }, |
4400 | 48024e4a | bellard | { "moval", "moveal", }, |
4401 | 48024e4a | bellard | { "movaw", "moveaw", }, |
4402 | 48024e4a | bellard | { "movb", "moveb", }, |
4403 | 48024e4a | bellard | { "movc", "movec", }, |
4404 | 48024e4a | bellard | { "movecl", "movec", }, |
4405 | 48024e4a | bellard | { "movpl", "movepl", }, |
4406 | 48024e4a | bellard | { "movw", "movew", }, |
4407 | 48024e4a | bellard | { "movsb", "movesb", }, |
4408 | 48024e4a | bellard | { "movsl", "movesl", }, |
4409 | 48024e4a | bellard | { "movsw", "movesw", }, |
4410 | 48024e4a | bellard | { "mov3q", "mov3ql", }, |
4411 | 48024e4a | bellard | |
4412 | 48024e4a | bellard | { "tdivul", "divul", }, /* For m68k-svr4. */ |
4413 | 48024e4a | bellard | { "fmovb", "fmoveb", }, |
4414 | 48024e4a | bellard | { "fsmovb", "fsmoveb", }, |
4415 | 48024e4a | bellard | { "fdmovb", "fdmoveb", }, |
4416 | 48024e4a | bellard | { "fmovd", "fmoved", }, |
4417 | 48024e4a | bellard | { "fsmovd", "fsmoved", }, |
4418 | 48024e4a | bellard | { "fmovl", "fmovel", }, |
4419 | 48024e4a | bellard | { "fsmovl", "fsmovel", }, |
4420 | 48024e4a | bellard | { "fdmovl", "fdmovel", }, |
4421 | 48024e4a | bellard | { "fmovp", "fmovep", }, |
4422 | 48024e4a | bellard | { "fsmovp", "fsmovep", }, |
4423 | 48024e4a | bellard | { "fdmovp", "fdmovep", }, |
4424 | 48024e4a | bellard | { "fmovs", "fmoves", }, |
4425 | 48024e4a | bellard | { "fsmovs", "fsmoves", }, |
4426 | 48024e4a | bellard | { "fdmovs", "fdmoves", }, |
4427 | 48024e4a | bellard | { "fmovw", "fmovew", }, |
4428 | 48024e4a | bellard | { "fsmovw", "fsmovew", }, |
4429 | 48024e4a | bellard | { "fdmovw", "fdmovew", }, |
4430 | 48024e4a | bellard | { "fmovx", "fmovex", }, |
4431 | 48024e4a | bellard | { "fsmovx", "fsmovex", }, |
4432 | 48024e4a | bellard | { "fdmovx", "fdmovex", }, |
4433 | 48024e4a | bellard | { "fmovcr", "fmovecr", }, |
4434 | 48024e4a | bellard | { "fmovcrx", "fmovecrx", }, |
4435 | 48024e4a | bellard | { "ftestb", "ftstb", }, |
4436 | 48024e4a | bellard | { "ftestd", "ftstd", }, |
4437 | 48024e4a | bellard | { "ftestl", "ftstl", }, |
4438 | 48024e4a | bellard | { "ftestp", "ftstp", }, |
4439 | 48024e4a | bellard | { "ftests", "ftsts", }, |
4440 | 48024e4a | bellard | { "ftestw", "ftstw", }, |
4441 | 48024e4a | bellard | { "ftestx", "ftstx", }, |
4442 | 48024e4a | bellard | |
4443 | 48024e4a | bellard | { "bitrevl", "bitrev", }, |
4444 | 48024e4a | bellard | { "byterevl", "byterev", }, |
4445 | 48024e4a | bellard | { "ff1l", "ff1", }, |
4446 | 48024e4a | bellard | |
4447 | 48024e4a | bellard | }; |
4448 | 48024e4a | bellard | |
4449 | 48024e4a | bellard | const int m68k_numaliases = |
4450 | 48024e4a | bellard | sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0]; |
4451 | 48024e4a | bellard | /* **** End of m68k-opc.c */
|
4452 | 48024e4a | bellard | /* **** floatformat.c from sourceware.org CVS 2005-08-14. */
|
4453 | 48024e4a | bellard | /* IEEE floating point support routines, for GDB, the GNU Debugger.
|
4454 | 48024e4a | bellard | Copyright (C) 1991, 1994, 1999, 2000, 2003 Free Software Foundation, Inc.
|
4455 | 48024e4a | bellard | |
4456 | 48024e4a | bellard | This file is part of GDB.
|
4457 | 48024e4a | bellard | |
4458 | 48024e4a | bellard | This program is free software; you can redistribute it and/or modify
|
4459 | 48024e4a | bellard | it under the terms of the GNU General Public License as published by
|
4460 | 48024e4a | bellard | the Free Software Foundation; either version 2 of the License, or
|
4461 | 48024e4a | bellard | (at your option) any later version.
|
4462 | 48024e4a | bellard | |
4463 | 48024e4a | bellard | This program is distributed in the hope that it will be useful,
|
4464 | 48024e4a | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
4465 | 48024e4a | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
4466 | 48024e4a | bellard | GNU General Public License for more details.
|
4467 | 48024e4a | bellard | |
4468 | 48024e4a | bellard | You should have received a copy of the GNU General Public License
|
4469 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
4470 | 48024e4a | bellard | |
4471 | 48024e4a | bellard | /* This is needed to pick up the NAN macro on some systems. */
|
4472 | 48024e4a | bellard | //#define _GNU_SOURCE
|
4473 | 48024e4a | bellard | |
4474 | 48024e4a | bellard | #ifndef INFINITY
|
4475 | 48024e4a | bellard | #ifdef HUGE_VAL
|
4476 | 48024e4a | bellard | #define INFINITY HUGE_VAL
|
4477 | 48024e4a | bellard | #else
|
4478 | 48024e4a | bellard | #define INFINITY (1.0 / 0.0) |
4479 | 48024e4a | bellard | #endif
|
4480 | 48024e4a | bellard | #endif
|
4481 | 48024e4a | bellard | |
4482 | 48024e4a | bellard | #ifndef NAN
|
4483 | 48024e4a | bellard | #define NAN (0.0 / 0.0) |
4484 | 48024e4a | bellard | #endif
|
4485 | 48024e4a | bellard | |
4486 | 48024e4a | bellard | static unsigned long get_field (const unsigned char *, |
4487 | 48024e4a | bellard | enum floatformat_byteorders,
|
4488 | 48024e4a | bellard | unsigned int, |
4489 | 48024e4a | bellard | unsigned int, |
4490 | 48024e4a | bellard | unsigned int); |
4491 | 48024e4a | bellard | static int floatformat_always_valid (const struct floatformat *fmt, |
4492 | 48024e4a | bellard | const char *from); |
4493 | 48024e4a | bellard | |
4494 | 48024e4a | bellard | static int |
4495 | 48024e4a | bellard | floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED, |
4496 | 48024e4a | bellard | const char *from ATTRIBUTE_UNUSED) |
4497 | 48024e4a | bellard | { |
4498 | 48024e4a | bellard | return 1; |
4499 | 48024e4a | bellard | } |
4500 | 48024e4a | bellard | |
4501 | 48024e4a | bellard | /* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not
|
4502 | 48024e4a | bellard | going to bother with trying to muck around with whether it is defined in
|
4503 | 48024e4a | bellard | a system header, what we do if not, etc. */
|
4504 | 48024e4a | bellard | #define FLOATFORMAT_CHAR_BIT 8 |
4505 | 48024e4a | bellard | |
4506 | 48024e4a | bellard | /* floatformats for IEEE single and double, big and little endian. */
|
4507 | 48024e4a | bellard | const struct floatformat floatformat_ieee_single_big = |
4508 | 48024e4a | bellard | { |
4509 | 48024e4a | bellard | floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23, |
4510 | 48024e4a | bellard | floatformat_intbit_no, |
4511 | 48024e4a | bellard | "floatformat_ieee_single_big",
|
4512 | 48024e4a | bellard | floatformat_always_valid |
4513 | 48024e4a | bellard | }; |
4514 | 48024e4a | bellard | const struct floatformat floatformat_ieee_single_little = |
4515 | 48024e4a | bellard | { |
4516 | 48024e4a | bellard | floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23, |
4517 | 48024e4a | bellard | floatformat_intbit_no, |
4518 | 48024e4a | bellard | "floatformat_ieee_single_little",
|
4519 | 48024e4a | bellard | floatformat_always_valid |
4520 | 48024e4a | bellard | }; |
4521 | 48024e4a | bellard | const struct floatformat floatformat_ieee_double_big = |
4522 | 48024e4a | bellard | { |
4523 | 48024e4a | bellard | floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52, |
4524 | 48024e4a | bellard | floatformat_intbit_no, |
4525 | 48024e4a | bellard | "floatformat_ieee_double_big",
|
4526 | 48024e4a | bellard | floatformat_always_valid |
4527 | 48024e4a | bellard | }; |
4528 | 48024e4a | bellard | const struct floatformat floatformat_ieee_double_little = |
4529 | 48024e4a | bellard | { |
4530 | 48024e4a | bellard | floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52, |
4531 | 48024e4a | bellard | floatformat_intbit_no, |
4532 | 48024e4a | bellard | "floatformat_ieee_double_little",
|
4533 | 48024e4a | bellard | floatformat_always_valid |
4534 | 48024e4a | bellard | }; |
4535 | 48024e4a | bellard | |
4536 | 48024e4a | bellard | /* floatformat for IEEE double, little endian byte order, with big endian word
|
4537 | 48024e4a | bellard | ordering, as on the ARM. */
|
4538 | 48024e4a | bellard | |
4539 | 48024e4a | bellard | const struct floatformat floatformat_ieee_double_littlebyte_bigword = |
4540 | 48024e4a | bellard | { |
4541 | 48024e4a | bellard | floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52, |
4542 | 48024e4a | bellard | floatformat_intbit_no, |
4543 | 48024e4a | bellard | "floatformat_ieee_double_littlebyte_bigword",
|
4544 | 48024e4a | bellard | floatformat_always_valid |
4545 | 48024e4a | bellard | }; |
4546 | 48024e4a | bellard | |
4547 | 48024e4a | bellard | static int floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from); |
4548 | 48024e4a | bellard | |
4549 | 48024e4a | bellard | static int |
4550 | 48024e4a | bellard | floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from) |
4551 | 48024e4a | bellard | { |
4552 | 48024e4a | bellard | /* In the i387 double-extended format, if the exponent is all ones,
|
4553 | 48024e4a | bellard | then the integer bit must be set. If the exponent is neither 0
|
4554 | 48024e4a | bellard | nor ~0, the intbit must also be set. Only if the exponent is
|
4555 | 48024e4a | bellard | zero can it be zero, and then it must be zero. */
|
4556 | 48024e4a | bellard | unsigned long exponent, int_bit; |
4557 | 48024e4a | bellard | const unsigned char *ufrom = (const unsigned char *) from; |
4558 | 3b46e624 | ths | |
4559 | 48024e4a | bellard | exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, |
4560 | 48024e4a | bellard | fmt->exp_start, fmt->exp_len); |
4561 | 48024e4a | bellard | int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize, |
4562 | 48024e4a | bellard | fmt->man_start, 1);
|
4563 | 3b46e624 | ths | |
4564 | 48024e4a | bellard | if ((exponent == 0) != (int_bit == 0)) |
4565 | 48024e4a | bellard | return 0; |
4566 | 48024e4a | bellard | else
|
4567 | 48024e4a | bellard | return 1; |
4568 | 48024e4a | bellard | } |
4569 | 48024e4a | bellard | |
4570 | 48024e4a | bellard | const struct floatformat floatformat_i387_ext = |
4571 | 48024e4a | bellard | { |
4572 | 48024e4a | bellard | floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, |
4573 | 48024e4a | bellard | floatformat_intbit_yes, |
4574 | 48024e4a | bellard | "floatformat_i387_ext",
|
4575 | 48024e4a | bellard | floatformat_i387_ext_is_valid |
4576 | 48024e4a | bellard | }; |
4577 | 48024e4a | bellard | const struct floatformat floatformat_m68881_ext = |
4578 | 48024e4a | bellard | { |
4579 | 48024e4a | bellard | /* Note that the bits from 16 to 31 are unused. */
|
4580 | 48024e4a | bellard | floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64, |
4581 | 48024e4a | bellard | floatformat_intbit_yes, |
4582 | 48024e4a | bellard | "floatformat_m68881_ext",
|
4583 | 48024e4a | bellard | floatformat_always_valid |
4584 | 48024e4a | bellard | }; |
4585 | 48024e4a | bellard | const struct floatformat floatformat_i960_ext = |
4586 | 48024e4a | bellard | { |
4587 | 48024e4a | bellard | /* Note that the bits from 0 to 15 are unused. */
|
4588 | 48024e4a | bellard | floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64, |
4589 | 48024e4a | bellard | floatformat_intbit_yes, |
4590 | 48024e4a | bellard | "floatformat_i960_ext",
|
4591 | 48024e4a | bellard | floatformat_always_valid |
4592 | 48024e4a | bellard | }; |
4593 | 48024e4a | bellard | const struct floatformat floatformat_m88110_ext = |
4594 | 48024e4a | bellard | { |
4595 | 48024e4a | bellard | floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, |
4596 | 48024e4a | bellard | floatformat_intbit_yes, |
4597 | 48024e4a | bellard | "floatformat_m88110_ext",
|
4598 | 48024e4a | bellard | floatformat_always_valid |
4599 | 48024e4a | bellard | }; |
4600 | 48024e4a | bellard | const struct floatformat floatformat_m88110_harris_ext = |
4601 | 48024e4a | bellard | { |
4602 | 48024e4a | bellard | /* Harris uses raw format 128 bytes long, but the number is just an ieee
|
4603 | 48024e4a | bellard | double, and the last 64 bits are wasted. */
|
4604 | 48024e4a | bellard | floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52, |
4605 | 48024e4a | bellard | floatformat_intbit_no, |
4606 | 48024e4a | bellard | "floatformat_m88110_ext_harris",
|
4607 | 48024e4a | bellard | floatformat_always_valid |
4608 | 48024e4a | bellard | }; |
4609 | 48024e4a | bellard | const struct floatformat floatformat_arm_ext_big = |
4610 | 48024e4a | bellard | { |
4611 | 48024e4a | bellard | /* Bits 1 to 16 are unused. */
|
4612 | 48024e4a | bellard | floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, |
4613 | 48024e4a | bellard | floatformat_intbit_yes, |
4614 | 48024e4a | bellard | "floatformat_arm_ext_big",
|
4615 | 48024e4a | bellard | floatformat_always_valid |
4616 | 48024e4a | bellard | }; |
4617 | 48024e4a | bellard | const struct floatformat floatformat_arm_ext_littlebyte_bigword = |
4618 | 48024e4a | bellard | { |
4619 | 48024e4a | bellard | /* Bits 1 to 16 are unused. */
|
4620 | 48024e4a | bellard | floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, |
4621 | 48024e4a | bellard | floatformat_intbit_yes, |
4622 | 48024e4a | bellard | "floatformat_arm_ext_littlebyte_bigword",
|
4623 | 48024e4a | bellard | floatformat_always_valid |
4624 | 48024e4a | bellard | }; |
4625 | 48024e4a | bellard | const struct floatformat floatformat_ia64_spill_big = |
4626 | 48024e4a | bellard | { |
4627 | 48024e4a | bellard | floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, |
4628 | 48024e4a | bellard | floatformat_intbit_yes, |
4629 | 48024e4a | bellard | "floatformat_ia64_spill_big",
|
4630 | 48024e4a | bellard | floatformat_always_valid |
4631 | 48024e4a | bellard | }; |
4632 | 48024e4a | bellard | const struct floatformat floatformat_ia64_spill_little = |
4633 | 48024e4a | bellard | { |
4634 | 48024e4a | bellard | floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, |
4635 | 48024e4a | bellard | floatformat_intbit_yes, |
4636 | 48024e4a | bellard | "floatformat_ia64_spill_little",
|
4637 | 48024e4a | bellard | floatformat_always_valid |
4638 | 48024e4a | bellard | }; |
4639 | 48024e4a | bellard | const struct floatformat floatformat_ia64_quad_big = |
4640 | 48024e4a | bellard | { |
4641 | 48024e4a | bellard | floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, |
4642 | 48024e4a | bellard | floatformat_intbit_no, |
4643 | 48024e4a | bellard | "floatformat_ia64_quad_big",
|
4644 | 48024e4a | bellard | floatformat_always_valid |
4645 | 48024e4a | bellard | }; |
4646 | 48024e4a | bellard | const struct floatformat floatformat_ia64_quad_little = |
4647 | 48024e4a | bellard | { |
4648 | 48024e4a | bellard | floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, |
4649 | 48024e4a | bellard | floatformat_intbit_no, |
4650 | 48024e4a | bellard | "floatformat_ia64_quad_little",
|
4651 | 48024e4a | bellard | floatformat_always_valid |
4652 | 48024e4a | bellard | }; |
4653 | 48024e4a | bellard | |
4654 | 48024e4a | bellard | /* Extract a field which starts at START and is LEN bits long. DATA and
|
4655 | 48024e4a | bellard | TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
|
4656 | 48024e4a | bellard | static unsigned long |
4657 | 48024e4a | bellard | get_field (const unsigned char *data, enum floatformat_byteorders order, |
4658 | 48024e4a | bellard | unsigned int total_len, unsigned int start, unsigned int len) |
4659 | 48024e4a | bellard | { |
4660 | 48024e4a | bellard | unsigned long result; |
4661 | 48024e4a | bellard | unsigned int cur_byte; |
4662 | 48024e4a | bellard | int cur_bitshift;
|
4663 | 48024e4a | bellard | |
4664 | 48024e4a | bellard | /* Start at the least significant part of the field. */
|
4665 | 48024e4a | bellard | cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT; |
4666 | 48024e4a | bellard | if (order == floatformat_little)
|
4667 | 48024e4a | bellard | cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
|
4668 | 48024e4a | bellard | cur_bitshift = |
4669 | 48024e4a | bellard | ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT; |
4670 | 48024e4a | bellard | result = *(data + cur_byte) >> (-cur_bitshift); |
4671 | 48024e4a | bellard | cur_bitshift += FLOATFORMAT_CHAR_BIT; |
4672 | 48024e4a | bellard | if (order == floatformat_little)
|
4673 | 48024e4a | bellard | ++cur_byte; |
4674 | 48024e4a | bellard | else
|
4675 | 48024e4a | bellard | --cur_byte; |
4676 | 48024e4a | bellard | |
4677 | 48024e4a | bellard | /* Move towards the most significant part of the field. */
|
4678 | 48024e4a | bellard | while ((unsigned int) cur_bitshift < len) |
4679 | 48024e4a | bellard | { |
4680 | 48024e4a | bellard | if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
|
4681 | 48024e4a | bellard | /* This is the last byte; zero out the bits which are not part of
|
4682 | 48024e4a | bellard | this field. */
|
4683 | 48024e4a | bellard | result |= |
4684 | 48024e4a | bellard | (*(data + cur_byte) & ((1 << (len - cur_bitshift)) - 1)) |
4685 | 48024e4a | bellard | << cur_bitshift; |
4686 | 48024e4a | bellard | else
|
4687 | 48024e4a | bellard | result |= *(data + cur_byte) << cur_bitshift; |
4688 | 48024e4a | bellard | cur_bitshift += FLOATFORMAT_CHAR_BIT; |
4689 | 48024e4a | bellard | if (order == floatformat_little)
|
4690 | 48024e4a | bellard | ++cur_byte; |
4691 | 48024e4a | bellard | else
|
4692 | 48024e4a | bellard | --cur_byte; |
4693 | 48024e4a | bellard | } |
4694 | 48024e4a | bellard | return result;
|
4695 | 48024e4a | bellard | } |
4696 | 3b46e624 | ths | |
4697 | 48024e4a | bellard | #ifndef min
|
4698 | 48024e4a | bellard | #define min(a, b) ((a) < (b) ? (a) : (b))
|
4699 | 48024e4a | bellard | #endif
|
4700 | 48024e4a | bellard | |
4701 | 48024e4a | bellard | /* Convert from FMT to a double.
|
4702 | 48024e4a | bellard | FROM is the address of the extended float.
|
4703 | 48024e4a | bellard | Store the double in *TO. */
|
4704 | 48024e4a | bellard | |
4705 | 48024e4a | bellard | void
|
4706 | 48024e4a | bellard | floatformat_to_double (const struct floatformat *fmt, |
4707 | 48024e4a | bellard | const char *from, double *to) |
4708 | 48024e4a | bellard | { |
4709 | 48024e4a | bellard | const unsigned char *ufrom = (const unsigned char *)from; |
4710 | 48024e4a | bellard | double dto;
|
4711 | 48024e4a | bellard | long exponent;
|
4712 | 48024e4a | bellard | unsigned long mant; |
4713 | 48024e4a | bellard | unsigned int mant_bits, mant_off; |
4714 | 48024e4a | bellard | int mant_bits_left;
|
4715 | 48024e4a | bellard | int special_exponent; /* It's a NaN, denorm or zero */ |
4716 | 48024e4a | bellard | |
4717 | 48024e4a | bellard | exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, |
4718 | 48024e4a | bellard | fmt->exp_start, fmt->exp_len); |
4719 | 48024e4a | bellard | |
4720 | 48024e4a | bellard | /* If the exponent indicates a NaN, we don't have information to
|
4721 | 48024e4a | bellard | decide what to do. So we handle it like IEEE, except that we
|
4722 | 48024e4a | bellard | don't try to preserve the type of NaN. FIXME. */
|
4723 | 48024e4a | bellard | if ((unsigned long) exponent == fmt->exp_nan) |
4724 | 48024e4a | bellard | { |
4725 | 48024e4a | bellard | int nan;
|
4726 | 48024e4a | bellard | |
4727 | 48024e4a | bellard | mant_off = fmt->man_start; |
4728 | 48024e4a | bellard | mant_bits_left = fmt->man_len; |
4729 | 48024e4a | bellard | nan = 0;
|
4730 | 48024e4a | bellard | while (mant_bits_left > 0) |
4731 | 48024e4a | bellard | { |
4732 | 48024e4a | bellard | mant_bits = min (mant_bits_left, 32);
|
4733 | 48024e4a | bellard | |
4734 | 48024e4a | bellard | if (get_field (ufrom, fmt->byteorder, fmt->totalsize,
|
4735 | 48024e4a | bellard | mant_off, mant_bits) != 0)
|
4736 | 48024e4a | bellard | { |
4737 | 48024e4a | bellard | /* This is a NaN. */
|
4738 | 48024e4a | bellard | nan = 1;
|
4739 | 48024e4a | bellard | break;
|
4740 | 48024e4a | bellard | } |
4741 | 48024e4a | bellard | |
4742 | 48024e4a | bellard | mant_off += mant_bits; |
4743 | 48024e4a | bellard | mant_bits_left -= mant_bits; |
4744 | 48024e4a | bellard | } |
4745 | 48024e4a | bellard | |
4746 | 48024e4a | bellard | /* On certain systems (such as GNU/Linux), the use of the
|
4747 | 48024e4a | bellard | INFINITY macro below may generate a warning that can not be
|
4748 | 48024e4a | bellard | silenced due to a bug in GCC (PR preprocessor/11931). The
|
4749 | 48024e4a | bellard | preprocessor fails to recognise the __extension__ keyword in
|
4750 | 48024e4a | bellard | conjunction with the GNU/C99 extension for hexadecimal
|
4751 | 48024e4a | bellard | floating point constants and will issue a warning when
|
4752 | 48024e4a | bellard | compiling with -pedantic. */
|
4753 | 48024e4a | bellard | if (nan)
|
4754 | 48024e4a | bellard | dto = NAN; |
4755 | 48024e4a | bellard | else
|
4756 | 48024e4a | bellard | dto = INFINITY; |
4757 | 48024e4a | bellard | |
4758 | 48024e4a | bellard | if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) |
4759 | 48024e4a | bellard | dto = -dto; |
4760 | 48024e4a | bellard | |
4761 | 48024e4a | bellard | *to = dto; |
4762 | 48024e4a | bellard | |
4763 | 48024e4a | bellard | return;
|
4764 | 48024e4a | bellard | } |
4765 | 48024e4a | bellard | |
4766 | 48024e4a | bellard | mant_bits_left = fmt->man_len; |
4767 | 48024e4a | bellard | mant_off = fmt->man_start; |
4768 | 48024e4a | bellard | dto = 0.0; |
4769 | 48024e4a | bellard | |
4770 | 48024e4a | bellard | special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan; |
4771 | 48024e4a | bellard | |
4772 | 48024e4a | bellard | /* Don't bias zero's, denorms or NaNs. */
|
4773 | 48024e4a | bellard | if (!special_exponent)
|
4774 | 48024e4a | bellard | exponent -= fmt->exp_bias; |
4775 | 48024e4a | bellard | |
4776 | 48024e4a | bellard | /* Build the result algebraically. Might go infinite, underflow, etc;
|
4777 | 48024e4a | bellard | who cares. */
|
4778 | 48024e4a | bellard | |
4779 | 48024e4a | bellard | /* If this format uses a hidden bit, explicitly add it in now. Otherwise,
|
4780 | 48024e4a | bellard | increment the exponent by one to account for the integer bit. */
|
4781 | 48024e4a | bellard | |
4782 | 48024e4a | bellard | if (!special_exponent)
|
4783 | 48024e4a | bellard | { |
4784 | 48024e4a | bellard | if (fmt->intbit == floatformat_intbit_no)
|
4785 | 48024e4a | bellard | dto = ldexp (1.0, exponent); |
4786 | 48024e4a | bellard | else
|
4787 | 48024e4a | bellard | exponent++; |
4788 | 48024e4a | bellard | } |
4789 | 48024e4a | bellard | |
4790 | 48024e4a | bellard | while (mant_bits_left > 0) |
4791 | 48024e4a | bellard | { |
4792 | 48024e4a | bellard | mant_bits = min (mant_bits_left, 32);
|
4793 | 48024e4a | bellard | |
4794 | 48024e4a | bellard | mant = get_field (ufrom, fmt->byteorder, fmt->totalsize, |
4795 | 48024e4a | bellard | mant_off, mant_bits); |
4796 | 48024e4a | bellard | |
4797 | 48024e4a | bellard | /* Handle denormalized numbers. FIXME: What should we do for
|
4798 | 48024e4a | bellard | non-IEEE formats? */
|
4799 | 48024e4a | bellard | if (exponent == 0 && mant != 0) |
4800 | 48024e4a | bellard | dto += ldexp ((double)mant,
|
4801 | 48024e4a | bellard | (- fmt->exp_bias |
4802 | 48024e4a | bellard | - mant_bits |
4803 | 48024e4a | bellard | - (mant_off - fmt->man_start) |
4804 | 48024e4a | bellard | + 1));
|
4805 | 48024e4a | bellard | else
|
4806 | 48024e4a | bellard | dto += ldexp ((double)mant, exponent - mant_bits);
|
4807 | 48024e4a | bellard | if (exponent != 0) |
4808 | 48024e4a | bellard | exponent -= mant_bits; |
4809 | 48024e4a | bellard | mant_off += mant_bits; |
4810 | 48024e4a | bellard | mant_bits_left -= mant_bits; |
4811 | 48024e4a | bellard | } |
4812 | 48024e4a | bellard | |
4813 | 48024e4a | bellard | /* Negate it if negative. */
|
4814 | 48024e4a | bellard | if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) |
4815 | 48024e4a | bellard | dto = -dto; |
4816 | 48024e4a | bellard | *to = dto; |
4817 | 48024e4a | bellard | } |
4818 | 48024e4a | bellard | |
4819 | 48024e4a | bellard | static void put_field (unsigned char *, enum floatformat_byteorders, |
4820 | 48024e4a | bellard | unsigned int, |
4821 | 48024e4a | bellard | unsigned int, |
4822 | 48024e4a | bellard | unsigned int, |
4823 | 48024e4a | bellard | unsigned long); |
4824 | 48024e4a | bellard | |
4825 | 48024e4a | bellard | /* Set a field which starts at START and is LEN bits long. DATA and
|
4826 | 48024e4a | bellard | TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
|
4827 | 48024e4a | bellard | static void |
4828 | 48024e4a | bellard | put_field (unsigned char *data, enum floatformat_byteorders order, |
4829 | 48024e4a | bellard | unsigned int total_len, unsigned int start, unsigned int len, |
4830 | 48024e4a | bellard | unsigned long stuff_to_put) |
4831 | 48024e4a | bellard | { |
4832 | 48024e4a | bellard | unsigned int cur_byte; |
4833 | 48024e4a | bellard | int cur_bitshift;
|
4834 | 48024e4a | bellard | |
4835 | 48024e4a | bellard | /* Start at the least significant part of the field. */
|
4836 | 48024e4a | bellard | cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT; |
4837 | 48024e4a | bellard | if (order == floatformat_little)
|
4838 | 48024e4a | bellard | cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
|
4839 | 48024e4a | bellard | cur_bitshift = |
4840 | 48024e4a | bellard | ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT; |
4841 | 48024e4a | bellard | *(data + cur_byte) &= |
4842 | 48024e4a | bellard | ~(((1 << ((start + len) % FLOATFORMAT_CHAR_BIT)) - 1) << (-cur_bitshift)); |
4843 | 48024e4a | bellard | *(data + cur_byte) |= |
4844 | 48024e4a | bellard | (stuff_to_put & ((1 << FLOATFORMAT_CHAR_BIT) - 1)) << (-cur_bitshift); |
4845 | 48024e4a | bellard | cur_bitshift += FLOATFORMAT_CHAR_BIT; |
4846 | 48024e4a | bellard | if (order == floatformat_little)
|
4847 | 48024e4a | bellard | ++cur_byte; |
4848 | 48024e4a | bellard | else
|
4849 | 48024e4a | bellard | --cur_byte; |
4850 | 48024e4a | bellard | |
4851 | 48024e4a | bellard | /* Move towards the most significant part of the field. */
|
4852 | 48024e4a | bellard | while ((unsigned int) cur_bitshift < len) |
4853 | 48024e4a | bellard | { |
4854 | 48024e4a | bellard | if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
|
4855 | 48024e4a | bellard | { |
4856 | 48024e4a | bellard | /* This is the last byte. */
|
4857 | 48024e4a | bellard | *(data + cur_byte) &= |
4858 | 48024e4a | bellard | ~((1 << (len - cur_bitshift)) - 1); |
4859 | 48024e4a | bellard | *(data + cur_byte) |= (stuff_to_put >> cur_bitshift); |
4860 | 48024e4a | bellard | } |
4861 | 48024e4a | bellard | else
|
4862 | 48024e4a | bellard | *(data + cur_byte) = ((stuff_to_put >> cur_bitshift) |
4863 | 48024e4a | bellard | & ((1 << FLOATFORMAT_CHAR_BIT) - 1)); |
4864 | 48024e4a | bellard | cur_bitshift += FLOATFORMAT_CHAR_BIT; |
4865 | 48024e4a | bellard | if (order == floatformat_little)
|
4866 | 48024e4a | bellard | ++cur_byte; |
4867 | 48024e4a | bellard | else
|
4868 | 48024e4a | bellard | --cur_byte; |
4869 | 48024e4a | bellard | } |
4870 | 48024e4a | bellard | } |
4871 | 48024e4a | bellard | |
4872 | 48024e4a | bellard | /* The converse: convert the double *FROM to an extended float
|
4873 | 48024e4a | bellard | and store where TO points. Neither FROM nor TO have any alignment
|
4874 | 48024e4a | bellard | restrictions. */
|
4875 | 48024e4a | bellard | |
4876 | 48024e4a | bellard | void
|
4877 | 48024e4a | bellard | floatformat_from_double (const struct floatformat *fmt, |
4878 | 48024e4a | bellard | const double *from, char *to) |
4879 | 48024e4a | bellard | { |
4880 | 48024e4a | bellard | double dfrom;
|
4881 | 48024e4a | bellard | int exponent;
|
4882 | 48024e4a | bellard | double mant;
|
4883 | 48024e4a | bellard | unsigned int mant_bits, mant_off; |
4884 | 48024e4a | bellard | int mant_bits_left;
|
4885 | 48024e4a | bellard | unsigned char *uto = (unsigned char *)to; |
4886 | 48024e4a | bellard | |
4887 | 48024e4a | bellard | dfrom = *from; |
4888 | 48024e4a | bellard | memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT);
|
4889 | 48024e4a | bellard | |
4890 | 48024e4a | bellard | /* If negative, set the sign bit. */
|
4891 | 48024e4a | bellard | if (dfrom < 0) |
4892 | 48024e4a | bellard | { |
4893 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1); |
4894 | 48024e4a | bellard | dfrom = -dfrom; |
4895 | 48024e4a | bellard | } |
4896 | 48024e4a | bellard | |
4897 | 48024e4a | bellard | if (dfrom == 0) |
4898 | 48024e4a | bellard | { |
4899 | 48024e4a | bellard | /* 0.0. */
|
4900 | 48024e4a | bellard | return;
|
4901 | 48024e4a | bellard | } |
4902 | 48024e4a | bellard | |
4903 | 48024e4a | bellard | if (dfrom != dfrom)
|
4904 | 48024e4a | bellard | { |
4905 | 48024e4a | bellard | /* NaN. */
|
4906 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, |
4907 | 48024e4a | bellard | fmt->exp_len, fmt->exp_nan); |
4908 | 48024e4a | bellard | /* Be sure it's not infinity, but NaN value is irrelevant. */
|
4909 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start, |
4910 | 48024e4a | bellard | 32, 1); |
4911 | 48024e4a | bellard | return;
|
4912 | 48024e4a | bellard | } |
4913 | 48024e4a | bellard | |
4914 | 48024e4a | bellard | if (dfrom + dfrom == dfrom)
|
4915 | 48024e4a | bellard | { |
4916 | 48024e4a | bellard | /* This can only happen for an infinite value (or zero, which we
|
4917 | 48024e4a | bellard | already handled above). */
|
4918 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, |
4919 | 48024e4a | bellard | fmt->exp_len, fmt->exp_nan); |
4920 | 48024e4a | bellard | return;
|
4921 | 48024e4a | bellard | } |
4922 | 48024e4a | bellard | |
4923 | 48024e4a | bellard | mant = frexp (dfrom, &exponent); |
4924 | 48024e4a | bellard | if (exponent + fmt->exp_bias - 1 > 0) |
4925 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, |
4926 | 48024e4a | bellard | fmt->exp_len, exponent + fmt->exp_bias - 1);
|
4927 | 48024e4a | bellard | else
|
4928 | 48024e4a | bellard | { |
4929 | 48024e4a | bellard | /* Handle a denormalized number. FIXME: What should we do for
|
4930 | 48024e4a | bellard | non-IEEE formats? */
|
4931 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, |
4932 | 48024e4a | bellard | fmt->exp_len, 0);
|
4933 | 48024e4a | bellard | mant = ldexp (mant, exponent + fmt->exp_bias - 1);
|
4934 | 48024e4a | bellard | } |
4935 | 48024e4a | bellard | |
4936 | 48024e4a | bellard | mant_bits_left = fmt->man_len; |
4937 | 48024e4a | bellard | mant_off = fmt->man_start; |
4938 | 48024e4a | bellard | while (mant_bits_left > 0) |
4939 | 48024e4a | bellard | { |
4940 | 48024e4a | bellard | unsigned long mant_long; |
4941 | 48024e4a | bellard | mant_bits = mant_bits_left < 32 ? mant_bits_left : 32; |
4942 | 48024e4a | bellard | |
4943 | 48024e4a | bellard | mant *= 4294967296.0; |
4944 | 48024e4a | bellard | mant_long = (unsigned long)mant; |
4945 | 48024e4a | bellard | mant -= mant_long; |
4946 | 48024e4a | bellard | |
4947 | 48024e4a | bellard | /* If the integer bit is implicit, and we are not creating a
|
4948 | 48024e4a | bellard | denormalized number, then we need to discard it. */
|
4949 | 48024e4a | bellard | if ((unsigned int) mant_bits_left == fmt->man_len |
4950 | 48024e4a | bellard | && fmt->intbit == floatformat_intbit_no |
4951 | 48024e4a | bellard | && exponent + fmt->exp_bias - 1 > 0) |
4952 | 48024e4a | bellard | { |
4953 | 48024e4a | bellard | mant_long &= 0x7fffffff;
|
4954 | 48024e4a | bellard | mant_bits -= 1;
|
4955 | 48024e4a | bellard | } |
4956 | 48024e4a | bellard | else if (mant_bits < 32) |
4957 | 48024e4a | bellard | { |
4958 | 48024e4a | bellard | /* The bits we want are in the most significant MANT_BITS bits of
|
4959 | 48024e4a | bellard | mant_long. Move them to the least significant. */
|
4960 | 48024e4a | bellard | mant_long >>= 32 - mant_bits;
|
4961 | 48024e4a | bellard | } |
4962 | 48024e4a | bellard | |
4963 | 48024e4a | bellard | put_field (uto, fmt->byteorder, fmt->totalsize, |
4964 | 48024e4a | bellard | mant_off, mant_bits, mant_long); |
4965 | 48024e4a | bellard | mant_off += mant_bits; |
4966 | 48024e4a | bellard | mant_bits_left -= mant_bits; |
4967 | 48024e4a | bellard | } |
4968 | 48024e4a | bellard | } |
4969 | 48024e4a | bellard | |
4970 | 48024e4a | bellard | /* Return non-zero iff the data at FROM is a valid number in format FMT. */
|
4971 | 48024e4a | bellard | |
4972 | 48024e4a | bellard | int
|
4973 | 48024e4a | bellard | floatformat_is_valid (const struct floatformat *fmt, const char *from) |
4974 | 48024e4a | bellard | { |
4975 | 48024e4a | bellard | return fmt->is_valid (fmt, from);
|
4976 | 48024e4a | bellard | } |
4977 | 48024e4a | bellard | |
4978 | 48024e4a | bellard | |
4979 | 48024e4a | bellard | #ifdef IEEE_DEBUG
|
4980 | 48024e4a | bellard | |
4981 | 48024e4a | bellard | /* This is to be run on a host which uses IEEE floating point. */
|
4982 | 48024e4a | bellard | |
4983 | 48024e4a | bellard | void
|
4984 | 48024e4a | bellard | ieee_test (double n)
|
4985 | 48024e4a | bellard | { |
4986 | 48024e4a | bellard | double result;
|
4987 | 48024e4a | bellard | |
4988 | 48024e4a | bellard | floatformat_to_double (&floatformat_ieee_double_little, (char *) &n,
|
4989 | 48024e4a | bellard | &result); |
4990 | 48024e4a | bellard | if ((n != result && (! isnan (n) || ! isnan (result)))
|
4991 | 48024e4a | bellard | || (n < 0 && result >= 0) |
4992 | 48024e4a | bellard | || (n >= 0 && result < 0)) |
4993 | 48024e4a | bellard | printf ("Differ(to): %.20g -> %.20g\n", n, result);
|
4994 | 48024e4a | bellard | |
4995 | 48024e4a | bellard | floatformat_from_double (&floatformat_ieee_double_little, &n, |
4996 | 48024e4a | bellard | (char *) &result);
|
4997 | 48024e4a | bellard | if ((n != result && (! isnan (n) || ! isnan (result)))
|
4998 | 48024e4a | bellard | || (n < 0 && result >= 0) |
4999 | 48024e4a | bellard | || (n >= 0 && result < 0)) |
5000 | 48024e4a | bellard | printf ("Differ(from): %.20g -> %.20g\n", n, result);
|
5001 | 48024e4a | bellard | |
5002 | 48024e4a | bellard | #if 0
|
5003 | 48024e4a | bellard | {
|
5004 | 48024e4a | bellard | char exten[16];
|
5005 | 48024e4a | bellard | |
5006 | 48024e4a | bellard | floatformat_from_double (&floatformat_m68881_ext, &n, exten);
|
5007 | 48024e4a | bellard | floatformat_to_double (&floatformat_m68881_ext, exten, &result);
|
5008 | 48024e4a | bellard | if (n != result)
|
5009 | 48024e4a | bellard | printf ("Differ(to+from): %.20g -> %.20g\n", n, result);
|
5010 | 48024e4a | bellard | }
|
5011 | 48024e4a | bellard | #endif
|
5012 | 48024e4a | bellard | |
5013 | 48024e4a | bellard | #if IEEE_DEBUG > 1 |
5014 | 48024e4a | bellard | /* This is to be run on a host which uses 68881 format. */
|
5015 | 48024e4a | bellard | { |
5016 | 48024e4a | bellard | long double ex = *(long double *)exten; |
5017 | 48024e4a | bellard | if (ex != n)
|
5018 | 48024e4a | bellard | printf ("Differ(from vs. extended): %.20g\n", n);
|
5019 | 48024e4a | bellard | } |
5020 | 48024e4a | bellard | #endif
|
5021 | 48024e4a | bellard | } |
5022 | 48024e4a | bellard | |
5023 | 48024e4a | bellard | int
|
5024 | 48024e4a | bellard | main (void)
|
5025 | 48024e4a | bellard | { |
5026 | 48024e4a | bellard | ieee_test (0.0); |
5027 | 48024e4a | bellard | ieee_test (0.5); |
5028 | 48024e4a | bellard | ieee_test (256.0); |
5029 | 48024e4a | bellard | ieee_test (0.12345); |
5030 | 48024e4a | bellard | ieee_test (234235.78907234); |
5031 | 48024e4a | bellard | ieee_test (-512.0); |
5032 | 48024e4a | bellard | ieee_test (-0.004321); |
5033 | 48024e4a | bellard | ieee_test (1.2E-70); |
5034 | 48024e4a | bellard | ieee_test (1.2E-316); |
5035 | 48024e4a | bellard | ieee_test (4.9406564584124654E-324); |
5036 | 48024e4a | bellard | ieee_test (- 4.9406564584124654E-324); |
5037 | 48024e4a | bellard | ieee_test (- 0.0); |
5038 | 48024e4a | bellard | ieee_test (- INFINITY); |
5039 | 48024e4a | bellard | ieee_test (- NAN); |
5040 | 48024e4a | bellard | ieee_test (INFINITY); |
5041 | 48024e4a | bellard | ieee_test (NAN); |
5042 | 48024e4a | bellard | return 0; |
5043 | 48024e4a | bellard | } |
5044 | 48024e4a | bellard | #endif
|
5045 | 48024e4a | bellard | /* **** End of floatformat.c */ |