root / hw / usb-uhci.c @ ac0cdda3
History | View | Annotate | Download (30.6 kB)
1 | bb36d470 | bellard | /*
|
---|---|---|---|
2 | bb36d470 | bellard | * USB UHCI controller emulation
|
3 | 5fafdf24 | ths | *
|
4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 54f254f9 | aliguori | * Copyright (c) 2008 Max Krasnyansky
|
7 | 54f254f9 | aliguori | * Magor rewrite of the UHCI data structures parser and frame processor
|
8 | 54f254f9 | aliguori | * Support for fully async operation and multiple outstanding transactions
|
9 | 54f254f9 | aliguori | *
|
10 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
11 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
12 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
|
13 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
14 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
15 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
|
16 | bb36d470 | bellard | *
|
17 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
|
18 | bb36d470 | bellard | * all copies or substantial portions of the Software.
|
19 | bb36d470 | bellard | *
|
20 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
21 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
22 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
23 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
24 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
25 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
26 | bb36d470 | bellard | * THE SOFTWARE.
|
27 | bb36d470 | bellard | */
|
28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "usb.h" |
30 | 87ecb68b | pbrook | #include "pci.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 18e08a55 | Michael S. Tsirkin | #include "usb-uhci.h" |
33 | bb36d470 | bellard | |
34 | bb36d470 | bellard | //#define DEBUG
|
35 | 54f254f9 | aliguori | //#define DEBUG_DUMP_DATA
|
36 | bb36d470 | bellard | |
37 | 96217e31 | ths | #define UHCI_CMD_FGR (1 << 4) |
38 | 96217e31 | ths | #define UHCI_CMD_EGSM (1 << 3) |
39 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
40 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
41 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
42 | bb36d470 | bellard | |
43 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
44 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
45 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
46 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
47 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
48 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
49 | bb36d470 | bellard | |
50 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
51 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
52 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
53 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
54 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
55 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
56 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
57 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
58 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
59 | bb36d470 | bellard | |
60 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
61 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
62 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
63 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
64 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
65 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
66 | bb36d470 | bellard | |
67 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
68 | bb36d470 | bellard | |
69 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
70 | bb36d470 | bellard | |
71 | bb36d470 | bellard | #define NB_PORTS 2 |
72 | bb36d470 | bellard | |
73 | 54f254f9 | aliguori | #ifdef DEBUG
|
74 | d0f2c4c6 | malc | #define DPRINTF printf
|
75 | 54f254f9 | aliguori | |
76 | 0bf9e31a | Blue Swirl | static const char *pid2str(int pid) |
77 | 54f254f9 | aliguori | { |
78 | 54f254f9 | aliguori | switch (pid) {
|
79 | 54f254f9 | aliguori | case USB_TOKEN_SETUP: return "SETUP"; |
80 | 54f254f9 | aliguori | case USB_TOKEN_IN: return "IN"; |
81 | 54f254f9 | aliguori | case USB_TOKEN_OUT: return "OUT"; |
82 | 54f254f9 | aliguori | } |
83 | 54f254f9 | aliguori | return "?"; |
84 | 54f254f9 | aliguori | } |
85 | 54f254f9 | aliguori | |
86 | 54f254f9 | aliguori | #else
|
87 | d0f2c4c6 | malc | #define DPRINTF(...)
|
88 | 54f254f9 | aliguori | #endif
|
89 | 54f254f9 | aliguori | |
90 | 54f254f9 | aliguori | #ifdef DEBUG_DUMP_DATA
|
91 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) |
92 | 54f254f9 | aliguori | { |
93 | 54f254f9 | aliguori | int i;
|
94 | 54f254f9 | aliguori | |
95 | 54f254f9 | aliguori | printf("uhci: data: ");
|
96 | 54f254f9 | aliguori | for(i = 0; i < len; i++) |
97 | 54f254f9 | aliguori | printf(" %02x", data[i]);
|
98 | 54f254f9 | aliguori | printf("\n");
|
99 | 54f254f9 | aliguori | } |
100 | 54f254f9 | aliguori | #else
|
101 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) {} |
102 | 54f254f9 | aliguori | #endif
|
103 | 54f254f9 | aliguori | |
104 | 54f254f9 | aliguori | /*
|
105 | 54f254f9 | aliguori | * Pending async transaction.
|
106 | 54f254f9 | aliguori | * 'packet' must be the first field because completion
|
107 | 54f254f9 | aliguori | * handler does "(UHCIAsync *) pkt" cast.
|
108 | 54f254f9 | aliguori | */
|
109 | 54f254f9 | aliguori | typedef struct UHCIAsync { |
110 | 54f254f9 | aliguori | USBPacket packet; |
111 | 54f254f9 | aliguori | struct UHCIAsync *next;
|
112 | 54f254f9 | aliguori | uint32_t td; |
113 | 54f254f9 | aliguori | uint32_t token; |
114 | 54f254f9 | aliguori | int8_t valid; |
115 | 8e65b7c0 | David S. Ahern | uint8_t isoc; |
116 | 54f254f9 | aliguori | uint8_t done; |
117 | 54f254f9 | aliguori | uint8_t buffer[2048];
|
118 | 54f254f9 | aliguori | } UHCIAsync; |
119 | 54f254f9 | aliguori | |
120 | bb36d470 | bellard | typedef struct UHCIPort { |
121 | bb36d470 | bellard | USBPort port; |
122 | bb36d470 | bellard | uint16_t ctrl; |
123 | bb36d470 | bellard | } UHCIPort; |
124 | bb36d470 | bellard | |
125 | bb36d470 | bellard | typedef struct UHCIState { |
126 | bb36d470 | bellard | PCIDevice dev; |
127 | b2317837 | Gerd Hoffmann | USBBus bus; |
128 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
|
129 | bb36d470 | bellard | uint16_t status; |
130 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
|
131 | bb36d470 | bellard | uint16_t frnum; /* frame number */
|
132 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
|
133 | bb36d470 | bellard | uint8_t sof_timing; |
134 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
|
135 | 8e65b7c0 | David S. Ahern | int64_t expire_time; |
136 | bb36d470 | bellard | QEMUTimer *frame_timer; |
137 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
138 | 4d611c9a | pbrook | |
139 | 4d611c9a | pbrook | /* Interrupts that should be raised at the end of the current frame. */
|
140 | 4d611c9a | pbrook | uint32_t pending_int_mask; |
141 | 54f254f9 | aliguori | |
142 | 54f254f9 | aliguori | /* Active packets */
|
143 | 54f254f9 | aliguori | UHCIAsync *async_pending; |
144 | 54f254f9 | aliguori | UHCIAsync *async_pool; |
145 | 64e58fe5 | Juan Quintela | uint8_t num_ports_vmstate; |
146 | bb36d470 | bellard | } UHCIState; |
147 | bb36d470 | bellard | |
148 | bb36d470 | bellard | typedef struct UHCI_TD { |
149 | bb36d470 | bellard | uint32_t link; |
150 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
|
151 | bb36d470 | bellard | uint32_t token; |
152 | bb36d470 | bellard | uint32_t buffer; |
153 | bb36d470 | bellard | } UHCI_TD; |
154 | bb36d470 | bellard | |
155 | bb36d470 | bellard | typedef struct UHCI_QH { |
156 | bb36d470 | bellard | uint32_t link; |
157 | bb36d470 | bellard | uint32_t el_link; |
158 | bb36d470 | bellard | } UHCI_QH; |
159 | bb36d470 | bellard | |
160 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_alloc(UHCIState *s)
|
161 | 54f254f9 | aliguori | { |
162 | 54f254f9 | aliguori | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
|
163 | 487414f1 | aliguori | |
164 | 487414f1 | aliguori | memset(&async->packet, 0, sizeof(async->packet)); |
165 | 487414f1 | aliguori | async->valid = 0;
|
166 | 487414f1 | aliguori | async->td = 0;
|
167 | 487414f1 | aliguori | async->token = 0;
|
168 | 487414f1 | aliguori | async->done = 0;
|
169 | 8e65b7c0 | David S. Ahern | async->isoc = 0;
|
170 | 487414f1 | aliguori | async->next = NULL;
|
171 | 54f254f9 | aliguori | |
172 | 54f254f9 | aliguori | return async;
|
173 | 54f254f9 | aliguori | } |
174 | 54f254f9 | aliguori | |
175 | 54f254f9 | aliguori | static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
176 | 54f254f9 | aliguori | { |
177 | 54f254f9 | aliguori | qemu_free(async); |
178 | 54f254f9 | aliguori | } |
179 | 54f254f9 | aliguori | |
180 | 54f254f9 | aliguori | static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
181 | 54f254f9 | aliguori | { |
182 | 54f254f9 | aliguori | async->next = s->async_pending; |
183 | 54f254f9 | aliguori | s->async_pending = async; |
184 | 54f254f9 | aliguori | } |
185 | 54f254f9 | aliguori | |
186 | 54f254f9 | aliguori | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
187 | 54f254f9 | aliguori | { |
188 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
189 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
190 | 54f254f9 | aliguori | |
191 | 54f254f9 | aliguori | while (curr) {
|
192 | 54f254f9 | aliguori | if (curr == async) {
|
193 | 54f254f9 | aliguori | *prev = curr->next; |
194 | 54f254f9 | aliguori | return;
|
195 | 54f254f9 | aliguori | } |
196 | 54f254f9 | aliguori | |
197 | 54f254f9 | aliguori | prev = &curr->next; |
198 | 54f254f9 | aliguori | curr = curr->next; |
199 | 54f254f9 | aliguori | } |
200 | 54f254f9 | aliguori | } |
201 | 54f254f9 | aliguori | |
202 | 54f254f9 | aliguori | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
203 | 54f254f9 | aliguori | { |
204 | d0f2c4c6 | malc | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
|
205 | 54f254f9 | aliguori | async->td, async->token, async->done); |
206 | 54f254f9 | aliguori | |
207 | 54f254f9 | aliguori | if (!async->done)
|
208 | 54f254f9 | aliguori | usb_cancel_packet(&async->packet); |
209 | 54f254f9 | aliguori | uhci_async_free(s, async); |
210 | 54f254f9 | aliguori | } |
211 | 54f254f9 | aliguori | |
212 | 54f254f9 | aliguori | /*
|
213 | 54f254f9 | aliguori | * Mark all outstanding async packets as invalid.
|
214 | 54f254f9 | aliguori | * This is used for canceling them when TDs are removed by the HCD.
|
215 | 54f254f9 | aliguori | */
|
216 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
|
217 | 54f254f9 | aliguori | { |
218 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
219 | 54f254f9 | aliguori | |
220 | 54f254f9 | aliguori | while (async) {
|
221 | 54f254f9 | aliguori | async->valid--; |
222 | 54f254f9 | aliguori | async = async->next; |
223 | 54f254f9 | aliguori | } |
224 | 54f254f9 | aliguori | return NULL; |
225 | 54f254f9 | aliguori | } |
226 | 54f254f9 | aliguori | |
227 | 54f254f9 | aliguori | /*
|
228 | 54f254f9 | aliguori | * Cancel async packets that are no longer valid
|
229 | 54f254f9 | aliguori | */
|
230 | 54f254f9 | aliguori | static void uhci_async_validate_end(UHCIState *s) |
231 | 54f254f9 | aliguori | { |
232 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
233 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
234 | 54f254f9 | aliguori | UHCIAsync *next; |
235 | 54f254f9 | aliguori | |
236 | 54f254f9 | aliguori | while (curr) {
|
237 | 54f254f9 | aliguori | if (curr->valid > 0) { |
238 | 54f254f9 | aliguori | prev = &curr->next; |
239 | 54f254f9 | aliguori | curr = curr->next; |
240 | 54f254f9 | aliguori | continue;
|
241 | 54f254f9 | aliguori | } |
242 | 54f254f9 | aliguori | |
243 | 54f254f9 | aliguori | next = curr->next; |
244 | 54f254f9 | aliguori | |
245 | 54f254f9 | aliguori | /* Unlink */
|
246 | 54f254f9 | aliguori | *prev = next; |
247 | 54f254f9 | aliguori | |
248 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
249 | 54f254f9 | aliguori | |
250 | 54f254f9 | aliguori | curr = next; |
251 | 54f254f9 | aliguori | } |
252 | 54f254f9 | aliguori | } |
253 | 54f254f9 | aliguori | |
254 | 54f254f9 | aliguori | static void uhci_async_cancel_all(UHCIState *s) |
255 | 54f254f9 | aliguori | { |
256 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
257 | 54f254f9 | aliguori | UHCIAsync *next; |
258 | 54f254f9 | aliguori | |
259 | 54f254f9 | aliguori | while (curr) {
|
260 | 54f254f9 | aliguori | next = curr->next; |
261 | 54f254f9 | aliguori | |
262 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
263 | 54f254f9 | aliguori | |
264 | 54f254f9 | aliguori | curr = next; |
265 | 54f254f9 | aliguori | } |
266 | 54f254f9 | aliguori | |
267 | 54f254f9 | aliguori | s->async_pending = NULL;
|
268 | 54f254f9 | aliguori | } |
269 | 54f254f9 | aliguori | |
270 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
|
271 | 54f254f9 | aliguori | { |
272 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
273 | e8ee3c72 | aurel32 | UHCIAsync *match = NULL;
|
274 | e8ee3c72 | aurel32 | int count = 0; |
275 | e8ee3c72 | aurel32 | |
276 | e8ee3c72 | aurel32 | /*
|
277 | e8ee3c72 | aurel32 | * We're looking for the best match here. ie both td addr and token.
|
278 | e8ee3c72 | aurel32 | * Otherwise we return last good match. ie just token.
|
279 | e8ee3c72 | aurel32 | * It's ok to match just token because it identifies the transaction
|
280 | e8ee3c72 | aurel32 | * rather well, token includes: device addr, endpoint, size, etc.
|
281 | e8ee3c72 | aurel32 | *
|
282 | e8ee3c72 | aurel32 | * Also since we queue async transactions in reverse order by returning
|
283 | e8ee3c72 | aurel32 | * last good match we restores the order.
|
284 | e8ee3c72 | aurel32 | *
|
285 | e8ee3c72 | aurel32 | * It's expected that we wont have a ton of outstanding transactions.
|
286 | e8ee3c72 | aurel32 | * If we ever do we'd want to optimize this algorithm.
|
287 | e8ee3c72 | aurel32 | */
|
288 | 54f254f9 | aliguori | |
289 | 54f254f9 | aliguori | while (async) {
|
290 | e8ee3c72 | aurel32 | if (async->token == token) {
|
291 | e8ee3c72 | aurel32 | /* Good match */
|
292 | e8ee3c72 | aurel32 | match = async; |
293 | e8ee3c72 | aurel32 | |
294 | e8ee3c72 | aurel32 | if (async->td == addr) {
|
295 | e8ee3c72 | aurel32 | /* Best match */
|
296 | e8ee3c72 | aurel32 | break;
|
297 | 54f254f9 | aliguori | } |
298 | 54f254f9 | aliguori | } |
299 | 54f254f9 | aliguori | |
300 | 54f254f9 | aliguori | async = async->next; |
301 | e8ee3c72 | aurel32 | count++; |
302 | 54f254f9 | aliguori | } |
303 | e8ee3c72 | aurel32 | |
304 | e8ee3c72 | aurel32 | if (count > 64) |
305 | e8ee3c72 | aurel32 | fprintf(stderr, "uhci: warning lots of async transactions\n");
|
306 | e8ee3c72 | aurel32 | |
307 | e8ee3c72 | aurel32 | return match;
|
308 | 54f254f9 | aliguori | } |
309 | 54f254f9 | aliguori | |
310 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev); |
311 | bb36d470 | bellard | |
312 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
313 | bb36d470 | bellard | { |
314 | bb36d470 | bellard | int level;
|
315 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
316 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
317 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
318 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
319 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
320 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
321 | bb36d470 | bellard | level = 1;
|
322 | bb36d470 | bellard | } else {
|
323 | bb36d470 | bellard | level = 0;
|
324 | bb36d470 | bellard | } |
325 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[3], level);
|
326 | bb36d470 | bellard | } |
327 | bb36d470 | bellard | |
328 | c8075ac3 | Gleb Natapov | static void uhci_reset(void *opaque) |
329 | bb36d470 | bellard | { |
330 | c8075ac3 | Gleb Natapov | UHCIState *s = opaque; |
331 | bb36d470 | bellard | uint8_t *pci_conf; |
332 | bb36d470 | bellard | int i;
|
333 | bb36d470 | bellard | UHCIPort *port; |
334 | bb36d470 | bellard | |
335 | d0f2c4c6 | malc | DPRINTF("uhci: full reset\n");
|
336 | 6f382b5e | aliguori | |
337 | bb36d470 | bellard | pci_conf = s->dev.config; |
338 | bb36d470 | bellard | |
339 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
340 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
341 | bb36d470 | bellard | s->cmd = 0;
|
342 | bb36d470 | bellard | s->status = 0;
|
343 | bb36d470 | bellard | s->status2 = 0;
|
344 | bb36d470 | bellard | s->intr = 0;
|
345 | bb36d470 | bellard | s->fl_base_addr = 0;
|
346 | bb36d470 | bellard | s->sof_timing = 64;
|
347 | 54f254f9 | aliguori | |
348 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
349 | bb36d470 | bellard | port = &s->ports[i]; |
350 | bb36d470 | bellard | port->ctrl = 0x0080;
|
351 | a594cfbf | bellard | if (port->port.dev)
|
352 | a594cfbf | bellard | uhci_attach(&port->port, port->port.dev); |
353 | bb36d470 | bellard | } |
354 | 54f254f9 | aliguori | |
355 | 54f254f9 | aliguori | uhci_async_cancel_all(s); |
356 | bb36d470 | bellard | } |
357 | bb36d470 | bellard | |
358 | 817afc61 | Juan Quintela | static void uhci_pre_save(void *opaque) |
359 | b9dc033c | balrog | { |
360 | b9dc033c | balrog | UHCIState *s = opaque; |
361 | b9dc033c | balrog | |
362 | 6f382b5e | aliguori | uhci_async_cancel_all(s); |
363 | b9dc033c | balrog | } |
364 | b9dc033c | balrog | |
365 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci_port = { |
366 | 817afc61 | Juan Quintela | .name = "uhci port",
|
367 | 817afc61 | Juan Quintela | .version_id = 1,
|
368 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
|
369 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
|
370 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
371 | 817afc61 | Juan Quintela | VMSTATE_UINT16(ctrl, UHCIPort), |
372 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
373 | 817afc61 | Juan Quintela | } |
374 | 817afc61 | Juan Quintela | }; |
375 | 817afc61 | Juan Quintela | |
376 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci = { |
377 | 817afc61 | Juan Quintela | .name = "uhci",
|
378 | 6881dd5f | TeLeMan | .version_id = 2,
|
379 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
|
380 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
|
381 | 817afc61 | Juan Quintela | .pre_save = uhci_pre_save, |
382 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
383 | 817afc61 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, UHCIState), |
384 | 817afc61 | Juan Quintela | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
385 | 817afc61 | Juan Quintela | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
386 | 817afc61 | Juan Quintela | vmstate_uhci_port, UHCIPort), |
387 | 817afc61 | Juan Quintela | VMSTATE_UINT16(cmd, UHCIState), |
388 | 817afc61 | Juan Quintela | VMSTATE_UINT16(status, UHCIState), |
389 | 817afc61 | Juan Quintela | VMSTATE_UINT16(intr, UHCIState), |
390 | 817afc61 | Juan Quintela | VMSTATE_UINT16(frnum, UHCIState), |
391 | 817afc61 | Juan Quintela | VMSTATE_UINT32(fl_base_addr, UHCIState), |
392 | 817afc61 | Juan Quintela | VMSTATE_UINT8(sof_timing, UHCIState), |
393 | 817afc61 | Juan Quintela | VMSTATE_UINT8(status2, UHCIState), |
394 | 817afc61 | Juan Quintela | VMSTATE_TIMER(frame_timer, UHCIState), |
395 | 6881dd5f | TeLeMan | VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
396 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
397 | 817afc61 | Juan Quintela | } |
398 | 817afc61 | Juan Quintela | }; |
399 | b9dc033c | balrog | |
400 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
401 | bb36d470 | bellard | { |
402 | bb36d470 | bellard | UHCIState *s = opaque; |
403 | 3b46e624 | ths | |
404 | bb36d470 | bellard | addr &= 0x1f;
|
405 | bb36d470 | bellard | switch(addr) {
|
406 | bb36d470 | bellard | case 0x0c: |
407 | bb36d470 | bellard | s->sof_timing = val; |
408 | bb36d470 | bellard | break;
|
409 | bb36d470 | bellard | } |
410 | bb36d470 | bellard | } |
411 | bb36d470 | bellard | |
412 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
413 | bb36d470 | bellard | { |
414 | bb36d470 | bellard | UHCIState *s = opaque; |
415 | bb36d470 | bellard | uint32_t val; |
416 | bb36d470 | bellard | |
417 | bb36d470 | bellard | addr &= 0x1f;
|
418 | bb36d470 | bellard | switch(addr) {
|
419 | bb36d470 | bellard | case 0x0c: |
420 | bb36d470 | bellard | val = s->sof_timing; |
421 | d80cfb3f | pbrook | break;
|
422 | bb36d470 | bellard | default:
|
423 | bb36d470 | bellard | val = 0xff;
|
424 | bb36d470 | bellard | break;
|
425 | bb36d470 | bellard | } |
426 | bb36d470 | bellard | return val;
|
427 | bb36d470 | bellard | } |
428 | bb36d470 | bellard | |
429 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
430 | bb36d470 | bellard | { |
431 | bb36d470 | bellard | UHCIState *s = opaque; |
432 | 3b46e624 | ths | |
433 | bb36d470 | bellard | addr &= 0x1f;
|
434 | d0f2c4c6 | malc | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
435 | 54f254f9 | aliguori | |
436 | bb36d470 | bellard | switch(addr) {
|
437 | bb36d470 | bellard | case 0x00: |
438 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
439 | bb36d470 | bellard | /* start frame processing */
|
440 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
441 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
442 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
443 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
444 | bb36d470 | bellard | } |
445 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
|
446 | bb36d470 | bellard | UHCIPort *port; |
447 | bb36d470 | bellard | USBDevice *dev; |
448 | bb36d470 | bellard | int i;
|
449 | bb36d470 | bellard | |
450 | bb36d470 | bellard | /* send reset on the USB bus */
|
451 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
452 | bb36d470 | bellard | port = &s->ports[i]; |
453 | a594cfbf | bellard | dev = port->port.dev; |
454 | bb36d470 | bellard | if (dev) {
|
455 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
456 | bb36d470 | bellard | } |
457 | bb36d470 | bellard | } |
458 | bb36d470 | bellard | uhci_reset(s); |
459 | bb36d470 | bellard | return;
|
460 | bb36d470 | bellard | } |
461 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
|
462 | bb36d470 | bellard | uhci_reset(s); |
463 | bb36d470 | bellard | return;
|
464 | bb36d470 | bellard | } |
465 | bb36d470 | bellard | s->cmd = val; |
466 | bb36d470 | bellard | break;
|
467 | bb36d470 | bellard | case 0x02: |
468 | bb36d470 | bellard | s->status &= ~val; |
469 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
|
470 | bb36d470 | bellard | register to distinguish between IOC and SPD */
|
471 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
|
472 | bb36d470 | bellard | s->status2 = 0;
|
473 | bb36d470 | bellard | uhci_update_irq(s); |
474 | bb36d470 | bellard | break;
|
475 | bb36d470 | bellard | case 0x04: |
476 | bb36d470 | bellard | s->intr = val; |
477 | bb36d470 | bellard | uhci_update_irq(s); |
478 | bb36d470 | bellard | break;
|
479 | bb36d470 | bellard | case 0x06: |
480 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
|
481 | bb36d470 | bellard | s->frnum = val & 0x7ff;
|
482 | bb36d470 | bellard | break;
|
483 | bb36d470 | bellard | case 0x10 ... 0x1f: |
484 | bb36d470 | bellard | { |
485 | bb36d470 | bellard | UHCIPort *port; |
486 | bb36d470 | bellard | USBDevice *dev; |
487 | bb36d470 | bellard | int n;
|
488 | bb36d470 | bellard | |
489 | bb36d470 | bellard | n = (addr >> 1) & 7; |
490 | bb36d470 | bellard | if (n >= NB_PORTS)
|
491 | bb36d470 | bellard | return;
|
492 | bb36d470 | bellard | port = &s->ports[n]; |
493 | a594cfbf | bellard | dev = port->port.dev; |
494 | bb36d470 | bellard | if (dev) {
|
495 | bb36d470 | bellard | /* port reset */
|
496 | 5fafdf24 | ths | if ( (val & UHCI_PORT_RESET) &&
|
497 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
498 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
499 | bb36d470 | bellard | } |
500 | bb36d470 | bellard | } |
501 | bb36d470 | bellard | port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
502 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
|
503 | bb36d470 | bellard | port->ctrl &= ~(val & 0x000a);
|
504 | bb36d470 | bellard | } |
505 | bb36d470 | bellard | break;
|
506 | bb36d470 | bellard | } |
507 | bb36d470 | bellard | } |
508 | bb36d470 | bellard | |
509 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
510 | bb36d470 | bellard | { |
511 | bb36d470 | bellard | UHCIState *s = opaque; |
512 | bb36d470 | bellard | uint32_t val; |
513 | bb36d470 | bellard | |
514 | bb36d470 | bellard | addr &= 0x1f;
|
515 | bb36d470 | bellard | switch(addr) {
|
516 | bb36d470 | bellard | case 0x00: |
517 | bb36d470 | bellard | val = s->cmd; |
518 | bb36d470 | bellard | break;
|
519 | bb36d470 | bellard | case 0x02: |
520 | bb36d470 | bellard | val = s->status; |
521 | bb36d470 | bellard | break;
|
522 | bb36d470 | bellard | case 0x04: |
523 | bb36d470 | bellard | val = s->intr; |
524 | bb36d470 | bellard | break;
|
525 | bb36d470 | bellard | case 0x06: |
526 | bb36d470 | bellard | val = s->frnum; |
527 | bb36d470 | bellard | break;
|
528 | bb36d470 | bellard | case 0x10 ... 0x1f: |
529 | bb36d470 | bellard | { |
530 | bb36d470 | bellard | UHCIPort *port; |
531 | bb36d470 | bellard | int n;
|
532 | bb36d470 | bellard | n = (addr >> 1) & 7; |
533 | 5fafdf24 | ths | if (n >= NB_PORTS)
|
534 | bb36d470 | bellard | goto read_default;
|
535 | bb36d470 | bellard | port = &s->ports[n]; |
536 | bb36d470 | bellard | val = port->ctrl; |
537 | bb36d470 | bellard | } |
538 | bb36d470 | bellard | break;
|
539 | bb36d470 | bellard | default:
|
540 | bb36d470 | bellard | read_default:
|
541 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
542 | bb36d470 | bellard | break;
|
543 | bb36d470 | bellard | } |
544 | 54f254f9 | aliguori | |
545 | d0f2c4c6 | malc | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
546 | 54f254f9 | aliguori | |
547 | bb36d470 | bellard | return val;
|
548 | bb36d470 | bellard | } |
549 | bb36d470 | bellard | |
550 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
551 | bb36d470 | bellard | { |
552 | bb36d470 | bellard | UHCIState *s = opaque; |
553 | bb36d470 | bellard | |
554 | bb36d470 | bellard | addr &= 0x1f;
|
555 | d0f2c4c6 | malc | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
556 | 54f254f9 | aliguori | |
557 | bb36d470 | bellard | switch(addr) {
|
558 | bb36d470 | bellard | case 0x08: |
559 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
|
560 | bb36d470 | bellard | break;
|
561 | bb36d470 | bellard | } |
562 | bb36d470 | bellard | } |
563 | bb36d470 | bellard | |
564 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
565 | bb36d470 | bellard | { |
566 | bb36d470 | bellard | UHCIState *s = opaque; |
567 | bb36d470 | bellard | uint32_t val; |
568 | bb36d470 | bellard | |
569 | bb36d470 | bellard | addr &= 0x1f;
|
570 | bb36d470 | bellard | switch(addr) {
|
571 | bb36d470 | bellard | case 0x08: |
572 | bb36d470 | bellard | val = s->fl_base_addr; |
573 | bb36d470 | bellard | break;
|
574 | bb36d470 | bellard | default:
|
575 | bb36d470 | bellard | val = 0xffffffff;
|
576 | bb36d470 | bellard | break;
|
577 | bb36d470 | bellard | } |
578 | bb36d470 | bellard | return val;
|
579 | bb36d470 | bellard | } |
580 | bb36d470 | bellard | |
581 | 96217e31 | ths | /* signal resume if controller suspended */
|
582 | 96217e31 | ths | static void uhci_resume (void *opaque) |
583 | 96217e31 | ths | { |
584 | 96217e31 | ths | UHCIState *s = (UHCIState *)opaque; |
585 | 96217e31 | ths | |
586 | 96217e31 | ths | if (!s)
|
587 | 96217e31 | ths | return;
|
588 | 96217e31 | ths | |
589 | 96217e31 | ths | if (s->cmd & UHCI_CMD_EGSM) {
|
590 | 96217e31 | ths | s->cmd |= UHCI_CMD_FGR; |
591 | 96217e31 | ths | s->status |= UHCI_STS_RD; |
592 | 96217e31 | ths | uhci_update_irq(s); |
593 | 96217e31 | ths | } |
594 | 96217e31 | ths | } |
595 | 96217e31 | ths | |
596 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev) |
597 | bb36d470 | bellard | { |
598 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
599 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
600 | bb36d470 | bellard | |
601 | bb36d470 | bellard | if (dev) {
|
602 | a594cfbf | bellard | if (port->port.dev) {
|
603 | bb36d470 | bellard | usb_attach(port1, NULL);
|
604 | bb36d470 | bellard | } |
605 | bb36d470 | bellard | /* set connect status */
|
606 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
607 | 61064870 | pbrook | |
608 | bb36d470 | bellard | /* update speed */
|
609 | bb36d470 | bellard | if (dev->speed == USB_SPEED_LOW)
|
610 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_LSDA; |
611 | bb36d470 | bellard | else
|
612 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_LSDA; |
613 | 96217e31 | ths | |
614 | 96217e31 | ths | uhci_resume(s); |
615 | 96217e31 | ths | |
616 | a594cfbf | bellard | port->port.dev = dev; |
617 | bb36d470 | bellard | /* send the attach message */
|
618 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_ATTACH); |
619 | bb36d470 | bellard | } else {
|
620 | bb36d470 | bellard | /* set connect status */
|
621 | 61064870 | pbrook | if (port->ctrl & UHCI_PORT_CCS) {
|
622 | 61064870 | pbrook | port->ctrl &= ~UHCI_PORT_CCS; |
623 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CSC; |
624 | bb36d470 | bellard | } |
625 | bb36d470 | bellard | /* disable port */
|
626 | bb36d470 | bellard | if (port->ctrl & UHCI_PORT_EN) {
|
627 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_EN; |
628 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_ENC; |
629 | bb36d470 | bellard | } |
630 | 96217e31 | ths | |
631 | 96217e31 | ths | uhci_resume(s); |
632 | 96217e31 | ths | |
633 | a594cfbf | bellard | dev = port->port.dev; |
634 | bb36d470 | bellard | if (dev) {
|
635 | bb36d470 | bellard | /* send the detach message */
|
636 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_DETACH); |
637 | bb36d470 | bellard | } |
638 | a594cfbf | bellard | port->port.dev = NULL;
|
639 | bb36d470 | bellard | } |
640 | bb36d470 | bellard | } |
641 | bb36d470 | bellard | |
642 | 4d611c9a | pbrook | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
643 | bb36d470 | bellard | { |
644 | bb36d470 | bellard | int i, ret;
|
645 | bb36d470 | bellard | |
646 | d0f2c4c6 | malc | DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
647 | 54f254f9 | aliguori | pid2str(p->pid), p->devaddr, p->devep, p->len); |
648 | 5d808245 | aurel32 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
649 | 54f254f9 | aliguori | dump_data(p->data, p->len); |
650 | 54f254f9 | aliguori | |
651 | 54f254f9 | aliguori | ret = USB_RET_NODEV; |
652 | 54f254f9 | aliguori | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
653 | 54f254f9 | aliguori | UHCIPort *port = &s->ports[i]; |
654 | 54f254f9 | aliguori | USBDevice *dev = port->port.dev; |
655 | 54f254f9 | aliguori | |
656 | 54f254f9 | aliguori | if (dev && (port->ctrl & UHCI_PORT_EN))
|
657 | 806b6024 | Gerd Hoffmann | ret = dev->info->handle_packet(dev, p); |
658 | bb36d470 | bellard | } |
659 | 54f254f9 | aliguori | |
660 | d0f2c4c6 | malc | DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
661 | 54f254f9 | aliguori | if (p->pid == USB_TOKEN_IN && ret > 0) |
662 | 54f254f9 | aliguori | dump_data(p->data, ret); |
663 | 54f254f9 | aliguori | |
664 | 54f254f9 | aliguori | return ret;
|
665 | bb36d470 | bellard | } |
666 | bb36d470 | bellard | |
667 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket * packet, void *opaque); |
668 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s); |
669 | 4d611c9a | pbrook | |
670 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
671 | bb36d470 | bellard | 0 if TD successful
|
672 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
673 | bb36d470 | bellard | */
|
674 | 54f254f9 | aliguori | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
675 | bb36d470 | bellard | { |
676 | 54f254f9 | aliguori | int len = 0, max_len, err, ret; |
677 | bb36d470 | bellard | uint8_t pid; |
678 | bb36d470 | bellard | |
679 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
680 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
681 | 54f254f9 | aliguori | |
682 | 54f254f9 | aliguori | ret = async->packet.len; |
683 | 54f254f9 | aliguori | |
684 | 54f254f9 | aliguori | if (td->ctrl & TD_CTRL_IOS)
|
685 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
686 | bb36d470 | bellard | |
687 | 54f254f9 | aliguori | if (ret < 0) |
688 | 54f254f9 | aliguori | goto out;
|
689 | b9dc033c | balrog | |
690 | 54f254f9 | aliguori | len = async->packet.len; |
691 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
692 | 54f254f9 | aliguori | |
693 | 54f254f9 | aliguori | /* The NAK bit may have been set by a previous frame, so clear it
|
694 | 54f254f9 | aliguori | here. The docs are somewhat unclear, but win2k relies on this
|
695 | 54f254f9 | aliguori | behavior. */
|
696 | 54f254f9 | aliguori | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
697 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
698 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
699 | 54f254f9 | aliguori | |
700 | 54f254f9 | aliguori | if (pid == USB_TOKEN_IN) {
|
701 | 54f254f9 | aliguori | if (len > max_len) {
|
702 | 54f254f9 | aliguori | ret = USB_RET_BABBLE; |
703 | 54f254f9 | aliguori | goto out;
|
704 | 4d611c9a | pbrook | } |
705 | b9dc033c | balrog | |
706 | 54f254f9 | aliguori | if (len > 0) { |
707 | 54f254f9 | aliguori | /* write the data back */
|
708 | 54f254f9 | aliguori | cpu_physical_memory_write(td->buffer, async->buffer, len); |
709 | 54f254f9 | aliguori | } |
710 | 54f254f9 | aliguori | |
711 | 54f254f9 | aliguori | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
712 | bb36d470 | bellard | *int_mask |= 0x02;
|
713 | bb36d470 | bellard | /* short packet: do not update QH */
|
714 | d0f2c4c6 | malc | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
715 | bb36d470 | bellard | return 1; |
716 | bb36d470 | bellard | } |
717 | 54f254f9 | aliguori | } |
718 | 54f254f9 | aliguori | |
719 | 54f254f9 | aliguori | /* success */
|
720 | 54f254f9 | aliguori | return 0; |
721 | 54f254f9 | aliguori | |
722 | 54f254f9 | aliguori | out:
|
723 | 54f254f9 | aliguori | switch(ret) {
|
724 | 54f254f9 | aliguori | case USB_RET_STALL:
|
725 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_STALL; |
726 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
727 | 54f254f9 | aliguori | return 1; |
728 | 54f254f9 | aliguori | |
729 | 54f254f9 | aliguori | case USB_RET_BABBLE:
|
730 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
731 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
732 | 54f254f9 | aliguori | /* frame interrupted */
|
733 | 54f254f9 | aliguori | return -1; |
734 | 54f254f9 | aliguori | |
735 | 54f254f9 | aliguori | case USB_RET_NAK:
|
736 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_NAK; |
737 | 54f254f9 | aliguori | if (pid == USB_TOKEN_SETUP)
|
738 | 54f254f9 | aliguori | break;
|
739 | 54f254f9 | aliguori | return 1; |
740 | 54f254f9 | aliguori | |
741 | 54f254f9 | aliguori | case USB_RET_NODEV:
|
742 | 54f254f9 | aliguori | default:
|
743 | 54f254f9 | aliguori | break;
|
744 | 54f254f9 | aliguori | } |
745 | 54f254f9 | aliguori | |
746 | 54f254f9 | aliguori | /* Retry the TD if error count is not zero */
|
747 | 54f254f9 | aliguori | |
748 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_TIMEOUT; |
749 | 54f254f9 | aliguori | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
750 | 54f254f9 | aliguori | if (err != 0) { |
751 | 54f254f9 | aliguori | err--; |
752 | 54f254f9 | aliguori | if (err == 0) { |
753 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
754 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBERR; |
755 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
756 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
757 | 54f254f9 | aliguori | uhci_update_irq(s); |
758 | bb36d470 | bellard | } |
759 | bb36d470 | bellard | } |
760 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
761 | 54f254f9 | aliguori | (err << TD_CTRL_ERROR_SHIFT); |
762 | 54f254f9 | aliguori | return 1; |
763 | bb36d470 | bellard | } |
764 | bb36d470 | bellard | |
765 | 54f254f9 | aliguori | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
766 | 54f254f9 | aliguori | { |
767 | 54f254f9 | aliguori | UHCIAsync *async; |
768 | 5d808245 | aurel32 | int len = 0, max_len; |
769 | 8e65b7c0 | David S. Ahern | uint8_t pid, isoc; |
770 | 8e65b7c0 | David S. Ahern | uint32_t token; |
771 | 54f254f9 | aliguori | |
772 | 54f254f9 | aliguori | /* Is active ? */
|
773 | 54f254f9 | aliguori | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
774 | 54f254f9 | aliguori | return 1; |
775 | 54f254f9 | aliguori | |
776 | 8e65b7c0 | David S. Ahern | /* token field is not unique for isochronous requests,
|
777 | 8e65b7c0 | David S. Ahern | * so use the destination buffer
|
778 | 8e65b7c0 | David S. Ahern | */
|
779 | 8e65b7c0 | David S. Ahern | if (td->ctrl & TD_CTRL_IOS) {
|
780 | 8e65b7c0 | David S. Ahern | token = td->buffer; |
781 | 8e65b7c0 | David S. Ahern | isoc = 1;
|
782 | 8e65b7c0 | David S. Ahern | } else {
|
783 | 8e65b7c0 | David S. Ahern | token = td->token; |
784 | 8e65b7c0 | David S. Ahern | isoc = 0;
|
785 | 8e65b7c0 | David S. Ahern | } |
786 | 8e65b7c0 | David S. Ahern | |
787 | 8e65b7c0 | David S. Ahern | async = uhci_async_find_td(s, addr, token); |
788 | 54f254f9 | aliguori | if (async) {
|
789 | 54f254f9 | aliguori | /* Already submitted */
|
790 | a145ea51 | aliguori | async->valid = 32;
|
791 | 54f254f9 | aliguori | |
792 | 54f254f9 | aliguori | if (!async->done)
|
793 | 54f254f9 | aliguori | return 1; |
794 | 54f254f9 | aliguori | |
795 | 54f254f9 | aliguori | uhci_async_unlink(s, async); |
796 | 54f254f9 | aliguori | goto done;
|
797 | 54f254f9 | aliguori | } |
798 | 54f254f9 | aliguori | |
799 | 54f254f9 | aliguori | /* Allocate new packet */
|
800 | 54f254f9 | aliguori | async = uhci_async_alloc(s); |
801 | 54f254f9 | aliguori | if (!async)
|
802 | 54f254f9 | aliguori | return 1; |
803 | 54f254f9 | aliguori | |
804 | 8e65b7c0 | David S. Ahern | /* valid needs to be large enough to handle 10 frame delay
|
805 | 8e65b7c0 | David S. Ahern | * for initial isochronous requests
|
806 | 8e65b7c0 | David S. Ahern | */
|
807 | 8e65b7c0 | David S. Ahern | async->valid = 32;
|
808 | 54f254f9 | aliguori | async->td = addr; |
809 | 8e65b7c0 | David S. Ahern | async->token = token; |
810 | 8e65b7c0 | David S. Ahern | async->isoc = isoc; |
811 | 54f254f9 | aliguori | |
812 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
813 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
814 | 54f254f9 | aliguori | |
815 | 54f254f9 | aliguori | async->packet.pid = pid; |
816 | 54f254f9 | aliguori | async->packet.devaddr = (td->token >> 8) & 0x7f; |
817 | 54f254f9 | aliguori | async->packet.devep = (td->token >> 15) & 0xf; |
818 | 54f254f9 | aliguori | async->packet.data = async->buffer; |
819 | 54f254f9 | aliguori | async->packet.len = max_len; |
820 | 54f254f9 | aliguori | async->packet.complete_cb = uhci_async_complete; |
821 | 54f254f9 | aliguori | async->packet.complete_opaque = s; |
822 | 54f254f9 | aliguori | |
823 | 54f254f9 | aliguori | switch(pid) {
|
824 | 54f254f9 | aliguori | case USB_TOKEN_OUT:
|
825 | 54f254f9 | aliguori | case USB_TOKEN_SETUP:
|
826 | 54f254f9 | aliguori | cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
827 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
828 | 5d808245 | aurel32 | if (len >= 0) |
829 | 5d808245 | aurel32 | len = max_len; |
830 | 54f254f9 | aliguori | break;
|
831 | 54f254f9 | aliguori | |
832 | 54f254f9 | aliguori | case USB_TOKEN_IN:
|
833 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
834 | 54f254f9 | aliguori | break;
|
835 | 54f254f9 | aliguori | |
836 | 54f254f9 | aliguori | default:
|
837 | 54f254f9 | aliguori | /* invalid pid : frame interrupted */
|
838 | 54f254f9 | aliguori | uhci_async_free(s, async); |
839 | 54f254f9 | aliguori | s->status |= UHCI_STS_HCPERR; |
840 | 54f254f9 | aliguori | uhci_update_irq(s); |
841 | 54f254f9 | aliguori | return -1; |
842 | 54f254f9 | aliguori | } |
843 | 54f254f9 | aliguori | |
844 | 5d808245 | aurel32 | if (len == USB_RET_ASYNC) {
|
845 | 54f254f9 | aliguori | uhci_async_link(s, async); |
846 | 54f254f9 | aliguori | return 2; |
847 | 54f254f9 | aliguori | } |
848 | 54f254f9 | aliguori | |
849 | 5d808245 | aurel32 | async->packet.len = len; |
850 | 54f254f9 | aliguori | |
851 | 54f254f9 | aliguori | done:
|
852 | 5d808245 | aurel32 | len = uhci_complete_td(s, td, async, int_mask); |
853 | 54f254f9 | aliguori | uhci_async_free(s, async); |
854 | 5d808245 | aurel32 | return len;
|
855 | 54f254f9 | aliguori | } |
856 | 54f254f9 | aliguori | |
857 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket *packet, void *opaque) |
858 | 4d611c9a | pbrook | { |
859 | 4d611c9a | pbrook | UHCIState *s = opaque; |
860 | 54f254f9 | aliguori | UHCIAsync *async = (UHCIAsync *) packet; |
861 | 54f254f9 | aliguori | |
862 | d0f2c4c6 | malc | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
863 | 54f254f9 | aliguori | |
864 | 8e65b7c0 | David S. Ahern | if (async->isoc) {
|
865 | 8e65b7c0 | David S. Ahern | UHCI_TD td; |
866 | 8e65b7c0 | David S. Ahern | uint32_t link = async->td; |
867 | 8e65b7c0 | David S. Ahern | uint32_t int_mask = 0, val;
|
868 | d4c4e6fd | Blue Swirl | |
869 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
870 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.link); |
871 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.ctrl); |
872 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.token); |
873 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.buffer); |
874 | 8e65b7c0 | David S. Ahern | |
875 | 8e65b7c0 | David S. Ahern | uhci_async_unlink(s, async); |
876 | d4c4e6fd | Blue Swirl | uhci_complete_td(s, &td, async, &int_mask); |
877 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
878 | 54f254f9 | aliguori | |
879 | 8e65b7c0 | David S. Ahern | /* update the status bits of the TD */
|
880 | 8e65b7c0 | David S. Ahern | val = cpu_to_le32(td.ctrl); |
881 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_write((link & ~0xf) + 4, |
882 | 8e65b7c0 | David S. Ahern | (const uint8_t *)&val, sizeof(val)); |
883 | 8e65b7c0 | David S. Ahern | uhci_async_free(s, async); |
884 | 8e65b7c0 | David S. Ahern | } else {
|
885 | 8e65b7c0 | David S. Ahern | async->done = 1;
|
886 | 8e65b7c0 | David S. Ahern | uhci_process_frame(s); |
887 | 8e65b7c0 | David S. Ahern | } |
888 | 54f254f9 | aliguori | } |
889 | 54f254f9 | aliguori | |
890 | 54f254f9 | aliguori | static int is_valid(uint32_t link) |
891 | 54f254f9 | aliguori | { |
892 | 54f254f9 | aliguori | return (link & 1) == 0; |
893 | 54f254f9 | aliguori | } |
894 | 54f254f9 | aliguori | |
895 | 54f254f9 | aliguori | static int is_qh(uint32_t link) |
896 | 54f254f9 | aliguori | { |
897 | 54f254f9 | aliguori | return (link & 2) != 0; |
898 | 54f254f9 | aliguori | } |
899 | 54f254f9 | aliguori | |
900 | 54f254f9 | aliguori | static int depth_first(uint32_t link) |
901 | 54f254f9 | aliguori | { |
902 | 54f254f9 | aliguori | return (link & 4) != 0; |
903 | 54f254f9 | aliguori | } |
904 | 54f254f9 | aliguori | |
905 | 54f254f9 | aliguori | /* QH DB used for detecting QH loops */
|
906 | 54f254f9 | aliguori | #define UHCI_MAX_QUEUES 128 |
907 | 54f254f9 | aliguori | typedef struct { |
908 | 54f254f9 | aliguori | uint32_t addr[UHCI_MAX_QUEUES]; |
909 | 54f254f9 | aliguori | int count;
|
910 | 54f254f9 | aliguori | } QhDb; |
911 | 54f254f9 | aliguori | |
912 | 54f254f9 | aliguori | static void qhdb_reset(QhDb *db) |
913 | 54f254f9 | aliguori | { |
914 | 54f254f9 | aliguori | db->count = 0;
|
915 | 54f254f9 | aliguori | } |
916 | 54f254f9 | aliguori | |
917 | 54f254f9 | aliguori | /* Add QH to DB. Returns 1 if already present or DB is full. */
|
918 | 54f254f9 | aliguori | static int qhdb_insert(QhDb *db, uint32_t addr) |
919 | 54f254f9 | aliguori | { |
920 | 54f254f9 | aliguori | int i;
|
921 | 54f254f9 | aliguori | for (i = 0; i < db->count; i++) |
922 | 54f254f9 | aliguori | if (db->addr[i] == addr)
|
923 | 54f254f9 | aliguori | return 1; |
924 | 54f254f9 | aliguori | |
925 | 54f254f9 | aliguori | if (db->count >= UHCI_MAX_QUEUES)
|
926 | 54f254f9 | aliguori | return 1; |
927 | 54f254f9 | aliguori | |
928 | 54f254f9 | aliguori | db->addr[db->count++] = addr; |
929 | 54f254f9 | aliguori | return 0; |
930 | 54f254f9 | aliguori | } |
931 | 54f254f9 | aliguori | |
932 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s) |
933 | 54f254f9 | aliguori | { |
934 | 54f254f9 | aliguori | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
935 | 54f254f9 | aliguori | uint32_t curr_qh; |
936 | 54f254f9 | aliguori | int cnt, ret;
|
937 | 4d611c9a | pbrook | UHCI_TD td; |
938 | 54f254f9 | aliguori | UHCI_QH qh; |
939 | 54f254f9 | aliguori | QhDb qhdb; |
940 | 4d611c9a | pbrook | |
941 | 54f254f9 | aliguori | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
942 | 54f254f9 | aliguori | |
943 | d0f2c4c6 | malc | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
944 | 54f254f9 | aliguori | |
945 | 54f254f9 | aliguori | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
946 | 54f254f9 | aliguori | le32_to_cpus(&link); |
947 | b9dc033c | balrog | |
948 | 54f254f9 | aliguori | int_mask = 0;
|
949 | 54f254f9 | aliguori | curr_qh = 0;
|
950 | 54f254f9 | aliguori | |
951 | 54f254f9 | aliguori | qhdb_reset(&qhdb); |
952 | 54f254f9 | aliguori | |
953 | 54f254f9 | aliguori | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
954 | 54f254f9 | aliguori | if (is_qh(link)) {
|
955 | 54f254f9 | aliguori | /* QH */
|
956 | 54f254f9 | aliguori | |
957 | 54f254f9 | aliguori | if (qhdb_insert(&qhdb, link)) {
|
958 | 54f254f9 | aliguori | /*
|
959 | 54f254f9 | aliguori | * We're going in circles. Which is not a bug because
|
960 | 54f254f9 | aliguori | * HCD is allowed to do that as part of the BW management.
|
961 | 54f254f9 | aliguori | * In our case though it makes no sense to spin here. Sync transations
|
962 | 54f254f9 | aliguori | * are already done, and async completion handler will re-process
|
963 | 54f254f9 | aliguori | * the frame when something is ready.
|
964 | 54f254f9 | aliguori | */
|
965 | d0f2c4c6 | malc | DPRINTF("uhci: detected loop. qh 0x%x\n", link);
|
966 | 54f254f9 | aliguori | break;
|
967 | 54f254f9 | aliguori | } |
968 | 54f254f9 | aliguori | |
969 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
970 | 54f254f9 | aliguori | le32_to_cpus(&qh.link); |
971 | 54f254f9 | aliguori | le32_to_cpus(&qh.el_link); |
972 | 54f254f9 | aliguori | |
973 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
974 | 54f254f9 | aliguori | link, qh.link, qh.el_link); |
975 | 54f254f9 | aliguori | |
976 | 54f254f9 | aliguori | if (!is_valid(qh.el_link)) {
|
977 | 54f254f9 | aliguori | /* QH w/o elements */
|
978 | 54f254f9 | aliguori | curr_qh = 0;
|
979 | 54f254f9 | aliguori | link = qh.link; |
980 | 54f254f9 | aliguori | } else {
|
981 | 54f254f9 | aliguori | /* QH with elements */
|
982 | 54f254f9 | aliguori | curr_qh = link; |
983 | 54f254f9 | aliguori | link = qh.el_link; |
984 | 54f254f9 | aliguori | } |
985 | 54f254f9 | aliguori | continue;
|
986 | 54f254f9 | aliguori | } |
987 | 54f254f9 | aliguori | |
988 | 54f254f9 | aliguori | /* TD */
|
989 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
990 | b9dc033c | balrog | le32_to_cpus(&td.link); |
991 | b9dc033c | balrog | le32_to_cpus(&td.ctrl); |
992 | b9dc033c | balrog | le32_to_cpus(&td.token); |
993 | b9dc033c | balrog | le32_to_cpus(&td.buffer); |
994 | b9dc033c | balrog | |
995 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
996 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
997 | 54f254f9 | aliguori | |
998 | 54f254f9 | aliguori | old_td_ctrl = td.ctrl; |
999 | 54f254f9 | aliguori | ret = uhci_handle_td(s, link, &td, &int_mask); |
1000 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
1001 | 54f254f9 | aliguori | /* update the status bits of the TD */
|
1002 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
1003 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
1004 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1005 | b9dc033c | balrog | } |
1006 | 54f254f9 | aliguori | |
1007 | 54f254f9 | aliguori | if (ret < 0) { |
1008 | 54f254f9 | aliguori | /* interrupted frame */
|
1009 | 54f254f9 | aliguori | break;
|
1010 | b9dc033c | balrog | } |
1011 | b9dc033c | balrog | |
1012 | 54f254f9 | aliguori | if (ret == 2 || ret == 1) { |
1013 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1014 | 54f254f9 | aliguori | link, ret == 2 ? "pend" : "skip", |
1015 | 54f254f9 | aliguori | td.link, td.ctrl, td.token, curr_qh); |
1016 | b9dc033c | balrog | |
1017 | 54f254f9 | aliguori | link = curr_qh ? qh.link : td.link; |
1018 | 54f254f9 | aliguori | continue;
|
1019 | 4d611c9a | pbrook | } |
1020 | 54f254f9 | aliguori | |
1021 | 54f254f9 | aliguori | /* completed TD */
|
1022 | 54f254f9 | aliguori | |
1023 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1024 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
1025 | 54f254f9 | aliguori | |
1026 | 54f254f9 | aliguori | link = td.link; |
1027 | 54f254f9 | aliguori | |
1028 | 54f254f9 | aliguori | if (curr_qh) {
|
1029 | 54f254f9 | aliguori | /* update QH element link */
|
1030 | 54f254f9 | aliguori | qh.el_link = link; |
1031 | 4d611c9a | pbrook | val = cpu_to_le32(qh.el_link); |
1032 | 54f254f9 | aliguori | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1033 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1034 | 54f254f9 | aliguori | |
1035 | 54f254f9 | aliguori | if (!depth_first(link)) {
|
1036 | 54f254f9 | aliguori | /* done with this QH */
|
1037 | 54f254f9 | aliguori | |
1038 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1039 | 54f254f9 | aliguori | curr_qh, qh.link, qh.el_link); |
1040 | 54f254f9 | aliguori | |
1041 | 54f254f9 | aliguori | curr_qh = 0;
|
1042 | 54f254f9 | aliguori | link = qh.link; |
1043 | 54f254f9 | aliguori | } |
1044 | 4d611c9a | pbrook | } |
1045 | 54f254f9 | aliguori | |
1046 | 54f254f9 | aliguori | /* go to the next entry */
|
1047 | 4d611c9a | pbrook | } |
1048 | 54f254f9 | aliguori | |
1049 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
1050 | 4d611c9a | pbrook | } |
1051 | 4d611c9a | pbrook | |
1052 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
1053 | bb36d470 | bellard | { |
1054 | bb36d470 | bellard | UHCIState *s = opaque; |
1055 | 8e65b7c0 | David S. Ahern | |
1056 | 8e65b7c0 | David S. Ahern | /* prepare the timer for the next frame */
|
1057 | 8e65b7c0 | David S. Ahern | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1058 | bb36d470 | bellard | |
1059 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
1060 | 54f254f9 | aliguori | /* Full stop */
|
1061 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
1062 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
1063 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
1064 | 6f382b5e | aliguori | |
1065 | d0f2c4c6 | malc | DPRINTF("uhci: halted\n");
|
1066 | bb36d470 | bellard | return;
|
1067 | bb36d470 | bellard | } |
1068 | 54f254f9 | aliguori | |
1069 | 54f254f9 | aliguori | /* Complete the previous frame */
|
1070 | 4d611c9a | pbrook | if (s->pending_int_mask) {
|
1071 | 4d611c9a | pbrook | s->status2 |= s->pending_int_mask; |
1072 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBINT; |
1073 | 4d611c9a | pbrook | uhci_update_irq(s); |
1074 | 4d611c9a | pbrook | } |
1075 | 8e65b7c0 | David S. Ahern | s->pending_int_mask = 0;
|
1076 | b9dc033c | balrog | |
1077 | 54f254f9 | aliguori | /* Start new frame */
|
1078 | 54f254f9 | aliguori | s->frnum = (s->frnum + 1) & 0x7ff; |
1079 | 54f254f9 | aliguori | |
1080 | d0f2c4c6 | malc | DPRINTF("uhci: new frame #%u\n" , s->frnum);
|
1081 | 54f254f9 | aliguori | |
1082 | 54f254f9 | aliguori | uhci_async_validate_begin(s); |
1083 | 54f254f9 | aliguori | |
1084 | 54f254f9 | aliguori | uhci_process_frame(s); |
1085 | 54f254f9 | aliguori | |
1086 | 54f254f9 | aliguori | uhci_async_validate_end(s); |
1087 | b9dc033c | balrog | |
1088 | 8e65b7c0 | David S. Ahern | qemu_mod_timer(s->frame_timer, s->expire_time); |
1089 | bb36d470 | bellard | } |
1090 | bb36d470 | bellard | |
1091 | 5fafdf24 | ths | static void uhci_map(PCIDevice *pci_dev, int region_num, |
1092 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
1093 | bb36d470 | bellard | { |
1094 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
1095 | bb36d470 | bellard | |
1096 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1097 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1098 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1099 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1100 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1101 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1102 | bb36d470 | bellard | } |
1103 | bb36d470 | bellard | |
1104 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_common_initfn(UHCIState *s) |
1105 | bb36d470 | bellard | { |
1106 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1107 | bb36d470 | bellard | int i;
|
1108 | bb36d470 | bellard | |
1109 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_REVISION_ID] = 0x01; // revision number |
1110 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_CLASS_PROG] = 0x00;
|
1111 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
1112 | db579e9e | Michael S. Tsirkin | /* TODO: reset value should be 0. */
|
1113 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 |
1114 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
1115 | 3b46e624 | ths | |
1116 | b2317837 | Gerd Hoffmann | usb_bus_new(&s->bus, &s->dev.qdev); |
1117 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
1118 | b2317837 | Gerd Hoffmann | usb_register_port(&s->bus, &s->ports[i].port, s, i, uhci_attach); |
1119 | bb36d470 | bellard | } |
1120 | bb36d470 | bellard | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1121 | 8e65b7c0 | David S. Ahern | s->expire_time = qemu_get_clock(vm_clock) + |
1122 | 8e65b7c0 | David S. Ahern | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1123 | 64e58fe5 | Juan Quintela | s->num_ports_vmstate = NB_PORTS; |
1124 | bb36d470 | bellard | |
1125 | a08d4367 | Jan Kiszka | qemu_register_reset(uhci_reset, s); |
1126 | bb36d470 | bellard | |
1127 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
1128 | 38ca0f6d | pbrook | to rely on this. */
|
1129 | 28c2c264 | Avi Kivity | pci_register_bar(&s->dev, 4, 0x20, |
1130 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, uhci_map); |
1131 | 6f382b5e | aliguori | |
1132 | 6cf9b6f1 | Gerd Hoffmann | return 0; |
1133 | bb36d470 | bellard | } |
1134 | afcc3cdf | ths | |
1135 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix3_initfn(PCIDevice *dev) |
1136 | afcc3cdf | ths | { |
1137 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1138 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1139 | 6cf9b6f1 | Gerd Hoffmann | |
1140 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1141 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); |
1142 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1143 | 6cf9b6f1 | Gerd Hoffmann | } |
1144 | 6cf9b6f1 | Gerd Hoffmann | |
1145 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix4_initfn(PCIDevice *dev) |
1146 | 6cf9b6f1 | Gerd Hoffmann | { |
1147 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1148 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1149 | afcc3cdf | ths | |
1150 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1151 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); |
1152 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1153 | 6cf9b6f1 | Gerd Hoffmann | } |
1154 | afcc3cdf | ths | |
1155 | 30235a54 | Huacai Chen | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1156 | 30235a54 | Huacai Chen | { |
1157 | 30235a54 | Huacai Chen | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1158 | 30235a54 | Huacai Chen | uint8_t *pci_conf = s->dev.config; |
1159 | 30235a54 | Huacai Chen | |
1160 | 30235a54 | Huacai Chen | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
1161 | 30235a54 | Huacai Chen | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI); |
1162 | 30235a54 | Huacai Chen | |
1163 | 30235a54 | Huacai Chen | /* USB misc control 1/2 */
|
1164 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x40,0x00001000); |
1165 | 30235a54 | Huacai Chen | /* PM capability */
|
1166 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x80,0x00020001); |
1167 | 30235a54 | Huacai Chen | /* USB legacy support */
|
1168 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0xc0,0x00002000); |
1169 | 30235a54 | Huacai Chen | |
1170 | 30235a54 | Huacai Chen | return usb_uhci_common_initfn(s);
|
1171 | 30235a54 | Huacai Chen | } |
1172 | 30235a54 | Huacai Chen | |
1173 | 6cf9b6f1 | Gerd Hoffmann | static PCIDeviceInfo uhci_info[] = {
|
1174 | 6cf9b6f1 | Gerd Hoffmann | { |
1175 | 556cd098 | Markus Armbruster | .qdev.name = "piix3-usb-uhci",
|
1176 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1177 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1178 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix3_initfn, |
1179 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1180 | 556cd098 | Markus Armbruster | .qdev.name = "piix4-usb-uhci",
|
1181 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1182 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1183 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix4_initfn, |
1184 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1185 | 30235a54 | Huacai Chen | .qdev.name = "vt82c686b-usb-uhci",
|
1186 | 30235a54 | Huacai Chen | .qdev.size = sizeof(UHCIState),
|
1187 | 30235a54 | Huacai Chen | .qdev.vmsd = &vmstate_uhci, |
1188 | 30235a54 | Huacai Chen | .init = usb_uhci_vt82c686b_initfn, |
1189 | 30235a54 | Huacai Chen | },{ |
1190 | 6cf9b6f1 | Gerd Hoffmann | /* end of list */
|
1191 | afcc3cdf | ths | } |
1192 | 6cf9b6f1 | Gerd Hoffmann | }; |
1193 | afcc3cdf | ths | |
1194 | 6cf9b6f1 | Gerd Hoffmann | static void uhci_register(void) |
1195 | 6cf9b6f1 | Gerd Hoffmann | { |
1196 | 6cf9b6f1 | Gerd Hoffmann | pci_qdev_register_many(uhci_info); |
1197 | 6cf9b6f1 | Gerd Hoffmann | } |
1198 | 6cf9b6f1 | Gerd Hoffmann | device_init(uhci_register); |
1199 | afcc3cdf | ths | |
1200 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1201 | 6cf9b6f1 | Gerd Hoffmann | { |
1202 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix3-usb-uhci");
|
1203 | 6cf9b6f1 | Gerd Hoffmann | } |
1204 | 54f254f9 | aliguori | |
1205 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1206 | 6cf9b6f1 | Gerd Hoffmann | { |
1207 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix4-usb-uhci");
|
1208 | afcc3cdf | ths | } |
1209 | 30235a54 | Huacai Chen | |
1210 | 30235a54 | Huacai Chen | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) |
1211 | 30235a54 | Huacai Chen | { |
1212 | 30235a54 | Huacai Chen | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
|
1213 | 30235a54 | Huacai Chen | } |