Revision ac404095 hw/acpi_piix4.c
| b/hw/acpi_piix4.c | ||
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| 29 | 29 |
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| 30 | 30 |
#define ACPI_DBG_IO_ADDR 0xb044 |
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#define GPE_BASE 0xafe0 |
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#define PCI_BASE 0xae00 |
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#define PCI_EJ_BASE 0xae08 |
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struct gpe_regs {
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uint16_t sts; /* status */ |
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uint16_t en; /* enabled */ |
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}; |
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struct pci_status {
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uint32_t up; |
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uint32_t down; |
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}; |
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typedef struct PIIX4PMState {
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PCIDevice dev; |
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uint16_t pmsts; |
| ... | ... | |
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qemu_irq cmos_s3; |
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qemu_irq smi_irq; |
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int kvm_enabled; |
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/* for pci hotplug */ |
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struct gpe_regs gpe; |
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struct pci_status pci0_status; |
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} PIIX4PMState; |
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static PIIX4PMState *pm_state; |
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static uint32_t get_pmtmr(PIIX4PMState *s) |
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{
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uint32_t d; |
| ... | ... | |
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
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uint8_t *pci_conf; |
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pm_state = s; |
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pci_conf = s->dev.config; |
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
| 331 | 348 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
| ... | ... | |
| 369 | 386 |
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pm_smbus_init(&s->dev.qdev, &s->smb); |
| 371 | 388 |
qemu_register_reset(piix4_reset, s); |
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piix4_acpi_system_hot_add_init(dev->bus, s); |
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| 372 | 390 |
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return 0; |
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} |
| ... | ... | |
| 414 | 432 |
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device_init(piix4_pm_register); |
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#define GPE_BASE 0xafe0 |
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#define PCI_BASE 0xae00 |
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#define PCI_EJ_BASE 0xae08 |
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struct gpe_regs {
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uint16_t sts; /* status */ |
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uint16_t en; /* enabled */ |
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}; |
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struct pci_status {
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uint32_t up; |
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uint32_t down; |
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}; |
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static struct gpe_regs gpe; |
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static struct pci_status pci0_status; |
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static uint32_t gpe_read_val(uint16_t val, uint32_t addr) |
| 435 | 436 |
{
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if (addr & 1) |
| ... | ... | |
| 570 | 571 |
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static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state); |
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void piix4_acpi_system_hot_add_init(PCIBus *bus)
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
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{
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register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
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register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
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struct gpe_regs *gpe = &s->gpe;
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struct pci_status *pci0_status = &s->pci0_status;
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register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
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register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
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register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe); |
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register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe); |
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register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); |
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register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); |
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| 580 | 584 |
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register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); |
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register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); |
| 583 | 587 |
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pci_bus_hotplug(bus, piix4_device_hotplug, NULL);
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pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
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} |
| 586 | 590 |
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static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
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static void enable_device(PIIX4PMState *s, int slot)
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{
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g->sts |= 2;
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p->up |= (1 << slot);
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s->gpe.sts |= 2;
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s->pci0_status.up |= (1 << slot);
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} |
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static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
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static void disable_device(PIIX4PMState *s, int slot)
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{
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g->sts |= 2;
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p->down |= (1 << slot);
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s->gpe.sts |= 2;
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s->pci0_status.down |= (1 << slot);
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} |
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static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state) |
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{
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int slot = PCI_SLOT(dev->devfn); |
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
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DO_UPCAST(PCIDevice, qdev, qdev)); |
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pci0_status.up = 0; |
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pci0_status.down = 0; |
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if (state) |
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enable_device(&pci0_status, &gpe, slot); |
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else |
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disable_device(&pci0_status, &gpe, slot); |
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if (gpe.en & 2) {
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qemu_set_irq(pm_state->irq, 1); |
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qemu_set_irq(pm_state->irq, 0); |
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s->pci0_status.up = 0; |
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s->pci0_status.down = 0; |
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if (state) {
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enable_device(s, slot); |
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} else {
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disable_device(s, slot); |
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} |
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if (s->gpe.en & 2) {
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qemu_set_irq(s->irq, 1); |
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qemu_set_irq(s->irq, 0); |
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| 612 | 619 |
} |
| 613 | 620 |
return 0; |
| 614 | 621 |
} |
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