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1 | fde7d5bd | ths | /*
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2 | fde7d5bd | ths | * QEMU GT64120 PCI host
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3 | fde7d5bd | ths | *
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4 | 4de9b249 | ths | * Copyright (c) 2006,2007 Aurelien Jarno
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5 | 5fafdf24 | ths | *
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6 | fde7d5bd | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | fde7d5bd | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | fde7d5bd | ths | * in the Software without restriction, including without limitation the rights
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9 | fde7d5bd | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | fde7d5bd | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | fde7d5bd | ths | * furnished to do so, subject to the following conditions:
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12 | fde7d5bd | ths | *
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13 | fde7d5bd | ths | * The above copyright notice and this permission notice shall be included in
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14 | fde7d5bd | ths | * all copies or substantial portions of the Software.
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15 | fde7d5bd | ths | *
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16 | fde7d5bd | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | fde7d5bd | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | fde7d5bd | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | fde7d5bd | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | fde7d5bd | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | fde7d5bd | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | fde7d5bd | ths | * THE SOFTWARE.
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23 | fde7d5bd | ths | */
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24 | fde7d5bd | ths | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "mips.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | fde7d5bd | ths | #include "pci_host.h" |
29 | 4f5e19e6 | Isaku Yamahata | #include "pc.h" |
30 | fde7d5bd | ths | |
31 | 05b4ff43 | ths | //#define DEBUG
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32 | 05b4ff43 | ths | |
33 | 05b4ff43 | ths | #ifdef DEBUG
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34 | d0f2c4c6 | malc | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
35 | 05b4ff43 | ths | #else
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36 | d0f2c4c6 | malc | #define DPRINTF(fmt, ...)
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37 | 05b4ff43 | ths | #endif
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38 | 05b4ff43 | ths | |
39 | fde7d5bd | ths | #define GT_REGS (0x1000 >> 2) |
40 | fde7d5bd | ths | |
41 | fde7d5bd | ths | /* CPU Configuration */
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42 | fde7d5bd | ths | #define GT_CPU (0x000 >> 2) |
43 | fde7d5bd | ths | #define GT_MULTI (0x120 >> 2) |
44 | fde7d5bd | ths | |
45 | fde7d5bd | ths | /* CPU Address Decode */
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46 | fde7d5bd | ths | #define GT_SCS10LD (0x008 >> 2) |
47 | fde7d5bd | ths | #define GT_SCS10HD (0x010 >> 2) |
48 | fde7d5bd | ths | #define GT_SCS32LD (0x018 >> 2) |
49 | fde7d5bd | ths | #define GT_SCS32HD (0x020 >> 2) |
50 | fde7d5bd | ths | #define GT_CS20LD (0x028 >> 2) |
51 | fde7d5bd | ths | #define GT_CS20HD (0x030 >> 2) |
52 | fde7d5bd | ths | #define GT_CS3BOOTLD (0x038 >> 2) |
53 | fde7d5bd | ths | #define GT_CS3BOOTHD (0x040 >> 2) |
54 | fde7d5bd | ths | #define GT_PCI0IOLD (0x048 >> 2) |
55 | fde7d5bd | ths | #define GT_PCI0IOHD (0x050 >> 2) |
56 | fde7d5bd | ths | #define GT_PCI0M0LD (0x058 >> 2) |
57 | fde7d5bd | ths | #define GT_PCI0M0HD (0x060 >> 2) |
58 | fde7d5bd | ths | #define GT_PCI0M1LD (0x080 >> 2) |
59 | fde7d5bd | ths | #define GT_PCI0M1HD (0x088 >> 2) |
60 | fde7d5bd | ths | #define GT_PCI1IOLD (0x090 >> 2) |
61 | fde7d5bd | ths | #define GT_PCI1IOHD (0x098 >> 2) |
62 | fde7d5bd | ths | #define GT_PCI1M0LD (0x0a0 >> 2) |
63 | fde7d5bd | ths | #define GT_PCI1M0HD (0x0a8 >> 2) |
64 | fde7d5bd | ths | #define GT_PCI1M1LD (0x0b0 >> 2) |
65 | fde7d5bd | ths | #define GT_PCI1M1HD (0x0b8 >> 2) |
66 | 05b4ff43 | ths | #define GT_ISD (0x068 >> 2) |
67 | fde7d5bd | ths | |
68 | fde7d5bd | ths | #define GT_SCS10AR (0x0d0 >> 2) |
69 | fde7d5bd | ths | #define GT_SCS32AR (0x0d8 >> 2) |
70 | fde7d5bd | ths | #define GT_CS20R (0x0e0 >> 2) |
71 | fde7d5bd | ths | #define GT_CS3BOOTR (0x0e8 >> 2) |
72 | fde7d5bd | ths | |
73 | fde7d5bd | ths | #define GT_PCI0IOREMAP (0x0f0 >> 2) |
74 | fde7d5bd | ths | #define GT_PCI0M0REMAP (0x0f8 >> 2) |
75 | fde7d5bd | ths | #define GT_PCI0M1REMAP (0x100 >> 2) |
76 | fde7d5bd | ths | #define GT_PCI1IOREMAP (0x108 >> 2) |
77 | fde7d5bd | ths | #define GT_PCI1M0REMAP (0x110 >> 2) |
78 | fde7d5bd | ths | #define GT_PCI1M1REMAP (0x118 >> 2) |
79 | fde7d5bd | ths | |
80 | fde7d5bd | ths | /* CPU Error Report */
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81 | fde7d5bd | ths | #define GT_CPUERR_ADDRLO (0x070 >> 2) |
82 | fde7d5bd | ths | #define GT_CPUERR_ADDRHI (0x078 >> 2) |
83 | fde7d5bd | ths | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
84 | fde7d5bd | ths | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
85 | fde7d5bd | ths | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
86 | fde7d5bd | ths | |
87 | fde7d5bd | ths | /* CPU Sync Barrier */
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88 | fde7d5bd | ths | #define GT_PCI0SYNC (0x0c0 >> 2) |
89 | fde7d5bd | ths | #define GT_PCI1SYNC (0x0c8 >> 2) |
90 | fde7d5bd | ths | |
91 | fde7d5bd | ths | /* SDRAM and Device Address Decode */
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92 | fde7d5bd | ths | #define GT_SCS0LD (0x400 >> 2) |
93 | fde7d5bd | ths | #define GT_SCS0HD (0x404 >> 2) |
94 | fde7d5bd | ths | #define GT_SCS1LD (0x408 >> 2) |
95 | fde7d5bd | ths | #define GT_SCS1HD (0x40c >> 2) |
96 | fde7d5bd | ths | #define GT_SCS2LD (0x410 >> 2) |
97 | fde7d5bd | ths | #define GT_SCS2HD (0x414 >> 2) |
98 | fde7d5bd | ths | #define GT_SCS3LD (0x418 >> 2) |
99 | fde7d5bd | ths | #define GT_SCS3HD (0x41c >> 2) |
100 | fde7d5bd | ths | #define GT_CS0LD (0x420 >> 2) |
101 | fde7d5bd | ths | #define GT_CS0HD (0x424 >> 2) |
102 | fde7d5bd | ths | #define GT_CS1LD (0x428 >> 2) |
103 | fde7d5bd | ths | #define GT_CS1HD (0x42c >> 2) |
104 | fde7d5bd | ths | #define GT_CS2LD (0x430 >> 2) |
105 | fde7d5bd | ths | #define GT_CS2HD (0x434 >> 2) |
106 | fde7d5bd | ths | #define GT_CS3LD (0x438 >> 2) |
107 | fde7d5bd | ths | #define GT_CS3HD (0x43c >> 2) |
108 | fde7d5bd | ths | #define GT_BOOTLD (0x440 >> 2) |
109 | fde7d5bd | ths | #define GT_BOOTHD (0x444 >> 2) |
110 | fde7d5bd | ths | #define GT_ADERR (0x470 >> 2) |
111 | fde7d5bd | ths | |
112 | fde7d5bd | ths | /* SDRAM Configuration */
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113 | fde7d5bd | ths | #define GT_SDRAM_CFG (0x448 >> 2) |
114 | fde7d5bd | ths | #define GT_SDRAM_OPMODE (0x474 >> 2) |
115 | fde7d5bd | ths | #define GT_SDRAM_BM (0x478 >> 2) |
116 | fde7d5bd | ths | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
117 | fde7d5bd | ths | |
118 | fde7d5bd | ths | /* SDRAM Parameters */
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119 | fde7d5bd | ths | #define GT_SDRAM_B0 (0x44c >> 2) |
120 | fde7d5bd | ths | #define GT_SDRAM_B1 (0x450 >> 2) |
121 | fde7d5bd | ths | #define GT_SDRAM_B2 (0x454 >> 2) |
122 | fde7d5bd | ths | #define GT_SDRAM_B3 (0x458 >> 2) |
123 | fde7d5bd | ths | |
124 | fde7d5bd | ths | /* Device Parameters */
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125 | fde7d5bd | ths | #define GT_DEV_B0 (0x45c >> 2) |
126 | fde7d5bd | ths | #define GT_DEV_B1 (0x460 >> 2) |
127 | fde7d5bd | ths | #define GT_DEV_B2 (0x464 >> 2) |
128 | fde7d5bd | ths | #define GT_DEV_B3 (0x468 >> 2) |
129 | fde7d5bd | ths | #define GT_DEV_BOOT (0x46c >> 2) |
130 | fde7d5bd | ths | |
131 | fde7d5bd | ths | /* ECC */
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132 | fde7d5bd | ths | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
133 | fde7d5bd | ths | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
134 | fde7d5bd | ths | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
135 | fde7d5bd | ths | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
136 | fde7d5bd | ths | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
137 | fde7d5bd | ths | |
138 | fde7d5bd | ths | /* DMA Record */
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139 | fde7d5bd | ths | #define GT_DMA0_CNT (0x800 >> 2) |
140 | fde7d5bd | ths | #define GT_DMA1_CNT (0x804 >> 2) |
141 | fde7d5bd | ths | #define GT_DMA2_CNT (0x808 >> 2) |
142 | fde7d5bd | ths | #define GT_DMA3_CNT (0x80c >> 2) |
143 | fde7d5bd | ths | #define GT_DMA0_SA (0x810 >> 2) |
144 | fde7d5bd | ths | #define GT_DMA1_SA (0x814 >> 2) |
145 | fde7d5bd | ths | #define GT_DMA2_SA (0x818 >> 2) |
146 | fde7d5bd | ths | #define GT_DMA3_SA (0x81c >> 2) |
147 | fde7d5bd | ths | #define GT_DMA0_DA (0x820 >> 2) |
148 | fde7d5bd | ths | #define GT_DMA1_DA (0x824 >> 2) |
149 | fde7d5bd | ths | #define GT_DMA2_DA (0x828 >> 2) |
150 | fde7d5bd | ths | #define GT_DMA3_DA (0x82c >> 2) |
151 | fde7d5bd | ths | #define GT_DMA0_NEXT (0x830 >> 2) |
152 | fde7d5bd | ths | #define GT_DMA1_NEXT (0x834 >> 2) |
153 | fde7d5bd | ths | #define GT_DMA2_NEXT (0x838 >> 2) |
154 | fde7d5bd | ths | #define GT_DMA3_NEXT (0x83c >> 2) |
155 | fde7d5bd | ths | #define GT_DMA0_CUR (0x870 >> 2) |
156 | fde7d5bd | ths | #define GT_DMA1_CUR (0x874 >> 2) |
157 | fde7d5bd | ths | #define GT_DMA2_CUR (0x878 >> 2) |
158 | fde7d5bd | ths | #define GT_DMA3_CUR (0x87c >> 2) |
159 | fde7d5bd | ths | |
160 | fde7d5bd | ths | /* DMA Channel Control */
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161 | fde7d5bd | ths | #define GT_DMA0_CTRL (0x840 >> 2) |
162 | fde7d5bd | ths | #define GT_DMA1_CTRL (0x844 >> 2) |
163 | fde7d5bd | ths | #define GT_DMA2_CTRL (0x848 >> 2) |
164 | fde7d5bd | ths | #define GT_DMA3_CTRL (0x84c >> 2) |
165 | fde7d5bd | ths | |
166 | fde7d5bd | ths | /* DMA Arbiter */
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167 | fde7d5bd | ths | #define GT_DMA_ARB (0x860 >> 2) |
168 | fde7d5bd | ths | |
169 | fde7d5bd | ths | /* Timer/Counter */
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170 | fde7d5bd | ths | #define GT_TC0 (0x850 >> 2) |
171 | fde7d5bd | ths | #define GT_TC1 (0x854 >> 2) |
172 | fde7d5bd | ths | #define GT_TC2 (0x858 >> 2) |
173 | fde7d5bd | ths | #define GT_TC3 (0x85c >> 2) |
174 | fde7d5bd | ths | #define GT_TC_CONTROL (0x864 >> 2) |
175 | fde7d5bd | ths | |
176 | fde7d5bd | ths | /* PCI Internal */
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177 | fde7d5bd | ths | #define GT_PCI0_CMD (0xc00 >> 2) |
178 | fde7d5bd | ths | #define GT_PCI0_TOR (0xc04 >> 2) |
179 | fde7d5bd | ths | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
180 | fde7d5bd | ths | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
181 | fde7d5bd | ths | #define GT_PCI0_BS_CS20 (0xc10 >> 2) |
182 | fde7d5bd | ths | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
183 | fde7d5bd | ths | #define GT_PCI1_IACK (0xc30 >> 2) |
184 | fde7d5bd | ths | #define GT_PCI0_IACK (0xc34 >> 2) |
185 | fde7d5bd | ths | #define GT_PCI0_BARE (0xc3c >> 2) |
186 | fde7d5bd | ths | #define GT_PCI0_PREFMBR (0xc40 >> 2) |
187 | fde7d5bd | ths | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
188 | fde7d5bd | ths | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
189 | fde7d5bd | ths | #define GT_PCI0_CS20_BAR (0xc50 >> 2) |
190 | fde7d5bd | ths | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
191 | fde7d5bd | ths | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
192 | fde7d5bd | ths | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
193 | fde7d5bd | ths | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
194 | fde7d5bd | ths | #define GT_PCI1_CMD (0xc80 >> 2) |
195 | fde7d5bd | ths | #define GT_PCI1_TOR (0xc84 >> 2) |
196 | fde7d5bd | ths | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
197 | fde7d5bd | ths | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
198 | fde7d5bd | ths | #define GT_PCI1_BS_CS20 (0xc90 >> 2) |
199 | fde7d5bd | ths | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
200 | fde7d5bd | ths | #define GT_PCI1_BARE (0xcbc >> 2) |
201 | fde7d5bd | ths | #define GT_PCI1_PREFMBR (0xcc0 >> 2) |
202 | fde7d5bd | ths | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
203 | fde7d5bd | ths | #define GT_PCI1_SCS32_BAR (0xccc >> 2) |
204 | fde7d5bd | ths | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
205 | fde7d5bd | ths | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
206 | fde7d5bd | ths | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
207 | fde7d5bd | ths | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
208 | fde7d5bd | ths | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
209 | fde7d5bd | ths | #define GT_PCI1_CFGADDR (0xcf0 >> 2) |
210 | fde7d5bd | ths | #define GT_PCI1_CFGDATA (0xcf4 >> 2) |
211 | fde7d5bd | ths | #define GT_PCI0_CFGADDR (0xcf8 >> 2) |
212 | fde7d5bd | ths | #define GT_PCI0_CFGDATA (0xcfc >> 2) |
213 | fde7d5bd | ths | |
214 | fde7d5bd | ths | /* Interrupts */
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215 | fde7d5bd | ths | #define GT_INTRCAUSE (0xc18 >> 2) |
216 | fde7d5bd | ths | #define GT_INTRMASK (0xc1c >> 2) |
217 | fde7d5bd | ths | #define GT_PCI0_ICMASK (0xc24 >> 2) |
218 | fde7d5bd | ths | #define GT_PCI0_SERR0MASK (0xc28 >> 2) |
219 | fde7d5bd | ths | #define GT_CPU_INTSEL (0xc70 >> 2) |
220 | fde7d5bd | ths | #define GT_PCI0_INTSEL (0xc74 >> 2) |
221 | fde7d5bd | ths | #define GT_HINTRCAUSE (0xc98 >> 2) |
222 | fde7d5bd | ths | #define GT_HINTRMASK (0xc9c >> 2) |
223 | fde7d5bd | ths | #define GT_PCI0_HICMASK (0xca4 >> 2) |
224 | fde7d5bd | ths | #define GT_PCI1_SERR1MASK (0xca8 >> 2) |
225 | fde7d5bd | ths | |
226 | a0a8793e | ths | #define PCI_MAPPING_ENTRY(regname) \
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227 | c227f099 | Anthony Liguori | target_phys_addr_t regname ##_start; \ |
228 | c227f099 | Anthony Liguori | target_phys_addr_t regname ##_length; \ |
229 | a0a8793e | ths | int regname ##_handle |
230 | a0a8793e | ths | |
231 | fde7d5bd | ths | typedef struct GT64120State { |
232 | c2dd2a23 | Aurelien Jarno | SysBusDevice busdev; |
233 | c2dd2a23 | Aurelien Jarno | PCIHostState pci; |
234 | fde7d5bd | ths | uint32_t regs[GT_REGS]; |
235 | a0a8793e | ths | PCI_MAPPING_ENTRY(PCI0IO); |
236 | a0a8793e | ths | PCI_MAPPING_ENTRY(ISD); |
237 | fde7d5bd | ths | } GT64120State; |
238 | fde7d5bd | ths | |
239 | a0a8793e | ths | /* Adjust range to avoid touching space which isn't mappable via PCI */
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240 | a0a8793e | ths | /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
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241 | a0a8793e | ths | 0x1fc00000 - 0x1fd00000 */
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242 | c227f099 | Anthony Liguori | static void check_reserved_space (target_phys_addr_t *start, |
243 | c227f099 | Anthony Liguori | target_phys_addr_t *length) |
244 | a0a8793e | ths | { |
245 | c227f099 | Anthony Liguori | target_phys_addr_t begin = *start; |
246 | c227f099 | Anthony Liguori | target_phys_addr_t end = *start + *length; |
247 | a0a8793e | ths | |
248 | a0a8793e | ths | if (end >= 0x1e000000LL && end < 0x1f100000LL) |
249 | a0a8793e | ths | end = 0x1e000000LL;
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250 | a0a8793e | ths | if (begin >= 0x1e000000LL && begin < 0x1f100000LL) |
251 | a0a8793e | ths | begin = 0x1f100000LL;
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252 | a0a8793e | ths | if (end >= 0x1fc00000LL && end < 0x1fd00000LL) |
253 | a0a8793e | ths | end = 0x1fc00000LL;
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254 | a0a8793e | ths | if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) |
255 | a0a8793e | ths | begin = 0x1fd00000LL;
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256 | a0a8793e | ths | /* XXX: This is broken when a reserved range splits the requested range */
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257 | a0a8793e | ths | if (end >= 0x1f100000LL && begin < 0x1e000000LL) |
258 | a0a8793e | ths | end = 0x1e000000LL;
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259 | a0a8793e | ths | if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) |
260 | a0a8793e | ths | end = 0x1fc00000LL;
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261 | a0a8793e | ths | |
262 | a0a8793e | ths | *start = begin; |
263 | a0a8793e | ths | *length = end - begin; |
264 | a0a8793e | ths | } |
265 | a0a8793e | ths | |
266 | a0a8793e | ths | static void gt64120_isd_mapping(GT64120State *s) |
267 | a0a8793e | ths | { |
268 | c227f099 | Anthony Liguori | target_phys_addr_t start = s->regs[GT_ISD] << 21;
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269 | c227f099 | Anthony Liguori | target_phys_addr_t length = 0x1000;
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270 | a0a8793e | ths | |
271 | a0a8793e | ths | if (s->ISD_length)
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272 | a0a8793e | ths | cpu_register_physical_memory(s->ISD_start, s->ISD_length, |
273 | a0a8793e | ths | IO_MEM_UNASSIGNED); |
274 | a0a8793e | ths | check_reserved_space(&start, &length); |
275 | a0a8793e | ths | length = 0x1000;
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276 | a0a8793e | ths | /* Map new address */
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277 | 82f24fcc | Riccardo Magliocchetti | DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start, |
278 | a0a8793e | ths | length, start, s->ISD_handle); |
279 | a0a8793e | ths | s->ISD_start = start; |
280 | a0a8793e | ths | s->ISD_length = length; |
281 | a0a8793e | ths | cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle); |
282 | a0a8793e | ths | } |
283 | a0a8793e | ths | |
284 | 9414cc6f | ths | static void gt64120_pci_mapping(GT64120State *s) |
285 | 2a1086d9 | ths | { |
286 | 9414cc6f | ths | /* Update IO mapping */
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287 | 9414cc6f | ths | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
288 | 9414cc6f | ths | { |
289 | 3b46e624 | ths | /* Unmap old IO address */
|
290 | 9414cc6f | ths | if (s->PCI0IO_length)
|
291 | 9414cc6f | ths | { |
292 | 3b46e624 | ths | cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); |
293 | 9414cc6f | ths | } |
294 | 9414cc6f | ths | /* Map new IO address */
|
295 | 9414cc6f | ths | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
|
296 | 9414cc6f | ths | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
297 | 9414cc6f | ths | isa_mem_base = s->PCI0IO_start; |
298 | 968d683c | Alexander Graf | isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
299 | 9414cc6f | ths | } |
300 | 2a1086d9 | ths | } |
301 | 2a1086d9 | ths | |
302 | c227f099 | Anthony Liguori | static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
303 | fde7d5bd | ths | uint32_t val) |
304 | fde7d5bd | ths | { |
305 | fde7d5bd | ths | GT64120State *s = opaque; |
306 | fde7d5bd | ths | uint32_t saddr; |
307 | fde7d5bd | ths | |
308 | c6c99c3f | aurel32 | if (!(s->regs[GT_CPU] & 0x00001000)) |
309 | 1931e260 | ths | val = bswap32(val); |
310 | 0da75eb1 | ths | |
311 | fde7d5bd | ths | saddr = (addr & 0xfff) >> 2; |
312 | fde7d5bd | ths | switch (saddr) {
|
313 | 0da75eb1 | ths | |
314 | 0da75eb1 | ths | /* CPU Configuration */
|
315 | fde7d5bd | ths | case GT_CPU:
|
316 | fde7d5bd | ths | s->regs[GT_CPU] = val; |
317 | fde7d5bd | ths | break;
|
318 | fde7d5bd | ths | case GT_MULTI:
|
319 | 0da75eb1 | ths | /* Read-only register as only one GT64xxx is present on the CPU bus */
|
320 | fde7d5bd | ths | break;
|
321 | fde7d5bd | ths | |
322 | fde7d5bd | ths | /* CPU Address Decode */
|
323 | fde7d5bd | ths | case GT_PCI0IOLD:
|
324 | fde7d5bd | ths | s->regs[GT_PCI0IOLD] = val & 0x00007fff;
|
325 | fde7d5bd | ths | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
|
326 | 9414cc6f | ths | gt64120_pci_mapping(s); |
327 | fde7d5bd | ths | break;
|
328 | fde7d5bd | ths | case GT_PCI0M0LD:
|
329 | fde7d5bd | ths | s->regs[GT_PCI0M0LD] = val & 0x00007fff;
|
330 | fde7d5bd | ths | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
|
331 | fde7d5bd | ths | break;
|
332 | fde7d5bd | ths | case GT_PCI0M1LD:
|
333 | fde7d5bd | ths | s->regs[GT_PCI0M1LD] = val & 0x00007fff;
|
334 | fde7d5bd | ths | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
|
335 | fde7d5bd | ths | break;
|
336 | fde7d5bd | ths | case GT_PCI1IOLD:
|
337 | fde7d5bd | ths | s->regs[GT_PCI1IOLD] = val & 0x00007fff;
|
338 | fde7d5bd | ths | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
|
339 | fde7d5bd | ths | break;
|
340 | fde7d5bd | ths | case GT_PCI1M0LD:
|
341 | fde7d5bd | ths | s->regs[GT_PCI1M0LD] = val & 0x00007fff;
|
342 | fde7d5bd | ths | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
|
343 | fde7d5bd | ths | break;
|
344 | fde7d5bd | ths | case GT_PCI1M1LD:
|
345 | fde7d5bd | ths | s->regs[GT_PCI1M1LD] = val & 0x00007fff;
|
346 | fde7d5bd | ths | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
|
347 | fde7d5bd | ths | break;
|
348 | fde7d5bd | ths | case GT_PCI0IOHD:
|
349 | bb433bef | ths | s->regs[saddr] = val & 0x0000007f;
|
350 | bb433bef | ths | gt64120_pci_mapping(s); |
351 | bb433bef | ths | break;
|
352 | fde7d5bd | ths | case GT_PCI0M0HD:
|
353 | fde7d5bd | ths | case GT_PCI0M1HD:
|
354 | fde7d5bd | ths | case GT_PCI1IOHD:
|
355 | fde7d5bd | ths | case GT_PCI1M0HD:
|
356 | fde7d5bd | ths | case GT_PCI1M1HD:
|
357 | fde7d5bd | ths | s->regs[saddr] = val & 0x0000007f;
|
358 | fde7d5bd | ths | break;
|
359 | a0a8793e | ths | case GT_ISD:
|
360 | a0a8793e | ths | s->regs[saddr] = val & 0x00007fff;
|
361 | a0a8793e | ths | gt64120_isd_mapping(s); |
362 | a0a8793e | ths | break;
|
363 | a0a8793e | ths | |
364 | fde7d5bd | ths | case GT_PCI0IOREMAP:
|
365 | fde7d5bd | ths | case GT_PCI0M0REMAP:
|
366 | fde7d5bd | ths | case GT_PCI0M1REMAP:
|
367 | fde7d5bd | ths | case GT_PCI1IOREMAP:
|
368 | fde7d5bd | ths | case GT_PCI1M0REMAP:
|
369 | fde7d5bd | ths | case GT_PCI1M1REMAP:
|
370 | fde7d5bd | ths | s->regs[saddr] = val & 0x000007ff;
|
371 | fde7d5bd | ths | break;
|
372 | fde7d5bd | ths | |
373 | fde7d5bd | ths | /* CPU Error Report */
|
374 | fde7d5bd | ths | case GT_CPUERR_ADDRLO:
|
375 | fde7d5bd | ths | case GT_CPUERR_ADDRHI:
|
376 | fde7d5bd | ths | case GT_CPUERR_DATALO:
|
377 | fde7d5bd | ths | case GT_CPUERR_DATAHI:
|
378 | fde7d5bd | ths | case GT_CPUERR_PARITY:
|
379 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
380 | 0da75eb1 | ths | break;
|
381 | 0da75eb1 | ths | |
382 | 0da75eb1 | ths | /* CPU Sync Barrier */
|
383 | 0da75eb1 | ths | case GT_PCI0SYNC:
|
384 | 0da75eb1 | ths | case GT_PCI1SYNC:
|
385 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
386 | fde7d5bd | ths | break;
|
387 | fde7d5bd | ths | |
388 | 05b4ff43 | ths | /* SDRAM and Device Address Decode */
|
389 | 05b4ff43 | ths | case GT_SCS0LD:
|
390 | 05b4ff43 | ths | case GT_SCS0HD:
|
391 | 05b4ff43 | ths | case GT_SCS1LD:
|
392 | 05b4ff43 | ths | case GT_SCS1HD:
|
393 | 05b4ff43 | ths | case GT_SCS2LD:
|
394 | 05b4ff43 | ths | case GT_SCS2HD:
|
395 | 05b4ff43 | ths | case GT_SCS3LD:
|
396 | 05b4ff43 | ths | case GT_SCS3HD:
|
397 | 05b4ff43 | ths | case GT_CS0LD:
|
398 | 05b4ff43 | ths | case GT_CS0HD:
|
399 | 05b4ff43 | ths | case GT_CS1LD:
|
400 | 05b4ff43 | ths | case GT_CS1HD:
|
401 | 05b4ff43 | ths | case GT_CS2LD:
|
402 | 05b4ff43 | ths | case GT_CS2HD:
|
403 | 05b4ff43 | ths | case GT_CS3LD:
|
404 | 05b4ff43 | ths | case GT_CS3HD:
|
405 | 05b4ff43 | ths | case GT_BOOTLD:
|
406 | 05b4ff43 | ths | case GT_BOOTHD:
|
407 | 05b4ff43 | ths | case GT_ADERR:
|
408 | 05b4ff43 | ths | /* SDRAM Configuration */
|
409 | 05b4ff43 | ths | case GT_SDRAM_CFG:
|
410 | 05b4ff43 | ths | case GT_SDRAM_OPMODE:
|
411 | 05b4ff43 | ths | case GT_SDRAM_BM:
|
412 | 05b4ff43 | ths | case GT_SDRAM_ADDRDECODE:
|
413 | 05b4ff43 | ths | /* Accept and ignore SDRAM interleave configuration */
|
414 | 05b4ff43 | ths | s->regs[saddr] = val; |
415 | 05b4ff43 | ths | break;
|
416 | 05b4ff43 | ths | |
417 | 05b4ff43 | ths | /* Device Parameters */
|
418 | 05b4ff43 | ths | case GT_DEV_B0:
|
419 | 05b4ff43 | ths | case GT_DEV_B1:
|
420 | 05b4ff43 | ths | case GT_DEV_B2:
|
421 | 05b4ff43 | ths | case GT_DEV_B3:
|
422 | 05b4ff43 | ths | case GT_DEV_BOOT:
|
423 | 05b4ff43 | ths | /* Not implemented */
|
424 | d0f2c4c6 | malc | DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); |
425 | 05b4ff43 | ths | break;
|
426 | 05b4ff43 | ths | |
427 | fde7d5bd | ths | /* ECC */
|
428 | fde7d5bd | ths | case GT_ECC_ERRDATALO:
|
429 | fde7d5bd | ths | case GT_ECC_ERRDATAHI:
|
430 | fde7d5bd | ths | case GT_ECC_MEM:
|
431 | fde7d5bd | ths | case GT_ECC_CALC:
|
432 | fde7d5bd | ths | case GT_ECC_ERRADDR:
|
433 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
434 | fde7d5bd | ths | break;
|
435 | fde7d5bd | ths | |
436 | 05b4ff43 | ths | /* DMA Record */
|
437 | 05b4ff43 | ths | case GT_DMA0_CNT:
|
438 | 05b4ff43 | ths | case GT_DMA1_CNT:
|
439 | 05b4ff43 | ths | case GT_DMA2_CNT:
|
440 | 05b4ff43 | ths | case GT_DMA3_CNT:
|
441 | 05b4ff43 | ths | case GT_DMA0_SA:
|
442 | 05b4ff43 | ths | case GT_DMA1_SA:
|
443 | 05b4ff43 | ths | case GT_DMA2_SA:
|
444 | 05b4ff43 | ths | case GT_DMA3_SA:
|
445 | 05b4ff43 | ths | case GT_DMA0_DA:
|
446 | 05b4ff43 | ths | case GT_DMA1_DA:
|
447 | 05b4ff43 | ths | case GT_DMA2_DA:
|
448 | 05b4ff43 | ths | case GT_DMA3_DA:
|
449 | 05b4ff43 | ths | case GT_DMA0_NEXT:
|
450 | 05b4ff43 | ths | case GT_DMA1_NEXT:
|
451 | 05b4ff43 | ths | case GT_DMA2_NEXT:
|
452 | 05b4ff43 | ths | case GT_DMA3_NEXT:
|
453 | 05b4ff43 | ths | case GT_DMA0_CUR:
|
454 | 05b4ff43 | ths | case GT_DMA1_CUR:
|
455 | 05b4ff43 | ths | case GT_DMA2_CUR:
|
456 | 05b4ff43 | ths | case GT_DMA3_CUR:
|
457 | 05b4ff43 | ths | /* Not implemented */
|
458 | d0f2c4c6 | malc | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
459 | 05b4ff43 | ths | break;
|
460 | 05b4ff43 | ths | |
461 | 05b4ff43 | ths | /* DMA Channel Control */
|
462 | 05b4ff43 | ths | case GT_DMA0_CTRL:
|
463 | 05b4ff43 | ths | case GT_DMA1_CTRL:
|
464 | 05b4ff43 | ths | case GT_DMA2_CTRL:
|
465 | 05b4ff43 | ths | case GT_DMA3_CTRL:
|
466 | 05b4ff43 | ths | /* Not implemented */
|
467 | d0f2c4c6 | malc | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
468 | 05b4ff43 | ths | break;
|
469 | 05b4ff43 | ths | |
470 | 05b4ff43 | ths | /* DMA Arbiter */
|
471 | 05b4ff43 | ths | case GT_DMA_ARB:
|
472 | 05b4ff43 | ths | /* Not implemented */
|
473 | d0f2c4c6 | malc | DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
474 | 05b4ff43 | ths | break;
|
475 | 05b4ff43 | ths | |
476 | 05b4ff43 | ths | /* Timer/Counter */
|
477 | 05b4ff43 | ths | case GT_TC0:
|
478 | 05b4ff43 | ths | case GT_TC1:
|
479 | 05b4ff43 | ths | case GT_TC2:
|
480 | 05b4ff43 | ths | case GT_TC3:
|
481 | 05b4ff43 | ths | case GT_TC_CONTROL:
|
482 | 05b4ff43 | ths | /* Not implemented */
|
483 | d0f2c4c6 | malc | DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); |
484 | 05b4ff43 | ths | break;
|
485 | 05b4ff43 | ths | |
486 | fde7d5bd | ths | /* PCI Internal */
|
487 | fde7d5bd | ths | case GT_PCI0_CMD:
|
488 | fde7d5bd | ths | case GT_PCI1_CMD:
|
489 | fde7d5bd | ths | s->regs[saddr] = val & 0x0401fc0f;
|
490 | fde7d5bd | ths | break;
|
491 | 05b4ff43 | ths | case GT_PCI0_TOR:
|
492 | 05b4ff43 | ths | case GT_PCI0_BS_SCS10:
|
493 | 05b4ff43 | ths | case GT_PCI0_BS_SCS32:
|
494 | 05b4ff43 | ths | case GT_PCI0_BS_CS20:
|
495 | 05b4ff43 | ths | case GT_PCI0_BS_CS3BT:
|
496 | 05b4ff43 | ths | case GT_PCI1_IACK:
|
497 | 05b4ff43 | ths | case GT_PCI0_IACK:
|
498 | 05b4ff43 | ths | case GT_PCI0_BARE:
|
499 | 05b4ff43 | ths | case GT_PCI0_PREFMBR:
|
500 | 05b4ff43 | ths | case GT_PCI0_SCS10_BAR:
|
501 | 05b4ff43 | ths | case GT_PCI0_SCS32_BAR:
|
502 | 05b4ff43 | ths | case GT_PCI0_CS20_BAR:
|
503 | 05b4ff43 | ths | case GT_PCI0_CS3BT_BAR:
|
504 | 05b4ff43 | ths | case GT_PCI0_SSCS10_BAR:
|
505 | 05b4ff43 | ths | case GT_PCI0_SSCS32_BAR:
|
506 | 05b4ff43 | ths | case GT_PCI0_SCS3BT_BAR:
|
507 | 05b4ff43 | ths | case GT_PCI1_TOR:
|
508 | 05b4ff43 | ths | case GT_PCI1_BS_SCS10:
|
509 | 05b4ff43 | ths | case GT_PCI1_BS_SCS32:
|
510 | 05b4ff43 | ths | case GT_PCI1_BS_CS20:
|
511 | 05b4ff43 | ths | case GT_PCI1_BS_CS3BT:
|
512 | 05b4ff43 | ths | case GT_PCI1_BARE:
|
513 | 05b4ff43 | ths | case GT_PCI1_PREFMBR:
|
514 | 05b4ff43 | ths | case GT_PCI1_SCS10_BAR:
|
515 | 05b4ff43 | ths | case GT_PCI1_SCS32_BAR:
|
516 | 05b4ff43 | ths | case GT_PCI1_CS20_BAR:
|
517 | 05b4ff43 | ths | case GT_PCI1_CS3BT_BAR:
|
518 | 05b4ff43 | ths | case GT_PCI1_SSCS10_BAR:
|
519 | 05b4ff43 | ths | case GT_PCI1_SSCS32_BAR:
|
520 | 05b4ff43 | ths | case GT_PCI1_SCS3BT_BAR:
|
521 | 05b4ff43 | ths | case GT_PCI1_CFGADDR:
|
522 | 05b4ff43 | ths | case GT_PCI1_CFGDATA:
|
523 | 05b4ff43 | ths | /* not implemented */
|
524 | 05b4ff43 | ths | break;
|
525 | fde7d5bd | ths | case GT_PCI0_CFGADDR:
|
526 | c2dd2a23 | Aurelien Jarno | s->pci.config_reg = val & 0x80fffffc;
|
527 | fde7d5bd | ths | break;
|
528 | fde7d5bd | ths | case GT_PCI0_CFGDATA:
|
529 | c2dd2a23 | Aurelien Jarno | if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800)) |
530 | c6c99c3f | aurel32 | val = bswap32(val); |
531 | c2dd2a23 | Aurelien Jarno | if (s->pci.config_reg & (1u << 31)) |
532 | c2dd2a23 | Aurelien Jarno | pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
|
533 | 05b4ff43 | ths | break;
|
534 | 05b4ff43 | ths | |
535 | 05b4ff43 | ths | /* Interrupts */
|
536 | 05b4ff43 | ths | case GT_INTRCAUSE:
|
537 | 05b4ff43 | ths | /* not really implemented */
|
538 | 05b4ff43 | ths | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
|
539 | 05b4ff43 | ths | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
|
540 | d0f2c4c6 | malc | DPRINTF("INTRCAUSE %x\n", val);
|
541 | 05b4ff43 | ths | break;
|
542 | 05b4ff43 | ths | case GT_INTRMASK:
|
543 | 05b4ff43 | ths | s->regs[saddr] = val & 0x3c3ffffe;
|
544 | d0f2c4c6 | malc | DPRINTF("INTRMASK %x\n", val);
|
545 | 05b4ff43 | ths | break;
|
546 | 05b4ff43 | ths | case GT_PCI0_ICMASK:
|
547 | 05b4ff43 | ths | s->regs[saddr] = val & 0x03fffffe;
|
548 | d0f2c4c6 | malc | DPRINTF("ICMASK %x\n", val);
|
549 | 05b4ff43 | ths | break;
|
550 | 05b4ff43 | ths | case GT_PCI0_SERR0MASK:
|
551 | 05b4ff43 | ths | s->regs[saddr] = val & 0x0000003f;
|
552 | d0f2c4c6 | malc | DPRINTF("SERR0MASK %x\n", val);
|
553 | 05b4ff43 | ths | break;
|
554 | 05b4ff43 | ths | |
555 | 05b4ff43 | ths | /* Reserved when only PCI_0 is configured. */
|
556 | 05b4ff43 | ths | case GT_HINTRCAUSE:
|
557 | 05b4ff43 | ths | case GT_CPU_INTSEL:
|
558 | 05b4ff43 | ths | case GT_PCI0_INTSEL:
|
559 | 05b4ff43 | ths | case GT_HINTRMASK:
|
560 | 05b4ff43 | ths | case GT_PCI0_HICMASK:
|
561 | 05b4ff43 | ths | case GT_PCI1_SERR1MASK:
|
562 | 05b4ff43 | ths | /* not implemented */
|
563 | fde7d5bd | ths | break;
|
564 | fde7d5bd | ths | |
565 | 0da75eb1 | ths | /* SDRAM Parameters */
|
566 | 0da75eb1 | ths | case GT_SDRAM_B0:
|
567 | 0da75eb1 | ths | case GT_SDRAM_B1:
|
568 | 0da75eb1 | ths | case GT_SDRAM_B2:
|
569 | 0da75eb1 | ths | case GT_SDRAM_B3:
|
570 | 0da75eb1 | ths | /* We don't simulate electrical parameters of the SDRAM.
|
571 | 0da75eb1 | ths | Accept, but ignore the values. */
|
572 | 0da75eb1 | ths | s->regs[saddr] = val; |
573 | 0da75eb1 | ths | break;
|
574 | 0da75eb1 | ths | |
575 | fde7d5bd | ths | default:
|
576 | d0f2c4c6 | malc | DPRINTF ("Bad register offset 0x%x\n", (int)addr); |
577 | fde7d5bd | ths | break;
|
578 | fde7d5bd | ths | } |
579 | fde7d5bd | ths | } |
580 | fde7d5bd | ths | |
581 | fde7d5bd | ths | static uint32_t gt64120_readl (void *opaque, |
582 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
583 | fde7d5bd | ths | { |
584 | fde7d5bd | ths | GT64120State *s = opaque; |
585 | fde7d5bd | ths | uint32_t val; |
586 | fde7d5bd | ths | uint32_t saddr; |
587 | fde7d5bd | ths | |
588 | fde7d5bd | ths | saddr = (addr & 0xfff) >> 2; |
589 | fde7d5bd | ths | switch (saddr) {
|
590 | fde7d5bd | ths | |
591 | 0da75eb1 | ths | /* CPU Configuration */
|
592 | 0da75eb1 | ths | case GT_MULTI:
|
593 | 0da75eb1 | ths | /* Only one GT64xxx is present on the CPU bus, return
|
594 | 0da75eb1 | ths | the initial value */
|
595 | 0da75eb1 | ths | val = s->regs[saddr]; |
596 | 0da75eb1 | ths | break;
|
597 | 0da75eb1 | ths | |
598 | fde7d5bd | ths | /* CPU Error Report */
|
599 | fde7d5bd | ths | case GT_CPUERR_ADDRLO:
|
600 | fde7d5bd | ths | case GT_CPUERR_ADDRHI:
|
601 | fde7d5bd | ths | case GT_CPUERR_DATALO:
|
602 | fde7d5bd | ths | case GT_CPUERR_DATAHI:
|
603 | fde7d5bd | ths | case GT_CPUERR_PARITY:
|
604 | 0da75eb1 | ths | /* Emulated memory has no error, always return the initial
|
605 | 5fafdf24 | ths | values */
|
606 | 0da75eb1 | ths | val = s->regs[saddr]; |
607 | 0da75eb1 | ths | break;
|
608 | 0da75eb1 | ths | |
609 | 0da75eb1 | ths | /* CPU Sync Barrier */
|
610 | 0da75eb1 | ths | case GT_PCI0SYNC:
|
611 | 0da75eb1 | ths | case GT_PCI1SYNC:
|
612 | 0da75eb1 | ths | /* Reading those register should empty all FIFO on the PCI
|
613 | 0da75eb1 | ths | bus, which are not emulated. The return value should be
|
614 | 0da75eb1 | ths | a random value that should be ignored. */
|
615 | 5fafdf24 | ths | val = 0xc000ffee;
|
616 | fde7d5bd | ths | break;
|
617 | fde7d5bd | ths | |
618 | fde7d5bd | ths | /* ECC */
|
619 | fde7d5bd | ths | case GT_ECC_ERRDATALO:
|
620 | fde7d5bd | ths | case GT_ECC_ERRDATAHI:
|
621 | fde7d5bd | ths | case GT_ECC_MEM:
|
622 | fde7d5bd | ths | case GT_ECC_CALC:
|
623 | fde7d5bd | ths | case GT_ECC_ERRADDR:
|
624 | 0da75eb1 | ths | /* Emulated memory has no error, always return the initial
|
625 | 5fafdf24 | ths | values */
|
626 | 0da75eb1 | ths | val = s->regs[saddr]; |
627 | fde7d5bd | ths | break;
|
628 | fde7d5bd | ths | |
629 | fde7d5bd | ths | case GT_CPU:
|
630 | 05b4ff43 | ths | case GT_SCS10LD:
|
631 | 05b4ff43 | ths | case GT_SCS10HD:
|
632 | 05b4ff43 | ths | case GT_SCS32LD:
|
633 | 05b4ff43 | ths | case GT_SCS32HD:
|
634 | 05b4ff43 | ths | case GT_CS20LD:
|
635 | 05b4ff43 | ths | case GT_CS20HD:
|
636 | 05b4ff43 | ths | case GT_CS3BOOTLD:
|
637 | 05b4ff43 | ths | case GT_CS3BOOTHD:
|
638 | 05b4ff43 | ths | case GT_SCS10AR:
|
639 | 05b4ff43 | ths | case GT_SCS32AR:
|
640 | 05b4ff43 | ths | case GT_CS20R:
|
641 | 05b4ff43 | ths | case GT_CS3BOOTR:
|
642 | fde7d5bd | ths | case GT_PCI0IOLD:
|
643 | fde7d5bd | ths | case GT_PCI0M0LD:
|
644 | fde7d5bd | ths | case GT_PCI0M1LD:
|
645 | fde7d5bd | ths | case GT_PCI1IOLD:
|
646 | fde7d5bd | ths | case GT_PCI1M0LD:
|
647 | fde7d5bd | ths | case GT_PCI1M1LD:
|
648 | fde7d5bd | ths | case GT_PCI0IOHD:
|
649 | fde7d5bd | ths | case GT_PCI0M0HD:
|
650 | fde7d5bd | ths | case GT_PCI0M1HD:
|
651 | fde7d5bd | ths | case GT_PCI1IOHD:
|
652 | fde7d5bd | ths | case GT_PCI1M0HD:
|
653 | fde7d5bd | ths | case GT_PCI1M1HD:
|
654 | fde7d5bd | ths | case GT_PCI0IOREMAP:
|
655 | fde7d5bd | ths | case GT_PCI0M0REMAP:
|
656 | fde7d5bd | ths | case GT_PCI0M1REMAP:
|
657 | fde7d5bd | ths | case GT_PCI1IOREMAP:
|
658 | fde7d5bd | ths | case GT_PCI1M0REMAP:
|
659 | fde7d5bd | ths | case GT_PCI1M1REMAP:
|
660 | 05b4ff43 | ths | case GT_ISD:
|
661 | fde7d5bd | ths | val = s->regs[saddr]; |
662 | fde7d5bd | ths | break;
|
663 | fde7d5bd | ths | case GT_PCI0_IACK:
|
664 | 5fafdf24 | ths | /* Read the IRQ number */
|
665 | 4de9b249 | ths | val = pic_read_irq(isa_pic); |
666 | fde7d5bd | ths | break;
|
667 | fde7d5bd | ths | |
668 | 05b4ff43 | ths | /* SDRAM and Device Address Decode */
|
669 | 05b4ff43 | ths | case GT_SCS0LD:
|
670 | 05b4ff43 | ths | case GT_SCS0HD:
|
671 | 05b4ff43 | ths | case GT_SCS1LD:
|
672 | 05b4ff43 | ths | case GT_SCS1HD:
|
673 | 05b4ff43 | ths | case GT_SCS2LD:
|
674 | 05b4ff43 | ths | case GT_SCS2HD:
|
675 | 05b4ff43 | ths | case GT_SCS3LD:
|
676 | 05b4ff43 | ths | case GT_SCS3HD:
|
677 | 05b4ff43 | ths | case GT_CS0LD:
|
678 | 05b4ff43 | ths | case GT_CS0HD:
|
679 | 05b4ff43 | ths | case GT_CS1LD:
|
680 | 05b4ff43 | ths | case GT_CS1HD:
|
681 | 05b4ff43 | ths | case GT_CS2LD:
|
682 | 05b4ff43 | ths | case GT_CS2HD:
|
683 | 05b4ff43 | ths | case GT_CS3LD:
|
684 | 05b4ff43 | ths | case GT_CS3HD:
|
685 | 05b4ff43 | ths | case GT_BOOTLD:
|
686 | 05b4ff43 | ths | case GT_BOOTHD:
|
687 | 05b4ff43 | ths | case GT_ADERR:
|
688 | 05b4ff43 | ths | val = s->regs[saddr]; |
689 | 05b4ff43 | ths | break;
|
690 | 05b4ff43 | ths | |
691 | 05b4ff43 | ths | /* SDRAM Configuration */
|
692 | 05b4ff43 | ths | case GT_SDRAM_CFG:
|
693 | 05b4ff43 | ths | case GT_SDRAM_OPMODE:
|
694 | 05b4ff43 | ths | case GT_SDRAM_BM:
|
695 | 05b4ff43 | ths | case GT_SDRAM_ADDRDECODE:
|
696 | 05b4ff43 | ths | val = s->regs[saddr]; |
697 | 05b4ff43 | ths | break;
|
698 | 05b4ff43 | ths | |
699 | 0da75eb1 | ths | /* SDRAM Parameters */
|
700 | 0da75eb1 | ths | case GT_SDRAM_B0:
|
701 | 0da75eb1 | ths | case GT_SDRAM_B1:
|
702 | 0da75eb1 | ths | case GT_SDRAM_B2:
|
703 | 0da75eb1 | ths | case GT_SDRAM_B3:
|
704 | 0da75eb1 | ths | /* We don't simulate electrical parameters of the SDRAM.
|
705 | 0da75eb1 | ths | Just return the last written value. */
|
706 | 0da75eb1 | ths | val = s->regs[saddr]; |
707 | 0da75eb1 | ths | break;
|
708 | 0da75eb1 | ths | |
709 | 05b4ff43 | ths | /* Device Parameters */
|
710 | 05b4ff43 | ths | case GT_DEV_B0:
|
711 | 05b4ff43 | ths | case GT_DEV_B1:
|
712 | 05b4ff43 | ths | case GT_DEV_B2:
|
713 | 05b4ff43 | ths | case GT_DEV_B3:
|
714 | 05b4ff43 | ths | case GT_DEV_BOOT:
|
715 | 05b4ff43 | ths | val = s->regs[saddr]; |
716 | 05b4ff43 | ths | break;
|
717 | 05b4ff43 | ths | |
718 | 05b4ff43 | ths | /* DMA Record */
|
719 | 05b4ff43 | ths | case GT_DMA0_CNT:
|
720 | 05b4ff43 | ths | case GT_DMA1_CNT:
|
721 | 05b4ff43 | ths | case GT_DMA2_CNT:
|
722 | 05b4ff43 | ths | case GT_DMA3_CNT:
|
723 | 05b4ff43 | ths | case GT_DMA0_SA:
|
724 | 05b4ff43 | ths | case GT_DMA1_SA:
|
725 | 05b4ff43 | ths | case GT_DMA2_SA:
|
726 | 05b4ff43 | ths | case GT_DMA3_SA:
|
727 | 05b4ff43 | ths | case GT_DMA0_DA:
|
728 | 05b4ff43 | ths | case GT_DMA1_DA:
|
729 | 05b4ff43 | ths | case GT_DMA2_DA:
|
730 | 05b4ff43 | ths | case GT_DMA3_DA:
|
731 | 05b4ff43 | ths | case GT_DMA0_NEXT:
|
732 | 05b4ff43 | ths | case GT_DMA1_NEXT:
|
733 | 05b4ff43 | ths | case GT_DMA2_NEXT:
|
734 | 05b4ff43 | ths | case GT_DMA3_NEXT:
|
735 | 05b4ff43 | ths | case GT_DMA0_CUR:
|
736 | 05b4ff43 | ths | case GT_DMA1_CUR:
|
737 | 05b4ff43 | ths | case GT_DMA2_CUR:
|
738 | 05b4ff43 | ths | case GT_DMA3_CUR:
|
739 | 05b4ff43 | ths | val = s->regs[saddr]; |
740 | 05b4ff43 | ths | break;
|
741 | 05b4ff43 | ths | |
742 | 05b4ff43 | ths | /* DMA Channel Control */
|
743 | 05b4ff43 | ths | case GT_DMA0_CTRL:
|
744 | 05b4ff43 | ths | case GT_DMA1_CTRL:
|
745 | 05b4ff43 | ths | case GT_DMA2_CTRL:
|
746 | 05b4ff43 | ths | case GT_DMA3_CTRL:
|
747 | 05b4ff43 | ths | val = s->regs[saddr]; |
748 | 05b4ff43 | ths | break;
|
749 | 05b4ff43 | ths | |
750 | 05b4ff43 | ths | /* DMA Arbiter */
|
751 | 05b4ff43 | ths | case GT_DMA_ARB:
|
752 | 05b4ff43 | ths | val = s->regs[saddr]; |
753 | 05b4ff43 | ths | break;
|
754 | 05b4ff43 | ths | |
755 | 05b4ff43 | ths | /* Timer/Counter */
|
756 | 05b4ff43 | ths | case GT_TC0:
|
757 | 05b4ff43 | ths | case GT_TC1:
|
758 | 05b4ff43 | ths | case GT_TC2:
|
759 | 05b4ff43 | ths | case GT_TC3:
|
760 | 05b4ff43 | ths | case GT_TC_CONTROL:
|
761 | 05b4ff43 | ths | val = s->regs[saddr]; |
762 | 05b4ff43 | ths | break;
|
763 | 05b4ff43 | ths | |
764 | fde7d5bd | ths | /* PCI Internal */
|
765 | fde7d5bd | ths | case GT_PCI0_CFGADDR:
|
766 | c2dd2a23 | Aurelien Jarno | val = s->pci.config_reg; |
767 | fde7d5bd | ths | break;
|
768 | fde7d5bd | ths | case GT_PCI0_CFGDATA:
|
769 | c2dd2a23 | Aurelien Jarno | if (!(s->pci.config_reg & (1 << 31))) |
770 | c6c99c3f | aurel32 | val = 0xffffffff;
|
771 | c6c99c3f | aurel32 | else
|
772 | c2dd2a23 | Aurelien Jarno | val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
|
773 | c2dd2a23 | Aurelien Jarno | if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800)) |
774 | c6c99c3f | aurel32 | val = bswap32(val); |
775 | 05b4ff43 | ths | break;
|
776 | 05b4ff43 | ths | |
777 | 05b4ff43 | ths | case GT_PCI0_CMD:
|
778 | 05b4ff43 | ths | case GT_PCI0_TOR:
|
779 | 05b4ff43 | ths | case GT_PCI0_BS_SCS10:
|
780 | 05b4ff43 | ths | case GT_PCI0_BS_SCS32:
|
781 | 05b4ff43 | ths | case GT_PCI0_BS_CS20:
|
782 | 05b4ff43 | ths | case GT_PCI0_BS_CS3BT:
|
783 | 05b4ff43 | ths | case GT_PCI1_IACK:
|
784 | 05b4ff43 | ths | case GT_PCI0_BARE:
|
785 | 05b4ff43 | ths | case GT_PCI0_PREFMBR:
|
786 | 05b4ff43 | ths | case GT_PCI0_SCS10_BAR:
|
787 | 05b4ff43 | ths | case GT_PCI0_SCS32_BAR:
|
788 | 05b4ff43 | ths | case GT_PCI0_CS20_BAR:
|
789 | 05b4ff43 | ths | case GT_PCI0_CS3BT_BAR:
|
790 | 05b4ff43 | ths | case GT_PCI0_SSCS10_BAR:
|
791 | 05b4ff43 | ths | case GT_PCI0_SSCS32_BAR:
|
792 | 05b4ff43 | ths | case GT_PCI0_SCS3BT_BAR:
|
793 | 05b4ff43 | ths | case GT_PCI1_CMD:
|
794 | 05b4ff43 | ths | case GT_PCI1_TOR:
|
795 | 05b4ff43 | ths | case GT_PCI1_BS_SCS10:
|
796 | 05b4ff43 | ths | case GT_PCI1_BS_SCS32:
|
797 | 05b4ff43 | ths | case GT_PCI1_BS_CS20:
|
798 | 05b4ff43 | ths | case GT_PCI1_BS_CS3BT:
|
799 | 05b4ff43 | ths | case GT_PCI1_BARE:
|
800 | 05b4ff43 | ths | case GT_PCI1_PREFMBR:
|
801 | 05b4ff43 | ths | case GT_PCI1_SCS10_BAR:
|
802 | 05b4ff43 | ths | case GT_PCI1_SCS32_BAR:
|
803 | 05b4ff43 | ths | case GT_PCI1_CS20_BAR:
|
804 | 05b4ff43 | ths | case GT_PCI1_CS3BT_BAR:
|
805 | 05b4ff43 | ths | case GT_PCI1_SSCS10_BAR:
|
806 | 05b4ff43 | ths | case GT_PCI1_SSCS32_BAR:
|
807 | 05b4ff43 | ths | case GT_PCI1_SCS3BT_BAR:
|
808 | 05b4ff43 | ths | case GT_PCI1_CFGADDR:
|
809 | 05b4ff43 | ths | case GT_PCI1_CFGDATA:
|
810 | 05b4ff43 | ths | val = s->regs[saddr]; |
811 | 05b4ff43 | ths | break;
|
812 | 05b4ff43 | ths | |
813 | 05b4ff43 | ths | /* Interrupts */
|
814 | 05b4ff43 | ths | case GT_INTRCAUSE:
|
815 | 05b4ff43 | ths | val = s->regs[saddr]; |
816 | d0f2c4c6 | malc | DPRINTF("INTRCAUSE %x\n", val);
|
817 | 05b4ff43 | ths | break;
|
818 | 05b4ff43 | ths | case GT_INTRMASK:
|
819 | 05b4ff43 | ths | val = s->regs[saddr]; |
820 | d0f2c4c6 | malc | DPRINTF("INTRMASK %x\n", val);
|
821 | 05b4ff43 | ths | break;
|
822 | 05b4ff43 | ths | case GT_PCI0_ICMASK:
|
823 | 05b4ff43 | ths | val = s->regs[saddr]; |
824 | d0f2c4c6 | malc | DPRINTF("ICMASK %x\n", val);
|
825 | 05b4ff43 | ths | break;
|
826 | 05b4ff43 | ths | case GT_PCI0_SERR0MASK:
|
827 | 05b4ff43 | ths | val = s->regs[saddr]; |
828 | d0f2c4c6 | malc | DPRINTF("SERR0MASK %x\n", val);
|
829 | 05b4ff43 | ths | break;
|
830 | 05b4ff43 | ths | |
831 | 05b4ff43 | ths | /* Reserved when only PCI_0 is configured. */
|
832 | 05b4ff43 | ths | case GT_HINTRCAUSE:
|
833 | 05b4ff43 | ths | case GT_CPU_INTSEL:
|
834 | 05b4ff43 | ths | case GT_PCI0_INTSEL:
|
835 | 05b4ff43 | ths | case GT_HINTRMASK:
|
836 | 05b4ff43 | ths | case GT_PCI0_HICMASK:
|
837 | 05b4ff43 | ths | case GT_PCI1_SERR1MASK:
|
838 | 05b4ff43 | ths | val = s->regs[saddr]; |
839 | fde7d5bd | ths | break;
|
840 | fde7d5bd | ths | |
841 | fde7d5bd | ths | default:
|
842 | fde7d5bd | ths | val = s->regs[saddr]; |
843 | d0f2c4c6 | malc | DPRINTF ("Bad register offset 0x%x\n", (int)addr); |
844 | fde7d5bd | ths | break;
|
845 | fde7d5bd | ths | } |
846 | fde7d5bd | ths | |
847 | c6c99c3f | aurel32 | if (!(s->regs[GT_CPU] & 0x00001000)) |
848 | 1931e260 | ths | val = bswap32(val); |
849 | 1931e260 | ths | |
850 | 05b4ff43 | ths | return val;
|
851 | fde7d5bd | ths | } |
852 | fde7d5bd | ths | |
853 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const gt64120_write[] = { |
854 | fde7d5bd | ths | >64120_writel, |
855 | fde7d5bd | ths | >64120_writel, |
856 | fde7d5bd | ths | >64120_writel, |
857 | fde7d5bd | ths | }; |
858 | fde7d5bd | ths | |
859 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const gt64120_read[] = { |
860 | fde7d5bd | ths | >64120_readl, |
861 | fde7d5bd | ths | >64120_readl, |
862 | fde7d5bd | ths | >64120_readl, |
863 | fde7d5bd | ths | }; |
864 | fde7d5bd | ths | |
865 | c2dd2a23 | Aurelien Jarno | static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
866 | fde7d5bd | ths | { |
867 | fde7d5bd | ths | int slot;
|
868 | fde7d5bd | ths | |
869 | fde7d5bd | ths | slot = (pci_dev->devfn >> 3);
|
870 | fde7d5bd | ths | |
871 | fde7d5bd | ths | switch (slot) {
|
872 | fde7d5bd | ths | /* PIIX4 USB */
|
873 | fde7d5bd | ths | case 10: |
874 | fde7d5bd | ths | return 3; |
875 | fde7d5bd | ths | /* AMD 79C973 Ethernet */
|
876 | fde7d5bd | ths | case 11: |
877 | d4a4d056 | ths | return 1; |
878 | fde7d5bd | ths | /* Crystal 4281 Sound */
|
879 | fde7d5bd | ths | case 12: |
880 | d4a4d056 | ths | return 2; |
881 | fde7d5bd | ths | /* PCI slot 1 to 4 */
|
882 | fde7d5bd | ths | case 18 ... 21: |
883 | fde7d5bd | ths | return ((slot - 18) + irq_num) & 0x03; |
884 | fde7d5bd | ths | /* Unknown device, don't do any translation */
|
885 | fde7d5bd | ths | default:
|
886 | fde7d5bd | ths | return irq_num;
|
887 | fde7d5bd | ths | } |
888 | fde7d5bd | ths | } |
889 | fde7d5bd | ths | |
890 | fde7d5bd | ths | static int pci_irq_levels[4]; |
891 | fde7d5bd | ths | |
892 | c2dd2a23 | Aurelien Jarno | static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) |
893 | fde7d5bd | ths | { |
894 | fde7d5bd | ths | int i, pic_irq, pic_level;
|
895 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
896 | fde7d5bd | ths | |
897 | fde7d5bd | ths | pci_irq_levels[irq_num] = level; |
898 | fde7d5bd | ths | |
899 | fde7d5bd | ths | /* now we change the pic irq level according to the piix irq mappings */
|
900 | fde7d5bd | ths | /* XXX: optimize */
|
901 | fde7d5bd | ths | pic_irq = piix4_dev->config[0x60 + irq_num];
|
902 | fde7d5bd | ths | if (pic_irq < 16) { |
903 | fde7d5bd | ths | /* The pic level is the logical OR of all the PCI irqs mapped
|
904 | fde7d5bd | ths | to it */
|
905 | fde7d5bd | ths | pic_level = 0;
|
906 | fde7d5bd | ths | for (i = 0; i < 4; i++) { |
907 | fde7d5bd | ths | if (pic_irq == piix4_dev->config[0x60 + i]) |
908 | fde7d5bd | ths | pic_level |= pci_irq_levels[i]; |
909 | fde7d5bd | ths | } |
910 | d537cf6c | pbrook | qemu_set_irq(pic[pic_irq], pic_level); |
911 | fde7d5bd | ths | } |
912 | fde7d5bd | ths | } |
913 | fde7d5bd | ths | |
914 | fde7d5bd | ths | |
915 | 9596ebb7 | pbrook | static void gt64120_reset(void *opaque) |
916 | fde7d5bd | ths | { |
917 | fde7d5bd | ths | GT64120State *s = opaque; |
918 | fde7d5bd | ths | |
919 | 30b6f3a8 | ths | /* FIXME: Malta specific hw assumptions ahead */
|
920 | 30b6f3a8 | ths | |
921 | fde7d5bd | ths | /* CPU Configuration */
|
922 | fde7d5bd | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
923 | fde7d5bd | ths | s->regs[GT_CPU] = 0x00000000;
|
924 | fde7d5bd | ths | #else
|
925 | bc687ec9 | ths | s->regs[GT_CPU] = 0x00001000;
|
926 | fde7d5bd | ths | #endif
|
927 | 30b6f3a8 | ths | s->regs[GT_MULTI] = 0x00000003;
|
928 | 30b6f3a8 | ths | |
929 | 30b6f3a8 | ths | /* CPU Address decode */
|
930 | 30b6f3a8 | ths | s->regs[GT_SCS10LD] = 0x00000000;
|
931 | 30b6f3a8 | ths | s->regs[GT_SCS10HD] = 0x00000007;
|
932 | 30b6f3a8 | ths | s->regs[GT_SCS32LD] = 0x00000008;
|
933 | 30b6f3a8 | ths | s->regs[GT_SCS32HD] = 0x0000000f;
|
934 | 30b6f3a8 | ths | s->regs[GT_CS20LD] = 0x000000e0;
|
935 | 30b6f3a8 | ths | s->regs[GT_CS20HD] = 0x00000070;
|
936 | 30b6f3a8 | ths | s->regs[GT_CS3BOOTLD] = 0x000000f8;
|
937 | 30b6f3a8 | ths | s->regs[GT_CS3BOOTHD] = 0x0000007f;
|
938 | fde7d5bd | ths | |
939 | fde7d5bd | ths | s->regs[GT_PCI0IOLD] = 0x00000080;
|
940 | fde7d5bd | ths | s->regs[GT_PCI0IOHD] = 0x0000000f;
|
941 | fde7d5bd | ths | s->regs[GT_PCI0M0LD] = 0x00000090;
|
942 | fde7d5bd | ths | s->regs[GT_PCI0M0HD] = 0x0000001f;
|
943 | 30b6f3a8 | ths | s->regs[GT_ISD] = 0x000000a0;
|
944 | fde7d5bd | ths | s->regs[GT_PCI0M1LD] = 0x00000790;
|
945 | fde7d5bd | ths | s->regs[GT_PCI0M1HD] = 0x0000001f;
|
946 | fde7d5bd | ths | s->regs[GT_PCI1IOLD] = 0x00000100;
|
947 | fde7d5bd | ths | s->regs[GT_PCI1IOHD] = 0x0000000f;
|
948 | fde7d5bd | ths | s->regs[GT_PCI1M0LD] = 0x00000110;
|
949 | fde7d5bd | ths | s->regs[GT_PCI1M0HD] = 0x0000001f;
|
950 | fde7d5bd | ths | s->regs[GT_PCI1M1LD] = 0x00000120;
|
951 | fde7d5bd | ths | s->regs[GT_PCI1M1HD] = 0x0000002f;
|
952 | 30b6f3a8 | ths | |
953 | 30b6f3a8 | ths | s->regs[GT_SCS10AR] = 0x00000000;
|
954 | 30b6f3a8 | ths | s->regs[GT_SCS32AR] = 0x00000008;
|
955 | 30b6f3a8 | ths | s->regs[GT_CS20R] = 0x000000e0;
|
956 | 30b6f3a8 | ths | s->regs[GT_CS3BOOTR] = 0x000000f8;
|
957 | 30b6f3a8 | ths | |
958 | fde7d5bd | ths | s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
959 | fde7d5bd | ths | s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
960 | fde7d5bd | ths | s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
961 | fde7d5bd | ths | s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
962 | fde7d5bd | ths | s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
963 | fde7d5bd | ths | s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
964 | fde7d5bd | ths | |
965 | fde7d5bd | ths | /* CPU Error Report */
|
966 | fde7d5bd | ths | s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
967 | fde7d5bd | ths | s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
968 | fde7d5bd | ths | s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
969 | fde7d5bd | ths | s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
970 | fde7d5bd | ths | s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
971 | fde7d5bd | ths | |
972 | 30b6f3a8 | ths | /* CPU Sync Barrier */
|
973 | 30b6f3a8 | ths | s->regs[GT_PCI0SYNC] = 0x00000000;
|
974 | 30b6f3a8 | ths | s->regs[GT_PCI1SYNC] = 0x00000000;
|
975 | 30b6f3a8 | ths | |
976 | 30b6f3a8 | ths | /* SDRAM and Device Address Decode */
|
977 | 30b6f3a8 | ths | s->regs[GT_SCS0LD] = 0x00000000;
|
978 | 30b6f3a8 | ths | s->regs[GT_SCS0HD] = 0x00000007;
|
979 | 30b6f3a8 | ths | s->regs[GT_SCS1LD] = 0x00000008;
|
980 | 30b6f3a8 | ths | s->regs[GT_SCS1HD] = 0x0000000f;
|
981 | 30b6f3a8 | ths | s->regs[GT_SCS2LD] = 0x00000010;
|
982 | 30b6f3a8 | ths | s->regs[GT_SCS2HD] = 0x00000017;
|
983 | 30b6f3a8 | ths | s->regs[GT_SCS3LD] = 0x00000018;
|
984 | 30b6f3a8 | ths | s->regs[GT_SCS3HD] = 0x0000001f;
|
985 | 30b6f3a8 | ths | s->regs[GT_CS0LD] = 0x000000c0;
|
986 | 30b6f3a8 | ths | s->regs[GT_CS0HD] = 0x000000c7;
|
987 | 30b6f3a8 | ths | s->regs[GT_CS1LD] = 0x000000c8;
|
988 | 30b6f3a8 | ths | s->regs[GT_CS1HD] = 0x000000cf;
|
989 | 30b6f3a8 | ths | s->regs[GT_CS2LD] = 0x000000d0;
|
990 | 30b6f3a8 | ths | s->regs[GT_CS2HD] = 0x000000df;
|
991 | 30b6f3a8 | ths | s->regs[GT_CS3LD] = 0x000000f0;
|
992 | 30b6f3a8 | ths | s->regs[GT_CS3HD] = 0x000000fb;
|
993 | 30b6f3a8 | ths | s->regs[GT_BOOTLD] = 0x000000fc;
|
994 | 30b6f3a8 | ths | s->regs[GT_BOOTHD] = 0x000000ff;
|
995 | 30b6f3a8 | ths | s->regs[GT_ADERR] = 0xffffffff;
|
996 | 30b6f3a8 | ths | |
997 | 30b6f3a8 | ths | /* SDRAM Configuration */
|
998 | 30b6f3a8 | ths | s->regs[GT_SDRAM_CFG] = 0x00000200;
|
999 | 30b6f3a8 | ths | s->regs[GT_SDRAM_OPMODE] = 0x00000000;
|
1000 | 30b6f3a8 | ths | s->regs[GT_SDRAM_BM] = 0x00000007;
|
1001 | 30b6f3a8 | ths | s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
|
1002 | 30b6f3a8 | ths | |
1003 | 30b6f3a8 | ths | /* SDRAM Parameters */
|
1004 | 30b6f3a8 | ths | s->regs[GT_SDRAM_B0] = 0x00000005;
|
1005 | 30b6f3a8 | ths | s->regs[GT_SDRAM_B1] = 0x00000005;
|
1006 | 30b6f3a8 | ths | s->regs[GT_SDRAM_B2] = 0x00000005;
|
1007 | 30b6f3a8 | ths | s->regs[GT_SDRAM_B3] = 0x00000005;
|
1008 | 30b6f3a8 | ths | |
1009 | fde7d5bd | ths | /* ECC */
|
1010 | fde7d5bd | ths | s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
1011 | fde7d5bd | ths | s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
1012 | fde7d5bd | ths | s->regs[GT_ECC_MEM] = 0x00000000;
|
1013 | fde7d5bd | ths | s->regs[GT_ECC_CALC] = 0x00000000;
|
1014 | fde7d5bd | ths | s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
1015 | fde7d5bd | ths | |
1016 | 30b6f3a8 | ths | /* Device Parameters */
|
1017 | 30b6f3a8 | ths | s->regs[GT_DEV_B0] = 0x386fffff;
|
1018 | 30b6f3a8 | ths | s->regs[GT_DEV_B1] = 0x386fffff;
|
1019 | 30b6f3a8 | ths | s->regs[GT_DEV_B2] = 0x386fffff;
|
1020 | 30b6f3a8 | ths | s->regs[GT_DEV_B3] = 0x386fffff;
|
1021 | 30b6f3a8 | ths | s->regs[GT_DEV_BOOT] = 0x146fffff;
|
1022 | 0da75eb1 | ths | |
1023 | 30b6f3a8 | ths | /* DMA registers are all zeroed at reset */
|
1024 | 30b6f3a8 | ths | |
1025 | 30b6f3a8 | ths | /* Timer/Counter */
|
1026 | 30b6f3a8 | ths | s->regs[GT_TC0] = 0xffffffff;
|
1027 | 30b6f3a8 | ths | s->regs[GT_TC1] = 0x00ffffff;
|
1028 | 30b6f3a8 | ths | s->regs[GT_TC2] = 0x00ffffff;
|
1029 | 30b6f3a8 | ths | s->regs[GT_TC3] = 0x00ffffff;
|
1030 | 30b6f3a8 | ths | s->regs[GT_TC_CONTROL] = 0x00000000;
|
1031 | 30b6f3a8 | ths | |
1032 | 30b6f3a8 | ths | /* PCI Internal */
|
1033 | fde7d5bd | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
1034 | fde7d5bd | ths | s->regs[GT_PCI0_CMD] = 0x00000000;
|
1035 | fde7d5bd | ths | #else
|
1036 | fde7d5bd | ths | s->regs[GT_PCI0_CMD] = 0x00010001;
|
1037 | fde7d5bd | ths | #endif
|
1038 | 30b6f3a8 | ths | s->regs[GT_PCI0_TOR] = 0x0000070f;
|
1039 | 30b6f3a8 | ths | s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
|
1040 | 30b6f3a8 | ths | s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
|
1041 | 30b6f3a8 | ths | s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
|
1042 | 30b6f3a8 | ths | s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
|
1043 | fde7d5bd | ths | s->regs[GT_PCI1_IACK] = 0x00000000;
|
1044 | 30b6f3a8 | ths | s->regs[GT_PCI0_IACK] = 0x00000000;
|
1045 | 30b6f3a8 | ths | s->regs[GT_PCI0_BARE] = 0x0000000f;
|
1046 | 30b6f3a8 | ths | s->regs[GT_PCI0_PREFMBR] = 0x00000040;
|
1047 | 30b6f3a8 | ths | s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
|
1048 | 30b6f3a8 | ths | s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
|
1049 | 30b6f3a8 | ths | s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
|
1050 | 30b6f3a8 | ths | s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
|
1051 | 30b6f3a8 | ths | s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
|
1052 | 30b6f3a8 | ths | s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
|
1053 | 30b6f3a8 | ths | s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
|
1054 | 30b6f3a8 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
1055 | 30b6f3a8 | ths | s->regs[GT_PCI1_CMD] = 0x00000000;
|
1056 | 30b6f3a8 | ths | #else
|
1057 | 30b6f3a8 | ths | s->regs[GT_PCI1_CMD] = 0x00010001;
|
1058 | 30b6f3a8 | ths | #endif
|
1059 | 30b6f3a8 | ths | s->regs[GT_PCI1_TOR] = 0x0000070f;
|
1060 | 30b6f3a8 | ths | s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
|
1061 | 30b6f3a8 | ths | s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
|
1062 | 30b6f3a8 | ths | s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
|
1063 | 30b6f3a8 | ths | s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
|
1064 | 30b6f3a8 | ths | s->regs[GT_PCI1_BARE] = 0x0000000f;
|
1065 | 30b6f3a8 | ths | s->regs[GT_PCI1_PREFMBR] = 0x00000040;
|
1066 | 30b6f3a8 | ths | s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
|
1067 | 30b6f3a8 | ths | s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
|
1068 | 30b6f3a8 | ths | s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
|
1069 | 30b6f3a8 | ths | s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
|
1070 | 30b6f3a8 | ths | s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
|
1071 | 30b6f3a8 | ths | s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
|
1072 | 30b6f3a8 | ths | s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
|
1073 | 30b6f3a8 | ths | s->regs[GT_PCI1_CFGADDR] = 0x00000000;
|
1074 | 30b6f3a8 | ths | s->regs[GT_PCI1_CFGDATA] = 0x00000000;
|
1075 | 30b6f3a8 | ths | s->regs[GT_PCI0_CFGADDR] = 0x00000000;
|
1076 | 30b6f3a8 | ths | |
1077 | 30b6f3a8 | ths | /* Interrupt registers are all zeroed at reset */
|
1078 | fde7d5bd | ths | |
1079 | a0a8793e | ths | gt64120_isd_mapping(s); |
1080 | 9414cc6f | ths | gt64120_pci_mapping(s); |
1081 | fde7d5bd | ths | } |
1082 | fde7d5bd | ths | |
1083 | 1823082c | ths | static void gt64120_save(QEMUFile* f, void *opaque) |
1084 | 1823082c | ths | { |
1085 | 1823082c | ths | PCIDevice *d = opaque; |
1086 | 1823082c | ths | pci_device_save(d, f); |
1087 | 1823082c | ths | } |
1088 | 1823082c | ths | |
1089 | 1823082c | ths | static int gt64120_load(QEMUFile* f, void *opaque, int version_id) |
1090 | 1823082c | ths | { |
1091 | 1823082c | ths | PCIDevice *d = opaque; |
1092 | 1823082c | ths | int ret;
|
1093 | 1823082c | ths | |
1094 | 1823082c | ths | if (version_id != 1) |
1095 | 1823082c | ths | return -EINVAL;
|
1096 | 1823082c | ths | ret = pci_device_load(d, f); |
1097 | 1823082c | ths | if (ret < 0) |
1098 | 1823082c | ths | return ret;
|
1099 | 1823082c | ths | return 0; |
1100 | 1823082c | ths | } |
1101 | 1823082c | ths | |
1102 | c2dd2a23 | Aurelien Jarno | PCIBus *gt64120_register(qemu_irq *pic) |
1103 | c2dd2a23 | Aurelien Jarno | { |
1104 | c2dd2a23 | Aurelien Jarno | SysBusDevice *s; |
1105 | c2dd2a23 | Aurelien Jarno | GT64120State *d; |
1106 | c2dd2a23 | Aurelien Jarno | DeviceState *dev; |
1107 | c2dd2a23 | Aurelien Jarno | |
1108 | c2dd2a23 | Aurelien Jarno | dev = qdev_create(NULL, "gt64120"); |
1109 | c2dd2a23 | Aurelien Jarno | qdev_init_nofail(dev); |
1110 | c2dd2a23 | Aurelien Jarno | s = sysbus_from_qdev(dev); |
1111 | c2dd2a23 | Aurelien Jarno | d = FROM_SYSBUS(GT64120State, s); |
1112 | c2dd2a23 | Aurelien Jarno | d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
|
1113 | c2dd2a23 | Aurelien Jarno | gt64120_pci_set_irq, gt64120_pci_map_irq, |
1114 | c2dd2a23 | Aurelien Jarno | pic, PCI_DEVFN(18, 0), 4); |
1115 | c2dd2a23 | Aurelien Jarno | d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d, |
1116 | c2dd2a23 | Aurelien Jarno | DEVICE_NATIVE_ENDIAN); |
1117 | c2dd2a23 | Aurelien Jarno | |
1118 | c2dd2a23 | Aurelien Jarno | pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci"); |
1119 | c2dd2a23 | Aurelien Jarno | return d->pci.bus;
|
1120 | c2dd2a23 | Aurelien Jarno | } |
1121 | c2dd2a23 | Aurelien Jarno | |
1122 | c2dd2a23 | Aurelien Jarno | static int gt64120_init(SysBusDevice *dev) |
1123 | fde7d5bd | ths | { |
1124 | fde7d5bd | ths | GT64120State *s; |
1125 | fde7d5bd | ths | |
1126 | c2dd2a23 | Aurelien Jarno | s = FROM_SYSBUS(GT64120State, dev); |
1127 | 9414cc6f | ths | |
1128 | 8e5977e5 | Aurelien Jarno | /* FIXME: This value is computed from registers during reset, but some
|
1129 | 8e5977e5 | Aurelien Jarno | devices (e.g. VGA card) need to know it when they are registered.
|
1130 | 8e5977e5 | Aurelien Jarno | This also mean that changing the register to change the mapping
|
1131 | 8e5977e5 | Aurelien Jarno | does not fully work. */
|
1132 | 8e5977e5 | Aurelien Jarno | isa_mem_base = 0x10000000;
|
1133 | c2dd2a23 | Aurelien Jarno | qemu_register_reset(gt64120_reset, s); |
1134 | c2dd2a23 | Aurelien Jarno | register_savevm(&dev->qdev, "GT64120 PCI Bus", 0, 1, |
1135 | c2dd2a23 | Aurelien Jarno | gt64120_save, gt64120_load, &s->pci); |
1136 | c2dd2a23 | Aurelien Jarno | return 0; |
1137 | c2dd2a23 | Aurelien Jarno | } |
1138 | fde7d5bd | ths | |
1139 | c2dd2a23 | Aurelien Jarno | static int gt64120_pci_init(PCIDevice *d) |
1140 | c2dd2a23 | Aurelien Jarno | { |
1141 | 0f78cf0c | ths | /* FIXME: Malta specific hw assumptions ahead */
|
1142 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL); |
1143 | a770dc7e | aliguori | pci_config_set_device_id(d->config, PCI_DEVICE_ID_MARVELL_GT6412X); |
1144 | c2dd2a23 | Aurelien Jarno | pci_set_word(d->config + PCI_COMMAND, 0);
|
1145 | c2dd2a23 | Aurelien Jarno | pci_set_word(d->config + PCI_STATUS, |
1146 | c2dd2a23 | Aurelien Jarno | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
1147 | c2dd2a23 | Aurelien Jarno | pci_set_byte(d->config + PCI_CLASS_REVISION, 0x10);
|
1148 | c2dd2a23 | Aurelien Jarno | pci_config_set_prog_interface(d->config, 0);
|
1149 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
1150 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
|
1151 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
|
1152 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
|
1153 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
|
1154 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
|
1155 | c2dd2a23 | Aurelien Jarno | pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
|
1156 | c2dd2a23 | Aurelien Jarno | pci_set_byte(d->config + 0x3d, 0x01); |
1157 | 0f78cf0c | ths | |
1158 | c2dd2a23 | Aurelien Jarno | return 0; |
1159 | c2dd2a23 | Aurelien Jarno | } |
1160 | a0a8793e | ths | |
1161 | c2dd2a23 | Aurelien Jarno | static PCIDeviceInfo gt64120_pci_info = {
|
1162 | c2dd2a23 | Aurelien Jarno | .qdev.name = "gt64120_pci",
|
1163 | c2dd2a23 | Aurelien Jarno | .qdev.size = sizeof(PCIDevice),
|
1164 | c2dd2a23 | Aurelien Jarno | .init = gt64120_pci_init, |
1165 | c2dd2a23 | Aurelien Jarno | }; |
1166 | 1823082c | ths | |
1167 | c2dd2a23 | Aurelien Jarno | static void gt64120_pci_register_devices(void) |
1168 | c2dd2a23 | Aurelien Jarno | { |
1169 | c2dd2a23 | Aurelien Jarno | sysbus_register_dev("gt64120", sizeof(GT64120State), |
1170 | c2dd2a23 | Aurelien Jarno | gt64120_init); |
1171 | c2dd2a23 | Aurelien Jarno | pci_qdev_register(>64120_pci_info); |
1172 | fde7d5bd | ths | } |
1173 | c2dd2a23 | Aurelien Jarno | |
1174 | c2dd2a23 | Aurelien Jarno | device_init(gt64120_pci_register_devices) |