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1 | 24859b68 | balrog | /*
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2 | 24859b68 | balrog | * Marvell MV88W8618 / Freecom MusicPal emulation.
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3 | 24859b68 | balrog | *
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4 | 24859b68 | balrog | * Copyright (c) 2008 Jan Kiszka
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5 | 24859b68 | balrog | *
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6 | 24859b68 | balrog | * This code is licenced under the GNU GPL v2.
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7 | 24859b68 | balrog | */
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8 | 24859b68 | balrog | |
9 | b47b50fa | Paul Brook | #include "sysbus.h" |
10 | 24859b68 | balrog | #include "arm-misc.h" |
11 | 24859b68 | balrog | #include "devices.h" |
12 | 24859b68 | balrog | #include "net.h" |
13 | 24859b68 | balrog | #include "sysemu.h" |
14 | 24859b68 | balrog | #include "boards.h" |
15 | 24859b68 | balrog | #include "pc.h" |
16 | 24859b68 | balrog | #include "qemu-timer.h" |
17 | 24859b68 | balrog | #include "block.h" |
18 | 24859b68 | balrog | #include "flash.h" |
19 | 24859b68 | balrog | #include "console.h" |
20 | 24859b68 | balrog | #include "i2c.h" |
21 | 2446333c | Blue Swirl | #include "blockdev.h" |
22 | 24859b68 | balrog | |
23 | 718ec0be | malc | #define MP_MISC_BASE 0x80002000 |
24 | 718ec0be | malc | #define MP_MISC_SIZE 0x00001000 |
25 | 718ec0be | malc | |
26 | 24859b68 | balrog | #define MP_ETH_BASE 0x80008000 |
27 | 24859b68 | balrog | #define MP_ETH_SIZE 0x00001000 |
28 | 24859b68 | balrog | |
29 | 718ec0be | malc | #define MP_WLAN_BASE 0x8000C000 |
30 | 718ec0be | malc | #define MP_WLAN_SIZE 0x00000800 |
31 | 718ec0be | malc | |
32 | 24859b68 | balrog | #define MP_UART1_BASE 0x8000C840 |
33 | 24859b68 | balrog | #define MP_UART2_BASE 0x8000C940 |
34 | 24859b68 | balrog | |
35 | 718ec0be | malc | #define MP_GPIO_BASE 0x8000D000 |
36 | 718ec0be | malc | #define MP_GPIO_SIZE 0x00001000 |
37 | 718ec0be | malc | |
38 | 24859b68 | balrog | #define MP_FLASHCFG_BASE 0x90006000 |
39 | 24859b68 | balrog | #define MP_FLASHCFG_SIZE 0x00001000 |
40 | 24859b68 | balrog | |
41 | 24859b68 | balrog | #define MP_AUDIO_BASE 0x90007000 |
42 | 24859b68 | balrog | |
43 | 24859b68 | balrog | #define MP_PIC_BASE 0x90008000 |
44 | 24859b68 | balrog | #define MP_PIC_SIZE 0x00001000 |
45 | 24859b68 | balrog | |
46 | 24859b68 | balrog | #define MP_PIT_BASE 0x90009000 |
47 | 24859b68 | balrog | #define MP_PIT_SIZE 0x00001000 |
48 | 24859b68 | balrog | |
49 | 24859b68 | balrog | #define MP_LCD_BASE 0x9000c000 |
50 | 24859b68 | balrog | #define MP_LCD_SIZE 0x00001000 |
51 | 24859b68 | balrog | |
52 | 24859b68 | balrog | #define MP_SRAM_BASE 0xC0000000 |
53 | 24859b68 | balrog | #define MP_SRAM_SIZE 0x00020000 |
54 | 24859b68 | balrog | |
55 | 24859b68 | balrog | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
56 | 24859b68 | balrog | #define MP_FLASH_SIZE_MAX 32*1024*1024 |
57 | 24859b68 | balrog | |
58 | 24859b68 | balrog | #define MP_TIMER1_IRQ 4 |
59 | b47b50fa | Paul Brook | #define MP_TIMER2_IRQ 5 |
60 | b47b50fa | Paul Brook | #define MP_TIMER3_IRQ 6 |
61 | 24859b68 | balrog | #define MP_TIMER4_IRQ 7 |
62 | 24859b68 | balrog | #define MP_EHCI_IRQ 8 |
63 | 24859b68 | balrog | #define MP_ETH_IRQ 9 |
64 | 24859b68 | balrog | #define MP_UART1_IRQ 11 |
65 | 24859b68 | balrog | #define MP_UART2_IRQ 11 |
66 | 24859b68 | balrog | #define MP_GPIO_IRQ 12 |
67 | 24859b68 | balrog | #define MP_RTC_IRQ 28 |
68 | 24859b68 | balrog | #define MP_AUDIO_IRQ 30 |
69 | 24859b68 | balrog | |
70 | 24859b68 | balrog | /* Wolfson 8750 I2C address */
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71 | 64258229 | Jan Kiszka | #define MP_WM_ADDR 0x1A |
72 | 24859b68 | balrog | |
73 | 24859b68 | balrog | /* Ethernet register offsets */
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74 | 24859b68 | balrog | #define MP_ETH_SMIR 0x010 |
75 | 24859b68 | balrog | #define MP_ETH_PCXR 0x408 |
76 | 24859b68 | balrog | #define MP_ETH_SDCMR 0x448 |
77 | 24859b68 | balrog | #define MP_ETH_ICR 0x450 |
78 | 24859b68 | balrog | #define MP_ETH_IMR 0x458 |
79 | 24859b68 | balrog | #define MP_ETH_FRDP0 0x480 |
80 | 24859b68 | balrog | #define MP_ETH_FRDP1 0x484 |
81 | 24859b68 | balrog | #define MP_ETH_FRDP2 0x488 |
82 | 24859b68 | balrog | #define MP_ETH_FRDP3 0x48C |
83 | 24859b68 | balrog | #define MP_ETH_CRDP0 0x4A0 |
84 | 24859b68 | balrog | #define MP_ETH_CRDP1 0x4A4 |
85 | 24859b68 | balrog | #define MP_ETH_CRDP2 0x4A8 |
86 | 24859b68 | balrog | #define MP_ETH_CRDP3 0x4AC |
87 | 24859b68 | balrog | #define MP_ETH_CTDP0 0x4E0 |
88 | 24859b68 | balrog | #define MP_ETH_CTDP1 0x4E4 |
89 | 24859b68 | balrog | #define MP_ETH_CTDP2 0x4E8 |
90 | 24859b68 | balrog | #define MP_ETH_CTDP3 0x4EC |
91 | 24859b68 | balrog | |
92 | 24859b68 | balrog | /* MII PHY access */
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93 | 24859b68 | balrog | #define MP_ETH_SMIR_DATA 0x0000FFFF |
94 | 24859b68 | balrog | #define MP_ETH_SMIR_ADDR 0x03FF0000 |
95 | 24859b68 | balrog | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
96 | 24859b68 | balrog | #define MP_ETH_SMIR_RDVALID (1 << 27) |
97 | 24859b68 | balrog | |
98 | 24859b68 | balrog | /* PHY registers */
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99 | 24859b68 | balrog | #define MP_ETH_PHY1_BMSR 0x00210000 |
100 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID1 0x00410000 |
101 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID2 0x00610000 |
102 | 24859b68 | balrog | |
103 | 24859b68 | balrog | #define MP_PHY_BMSR_LINK 0x0004 |
104 | 24859b68 | balrog | #define MP_PHY_BMSR_AUTONEG 0x0008 |
105 | 24859b68 | balrog | |
106 | 24859b68 | balrog | #define MP_PHY_88E3015 0x01410E20 |
107 | 24859b68 | balrog | |
108 | 24859b68 | balrog | /* TX descriptor status */
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109 | 24859b68 | balrog | #define MP_ETH_TX_OWN (1 << 31) |
110 | 24859b68 | balrog | |
111 | 24859b68 | balrog | /* RX descriptor status */
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112 | 24859b68 | balrog | #define MP_ETH_RX_OWN (1 << 31) |
113 | 24859b68 | balrog | |
114 | 24859b68 | balrog | /* Interrupt cause/mask bits */
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115 | 24859b68 | balrog | #define MP_ETH_IRQ_RX_BIT 0 |
116 | 24859b68 | balrog | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
117 | 24859b68 | balrog | #define MP_ETH_IRQ_TXHI_BIT 2 |
118 | 24859b68 | balrog | #define MP_ETH_IRQ_TXLO_BIT 3 |
119 | 24859b68 | balrog | |
120 | 24859b68 | balrog | /* Port config bits */
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121 | 24859b68 | balrog | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
122 | 24859b68 | balrog | |
123 | 24859b68 | balrog | /* SDMA command bits */
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124 | 24859b68 | balrog | #define MP_ETH_CMD_TXHI (1 << 23) |
125 | 24859b68 | balrog | #define MP_ETH_CMD_TXLO (1 << 22) |
126 | 24859b68 | balrog | |
127 | 24859b68 | balrog | typedef struct mv88w8618_tx_desc { |
128 | 24859b68 | balrog | uint32_t cmdstat; |
129 | 24859b68 | balrog | uint16_t res; |
130 | 24859b68 | balrog | uint16_t bytes; |
131 | 24859b68 | balrog | uint32_t buffer; |
132 | 24859b68 | balrog | uint32_t next; |
133 | 24859b68 | balrog | } mv88w8618_tx_desc; |
134 | 24859b68 | balrog | |
135 | 24859b68 | balrog | typedef struct mv88w8618_rx_desc { |
136 | 24859b68 | balrog | uint32_t cmdstat; |
137 | 24859b68 | balrog | uint16_t bytes; |
138 | 24859b68 | balrog | uint16_t buffer_size; |
139 | 24859b68 | balrog | uint32_t buffer; |
140 | 24859b68 | balrog | uint32_t next; |
141 | 24859b68 | balrog | } mv88w8618_rx_desc; |
142 | 24859b68 | balrog | |
143 | 24859b68 | balrog | typedef struct mv88w8618_eth_state { |
144 | b47b50fa | Paul Brook | SysBusDevice busdev; |
145 | 24859b68 | balrog | qemu_irq irq; |
146 | 24859b68 | balrog | uint32_t smir; |
147 | 24859b68 | balrog | uint32_t icr; |
148 | 24859b68 | balrog | uint32_t imr; |
149 | b946a153 | aliguori | int mmio_index;
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150 | d5b61ddd | Jan Kiszka | uint32_t vlan_header; |
151 | 930c8682 | pbrook | uint32_t tx_queue[2];
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152 | 930c8682 | pbrook | uint32_t rx_queue[4];
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153 | 930c8682 | pbrook | uint32_t frx_queue[4];
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154 | 930c8682 | pbrook | uint32_t cur_rx[4];
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155 | 3a94dd18 | Mark McLoughlin | NICState *nic; |
156 | 4c91cd28 | Gerd Hoffmann | NICConf conf; |
157 | 24859b68 | balrog | } mv88w8618_eth_state; |
158 | 24859b68 | balrog | |
159 | 930c8682 | pbrook | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
160 | 930c8682 | pbrook | { |
161 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
162 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
163 | 930c8682 | pbrook | cpu_to_le16s(&desc->buffer_size); |
164 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
165 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
166 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
167 | 930c8682 | pbrook | } |
168 | 930c8682 | pbrook | |
169 | 930c8682 | pbrook | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
170 | 930c8682 | pbrook | { |
171 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
172 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
173 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
174 | 930c8682 | pbrook | le16_to_cpus(&desc->buffer_size); |
175 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
176 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
177 | 930c8682 | pbrook | } |
178 | 930c8682 | pbrook | |
179 | 3a94dd18 | Mark McLoughlin | static int eth_can_receive(VLANClientState *nc) |
180 | 24859b68 | balrog | { |
181 | 24859b68 | balrog | return 1; |
182 | 24859b68 | balrog | } |
183 | 24859b68 | balrog | |
184 | 3a94dd18 | Mark McLoughlin | static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
185 | 24859b68 | balrog | { |
186 | 3a94dd18 | Mark McLoughlin | mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
187 | 930c8682 | pbrook | uint32_t desc_addr; |
188 | 930c8682 | pbrook | mv88w8618_rx_desc desc; |
189 | 24859b68 | balrog | int i;
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190 | 24859b68 | balrog | |
191 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
192 | 930c8682 | pbrook | desc_addr = s->cur_rx[i]; |
193 | 49fedd0d | Jan Kiszka | if (!desc_addr) {
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194 | 24859b68 | balrog | continue;
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195 | 49fedd0d | Jan Kiszka | } |
196 | 24859b68 | balrog | do {
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197 | 930c8682 | pbrook | eth_rx_desc_get(desc_addr, &desc); |
198 | 930c8682 | pbrook | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
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199 | 930c8682 | pbrook | cpu_physical_memory_write(desc.buffer + s->vlan_header, |
200 | 930c8682 | pbrook | buf, size); |
201 | 930c8682 | pbrook | desc.bytes = size + s->vlan_header; |
202 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_RX_OWN; |
203 | 930c8682 | pbrook | s->cur_rx[i] = desc.next; |
204 | 24859b68 | balrog | |
205 | 24859b68 | balrog | s->icr |= MP_ETH_IRQ_RX; |
206 | 49fedd0d | Jan Kiszka | if (s->icr & s->imr) {
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207 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
208 | 49fedd0d | Jan Kiszka | } |
209 | 930c8682 | pbrook | eth_rx_desc_put(desc_addr, &desc); |
210 | 4f1c942b | Mark McLoughlin | return size;
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211 | 24859b68 | balrog | } |
212 | 930c8682 | pbrook | desc_addr = desc.next; |
213 | 930c8682 | pbrook | } while (desc_addr != s->rx_queue[i]);
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214 | 24859b68 | balrog | } |
215 | 4f1c942b | Mark McLoughlin | return size;
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216 | 24859b68 | balrog | } |
217 | 24859b68 | balrog | |
218 | 930c8682 | pbrook | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
219 | 930c8682 | pbrook | { |
220 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
221 | 930c8682 | pbrook | cpu_to_le16s(&desc->res); |
222 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
223 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
224 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
225 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
226 | 930c8682 | pbrook | } |
227 | 930c8682 | pbrook | |
228 | 930c8682 | pbrook | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
229 | 930c8682 | pbrook | { |
230 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
231 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
232 | 930c8682 | pbrook | le16_to_cpus(&desc->res); |
233 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
234 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
235 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
236 | 930c8682 | pbrook | } |
237 | 930c8682 | pbrook | |
238 | 24859b68 | balrog | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
239 | 24859b68 | balrog | { |
240 | 930c8682 | pbrook | uint32_t desc_addr = s->tx_queue[queue_index]; |
241 | 930c8682 | pbrook | mv88w8618_tx_desc desc; |
242 | 07b064e9 | Jan Kiszka | uint32_t next_desc; |
243 | 930c8682 | pbrook | uint8_t buf[2048];
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244 | 930c8682 | pbrook | int len;
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245 | 930c8682 | pbrook | |
246 | 24859b68 | balrog | do {
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247 | 930c8682 | pbrook | eth_tx_desc_get(desc_addr, &desc); |
248 | 07b064e9 | Jan Kiszka | next_desc = desc.next; |
249 | 930c8682 | pbrook | if (desc.cmdstat & MP_ETH_TX_OWN) {
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250 | 930c8682 | pbrook | len = desc.bytes; |
251 | 930c8682 | pbrook | if (len < 2048) { |
252 | 930c8682 | pbrook | cpu_physical_memory_read(desc.buffer, buf, len); |
253 | 3a94dd18 | Mark McLoughlin | qemu_send_packet(&s->nic->nc, buf, len); |
254 | 930c8682 | pbrook | } |
255 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_TX_OWN; |
256 | 24859b68 | balrog | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
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257 | 930c8682 | pbrook | eth_tx_desc_put(desc_addr, &desc); |
258 | 24859b68 | balrog | } |
259 | 07b064e9 | Jan Kiszka | desc_addr = next_desc; |
260 | 930c8682 | pbrook | } while (desc_addr != s->tx_queue[queue_index]);
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261 | 24859b68 | balrog | } |
262 | 24859b68 | balrog | |
263 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
264 | 24859b68 | balrog | { |
265 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
266 | 24859b68 | balrog | |
267 | 24859b68 | balrog | switch (offset) {
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268 | 24859b68 | balrog | case MP_ETH_SMIR:
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269 | 24859b68 | balrog | if (s->smir & MP_ETH_SMIR_OPCODE) {
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270 | 24859b68 | balrog | switch (s->smir & MP_ETH_SMIR_ADDR) {
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271 | 24859b68 | balrog | case MP_ETH_PHY1_BMSR:
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272 | 24859b68 | balrog | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
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273 | 24859b68 | balrog | MP_ETH_SMIR_RDVALID; |
274 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID1:
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275 | 24859b68 | balrog | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
276 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID2:
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277 | 24859b68 | balrog | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
278 | 24859b68 | balrog | default:
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279 | 24859b68 | balrog | return MP_ETH_SMIR_RDVALID;
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280 | 24859b68 | balrog | } |
281 | 24859b68 | balrog | } |
282 | 24859b68 | balrog | return 0; |
283 | 24859b68 | balrog | |
284 | 24859b68 | balrog | case MP_ETH_ICR:
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285 | 24859b68 | balrog | return s->icr;
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286 | 24859b68 | balrog | |
287 | 24859b68 | balrog | case MP_ETH_IMR:
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288 | 24859b68 | balrog | return s->imr;
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289 | 24859b68 | balrog | |
290 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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291 | 930c8682 | pbrook | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
292 | 24859b68 | balrog | |
293 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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294 | 930c8682 | pbrook | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
295 | 24859b68 | balrog | |
296 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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297 | 930c8682 | pbrook | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
298 | 24859b68 | balrog | |
299 | 24859b68 | balrog | default:
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300 | 24859b68 | balrog | return 0; |
301 | 24859b68 | balrog | } |
302 | 24859b68 | balrog | } |
303 | 24859b68 | balrog | |
304 | c227f099 | Anthony Liguori | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
305 | 24859b68 | balrog | uint32_t value) |
306 | 24859b68 | balrog | { |
307 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
308 | 24859b68 | balrog | |
309 | 24859b68 | balrog | switch (offset) {
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310 | 24859b68 | balrog | case MP_ETH_SMIR:
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311 | 24859b68 | balrog | s->smir = value; |
312 | 24859b68 | balrog | break;
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313 | 24859b68 | balrog | |
314 | 24859b68 | balrog | case MP_ETH_PCXR:
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315 | 24859b68 | balrog | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
316 | 24859b68 | balrog | break;
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317 | 24859b68 | balrog | |
318 | 24859b68 | balrog | case MP_ETH_SDCMR:
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319 | 49fedd0d | Jan Kiszka | if (value & MP_ETH_CMD_TXHI) {
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320 | 24859b68 | balrog | eth_send(s, 1);
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321 | 49fedd0d | Jan Kiszka | } |
322 | 49fedd0d | Jan Kiszka | if (value & MP_ETH_CMD_TXLO) {
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323 | 24859b68 | balrog | eth_send(s, 0);
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324 | 49fedd0d | Jan Kiszka | } |
325 | 49fedd0d | Jan Kiszka | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
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326 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
327 | 49fedd0d | Jan Kiszka | } |
328 | 24859b68 | balrog | break;
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329 | 24859b68 | balrog | |
330 | 24859b68 | balrog | case MP_ETH_ICR:
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331 | 24859b68 | balrog | s->icr &= value; |
332 | 24859b68 | balrog | break;
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333 | 24859b68 | balrog | |
334 | 24859b68 | balrog | case MP_ETH_IMR:
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335 | 24859b68 | balrog | s->imr = value; |
336 | 49fedd0d | Jan Kiszka | if (s->icr & s->imr) {
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337 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
338 | 49fedd0d | Jan Kiszka | } |
339 | 24859b68 | balrog | break;
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340 | 24859b68 | balrog | |
341 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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342 | 930c8682 | pbrook | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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343 | 24859b68 | balrog | break;
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344 | 24859b68 | balrog | |
345 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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346 | 24859b68 | balrog | s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
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347 | 930c8682 | pbrook | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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348 | 24859b68 | balrog | break;
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349 | 24859b68 | balrog | |
350 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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351 | 930c8682 | pbrook | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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352 | 24859b68 | balrog | break;
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353 | 24859b68 | balrog | } |
354 | 24859b68 | balrog | } |
355 | 24859b68 | balrog | |
356 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
357 | 24859b68 | balrog | mv88w8618_eth_read, |
358 | 24859b68 | balrog | mv88w8618_eth_read, |
359 | 24859b68 | balrog | mv88w8618_eth_read |
360 | 24859b68 | balrog | }; |
361 | 24859b68 | balrog | |
362 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
363 | 24859b68 | balrog | mv88w8618_eth_write, |
364 | 24859b68 | balrog | mv88w8618_eth_write, |
365 | 24859b68 | balrog | mv88w8618_eth_write |
366 | 24859b68 | balrog | }; |
367 | 24859b68 | balrog | |
368 | 3a94dd18 | Mark McLoughlin | static void eth_cleanup(VLANClientState *nc) |
369 | b946a153 | aliguori | { |
370 | 3a94dd18 | Mark McLoughlin | mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
371 | b946a153 | aliguori | |
372 | 3a94dd18 | Mark McLoughlin | s->nic = NULL;
|
373 | b946a153 | aliguori | } |
374 | b946a153 | aliguori | |
375 | 3a94dd18 | Mark McLoughlin | static NetClientInfo net_mv88w8618_info = {
|
376 | 3a94dd18 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
377 | 3a94dd18 | Mark McLoughlin | .size = sizeof(NICState),
|
378 | 3a94dd18 | Mark McLoughlin | .can_receive = eth_can_receive, |
379 | 3a94dd18 | Mark McLoughlin | .receive = eth_receive, |
380 | 3a94dd18 | Mark McLoughlin | .cleanup = eth_cleanup, |
381 | 3a94dd18 | Mark McLoughlin | }; |
382 | 3a94dd18 | Mark McLoughlin | |
383 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_eth_init(SysBusDevice *dev) |
384 | 24859b68 | balrog | { |
385 | b47b50fa | Paul Brook | mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
386 | 0ae18cee | aliguori | |
387 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
388 | 3a94dd18 | Mark McLoughlin | s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, |
389 | 3a94dd18 | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
390 | 1eed09cb | Avi Kivity | s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
391 | 2507c12a | Alexander Graf | mv88w8618_eth_writefn, s, |
392 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
393 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
394 | 81a322d4 | Gerd Hoffmann | return 0; |
395 | 24859b68 | balrog | } |
396 | 24859b68 | balrog | |
397 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_eth_vmsd = { |
398 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_eth",
|
399 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
400 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
401 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
402 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
403 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(smir, mv88w8618_eth_state), |
404 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(icr, mv88w8618_eth_state), |
405 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(imr, mv88w8618_eth_state), |
406 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), |
407 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
|
408 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
|
409 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
|
410 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
|
411 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
412 | d5b61ddd | Jan Kiszka | } |
413 | d5b61ddd | Jan Kiszka | }; |
414 | d5b61ddd | Jan Kiszka | |
415 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_eth_info = {
|
416 | d5b61ddd | Jan Kiszka | .init = mv88w8618_eth_init, |
417 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_eth",
|
418 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_eth_state),
|
419 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_eth_vmsd, |
420 | 4c91cd28 | Gerd Hoffmann | .qdev.props = (Property[]) { |
421 | 4c91cd28 | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), |
422 | 4c91cd28 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
423 | 4c91cd28 | Gerd Hoffmann | }, |
424 | d5b61ddd | Jan Kiszka | }; |
425 | d5b61ddd | Jan Kiszka | |
426 | 24859b68 | balrog | /* LCD register offsets */
|
427 | 24859b68 | balrog | #define MP_LCD_IRQCTRL 0x180 |
428 | 24859b68 | balrog | #define MP_LCD_IRQSTAT 0x184 |
429 | 24859b68 | balrog | #define MP_LCD_SPICTRL 0x1ac |
430 | 24859b68 | balrog | #define MP_LCD_INST 0x1bc |
431 | 24859b68 | balrog | #define MP_LCD_DATA 0x1c0 |
432 | 24859b68 | balrog | |
433 | 24859b68 | balrog | /* Mode magics */
|
434 | 24859b68 | balrog | #define MP_LCD_SPI_DATA 0x00100011 |
435 | 24859b68 | balrog | #define MP_LCD_SPI_CMD 0x00104011 |
436 | 24859b68 | balrog | #define MP_LCD_SPI_INVALID 0x00000000 |
437 | 24859b68 | balrog | |
438 | 24859b68 | balrog | /* Commmands */
|
439 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE0 0xB0 |
440 | 24859b68 | balrog | /* ... */
|
441 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE7 0xB7 |
442 | 24859b68 | balrog | |
443 | 24859b68 | balrog | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
444 | 24859b68 | balrog | |
445 | 24859b68 | balrog | typedef struct musicpal_lcd_state { |
446 | b47b50fa | Paul Brook | SysBusDevice busdev; |
447 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
448 | 24859b68 | balrog | uint32_t mode; |
449 | 24859b68 | balrog | uint32_t irqctrl; |
450 | d5b61ddd | Jan Kiszka | uint32_t page; |
451 | d5b61ddd | Jan Kiszka | uint32_t page_off; |
452 | 24859b68 | balrog | DisplayState *ds; |
453 | 24859b68 | balrog | uint8_t video_ram[128*64/8]; |
454 | 24859b68 | balrog | } musicpal_lcd_state; |
455 | 24859b68 | balrog | |
456 | 343ec8e4 | Benoit Canet | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
|
457 | 24859b68 | balrog | { |
458 | 343ec8e4 | Benoit Canet | switch (s->brightness) {
|
459 | 343ec8e4 | Benoit Canet | case 7: |
460 | 343ec8e4 | Benoit Canet | return col;
|
461 | 343ec8e4 | Benoit Canet | case 0: |
462 | 24859b68 | balrog | return 0; |
463 | 24859b68 | balrog | default:
|
464 | 343ec8e4 | Benoit Canet | return (col * s->brightness) / 7; |
465 | 24859b68 | balrog | } |
466 | 24859b68 | balrog | } |
467 | 24859b68 | balrog | |
468 | 0266f2c7 | balrog | #define SET_LCD_PIXEL(depth, type) \
|
469 | 0266f2c7 | balrog | static inline void glue(set_lcd_pixel, depth) \ |
470 | 0266f2c7 | balrog | (musicpal_lcd_state *s, int x, int y, type col) \ |
471 | 0266f2c7 | balrog | { \ |
472 | 0266f2c7 | balrog | int dx, dy; \
|
473 | 0e1f5a0c | aliguori | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
474 | 0266f2c7 | balrog | \ |
475 | 0266f2c7 | balrog | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
476 | 0266f2c7 | balrog | for (dx = 0; dx < 3; dx++, pixel++) \ |
477 | 0266f2c7 | balrog | *pixel = col; \ |
478 | 24859b68 | balrog | } |
479 | 0266f2c7 | balrog | SET_LCD_PIXEL(8, uint8_t)
|
480 | 0266f2c7 | balrog | SET_LCD_PIXEL(16, uint16_t)
|
481 | 0266f2c7 | balrog | SET_LCD_PIXEL(32, uint32_t)
|
482 | 0266f2c7 | balrog | |
483 | 0266f2c7 | balrog | #include "pixel_ops.h" |
484 | 24859b68 | balrog | |
485 | 24859b68 | balrog | static void lcd_refresh(void *opaque) |
486 | 24859b68 | balrog | { |
487 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
488 | 0266f2c7 | balrog | int x, y, col;
|
489 | 24859b68 | balrog | |
490 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
491 | 0266f2c7 | balrog | case 0: |
492 | 0266f2c7 | balrog | return;
|
493 | 0266f2c7 | balrog | #define LCD_REFRESH(depth, func) \
|
494 | 0266f2c7 | balrog | case depth: \
|
495 | 343ec8e4 | Benoit Canet | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
496 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
497 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
|
498 | 49fedd0d | Jan Kiszka | for (x = 0; x < 128; x++) { \ |
499 | 49fedd0d | Jan Kiszka | for (y = 0; y < 64; y++) { \ |
500 | 49fedd0d | Jan Kiszka | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ |
501 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
502 | 49fedd0d | Jan Kiszka | } else { \
|
503 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
504 | 49fedd0d | Jan Kiszka | } \ |
505 | 49fedd0d | Jan Kiszka | } \ |
506 | 49fedd0d | Jan Kiszka | } \ |
507 | 0266f2c7 | balrog | break;
|
508 | 0266f2c7 | balrog | LCD_REFRESH(8, rgb_to_pixel8)
|
509 | 0266f2c7 | balrog | LCD_REFRESH(16, rgb_to_pixel16)
|
510 | bf9b48af | aliguori | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
511 | bf9b48af | aliguori | rgb_to_pixel32bgr : rgb_to_pixel32)) |
512 | 0266f2c7 | balrog | default:
|
513 | 2ac71179 | Paul Brook | hw_error("unsupported colour depth %i\n",
|
514 | 0e1f5a0c | aliguori | ds_get_bits_per_pixel(s->ds)); |
515 | 0266f2c7 | balrog | } |
516 | 24859b68 | balrog | |
517 | 24859b68 | balrog | dpy_update(s->ds, 0, 0, 128*3, 64*3); |
518 | 24859b68 | balrog | } |
519 | 24859b68 | balrog | |
520 | 167bc3d2 | balrog | static void lcd_invalidate(void *opaque) |
521 | 167bc3d2 | balrog | { |
522 | 167bc3d2 | balrog | } |
523 | 167bc3d2 | balrog | |
524 | 343ec8e4 | Benoit Canet | static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
525 | 343ec8e4 | Benoit Canet | { |
526 | 243cd13c | Jan Kiszka | musicpal_lcd_state *s = opaque; |
527 | 343ec8e4 | Benoit Canet | s->brightness &= ~(1 << irq);
|
528 | 343ec8e4 | Benoit Canet | s->brightness |= level << irq; |
529 | 343ec8e4 | Benoit Canet | } |
530 | 343ec8e4 | Benoit Canet | |
531 | c227f099 | Anthony Liguori | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
532 | 24859b68 | balrog | { |
533 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
534 | 24859b68 | balrog | |
535 | 24859b68 | balrog | switch (offset) {
|
536 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
537 | 24859b68 | balrog | return s->irqctrl;
|
538 | 24859b68 | balrog | |
539 | 24859b68 | balrog | default:
|
540 | 24859b68 | balrog | return 0; |
541 | 24859b68 | balrog | } |
542 | 24859b68 | balrog | } |
543 | 24859b68 | balrog | |
544 | c227f099 | Anthony Liguori | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
545 | 24859b68 | balrog | uint32_t value) |
546 | 24859b68 | balrog | { |
547 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
548 | 24859b68 | balrog | |
549 | 24859b68 | balrog | switch (offset) {
|
550 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
551 | 24859b68 | balrog | s->irqctrl = value; |
552 | 24859b68 | balrog | break;
|
553 | 24859b68 | balrog | |
554 | 24859b68 | balrog | case MP_LCD_SPICTRL:
|
555 | 49fedd0d | Jan Kiszka | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
|
556 | 24859b68 | balrog | s->mode = value; |
557 | 49fedd0d | Jan Kiszka | } else {
|
558 | 24859b68 | balrog | s->mode = MP_LCD_SPI_INVALID; |
559 | 49fedd0d | Jan Kiszka | } |
560 | 24859b68 | balrog | break;
|
561 | 24859b68 | balrog | |
562 | 24859b68 | balrog | case MP_LCD_INST:
|
563 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
564 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
565 | 24859b68 | balrog | s->page_off = 0;
|
566 | 24859b68 | balrog | } |
567 | 24859b68 | balrog | break;
|
568 | 24859b68 | balrog | |
569 | 24859b68 | balrog | case MP_LCD_DATA:
|
570 | 24859b68 | balrog | if (s->mode == MP_LCD_SPI_CMD) {
|
571 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 &&
|
572 | 24859b68 | balrog | value <= MP_LCD_INST_SETPAGE7) { |
573 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
574 | 24859b68 | balrog | s->page_off = 0;
|
575 | 24859b68 | balrog | } |
576 | 24859b68 | balrog | } else if (s->mode == MP_LCD_SPI_DATA) { |
577 | 24859b68 | balrog | s->video_ram[s->page*128 + s->page_off] = value;
|
578 | 24859b68 | balrog | s->page_off = (s->page_off + 1) & 127; |
579 | 24859b68 | balrog | } |
580 | 24859b68 | balrog | break;
|
581 | 24859b68 | balrog | } |
582 | 24859b68 | balrog | } |
583 | 24859b68 | balrog | |
584 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
585 | 24859b68 | balrog | musicpal_lcd_read, |
586 | 24859b68 | balrog | musicpal_lcd_read, |
587 | 24859b68 | balrog | musicpal_lcd_read |
588 | 24859b68 | balrog | }; |
589 | 24859b68 | balrog | |
590 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
591 | 24859b68 | balrog | musicpal_lcd_write, |
592 | 24859b68 | balrog | musicpal_lcd_write, |
593 | 24859b68 | balrog | musicpal_lcd_write |
594 | 24859b68 | balrog | }; |
595 | 24859b68 | balrog | |
596 | 81a322d4 | Gerd Hoffmann | static int musicpal_lcd_init(SysBusDevice *dev) |
597 | 24859b68 | balrog | { |
598 | b47b50fa | Paul Brook | musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
599 | 24859b68 | balrog | int iomemtype;
|
600 | 24859b68 | balrog | |
601 | 343ec8e4 | Benoit Canet | s->brightness = 7;
|
602 | 343ec8e4 | Benoit Canet | |
603 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
604 | 2507c12a | Alexander Graf | musicpal_lcd_writefn, s, |
605 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
606 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
607 | 24859b68 | balrog | |
608 | 3023f332 | aliguori | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
609 | 3023f332 | aliguori | NULL, NULL, s); |
610 | 3023f332 | aliguori | qemu_console_resize(s->ds, 128*3, 64*3); |
611 | 343ec8e4 | Benoit Canet | |
612 | 343ec8e4 | Benoit Canet | qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
|
613 | 81a322d4 | Gerd Hoffmann | |
614 | 81a322d4 | Gerd Hoffmann | return 0; |
615 | 24859b68 | balrog | } |
616 | 24859b68 | balrog | |
617 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_lcd_vmsd = { |
618 | d5b61ddd | Jan Kiszka | .name = "musicpal_lcd",
|
619 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
620 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
621 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
622 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
623 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(brightness, musicpal_lcd_state), |
624 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(mode, musicpal_lcd_state), |
625 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(irqctrl, musicpal_lcd_state), |
626 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(page, musicpal_lcd_state), |
627 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(page_off, musicpal_lcd_state), |
628 | d5b61ddd | Jan Kiszka | VMSTATE_BUFFER(video_ram, musicpal_lcd_state), |
629 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
630 | d5b61ddd | Jan Kiszka | } |
631 | d5b61ddd | Jan Kiszka | }; |
632 | d5b61ddd | Jan Kiszka | |
633 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo musicpal_lcd_info = {
|
634 | d5b61ddd | Jan Kiszka | .init = musicpal_lcd_init, |
635 | d5b61ddd | Jan Kiszka | .qdev.name = "musicpal_lcd",
|
636 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(musicpal_lcd_state),
|
637 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_lcd_vmsd, |
638 | d5b61ddd | Jan Kiszka | }; |
639 | d5b61ddd | Jan Kiszka | |
640 | 24859b68 | balrog | /* PIC register offsets */
|
641 | 24859b68 | balrog | #define MP_PIC_STATUS 0x00 |
642 | 24859b68 | balrog | #define MP_PIC_ENABLE_SET 0x08 |
643 | 24859b68 | balrog | #define MP_PIC_ENABLE_CLR 0x0C |
644 | 24859b68 | balrog | |
645 | 24859b68 | balrog | typedef struct mv88w8618_pic_state |
646 | 24859b68 | balrog | { |
647 | b47b50fa | Paul Brook | SysBusDevice busdev; |
648 | 24859b68 | balrog | uint32_t level; |
649 | 24859b68 | balrog | uint32_t enabled; |
650 | 24859b68 | balrog | qemu_irq parent_irq; |
651 | 24859b68 | balrog | } mv88w8618_pic_state; |
652 | 24859b68 | balrog | |
653 | 24859b68 | balrog | static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
654 | 24859b68 | balrog | { |
655 | 24859b68 | balrog | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
656 | 24859b68 | balrog | } |
657 | 24859b68 | balrog | |
658 | 24859b68 | balrog | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
659 | 24859b68 | balrog | { |
660 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
661 | 24859b68 | balrog | |
662 | 49fedd0d | Jan Kiszka | if (level) {
|
663 | 24859b68 | balrog | s->level |= 1 << irq;
|
664 | 49fedd0d | Jan Kiszka | } else {
|
665 | 24859b68 | balrog | s->level &= ~(1 << irq);
|
666 | 49fedd0d | Jan Kiszka | } |
667 | 24859b68 | balrog | mv88w8618_pic_update(s); |
668 | 24859b68 | balrog | } |
669 | 24859b68 | balrog | |
670 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
671 | 24859b68 | balrog | { |
672 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
673 | 24859b68 | balrog | |
674 | 24859b68 | balrog | switch (offset) {
|
675 | 24859b68 | balrog | case MP_PIC_STATUS:
|
676 | 24859b68 | balrog | return s->level & s->enabled;
|
677 | 24859b68 | balrog | |
678 | 24859b68 | balrog | default:
|
679 | 24859b68 | balrog | return 0; |
680 | 24859b68 | balrog | } |
681 | 24859b68 | balrog | } |
682 | 24859b68 | balrog | |
683 | c227f099 | Anthony Liguori | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
684 | 24859b68 | balrog | uint32_t value) |
685 | 24859b68 | balrog | { |
686 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
687 | 24859b68 | balrog | |
688 | 24859b68 | balrog | switch (offset) {
|
689 | 24859b68 | balrog | case MP_PIC_ENABLE_SET:
|
690 | 24859b68 | balrog | s->enabled |= value; |
691 | 24859b68 | balrog | break;
|
692 | 24859b68 | balrog | |
693 | 24859b68 | balrog | case MP_PIC_ENABLE_CLR:
|
694 | 24859b68 | balrog | s->enabled &= ~value; |
695 | 24859b68 | balrog | s->level &= ~value; |
696 | 24859b68 | balrog | break;
|
697 | 24859b68 | balrog | } |
698 | 24859b68 | balrog | mv88w8618_pic_update(s); |
699 | 24859b68 | balrog | } |
700 | 24859b68 | balrog | |
701 | d5b61ddd | Jan Kiszka | static void mv88w8618_pic_reset(DeviceState *d) |
702 | 24859b68 | balrog | { |
703 | d5b61ddd | Jan Kiszka | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, |
704 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
705 | 24859b68 | balrog | |
706 | 24859b68 | balrog | s->level = 0;
|
707 | 24859b68 | balrog | s->enabled = 0;
|
708 | 24859b68 | balrog | } |
709 | 24859b68 | balrog | |
710 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
711 | 24859b68 | balrog | mv88w8618_pic_read, |
712 | 24859b68 | balrog | mv88w8618_pic_read, |
713 | 24859b68 | balrog | mv88w8618_pic_read |
714 | 24859b68 | balrog | }; |
715 | 24859b68 | balrog | |
716 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
717 | 24859b68 | balrog | mv88w8618_pic_write, |
718 | 24859b68 | balrog | mv88w8618_pic_write, |
719 | 24859b68 | balrog | mv88w8618_pic_write |
720 | 24859b68 | balrog | }; |
721 | 24859b68 | balrog | |
722 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_pic_init(SysBusDevice *dev) |
723 | 24859b68 | balrog | { |
724 | b47b50fa | Paul Brook | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
725 | 24859b68 | balrog | int iomemtype;
|
726 | 24859b68 | balrog | |
727 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
728 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->parent_irq); |
729 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
730 | 2507c12a | Alexander Graf | mv88w8618_pic_writefn, s, |
731 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
732 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
733 | 81a322d4 | Gerd Hoffmann | return 0; |
734 | 24859b68 | balrog | } |
735 | 24859b68 | balrog | |
736 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_pic_vmsd = { |
737 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_pic",
|
738 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
739 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
740 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
741 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
742 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(level, mv88w8618_pic_state), |
743 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(enabled, mv88w8618_pic_state), |
744 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
745 | d5b61ddd | Jan Kiszka | } |
746 | d5b61ddd | Jan Kiszka | }; |
747 | d5b61ddd | Jan Kiszka | |
748 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_pic_info = {
|
749 | d5b61ddd | Jan Kiszka | .init = mv88w8618_pic_init, |
750 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_pic",
|
751 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_pic_state),
|
752 | d5b61ddd | Jan Kiszka | .qdev.reset = mv88w8618_pic_reset, |
753 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_pic_vmsd, |
754 | d5b61ddd | Jan Kiszka | }; |
755 | d5b61ddd | Jan Kiszka | |
756 | 24859b68 | balrog | /* PIT register offsets */
|
757 | 24859b68 | balrog | #define MP_PIT_TIMER1_LENGTH 0x00 |
758 | 24859b68 | balrog | /* ... */
|
759 | 24859b68 | balrog | #define MP_PIT_TIMER4_LENGTH 0x0C |
760 | 24859b68 | balrog | #define MP_PIT_CONTROL 0x10 |
761 | 24859b68 | balrog | #define MP_PIT_TIMER1_VALUE 0x14 |
762 | 24859b68 | balrog | /* ... */
|
763 | 24859b68 | balrog | #define MP_PIT_TIMER4_VALUE 0x20 |
764 | 24859b68 | balrog | #define MP_BOARD_RESET 0x34 |
765 | 24859b68 | balrog | |
766 | 24859b68 | balrog | /* Magic board reset value (probably some watchdog behind it) */
|
767 | 24859b68 | balrog | #define MP_BOARD_RESET_MAGIC 0x10000 |
768 | 24859b68 | balrog | |
769 | 24859b68 | balrog | typedef struct mv88w8618_timer_state { |
770 | b47b50fa | Paul Brook | ptimer_state *ptimer; |
771 | 24859b68 | balrog | uint32_t limit; |
772 | 24859b68 | balrog | int freq;
|
773 | 24859b68 | balrog | qemu_irq irq; |
774 | 24859b68 | balrog | } mv88w8618_timer_state; |
775 | 24859b68 | balrog | |
776 | 24859b68 | balrog | typedef struct mv88w8618_pit_state { |
777 | b47b50fa | Paul Brook | SysBusDevice busdev; |
778 | b47b50fa | Paul Brook | mv88w8618_timer_state timer[4];
|
779 | 24859b68 | balrog | } mv88w8618_pit_state; |
780 | 24859b68 | balrog | |
781 | 24859b68 | balrog | static void mv88w8618_timer_tick(void *opaque) |
782 | 24859b68 | balrog | { |
783 | 24859b68 | balrog | mv88w8618_timer_state *s = opaque; |
784 | 24859b68 | balrog | |
785 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
786 | 24859b68 | balrog | } |
787 | 24859b68 | balrog | |
788 | b47b50fa | Paul Brook | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
789 | b47b50fa | Paul Brook | uint32_t freq) |
790 | 24859b68 | balrog | { |
791 | 24859b68 | balrog | QEMUBH *bh; |
792 | 24859b68 | balrog | |
793 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
794 | 24859b68 | balrog | s->freq = freq; |
795 | 24859b68 | balrog | |
796 | 24859b68 | balrog | bh = qemu_bh_new(mv88w8618_timer_tick, s); |
797 | b47b50fa | Paul Brook | s->ptimer = ptimer_init(bh); |
798 | 24859b68 | balrog | } |
799 | 24859b68 | balrog | |
800 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
801 | 24859b68 | balrog | { |
802 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
803 | 24859b68 | balrog | mv88w8618_timer_state *t; |
804 | 24859b68 | balrog | |
805 | 24859b68 | balrog | switch (offset) {
|
806 | 24859b68 | balrog | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
807 | b47b50fa | Paul Brook | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
808 | b47b50fa | Paul Brook | return ptimer_get_count(t->ptimer);
|
809 | 24859b68 | balrog | |
810 | 24859b68 | balrog | default:
|
811 | 24859b68 | balrog | return 0; |
812 | 24859b68 | balrog | } |
813 | 24859b68 | balrog | } |
814 | 24859b68 | balrog | |
815 | c227f099 | Anthony Liguori | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
816 | 24859b68 | balrog | uint32_t value) |
817 | 24859b68 | balrog | { |
818 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
819 | 24859b68 | balrog | mv88w8618_timer_state *t; |
820 | 24859b68 | balrog | int i;
|
821 | 24859b68 | balrog | |
822 | 24859b68 | balrog | switch (offset) {
|
823 | 24859b68 | balrog | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
824 | b47b50fa | Paul Brook | t = &s->timer[offset >> 2];
|
825 | 24859b68 | balrog | t->limit = value; |
826 | c88d6bde | Jan Kiszka | if (t->limit > 0) { |
827 | c88d6bde | Jan Kiszka | ptimer_set_limit(t->ptimer, t->limit, 1);
|
828 | c88d6bde | Jan Kiszka | } else {
|
829 | c88d6bde | Jan Kiszka | ptimer_stop(t->ptimer); |
830 | c88d6bde | Jan Kiszka | } |
831 | 24859b68 | balrog | break;
|
832 | 24859b68 | balrog | |
833 | 24859b68 | balrog | case MP_PIT_CONTROL:
|
834 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
835 | c88d6bde | Jan Kiszka | t = &s->timer[i]; |
836 | c88d6bde | Jan Kiszka | if (value & 0xf && t->limit > 0) { |
837 | b47b50fa | Paul Brook | ptimer_set_limit(t->ptimer, t->limit, 0);
|
838 | b47b50fa | Paul Brook | ptimer_set_freq(t->ptimer, t->freq); |
839 | b47b50fa | Paul Brook | ptimer_run(t->ptimer, 0);
|
840 | c88d6bde | Jan Kiszka | } else {
|
841 | c88d6bde | Jan Kiszka | ptimer_stop(t->ptimer); |
842 | 24859b68 | balrog | } |
843 | 24859b68 | balrog | value >>= 4;
|
844 | 24859b68 | balrog | } |
845 | 24859b68 | balrog | break;
|
846 | 24859b68 | balrog | |
847 | 24859b68 | balrog | case MP_BOARD_RESET:
|
848 | 49fedd0d | Jan Kiszka | if (value == MP_BOARD_RESET_MAGIC) {
|
849 | 24859b68 | balrog | qemu_system_reset_request(); |
850 | 49fedd0d | Jan Kiszka | } |
851 | 24859b68 | balrog | break;
|
852 | 24859b68 | balrog | } |
853 | 24859b68 | balrog | } |
854 | 24859b68 | balrog | |
855 | d5b61ddd | Jan Kiszka | static void mv88w8618_pit_reset(DeviceState *d) |
856 | c88d6bde | Jan Kiszka | { |
857 | d5b61ddd | Jan Kiszka | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, |
858 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
859 | c88d6bde | Jan Kiszka | int i;
|
860 | c88d6bde | Jan Kiszka | |
861 | c88d6bde | Jan Kiszka | for (i = 0; i < 4; i++) { |
862 | c88d6bde | Jan Kiszka | ptimer_stop(s->timer[i].ptimer); |
863 | c88d6bde | Jan Kiszka | s->timer[i].limit = 0;
|
864 | c88d6bde | Jan Kiszka | } |
865 | c88d6bde | Jan Kiszka | } |
866 | c88d6bde | Jan Kiszka | |
867 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
868 | 24859b68 | balrog | mv88w8618_pit_read, |
869 | 24859b68 | balrog | mv88w8618_pit_read, |
870 | 24859b68 | balrog | mv88w8618_pit_read |
871 | 24859b68 | balrog | }; |
872 | 24859b68 | balrog | |
873 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
874 | 24859b68 | balrog | mv88w8618_pit_write, |
875 | 24859b68 | balrog | mv88w8618_pit_write, |
876 | 24859b68 | balrog | mv88w8618_pit_write |
877 | 24859b68 | balrog | }; |
878 | 24859b68 | balrog | |
879 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_pit_init(SysBusDevice *dev) |
880 | 24859b68 | balrog | { |
881 | 24859b68 | balrog | int iomemtype;
|
882 | b47b50fa | Paul Brook | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
883 | b47b50fa | Paul Brook | int i;
|
884 | 24859b68 | balrog | |
885 | 24859b68 | balrog | /* Letting them all run at 1 MHz is likely just a pragmatic
|
886 | 24859b68 | balrog | * simplification. */
|
887 | b47b50fa | Paul Brook | for (i = 0; i < 4; i++) { |
888 | b47b50fa | Paul Brook | mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
889 | b47b50fa | Paul Brook | } |
890 | 24859b68 | balrog | |
891 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
892 | 2507c12a | Alexander Graf | mv88w8618_pit_writefn, s, |
893 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
894 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
895 | 81a322d4 | Gerd Hoffmann | return 0; |
896 | 24859b68 | balrog | } |
897 | 24859b68 | balrog | |
898 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_timer_vmsd = { |
899 | d5b61ddd | Jan Kiszka | .name = "timer",
|
900 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
901 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
902 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
903 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
904 | d5b61ddd | Jan Kiszka | VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), |
905 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(limit, mv88w8618_timer_state), |
906 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
907 | d5b61ddd | Jan Kiszka | } |
908 | d5b61ddd | Jan Kiszka | }; |
909 | d5b61ddd | Jan Kiszka | |
910 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_pit_vmsd = { |
911 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_pit",
|
912 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
913 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
914 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
915 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
916 | d5b61ddd | Jan Kiszka | VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, |
917 | d5b61ddd | Jan Kiszka | mv88w8618_timer_vmsd, mv88w8618_timer_state), |
918 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
919 | d5b61ddd | Jan Kiszka | } |
920 | d5b61ddd | Jan Kiszka | }; |
921 | d5b61ddd | Jan Kiszka | |
922 | c88d6bde | Jan Kiszka | static SysBusDeviceInfo mv88w8618_pit_info = {
|
923 | c88d6bde | Jan Kiszka | .init = mv88w8618_pit_init, |
924 | c88d6bde | Jan Kiszka | .qdev.name = "mv88w8618_pit",
|
925 | c88d6bde | Jan Kiszka | .qdev.size = sizeof(mv88w8618_pit_state),
|
926 | c88d6bde | Jan Kiszka | .qdev.reset = mv88w8618_pit_reset, |
927 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_pit_vmsd, |
928 | c88d6bde | Jan Kiszka | }; |
929 | c88d6bde | Jan Kiszka | |
930 | 24859b68 | balrog | /* Flash config register offsets */
|
931 | 24859b68 | balrog | #define MP_FLASHCFG_CFGR0 0x04 |
932 | 24859b68 | balrog | |
933 | 24859b68 | balrog | typedef struct mv88w8618_flashcfg_state { |
934 | b47b50fa | Paul Brook | SysBusDevice busdev; |
935 | 24859b68 | balrog | uint32_t cfgr0; |
936 | 24859b68 | balrog | } mv88w8618_flashcfg_state; |
937 | 24859b68 | balrog | |
938 | 24859b68 | balrog | static uint32_t mv88w8618_flashcfg_read(void *opaque, |
939 | c227f099 | Anthony Liguori | target_phys_addr_t offset) |
940 | 24859b68 | balrog | { |
941 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
942 | 24859b68 | balrog | |
943 | 24859b68 | balrog | switch (offset) {
|
944 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
945 | 24859b68 | balrog | return s->cfgr0;
|
946 | 24859b68 | balrog | |
947 | 24859b68 | balrog | default:
|
948 | 24859b68 | balrog | return 0; |
949 | 24859b68 | balrog | } |
950 | 24859b68 | balrog | } |
951 | 24859b68 | balrog | |
952 | c227f099 | Anthony Liguori | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
953 | 24859b68 | balrog | uint32_t value) |
954 | 24859b68 | balrog | { |
955 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
956 | 24859b68 | balrog | |
957 | 24859b68 | balrog | switch (offset) {
|
958 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
959 | 24859b68 | balrog | s->cfgr0 = value; |
960 | 24859b68 | balrog | break;
|
961 | 24859b68 | balrog | } |
962 | 24859b68 | balrog | } |
963 | 24859b68 | balrog | |
964 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
965 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
966 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
967 | 24859b68 | balrog | mv88w8618_flashcfg_read |
968 | 24859b68 | balrog | }; |
969 | 24859b68 | balrog | |
970 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
971 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
972 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
973 | 24859b68 | balrog | mv88w8618_flashcfg_write |
974 | 24859b68 | balrog | }; |
975 | 24859b68 | balrog | |
976 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_flashcfg_init(SysBusDevice *dev) |
977 | 24859b68 | balrog | { |
978 | 24859b68 | balrog | int iomemtype;
|
979 | b47b50fa | Paul Brook | mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
980 | 24859b68 | balrog | |
981 | 24859b68 | balrog | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
982 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
983 | 2507c12a | Alexander Graf | mv88w8618_flashcfg_writefn, s, |
984 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
985 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
986 | 81a322d4 | Gerd Hoffmann | return 0; |
987 | 24859b68 | balrog | } |
988 | 24859b68 | balrog | |
989 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
990 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_flashcfg",
|
991 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
992 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
993 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
994 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
995 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), |
996 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
997 | d5b61ddd | Jan Kiszka | } |
998 | d5b61ddd | Jan Kiszka | }; |
999 | d5b61ddd | Jan Kiszka | |
1000 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_flashcfg_info = {
|
1001 | d5b61ddd | Jan Kiszka | .init = mv88w8618_flashcfg_init, |
1002 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_flashcfg",
|
1003 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_flashcfg_state),
|
1004 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_flashcfg_vmsd, |
1005 | d5b61ddd | Jan Kiszka | }; |
1006 | d5b61ddd | Jan Kiszka | |
1007 | 718ec0be | malc | /* Misc register offsets */
|
1008 | 718ec0be | malc | #define MP_MISC_BOARD_REVISION 0x18 |
1009 | 718ec0be | malc | |
1010 | 718ec0be | malc | #define MP_BOARD_REVISION 0x31 |
1011 | 718ec0be | malc | |
1012 | c227f099 | Anthony Liguori | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
1013 | 718ec0be | malc | { |
1014 | 718ec0be | malc | switch (offset) {
|
1015 | 718ec0be | malc | case MP_MISC_BOARD_REVISION:
|
1016 | 718ec0be | malc | return MP_BOARD_REVISION;
|
1017 | 718ec0be | malc | |
1018 | 718ec0be | malc | default:
|
1019 | 718ec0be | malc | return 0; |
1020 | 718ec0be | malc | } |
1021 | 718ec0be | malc | } |
1022 | 718ec0be | malc | |
1023 | c227f099 | Anthony Liguori | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
1024 | 718ec0be | malc | uint32_t value) |
1025 | 718ec0be | malc | { |
1026 | 718ec0be | malc | } |
1027 | 718ec0be | malc | |
1028 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
1029 | 718ec0be | malc | musicpal_misc_read, |
1030 | 718ec0be | malc | musicpal_misc_read, |
1031 | 718ec0be | malc | musicpal_misc_read, |
1032 | 718ec0be | malc | }; |
1033 | 718ec0be | malc | |
1034 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
1035 | 718ec0be | malc | musicpal_misc_write, |
1036 | 718ec0be | malc | musicpal_misc_write, |
1037 | 718ec0be | malc | musicpal_misc_write, |
1038 | 718ec0be | malc | }; |
1039 | 718ec0be | malc | |
1040 | 718ec0be | malc | static void musicpal_misc_init(void) |
1041 | 718ec0be | malc | { |
1042 | 718ec0be | malc | int iomemtype;
|
1043 | 718ec0be | malc | |
1044 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
1045 | 2507c12a | Alexander Graf | musicpal_misc_writefn, NULL,
|
1046 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1047 | 718ec0be | malc | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
1048 | 718ec0be | malc | } |
1049 | 718ec0be | malc | |
1050 | 718ec0be | malc | /* WLAN register offsets */
|
1051 | 718ec0be | malc | #define MP_WLAN_MAGIC1 0x11c |
1052 | 718ec0be | malc | #define MP_WLAN_MAGIC2 0x124 |
1053 | 718ec0be | malc | |
1054 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
1055 | 718ec0be | malc | { |
1056 | 718ec0be | malc | switch (offset) {
|
1057 | 718ec0be | malc | /* Workaround to allow loading the binary-only wlandrv.ko crap
|
1058 | 718ec0be | malc | * from the original Freecom firmware. */
|
1059 | 718ec0be | malc | case MP_WLAN_MAGIC1:
|
1060 | 718ec0be | malc | return ~3; |
1061 | 718ec0be | malc | case MP_WLAN_MAGIC2:
|
1062 | 718ec0be | malc | return -1; |
1063 | 718ec0be | malc | |
1064 | 718ec0be | malc | default:
|
1065 | 718ec0be | malc | return 0; |
1066 | 718ec0be | malc | } |
1067 | 718ec0be | malc | } |
1068 | 718ec0be | malc | |
1069 | c227f099 | Anthony Liguori | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
1070 | 718ec0be | malc | uint32_t value) |
1071 | 718ec0be | malc | { |
1072 | 718ec0be | malc | } |
1073 | 718ec0be | malc | |
1074 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
1075 | 718ec0be | malc | mv88w8618_wlan_read, |
1076 | 718ec0be | malc | mv88w8618_wlan_read, |
1077 | 718ec0be | malc | mv88w8618_wlan_read, |
1078 | 718ec0be | malc | }; |
1079 | 718ec0be | malc | |
1080 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
1081 | 718ec0be | malc | mv88w8618_wlan_write, |
1082 | 718ec0be | malc | mv88w8618_wlan_write, |
1083 | 718ec0be | malc | mv88w8618_wlan_write, |
1084 | 718ec0be | malc | }; |
1085 | 718ec0be | malc | |
1086 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_wlan_init(SysBusDevice *dev) |
1087 | 718ec0be | malc | { |
1088 | 718ec0be | malc | int iomemtype;
|
1089 | 24859b68 | balrog | |
1090 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
1091 | 2507c12a | Alexander Graf | mv88w8618_wlan_writefn, NULL,
|
1092 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1093 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
1094 | 81a322d4 | Gerd Hoffmann | return 0; |
1095 | 718ec0be | malc | } |
1096 | 24859b68 | balrog | |
1097 | 718ec0be | malc | /* GPIO register offsets */
|
1098 | 718ec0be | malc | #define MP_GPIO_OE_LO 0x008 |
1099 | 718ec0be | malc | #define MP_GPIO_OUT_LO 0x00c |
1100 | 718ec0be | malc | #define MP_GPIO_IN_LO 0x010 |
1101 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IER_LO 0x014 |
1102 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IMR_LO 0x018 |
1103 | 718ec0be | malc | #define MP_GPIO_ISR_LO 0x020 |
1104 | 718ec0be | malc | #define MP_GPIO_OE_HI 0x508 |
1105 | 718ec0be | malc | #define MP_GPIO_OUT_HI 0x50c |
1106 | 718ec0be | malc | #define MP_GPIO_IN_HI 0x510 |
1107 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IER_HI 0x514 |
1108 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IMR_HI 0x518 |
1109 | 718ec0be | malc | #define MP_GPIO_ISR_HI 0x520 |
1110 | 24859b68 | balrog | |
1111 | 24859b68 | balrog | /* GPIO bits & masks */
|
1112 | 24859b68 | balrog | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1113 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA_BIT 29 |
1114 | 24859b68 | balrog | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1115 | 24859b68 | balrog | |
1116 | 24859b68 | balrog | /* LCD brightness bits in GPIO_OE_HI */
|
1117 | 24859b68 | balrog | #define MP_OE_LCD_BRIGHTNESS 0x0007 |
1118 | 24859b68 | balrog | |
1119 | 343ec8e4 | Benoit Canet | typedef struct musicpal_gpio_state { |
1120 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
1121 | 343ec8e4 | Benoit Canet | uint32_t lcd_brightness; |
1122 | 343ec8e4 | Benoit Canet | uint32_t out_state; |
1123 | 343ec8e4 | Benoit Canet | uint32_t in_state; |
1124 | 708afdf3 | Jan Kiszka | uint32_t ier; |
1125 | 708afdf3 | Jan Kiszka | uint32_t imr; |
1126 | 343ec8e4 | Benoit Canet | uint32_t isr; |
1127 | 343ec8e4 | Benoit Canet | qemu_irq irq; |
1128 | 708afdf3 | Jan Kiszka | qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
1129 | 343ec8e4 | Benoit Canet | } musicpal_gpio_state; |
1130 | 343ec8e4 | Benoit Canet | |
1131 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { |
1132 | 343ec8e4 | Benoit Canet | int i;
|
1133 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
1134 | 343ec8e4 | Benoit Canet | |
1135 | 343ec8e4 | Benoit Canet | /* compute brightness ratio */
|
1136 | 343ec8e4 | Benoit Canet | switch (s->lcd_brightness) {
|
1137 | 343ec8e4 | Benoit Canet | case 0x00000007: |
1138 | 343ec8e4 | Benoit Canet | brightness = 0;
|
1139 | 343ec8e4 | Benoit Canet | break;
|
1140 | 343ec8e4 | Benoit Canet | |
1141 | 343ec8e4 | Benoit Canet | case 0x00020000: |
1142 | 343ec8e4 | Benoit Canet | brightness = 1;
|
1143 | 343ec8e4 | Benoit Canet | break;
|
1144 | 343ec8e4 | Benoit Canet | |
1145 | 343ec8e4 | Benoit Canet | case 0x00020001: |
1146 | 343ec8e4 | Benoit Canet | brightness = 2;
|
1147 | 343ec8e4 | Benoit Canet | break;
|
1148 | 343ec8e4 | Benoit Canet | |
1149 | 343ec8e4 | Benoit Canet | case 0x00040000: |
1150 | 343ec8e4 | Benoit Canet | brightness = 3;
|
1151 | 343ec8e4 | Benoit Canet | break;
|
1152 | 343ec8e4 | Benoit Canet | |
1153 | 343ec8e4 | Benoit Canet | case 0x00010006: |
1154 | 343ec8e4 | Benoit Canet | brightness = 4;
|
1155 | 343ec8e4 | Benoit Canet | break;
|
1156 | 343ec8e4 | Benoit Canet | |
1157 | 343ec8e4 | Benoit Canet | case 0x00020005: |
1158 | 343ec8e4 | Benoit Canet | brightness = 5;
|
1159 | 343ec8e4 | Benoit Canet | break;
|
1160 | 343ec8e4 | Benoit Canet | |
1161 | 343ec8e4 | Benoit Canet | case 0x00040003: |
1162 | 343ec8e4 | Benoit Canet | brightness = 6;
|
1163 | 343ec8e4 | Benoit Canet | break;
|
1164 | 343ec8e4 | Benoit Canet | |
1165 | 343ec8e4 | Benoit Canet | case 0x00030004: |
1166 | 343ec8e4 | Benoit Canet | default:
|
1167 | 343ec8e4 | Benoit Canet | brightness = 7;
|
1168 | 343ec8e4 | Benoit Canet | } |
1169 | 343ec8e4 | Benoit Canet | |
1170 | 343ec8e4 | Benoit Canet | /* set lcd brightness GPIOs */
|
1171 | 49fedd0d | Jan Kiszka | for (i = 0; i <= 2; i++) { |
1172 | 343ec8e4 | Benoit Canet | qemu_set_irq(s->out[i], (brightness >> i) & 1);
|
1173 | 49fedd0d | Jan Kiszka | } |
1174 | 343ec8e4 | Benoit Canet | } |
1175 | 343ec8e4 | Benoit Canet | |
1176 | 708afdf3 | Jan Kiszka | static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
1177 | 343ec8e4 | Benoit Canet | { |
1178 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1179 | 708afdf3 | Jan Kiszka | uint32_t mask = 1 << pin;
|
1180 | 708afdf3 | Jan Kiszka | uint32_t delta = level << pin; |
1181 | 708afdf3 | Jan Kiszka | uint32_t old = s->in_state & mask; |
1182 | 343ec8e4 | Benoit Canet | |
1183 | 708afdf3 | Jan Kiszka | s->in_state &= ~mask; |
1184 | 708afdf3 | Jan Kiszka | s->in_state |= delta; |
1185 | 343ec8e4 | Benoit Canet | |
1186 | 708afdf3 | Jan Kiszka | if ((old ^ delta) &&
|
1187 | 708afdf3 | Jan Kiszka | ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { |
1188 | 708afdf3 | Jan Kiszka | s->isr = mask; |
1189 | 708afdf3 | Jan Kiszka | qemu_irq_raise(s->irq); |
1190 | 343ec8e4 | Benoit Canet | } |
1191 | 343ec8e4 | Benoit Canet | } |
1192 | 343ec8e4 | Benoit Canet | |
1193 | c227f099 | Anthony Liguori | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1194 | 24859b68 | balrog | { |
1195 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1196 | 343ec8e4 | Benoit Canet | |
1197 | 24859b68 | balrog | switch (offset) {
|
1198 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1199 | 343ec8e4 | Benoit Canet | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1200 | 24859b68 | balrog | |
1201 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1202 | 343ec8e4 | Benoit Canet | return s->out_state & 0xFFFF; |
1203 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1204 | 343ec8e4 | Benoit Canet | return s->out_state >> 16; |
1205 | 24859b68 | balrog | |
1206 | 24859b68 | balrog | case MP_GPIO_IN_LO:
|
1207 | 343ec8e4 | Benoit Canet | return s->in_state & 0xFFFF; |
1208 | 24859b68 | balrog | case MP_GPIO_IN_HI:
|
1209 | 343ec8e4 | Benoit Canet | return s->in_state >> 16; |
1210 | 24859b68 | balrog | |
1211 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_LO:
|
1212 | 708afdf3 | Jan Kiszka | return s->ier & 0xFFFF; |
1213 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_HI:
|
1214 | 708afdf3 | Jan Kiszka | return s->ier >> 16; |
1215 | 708afdf3 | Jan Kiszka | |
1216 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_LO:
|
1217 | 708afdf3 | Jan Kiszka | return s->imr & 0xFFFF; |
1218 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_HI:
|
1219 | 708afdf3 | Jan Kiszka | return s->imr >> 16; |
1220 | 708afdf3 | Jan Kiszka | |
1221 | 24859b68 | balrog | case MP_GPIO_ISR_LO:
|
1222 | 343ec8e4 | Benoit Canet | return s->isr & 0xFFFF; |
1223 | 24859b68 | balrog | case MP_GPIO_ISR_HI:
|
1224 | 343ec8e4 | Benoit Canet | return s->isr >> 16; |
1225 | 24859b68 | balrog | |
1226 | 24859b68 | balrog | default:
|
1227 | 24859b68 | balrog | return 0; |
1228 | 24859b68 | balrog | } |
1229 | 24859b68 | balrog | } |
1230 | 24859b68 | balrog | |
1231 | c227f099 | Anthony Liguori | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1232 | 718ec0be | malc | uint32_t value) |
1233 | 24859b68 | balrog | { |
1234 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1235 | 24859b68 | balrog | switch (offset) {
|
1236 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1237 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1238 | 24859b68 | balrog | (value & MP_OE_LCD_BRIGHTNESS); |
1239 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1240 | 24859b68 | balrog | break;
|
1241 | 24859b68 | balrog | |
1242 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1243 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
1244 | 24859b68 | balrog | break;
|
1245 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1246 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1247 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
|
1248 | 343ec8e4 | Benoit Canet | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); |
1249 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1250 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1251 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); |
1252 | 24859b68 | balrog | break;
|
1253 | 24859b68 | balrog | |
1254 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_LO:
|
1255 | 708afdf3 | Jan Kiszka | s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); |
1256 | 708afdf3 | Jan Kiszka | break;
|
1257 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_HI:
|
1258 | 708afdf3 | Jan Kiszka | s->ier = (s->ier & 0xFFFF) | (value << 16); |
1259 | 708afdf3 | Jan Kiszka | break;
|
1260 | 708afdf3 | Jan Kiszka | |
1261 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_LO:
|
1262 | 708afdf3 | Jan Kiszka | s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); |
1263 | 708afdf3 | Jan Kiszka | break;
|
1264 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_HI:
|
1265 | 708afdf3 | Jan Kiszka | s->imr = (s->imr & 0xFFFF) | (value << 16); |
1266 | 708afdf3 | Jan Kiszka | break;
|
1267 | 24859b68 | balrog | } |
1268 | 24859b68 | balrog | } |
1269 | 24859b68 | balrog | |
1270 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
1271 | 718ec0be | malc | musicpal_gpio_read, |
1272 | 718ec0be | malc | musicpal_gpio_read, |
1273 | 718ec0be | malc | musicpal_gpio_read, |
1274 | 718ec0be | malc | }; |
1275 | 718ec0be | malc | |
1276 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
1277 | 718ec0be | malc | musicpal_gpio_write, |
1278 | 718ec0be | malc | musicpal_gpio_write, |
1279 | 718ec0be | malc | musicpal_gpio_write, |
1280 | 718ec0be | malc | }; |
1281 | 718ec0be | malc | |
1282 | d5b61ddd | Jan Kiszka | static void musicpal_gpio_reset(DeviceState *d) |
1283 | 718ec0be | malc | { |
1284 | d5b61ddd | Jan Kiszka | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, |
1285 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
1286 | 30624c92 | Jan Kiszka | |
1287 | 30624c92 | Jan Kiszka | s->lcd_brightness = 0;
|
1288 | 30624c92 | Jan Kiszka | s->out_state = 0;
|
1289 | 343ec8e4 | Benoit Canet | s->in_state = 0xffffffff;
|
1290 | 708afdf3 | Jan Kiszka | s->ier = 0;
|
1291 | 708afdf3 | Jan Kiszka | s->imr = 0;
|
1292 | 343ec8e4 | Benoit Canet | s->isr = 0;
|
1293 | 343ec8e4 | Benoit Canet | } |
1294 | 343ec8e4 | Benoit Canet | |
1295 | 81a322d4 | Gerd Hoffmann | static int musicpal_gpio_init(SysBusDevice *dev) |
1296 | 343ec8e4 | Benoit Canet | { |
1297 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); |
1298 | 718ec0be | malc | int iomemtype;
|
1299 | 718ec0be | malc | |
1300 | 343ec8e4 | Benoit Canet | sysbus_init_irq(dev, &s->irq); |
1301 | 343ec8e4 | Benoit Canet | |
1302 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
1303 | 2507c12a | Alexander Graf | musicpal_gpio_writefn, s, |
1304 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1305 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); |
1306 | 343ec8e4 | Benoit Canet | |
1307 | 708afdf3 | Jan Kiszka | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1308 | 708afdf3 | Jan Kiszka | |
1309 | 708afdf3 | Jan Kiszka | qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
|
1310 | 81a322d4 | Gerd Hoffmann | |
1311 | 81a322d4 | Gerd Hoffmann | return 0; |
1312 | 718ec0be | malc | } |
1313 | 718ec0be | malc | |
1314 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_gpio_vmsd = { |
1315 | d5b61ddd | Jan Kiszka | .name = "musicpal_gpio",
|
1316 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
1317 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
1318 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
1319 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
1320 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), |
1321 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(out_state, musicpal_gpio_state), |
1322 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(in_state, musicpal_gpio_state), |
1323 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(ier, musicpal_gpio_state), |
1324 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(imr, musicpal_gpio_state), |
1325 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(isr, musicpal_gpio_state), |
1326 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
1327 | d5b61ddd | Jan Kiszka | } |
1328 | d5b61ddd | Jan Kiszka | }; |
1329 | d5b61ddd | Jan Kiszka | |
1330 | 30624c92 | Jan Kiszka | static SysBusDeviceInfo musicpal_gpio_info = {
|
1331 | 30624c92 | Jan Kiszka | .init = musicpal_gpio_init, |
1332 | 30624c92 | Jan Kiszka | .qdev.name = "musicpal_gpio",
|
1333 | 30624c92 | Jan Kiszka | .qdev.size = sizeof(musicpal_gpio_state),
|
1334 | 30624c92 | Jan Kiszka | .qdev.reset = musicpal_gpio_reset, |
1335 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_gpio_vmsd, |
1336 | 30624c92 | Jan Kiszka | }; |
1337 | 30624c92 | Jan Kiszka | |
1338 | 24859b68 | balrog | /* Keyboard codes & masks */
|
1339 | 7c6ce4ba | balrog | #define KEY_RELEASED 0x80 |
1340 | 24859b68 | balrog | #define KEY_CODE 0x7f |
1341 | 24859b68 | balrog | |
1342 | 24859b68 | balrog | #define KEYCODE_TAB 0x0f |
1343 | 24859b68 | balrog | #define KEYCODE_ENTER 0x1c |
1344 | 24859b68 | balrog | #define KEYCODE_F 0x21 |
1345 | 24859b68 | balrog | #define KEYCODE_M 0x32 |
1346 | 24859b68 | balrog | |
1347 | 24859b68 | balrog | #define KEYCODE_EXTENDED 0xe0 |
1348 | 24859b68 | balrog | #define KEYCODE_UP 0x48 |
1349 | 24859b68 | balrog | #define KEYCODE_DOWN 0x50 |
1350 | 24859b68 | balrog | #define KEYCODE_LEFT 0x4b |
1351 | 24859b68 | balrog | #define KEYCODE_RIGHT 0x4d |
1352 | 24859b68 | balrog | |
1353 | 708afdf3 | Jan Kiszka | #define MP_KEY_WHEEL_VOL (1 << 0) |
1354 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1355 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV (1 << 2) |
1356 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV_INV (1 << 3) |
1357 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_FAVORITS (1 << 4) |
1358 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_MENU (1 << 5) |
1359 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_VOLUME (1 << 6) |
1360 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_NAVIGATION (1 << 7) |
1361 | 343ec8e4 | Benoit Canet | |
1362 | 343ec8e4 | Benoit Canet | typedef struct musicpal_key_state { |
1363 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
1364 | 343ec8e4 | Benoit Canet | uint32_t kbd_extended; |
1365 | 708afdf3 | Jan Kiszka | uint32_t pressed_keys; |
1366 | 708afdf3 | Jan Kiszka | qemu_irq out[8];
|
1367 | 343ec8e4 | Benoit Canet | } musicpal_key_state; |
1368 | 343ec8e4 | Benoit Canet | |
1369 | 24859b68 | balrog | static void musicpal_key_event(void *opaque, int keycode) |
1370 | 24859b68 | balrog | { |
1371 | 243cd13c | Jan Kiszka | musicpal_key_state *s = opaque; |
1372 | 24859b68 | balrog | uint32_t event = 0;
|
1373 | 343ec8e4 | Benoit Canet | int i;
|
1374 | 24859b68 | balrog | |
1375 | 24859b68 | balrog | if (keycode == KEYCODE_EXTENDED) {
|
1376 | 343ec8e4 | Benoit Canet | s->kbd_extended = 1;
|
1377 | 24859b68 | balrog | return;
|
1378 | 24859b68 | balrog | } |
1379 | 24859b68 | balrog | |
1380 | 49fedd0d | Jan Kiszka | if (s->kbd_extended) {
|
1381 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1382 | 24859b68 | balrog | case KEYCODE_UP:
|
1383 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
1384 | 24859b68 | balrog | break;
|
1385 | 24859b68 | balrog | |
1386 | 24859b68 | balrog | case KEYCODE_DOWN:
|
1387 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV; |
1388 | 24859b68 | balrog | break;
|
1389 | 24859b68 | balrog | |
1390 | 24859b68 | balrog | case KEYCODE_LEFT:
|
1391 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
1392 | 24859b68 | balrog | break;
|
1393 | 24859b68 | balrog | |
1394 | 24859b68 | balrog | case KEYCODE_RIGHT:
|
1395 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL; |
1396 | 24859b68 | balrog | break;
|
1397 | 24859b68 | balrog | } |
1398 | 49fedd0d | Jan Kiszka | } else {
|
1399 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1400 | 24859b68 | balrog | case KEYCODE_F:
|
1401 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_FAVORITS; |
1402 | 24859b68 | balrog | break;
|
1403 | 24859b68 | balrog | |
1404 | 24859b68 | balrog | case KEYCODE_TAB:
|
1405 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_VOLUME; |
1406 | 24859b68 | balrog | break;
|
1407 | 24859b68 | balrog | |
1408 | 24859b68 | balrog | case KEYCODE_ENTER:
|
1409 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_NAVIGATION; |
1410 | 24859b68 | balrog | break;
|
1411 | 24859b68 | balrog | |
1412 | 24859b68 | balrog | case KEYCODE_M:
|
1413 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_MENU; |
1414 | 24859b68 | balrog | break;
|
1415 | 24859b68 | balrog | } |
1416 | 7c6ce4ba | balrog | /* Do not repeat already pressed buttons */
|
1417 | 708afdf3 | Jan Kiszka | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1418 | 7c6ce4ba | balrog | event = 0;
|
1419 | 708afdf3 | Jan Kiszka | } |
1420 | 7c6ce4ba | balrog | } |
1421 | 24859b68 | balrog | |
1422 | 7c6ce4ba | balrog | if (event) {
|
1423 | 708afdf3 | Jan Kiszka | /* Raise GPIO pin first if repeating a key */
|
1424 | 708afdf3 | Jan Kiszka | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1425 | 708afdf3 | Jan Kiszka | for (i = 0; i <= 7; i++) { |
1426 | 708afdf3 | Jan Kiszka | if (event & (1 << i)) { |
1427 | 708afdf3 | Jan Kiszka | qemu_set_irq(s->out[i], 1);
|
1428 | 708afdf3 | Jan Kiszka | } |
1429 | 708afdf3 | Jan Kiszka | } |
1430 | 708afdf3 | Jan Kiszka | } |
1431 | 708afdf3 | Jan Kiszka | for (i = 0; i <= 7; i++) { |
1432 | 708afdf3 | Jan Kiszka | if (event & (1 << i)) { |
1433 | 708afdf3 | Jan Kiszka | qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); |
1434 | 708afdf3 | Jan Kiszka | } |
1435 | 708afdf3 | Jan Kiszka | } |
1436 | 7c6ce4ba | balrog | if (keycode & KEY_RELEASED) {
|
1437 | 708afdf3 | Jan Kiszka | s->pressed_keys &= ~event; |
1438 | 7c6ce4ba | balrog | } else {
|
1439 | 708afdf3 | Jan Kiszka | s->pressed_keys |= event; |
1440 | 7c6ce4ba | balrog | } |
1441 | 24859b68 | balrog | } |
1442 | 24859b68 | balrog | |
1443 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1444 | 343ec8e4 | Benoit Canet | } |
1445 | 343ec8e4 | Benoit Canet | |
1446 | 81a322d4 | Gerd Hoffmann | static int musicpal_key_init(SysBusDevice *dev) |
1447 | 343ec8e4 | Benoit Canet | { |
1448 | 343ec8e4 | Benoit Canet | musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); |
1449 | 343ec8e4 | Benoit Canet | |
1450 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, 0x0, 0); |
1451 | 343ec8e4 | Benoit Canet | |
1452 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1453 | 708afdf3 | Jan Kiszka | s->pressed_keys = 0;
|
1454 | 343ec8e4 | Benoit Canet | |
1455 | 708afdf3 | Jan Kiszka | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1456 | 343ec8e4 | Benoit Canet | |
1457 | 343ec8e4 | Benoit Canet | qemu_add_kbd_event_handler(musicpal_key_event, s); |
1458 | 81a322d4 | Gerd Hoffmann | |
1459 | 81a322d4 | Gerd Hoffmann | return 0; |
1460 | 24859b68 | balrog | } |
1461 | 24859b68 | balrog | |
1462 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_key_vmsd = { |
1463 | d5b61ddd | Jan Kiszka | .name = "musicpal_key",
|
1464 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
1465 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
1466 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
1467 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
1468 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(kbd_extended, musicpal_key_state), |
1469 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(pressed_keys, musicpal_key_state), |
1470 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
1471 | d5b61ddd | Jan Kiszka | } |
1472 | d5b61ddd | Jan Kiszka | }; |
1473 | d5b61ddd | Jan Kiszka | |
1474 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo musicpal_key_info = {
|
1475 | d5b61ddd | Jan Kiszka | .init = musicpal_key_init, |
1476 | d5b61ddd | Jan Kiszka | .qdev.name = "musicpal_key",
|
1477 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(musicpal_key_state),
|
1478 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_key_vmsd, |
1479 | d5b61ddd | Jan Kiszka | }; |
1480 | d5b61ddd | Jan Kiszka | |
1481 | 24859b68 | balrog | static struct arm_boot_info musicpal_binfo = { |
1482 | 24859b68 | balrog | .loader_start = 0x0,
|
1483 | 24859b68 | balrog | .board_id = 0x20e,
|
1484 | 24859b68 | balrog | }; |
1485 | 24859b68 | balrog | |
1486 | c227f099 | Anthony Liguori | static void musicpal_init(ram_addr_t ram_size, |
1487 | 3023f332 | aliguori | const char *boot_device, |
1488 | 24859b68 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1489 | 24859b68 | balrog | const char *initrd_filename, const char *cpu_model) |
1490 | 24859b68 | balrog | { |
1491 | 24859b68 | balrog | CPUState *env; |
1492 | b47b50fa | Paul Brook | qemu_irq *cpu_pic; |
1493 | b47b50fa | Paul Brook | qemu_irq pic[32];
|
1494 | b47b50fa | Paul Brook | DeviceState *dev; |
1495 | d074769c | Andrzej Zaborowski | DeviceState *i2c_dev; |
1496 | 343ec8e4 | Benoit Canet | DeviceState *lcd_dev; |
1497 | 343ec8e4 | Benoit Canet | DeviceState *key_dev; |
1498 | d074769c | Andrzej Zaborowski | DeviceState *wm8750_dev; |
1499 | d074769c | Andrzej Zaborowski | SysBusDevice *s; |
1500 | d074769c | Andrzej Zaborowski | i2c_bus *i2c; |
1501 | b47b50fa | Paul Brook | int i;
|
1502 | 24859b68 | balrog | unsigned long flash_size; |
1503 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
1504 | c227f099 | Anthony Liguori | ram_addr_t sram_off; |
1505 | 24859b68 | balrog | |
1506 | 49fedd0d | Jan Kiszka | if (!cpu_model) {
|
1507 | 24859b68 | balrog | cpu_model = "arm926";
|
1508 | 49fedd0d | Jan Kiszka | } |
1509 | 24859b68 | balrog | env = cpu_init(cpu_model); |
1510 | 24859b68 | balrog | if (!env) {
|
1511 | 24859b68 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
1512 | 24859b68 | balrog | exit(1);
|
1513 | 24859b68 | balrog | } |
1514 | b47b50fa | Paul Brook | cpu_pic = arm_pic_init_cpu(env); |
1515 | 24859b68 | balrog | |
1516 | 24859b68 | balrog | /* For now we use a fixed - the original - RAM size */
|
1517 | 24859b68 | balrog | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1518 | 1724f049 | Alex Williamson | qemu_ram_alloc(NULL, "musicpal.ram", |
1519 | 1724f049 | Alex Williamson | MP_RAM_DEFAULT_SIZE)); |
1520 | 24859b68 | balrog | |
1521 | 1724f049 | Alex Williamson | sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE); |
1522 | 24859b68 | balrog | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1523 | 24859b68 | balrog | |
1524 | b47b50fa | Paul Brook | dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
|
1525 | b47b50fa | Paul Brook | cpu_pic[ARM_PIC_CPU_IRQ]); |
1526 | b47b50fa | Paul Brook | for (i = 0; i < 32; i++) { |
1527 | 067a3ddc | Paul Brook | pic[i] = qdev_get_gpio_in(dev, i); |
1528 | b47b50fa | Paul Brook | } |
1529 | b47b50fa | Paul Brook | sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
|
1530 | b47b50fa | Paul Brook | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1531 | b47b50fa | Paul Brook | pic[MP_TIMER4_IRQ], NULL);
|
1532 | 24859b68 | balrog | |
1533 | 49fedd0d | Jan Kiszka | if (serial_hds[0]) { |
1534 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
|
1535 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1536 | 2d48377a | Blue Swirl | serial_hds[0], 1, 1); |
1537 | 2d48377a | Blue Swirl | #else
|
1538 | 2d48377a | Blue Swirl | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1539 | 2d48377a | Blue Swirl | serial_hds[0], 1, 0); |
1540 | 2d48377a | Blue Swirl | #endif
|
1541 | 49fedd0d | Jan Kiszka | } |
1542 | 49fedd0d | Jan Kiszka | if (serial_hds[1]) { |
1543 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
|
1544 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1545 | 2d48377a | Blue Swirl | serial_hds[1], 1, 1); |
1546 | 2d48377a | Blue Swirl | #else
|
1547 | 2d48377a | Blue Swirl | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1548 | 2d48377a | Blue Swirl | serial_hds[1], 1, 0); |
1549 | 2d48377a | Blue Swirl | #endif
|
1550 | 49fedd0d | Jan Kiszka | } |
1551 | 24859b68 | balrog | |
1552 | 24859b68 | balrog | /* Register flash */
|
1553 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_PFLASH, 0, 0); |
1554 | 751c6a17 | Gerd Hoffmann | if (dinfo) {
|
1555 | 751c6a17 | Gerd Hoffmann | flash_size = bdrv_getlength(dinfo->bdrv); |
1556 | 24859b68 | balrog | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1557 | 24859b68 | balrog | flash_size != 32*1024*1024) { |
1558 | 24859b68 | balrog | fprintf(stderr, "Invalid flash image size\n");
|
1559 | 24859b68 | balrog | exit(1);
|
1560 | 24859b68 | balrog | } |
1561 | 24859b68 | balrog | |
1562 | 24859b68 | balrog | /*
|
1563 | 24859b68 | balrog | * The original U-Boot accesses the flash at 0xFE000000 instead of
|
1564 | 24859b68 | balrog | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1565 | 24859b68 | balrog | * image is smaller than 32 MB.
|
1566 | 24859b68 | balrog | */
|
1567 | 5f9fc5ad | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
|
1568 | 1724f049 | Alex Williamson | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL, |
1569 | 1724f049 | Alex Williamson | "musicpal.flash", flash_size),
|
1570 | 751c6a17 | Gerd Hoffmann | dinfo->bdrv, 0x10000,
|
1571 | 24859b68 | balrog | (flash_size + 0xffff) >> 16, |
1572 | 24859b68 | balrog | MP_FLASH_SIZE_MAX / flash_size, |
1573 | 24859b68 | balrog | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1574 | 5f9fc5ad | Blue Swirl | 0x5555, 0x2AAA, 1); |
1575 | 5f9fc5ad | Blue Swirl | #else
|
1576 | 1724f049 | Alex Williamson | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL, |
1577 | 1724f049 | Alex Williamson | "musicpal.flash", flash_size),
|
1578 | 5f9fc5ad | Blue Swirl | dinfo->bdrv, 0x10000,
|
1579 | 5f9fc5ad | Blue Swirl | (flash_size + 0xffff) >> 16, |
1580 | 5f9fc5ad | Blue Swirl | MP_FLASH_SIZE_MAX / flash_size, |
1581 | 5f9fc5ad | Blue Swirl | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1582 | 5f9fc5ad | Blue Swirl | 0x5555, 0x2AAA, 0); |
1583 | 5f9fc5ad | Blue Swirl | #endif
|
1584 | 5f9fc5ad | Blue Swirl | |
1585 | 24859b68 | balrog | } |
1586 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
1587 | 24859b68 | balrog | |
1588 | b47b50fa | Paul Brook | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1589 | b47b50fa | Paul Brook | dev = qdev_create(NULL, "mv88w8618_eth"); |
1590 | 4c91cd28 | Gerd Hoffmann | qdev_set_nic_properties(dev, &nd_table[0]);
|
1591 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1592 | b47b50fa | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
|
1593 | b47b50fa | Paul Brook | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
|
1594 | 24859b68 | balrog | |
1595 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
1596 | 718ec0be | malc | |
1597 | 718ec0be | malc | musicpal_misc_init(); |
1598 | 343ec8e4 | Benoit Canet | |
1599 | 343ec8e4 | Benoit Canet | dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
|
1600 | 3cd035d8 | Paul Brook | i2c_dev = sysbus_create_simple("gpio_i2c", 0, NULL); |
1601 | d074769c | Andrzej Zaborowski | i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
|
1602 | d074769c | Andrzej Zaborowski | |
1603 | 343ec8e4 | Benoit Canet | lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1604 | 343ec8e4 | Benoit Canet | key_dev = sysbus_create_simple("musicpal_key", 0, NULL); |
1605 | 343ec8e4 | Benoit Canet | |
1606 | d074769c | Andrzej Zaborowski | /* I2C read data */
|
1607 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(i2c_dev, 0,
|
1608 | 708afdf3 | Jan Kiszka | qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); |
1609 | d074769c | Andrzej Zaborowski | /* I2C data */
|
1610 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); |
1611 | d074769c | Andrzej Zaborowski | /* I2C clock */
|
1612 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); |
1613 | d074769c | Andrzej Zaborowski | |
1614 | 49fedd0d | Jan Kiszka | for (i = 0; i < 3; i++) { |
1615 | 343ec8e4 | Benoit Canet | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
1616 | 49fedd0d | Jan Kiszka | } |
1617 | 708afdf3 | Jan Kiszka | for (i = 0; i < 4; i++) { |
1618 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
|
1619 | 708afdf3 | Jan Kiszka | } |
1620 | 708afdf3 | Jan Kiszka | for (i = 4; i < 8; i++) { |
1621 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
|
1622 | 708afdf3 | Jan Kiszka | } |
1623 | 24859b68 | balrog | |
1624 | d074769c | Andrzej Zaborowski | wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
|
1625 | d074769c | Andrzej Zaborowski | dev = qdev_create(NULL, "mv88w8618_audio"); |
1626 | d074769c | Andrzej Zaborowski | s = sysbus_from_qdev(dev); |
1627 | d074769c | Andrzej Zaborowski | qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
|
1628 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1629 | d074769c | Andrzej Zaborowski | sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
1630 | d074769c | Andrzej Zaborowski | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
|
1631 | d074769c | Andrzej Zaborowski | |
1632 | 24859b68 | balrog | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1633 | 24859b68 | balrog | musicpal_binfo.kernel_filename = kernel_filename; |
1634 | 24859b68 | balrog | musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1635 | 24859b68 | balrog | musicpal_binfo.initrd_filename = initrd_filename; |
1636 | b0f6edb1 | balrog | arm_load_kernel(env, &musicpal_binfo); |
1637 | 24859b68 | balrog | } |
1638 | 24859b68 | balrog | |
1639 | f80f9ec9 | Anthony Liguori | static QEMUMachine musicpal_machine = {
|
1640 | 4b32e168 | aliguori | .name = "musicpal",
|
1641 | 4b32e168 | aliguori | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1642 | 4b32e168 | aliguori | .init = musicpal_init, |
1643 | 24859b68 | balrog | }; |
1644 | b47b50fa | Paul Brook | |
1645 | f80f9ec9 | Anthony Liguori | static void musicpal_machine_init(void) |
1646 | f80f9ec9 | Anthony Liguori | { |
1647 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&musicpal_machine); |
1648 | f80f9ec9 | Anthony Liguori | } |
1649 | f80f9ec9 | Anthony Liguori | |
1650 | f80f9ec9 | Anthony Liguori | machine_init(musicpal_machine_init); |
1651 | f80f9ec9 | Anthony Liguori | |
1652 | b47b50fa | Paul Brook | static void musicpal_register_devices(void) |
1653 | b47b50fa | Paul Brook | { |
1654 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_pic_info); |
1655 | c88d6bde | Jan Kiszka | sysbus_register_withprop(&mv88w8618_pit_info); |
1656 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_flashcfg_info); |
1657 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_eth_info); |
1658 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), |
1659 | b47b50fa | Paul Brook | mv88w8618_wlan_init); |
1660 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&musicpal_lcd_info); |
1661 | 30624c92 | Jan Kiszka | sysbus_register_withprop(&musicpal_gpio_info); |
1662 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&musicpal_key_info); |
1663 | b47b50fa | Paul Brook | } |
1664 | b47b50fa | Paul Brook | |
1665 | b47b50fa | Paul Brook | device_init(musicpal_register_devices) |