root / hw / milkymist-pfpu.c @ ad03502b
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1 | 5ee18b9c | Michael Walle | /*
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2 | 5ee18b9c | Michael Walle | * QEMU model of the Milkymist programmable FPU.
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3 | 5ee18b9c | Michael Walle | *
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4 | 5ee18b9c | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | 5ee18b9c | Michael Walle | *
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6 | 5ee18b9c | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | 5ee18b9c | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | 5ee18b9c | Michael Walle | * License as published by the Free Software Foundation; either
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9 | 5ee18b9c | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | 5ee18b9c | Michael Walle | *
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11 | 5ee18b9c | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | 5ee18b9c | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 5ee18b9c | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 5ee18b9c | Michael Walle | * Lesser General Public License for more details.
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15 | 5ee18b9c | Michael Walle | *
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16 | 5ee18b9c | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | 5ee18b9c | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 5ee18b9c | Michael Walle | *
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19 | 5ee18b9c | Michael Walle | *
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20 | 5ee18b9c | Michael Walle | * Specification available at:
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21 | 5ee18b9c | Michael Walle | * http://www.milkymist.org/socdoc/pfpu.pdf
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22 | 5ee18b9c | Michael Walle | *
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23 | 5ee18b9c | Michael Walle | */
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24 | 5ee18b9c | Michael Walle | |
25 | 5ee18b9c | Michael Walle | #include "hw.h" |
26 | 5ee18b9c | Michael Walle | #include "sysbus.h" |
27 | 5ee18b9c | Michael Walle | #include "trace.h" |
28 | 5ee18b9c | Michael Walle | #include "qemu-log.h" |
29 | 5ee18b9c | Michael Walle | #include "qemu-error.h" |
30 | 5ee18b9c | Michael Walle | #include <math.h> |
31 | 5ee18b9c | Michael Walle | |
32 | 5ee18b9c | Michael Walle | /* #define TRACE_EXEC */
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33 | 5ee18b9c | Michael Walle | |
34 | 5ee18b9c | Michael Walle | #ifdef TRACE_EXEC
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35 | 5ee18b9c | Michael Walle | # define D_EXEC(x) x
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36 | 5ee18b9c | Michael Walle | #else
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37 | 5ee18b9c | Michael Walle | # define D_EXEC(x)
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38 | 5ee18b9c | Michael Walle | #endif
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39 | 5ee18b9c | Michael Walle | |
40 | 5ee18b9c | Michael Walle | enum {
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41 | 5ee18b9c | Michael Walle | R_CTL = 0,
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42 | 5ee18b9c | Michael Walle | R_MESHBASE, |
43 | 5ee18b9c | Michael Walle | R_HMESHLAST, |
44 | 5ee18b9c | Michael Walle | R_VMESHLAST, |
45 | 5ee18b9c | Michael Walle | R_CODEPAGE, |
46 | 5ee18b9c | Michael Walle | R_VERTICES, |
47 | 5ee18b9c | Michael Walle | R_COLLISIONS, |
48 | 5ee18b9c | Michael Walle | R_STRAYWRITES, |
49 | 5ee18b9c | Michael Walle | R_LASTDMA, |
50 | 5ee18b9c | Michael Walle | R_PC, |
51 | 5ee18b9c | Michael Walle | R_DREGBASE, |
52 | 5ee18b9c | Michael Walle | R_CODEBASE, |
53 | 5ee18b9c | Michael Walle | R_MAX |
54 | 5ee18b9c | Michael Walle | }; |
55 | 5ee18b9c | Michael Walle | |
56 | 5ee18b9c | Michael Walle | enum {
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57 | 5ee18b9c | Michael Walle | CTL_START_BUSY = (1<<0), |
58 | 5ee18b9c | Michael Walle | }; |
59 | 5ee18b9c | Michael Walle | |
60 | 5ee18b9c | Michael Walle | enum {
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61 | 5ee18b9c | Michael Walle | OP_NOP = 0,
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62 | 5ee18b9c | Michael Walle | OP_FADD, |
63 | 5ee18b9c | Michael Walle | OP_FSUB, |
64 | 5ee18b9c | Michael Walle | OP_FMUL, |
65 | 5ee18b9c | Michael Walle | OP_FABS, |
66 | 5ee18b9c | Michael Walle | OP_F2I, |
67 | 5ee18b9c | Michael Walle | OP_I2F, |
68 | 5ee18b9c | Michael Walle | OP_VECTOUT, |
69 | 5ee18b9c | Michael Walle | OP_SIN, |
70 | 5ee18b9c | Michael Walle | OP_COS, |
71 | 5ee18b9c | Michael Walle | OP_ABOVE, |
72 | 5ee18b9c | Michael Walle | OP_EQUAL, |
73 | 5ee18b9c | Michael Walle | OP_COPY, |
74 | 5ee18b9c | Michael Walle | OP_IF, |
75 | 5ee18b9c | Michael Walle | OP_TSIGN, |
76 | 5ee18b9c | Michael Walle | OP_QUAKE, |
77 | 5ee18b9c | Michael Walle | }; |
78 | 5ee18b9c | Michael Walle | |
79 | 5ee18b9c | Michael Walle | enum {
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80 | 5ee18b9c | Michael Walle | GPR_X = 0,
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81 | 5ee18b9c | Michael Walle | GPR_Y = 1,
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82 | 5ee18b9c | Michael Walle | GPR_FLAGS = 2,
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83 | 5ee18b9c | Michael Walle | }; |
84 | 5ee18b9c | Michael Walle | |
85 | 5ee18b9c | Michael Walle | enum {
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86 | 5ee18b9c | Michael Walle | LATENCY_FADD = 5,
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87 | 5ee18b9c | Michael Walle | LATENCY_FSUB = 5,
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88 | 5ee18b9c | Michael Walle | LATENCY_FMUL = 7,
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89 | 5ee18b9c | Michael Walle | LATENCY_FABS = 2,
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90 | 5ee18b9c | Michael Walle | LATENCY_F2I = 2,
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91 | 5ee18b9c | Michael Walle | LATENCY_I2F = 3,
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92 | 5ee18b9c | Michael Walle | LATENCY_VECTOUT = 0,
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93 | 5ee18b9c | Michael Walle | LATENCY_SIN = 4,
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94 | 5ee18b9c | Michael Walle | LATENCY_COS = 4,
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95 | 5ee18b9c | Michael Walle | LATENCY_ABOVE = 2,
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96 | 5ee18b9c | Michael Walle | LATENCY_EQUAL = 2,
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97 | 5ee18b9c | Michael Walle | LATENCY_COPY = 2,
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98 | 5ee18b9c | Michael Walle | LATENCY_IF = 2,
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99 | 5ee18b9c | Michael Walle | LATENCY_TSIGN = 2,
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100 | 5ee18b9c | Michael Walle | LATENCY_QUAKE = 2,
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101 | 5ee18b9c | Michael Walle | MAX_LATENCY = 7
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102 | 5ee18b9c | Michael Walle | }; |
103 | 5ee18b9c | Michael Walle | |
104 | 5ee18b9c | Michael Walle | #define GPR_BEGIN 0x100 |
105 | 5ee18b9c | Michael Walle | #define GPR_END 0x17f |
106 | 5ee18b9c | Michael Walle | #define MICROCODE_BEGIN 0x200 |
107 | 5ee18b9c | Michael Walle | #define MICROCODE_END 0x3ff |
108 | 5ee18b9c | Michael Walle | #define MICROCODE_WORDS 2048 |
109 | 5ee18b9c | Michael Walle | |
110 | 5ee18b9c | Michael Walle | #define REINTERPRET_CAST(type, val) (*((type *)&(val)))
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111 | 5ee18b9c | Michael Walle | |
112 | 5ee18b9c | Michael Walle | #ifdef TRACE_EXEC
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113 | 5ee18b9c | Michael Walle | static const char *opcode_to_str[] = { |
114 | 5ee18b9c | Michael Walle | "NOP", "FADD", "FSUB", "FMUL", "FABS", "F2I", "I2F", "VECTOUT", |
115 | 5ee18b9c | Michael Walle | "SIN", "COS", "ABOVE", "EQUAL", "COPY", "IF", "TSIGN", "QUAKE", |
116 | 5ee18b9c | Michael Walle | }; |
117 | 5ee18b9c | Michael Walle | #endif
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118 | 5ee18b9c | Michael Walle | |
119 | 5ee18b9c | Michael Walle | struct MilkymistPFPUState {
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120 | 5ee18b9c | Michael Walle | SysBusDevice busdev; |
121 | 5ee18b9c | Michael Walle | CharDriverState *chr; |
122 | 5ee18b9c | Michael Walle | qemu_irq irq; |
123 | 5ee18b9c | Michael Walle | |
124 | 5ee18b9c | Michael Walle | uint32_t regs[R_MAX]; |
125 | 5ee18b9c | Michael Walle | uint32_t gp_regs[128];
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126 | 5ee18b9c | Michael Walle | uint32_t microcode[MICROCODE_WORDS]; |
127 | 5ee18b9c | Michael Walle | |
128 | 5ee18b9c | Michael Walle | int output_queue_pos;
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129 | 5ee18b9c | Michael Walle | uint32_t output_queue[MAX_LATENCY]; |
130 | 5ee18b9c | Michael Walle | }; |
131 | 5ee18b9c | Michael Walle | typedef struct MilkymistPFPUState MilkymistPFPUState; |
132 | 5ee18b9c | Michael Walle | |
133 | 5ee18b9c | Michael Walle | static inline target_phys_addr_t |
134 | 5ee18b9c | Michael Walle | get_dma_address(uint32_t base, uint32_t x, uint32_t y) |
135 | 5ee18b9c | Michael Walle | { |
136 | 5ee18b9c | Michael Walle | return base + 8 * (128 * y + x); |
137 | 5ee18b9c | Michael Walle | } |
138 | 5ee18b9c | Michael Walle | |
139 | 5ee18b9c | Michael Walle | static inline void |
140 | 5ee18b9c | Michael Walle | output_queue_insert(MilkymistPFPUState *s, uint32_t val, int pos)
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141 | 5ee18b9c | Michael Walle | { |
142 | 5ee18b9c | Michael Walle | s->output_queue[(s->output_queue_pos + pos) % MAX_LATENCY] = val; |
143 | 5ee18b9c | Michael Walle | } |
144 | 5ee18b9c | Michael Walle | |
145 | 5ee18b9c | Michael Walle | static inline uint32_t |
146 | 5ee18b9c | Michael Walle | output_queue_remove(MilkymistPFPUState *s) |
147 | 5ee18b9c | Michael Walle | { |
148 | 5ee18b9c | Michael Walle | return s->output_queue[s->output_queue_pos];
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149 | 5ee18b9c | Michael Walle | } |
150 | 5ee18b9c | Michael Walle | |
151 | 5ee18b9c | Michael Walle | static inline void |
152 | 5ee18b9c | Michael Walle | output_queue_advance(MilkymistPFPUState *s) |
153 | 5ee18b9c | Michael Walle | { |
154 | 5ee18b9c | Michael Walle | s->output_queue[s->output_queue_pos] = 0;
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155 | 5ee18b9c | Michael Walle | s->output_queue_pos = (s->output_queue_pos + 1) % MAX_LATENCY;
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156 | 5ee18b9c | Michael Walle | } |
157 | 5ee18b9c | Michael Walle | |
158 | 5ee18b9c | Michael Walle | static int pfpu_decode_insn(MilkymistPFPUState *s) |
159 | 5ee18b9c | Michael Walle | { |
160 | 5ee18b9c | Michael Walle | uint32_t pc = s->regs[R_PC]; |
161 | 5ee18b9c | Michael Walle | uint32_t insn = s->microcode[pc]; |
162 | 5ee18b9c | Michael Walle | uint32_t reg_a = (insn >> 18) & 0x7f; |
163 | 5ee18b9c | Michael Walle | uint32_t reg_b = (insn >> 11) & 0x7f; |
164 | 5ee18b9c | Michael Walle | uint32_t op = (insn >> 7) & 0xf; |
165 | 5ee18b9c | Michael Walle | uint32_t reg_d = insn & 0x7f;
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166 | 7f7454ec | Anthony Liguori | uint32_t r = 0;
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167 | 5ee18b9c | Michael Walle | int latency = 0; |
168 | 5ee18b9c | Michael Walle | |
169 | 5ee18b9c | Michael Walle | switch (op) {
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170 | 5ee18b9c | Michael Walle | case OP_NOP:
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171 | 5ee18b9c | Michael Walle | break;
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172 | 5ee18b9c | Michael Walle | case OP_FADD:
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173 | 5ee18b9c | Michael Walle | { |
174 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
175 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
176 | 5ee18b9c | Michael Walle | float t = a + b;
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177 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
178 | 5ee18b9c | Michael Walle | latency = LATENCY_FADD; |
179 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("ADD a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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180 | 5ee18b9c | Michael Walle | } break;
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181 | 5ee18b9c | Michael Walle | case OP_FSUB:
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182 | 5ee18b9c | Michael Walle | { |
183 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
184 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
185 | 5ee18b9c | Michael Walle | float t = a - b;
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186 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
187 | 5ee18b9c | Michael Walle | latency = LATENCY_FSUB; |
188 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("SUB a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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189 | 5ee18b9c | Michael Walle | } break;
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190 | 5ee18b9c | Michael Walle | case OP_FMUL:
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191 | 5ee18b9c | Michael Walle | { |
192 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
193 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
194 | 5ee18b9c | Michael Walle | float t = a * b;
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195 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
196 | 5ee18b9c | Michael Walle | latency = LATENCY_FMUL; |
197 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("MUL a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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198 | 5ee18b9c | Michael Walle | } break;
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199 | 5ee18b9c | Michael Walle | case OP_FABS:
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200 | 5ee18b9c | Michael Walle | { |
201 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
202 | 5ee18b9c | Michael Walle | float t = fabsf(a);
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203 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
204 | 5ee18b9c | Michael Walle | latency = LATENCY_FABS; |
205 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("ABS a=%f t=%f, r=%08x\n", a, t, r));
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206 | 5ee18b9c | Michael Walle | } break;
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207 | 5ee18b9c | Michael Walle | case OP_F2I:
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208 | 5ee18b9c | Michael Walle | { |
209 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
210 | 5ee18b9c | Michael Walle | int32_t t = a; |
211 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
212 | 5ee18b9c | Michael Walle | latency = LATENCY_F2I; |
213 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("F2I a=%f t=%d, r=%08x\n", a, t, r));
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214 | 5ee18b9c | Michael Walle | } break;
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215 | 5ee18b9c | Michael Walle | case OP_I2F:
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216 | 5ee18b9c | Michael Walle | { |
217 | 5ee18b9c | Michael Walle | int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]); |
218 | 5ee18b9c | Michael Walle | float t = a;
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219 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
220 | 5ee18b9c | Michael Walle | latency = LATENCY_I2F; |
221 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("I2F a=%08x t=%f, r=%08x\n", a, t, r));
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222 | 5ee18b9c | Michael Walle | } break;
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223 | 5ee18b9c | Michael Walle | case OP_VECTOUT:
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224 | 5ee18b9c | Michael Walle | { |
225 | 5ee18b9c | Michael Walle | uint32_t a = cpu_to_be32(s->gp_regs[reg_a]); |
226 | 5ee18b9c | Michael Walle | uint32_t b = cpu_to_be32(s->gp_regs[reg_b]); |
227 | 5ee18b9c | Michael Walle | target_phys_addr_t dma_ptr = |
228 | 5ee18b9c | Michael Walle | get_dma_address(s->regs[R_MESHBASE], |
229 | 5ee18b9c | Michael Walle | s->gp_regs[GPR_X], s->gp_regs[GPR_Y]); |
230 | 5ee18b9c | Michael Walle | cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
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231 | 5ee18b9c | Michael Walle | cpu_physical_memory_write(dma_ptr + 4, (uint8_t *)&b, 4); |
232 | 5ee18b9c | Michael Walle | s->regs[R_LASTDMA] = dma_ptr + 4;
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233 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("VECTOUT a=%08x b=%08x dma=%08x\n", a, b, dma_ptr));
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234 | 5ee18b9c | Michael Walle | trace_milkymist_pfpu_vectout(a, b, dma_ptr); |
235 | 5ee18b9c | Michael Walle | } break;
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236 | 5ee18b9c | Michael Walle | case OP_SIN:
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237 | 5ee18b9c | Michael Walle | { |
238 | 5ee18b9c | Michael Walle | int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]); |
239 | 5ee18b9c | Michael Walle | float t = sinf(a * (1.0f / (M_PI * 4096.0f))); |
240 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
241 | 5ee18b9c | Michael Walle | latency = LATENCY_SIN; |
242 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("SIN a=%d t=%f, r=%08x\n", a, t, r));
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243 | 5ee18b9c | Michael Walle | } break;
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244 | 5ee18b9c | Michael Walle | case OP_COS:
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245 | 5ee18b9c | Michael Walle | { |
246 | 5ee18b9c | Michael Walle | int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]); |
247 | 5ee18b9c | Michael Walle | float t = cosf(a * (1.0f / (M_PI * 4096.0f))); |
248 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
249 | 5ee18b9c | Michael Walle | latency = LATENCY_COS; |
250 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("COS a=%d t=%f, r=%08x\n", a, t, r));
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251 | 5ee18b9c | Michael Walle | } break;
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252 | 5ee18b9c | Michael Walle | case OP_ABOVE:
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253 | 5ee18b9c | Michael Walle | { |
254 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
255 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
256 | 5ee18b9c | Michael Walle | float t = (a > b) ? 1.0f : 0.0f; |
257 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
258 | 5ee18b9c | Michael Walle | latency = LATENCY_ABOVE; |
259 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("ABOVE a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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260 | 5ee18b9c | Michael Walle | } break;
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261 | 5ee18b9c | Michael Walle | case OP_EQUAL:
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262 | 5ee18b9c | Michael Walle | { |
263 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
264 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
265 | 5ee18b9c | Michael Walle | float t = (a == b) ? 1.0f : 0.0f; |
266 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
267 | 5ee18b9c | Michael Walle | latency = LATENCY_EQUAL; |
268 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("EQUAL a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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269 | 5ee18b9c | Michael Walle | } break;
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270 | 5ee18b9c | Michael Walle | case OP_COPY:
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271 | 5ee18b9c | Michael Walle | { |
272 | 5ee18b9c | Michael Walle | r = s->gp_regs[reg_a]; |
273 | 5ee18b9c | Michael Walle | latency = LATENCY_COPY; |
274 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("COPY"));
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275 | 5ee18b9c | Michael Walle | } break;
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276 | 5ee18b9c | Michael Walle | case OP_IF:
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277 | 5ee18b9c | Michael Walle | { |
278 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
279 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
280 | 5ee18b9c | Michael Walle | uint32_t f = s->gp_regs[GPR_FLAGS]; |
281 | 5ee18b9c | Michael Walle | float t = (f != 0) ? a : b; |
282 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
283 | 5ee18b9c | Michael Walle | latency = LATENCY_IF; |
284 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("IF f=%u a=%f b=%f t=%f, r=%08x\n", f, a, b, t, r));
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285 | 5ee18b9c | Michael Walle | } break;
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286 | 5ee18b9c | Michael Walle | case OP_TSIGN:
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287 | 5ee18b9c | Michael Walle | { |
288 | 5ee18b9c | Michael Walle | float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]); |
289 | 5ee18b9c | Michael Walle | float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]); |
290 | 5ee18b9c | Michael Walle | float t = (b < 0) ? -a : a; |
291 | 5ee18b9c | Michael Walle | r = REINTERPRET_CAST(uint32_t, t); |
292 | 5ee18b9c | Michael Walle | latency = LATENCY_TSIGN; |
293 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("TSIGN a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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294 | 5ee18b9c | Michael Walle | } break;
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295 | 5ee18b9c | Michael Walle | case OP_QUAKE:
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296 | 5ee18b9c | Michael Walle | { |
297 | 5ee18b9c | Michael Walle | uint32_t a = s->gp_regs[reg_a]; |
298 | 5ee18b9c | Michael Walle | r = 0x5f3759df - (a >> 1); |
299 | 5ee18b9c | Michael Walle | latency = LATENCY_QUAKE; |
300 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("QUAKE a=%d r=%08x\n", a, r));
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301 | 5ee18b9c | Michael Walle | } break;
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302 | 5ee18b9c | Michael Walle | |
303 | 5ee18b9c | Michael Walle | default:
|
304 | 5ee18b9c | Michael Walle | error_report("milkymist_pfpu: unknown opcode %d\n", op);
|
305 | 5ee18b9c | Michael Walle | break;
|
306 | 5ee18b9c | Michael Walle | } |
307 | 5ee18b9c | Michael Walle | |
308 | 5ee18b9c | Michael Walle | if (!reg_d) {
|
309 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d>\n",
|
310 | 5ee18b9c | Michael Walle | s->regs[R_PC], opcode_to_str[op], reg_a, reg_b, latency, |
311 | 5ee18b9c | Michael Walle | s->regs[R_PC] + latency)); |
312 | 5ee18b9c | Michael Walle | } else {
|
313 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d> -> R%03d\n",
|
314 | 5ee18b9c | Michael Walle | s->regs[R_PC], opcode_to_str[op], reg_a, reg_b, latency, |
315 | 5ee18b9c | Michael Walle | s->regs[R_PC] + latency, reg_d)); |
316 | 5ee18b9c | Michael Walle | } |
317 | 5ee18b9c | Michael Walle | |
318 | 5ee18b9c | Michael Walle | if (op == OP_VECTOUT) {
|
319 | 5ee18b9c | Michael Walle | return 0; |
320 | 5ee18b9c | Michael Walle | } |
321 | 5ee18b9c | Michael Walle | |
322 | 5ee18b9c | Michael Walle | /* store output for this cycle */
|
323 | 5ee18b9c | Michael Walle | if (reg_d) {
|
324 | 5ee18b9c | Michael Walle | uint32_t val = output_queue_remove(s); |
325 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("R%03d <- 0x%08x\n", reg_d, val));
|
326 | 5ee18b9c | Michael Walle | s->gp_regs[reg_d] = val; |
327 | 5ee18b9c | Michael Walle | } |
328 | 5ee18b9c | Michael Walle | |
329 | 5ee18b9c | Michael Walle | output_queue_advance(s); |
330 | 5ee18b9c | Michael Walle | |
331 | 5ee18b9c | Michael Walle | /* store op output */
|
332 | 5ee18b9c | Michael Walle | if (op != OP_NOP) {
|
333 | 5ee18b9c | Michael Walle | output_queue_insert(s, r, latency-1);
|
334 | 5ee18b9c | Michael Walle | } |
335 | 5ee18b9c | Michael Walle | |
336 | 5ee18b9c | Michael Walle | /* advance PC */
|
337 | 5ee18b9c | Michael Walle | s->regs[R_PC]++; |
338 | 5ee18b9c | Michael Walle | |
339 | 5ee18b9c | Michael Walle | return 1; |
340 | 5ee18b9c | Michael Walle | }; |
341 | 5ee18b9c | Michael Walle | |
342 | 5ee18b9c | Michael Walle | static void pfpu_start(MilkymistPFPUState *s) |
343 | 5ee18b9c | Michael Walle | { |
344 | 5ee18b9c | Michael Walle | int x, y;
|
345 | 5ee18b9c | Michael Walle | int i;
|
346 | 5ee18b9c | Michael Walle | |
347 | 5ee18b9c | Michael Walle | for (y = 0; y <= s->regs[R_VMESHLAST]; y++) { |
348 | 5ee18b9c | Michael Walle | for (x = 0; x <= s->regs[R_HMESHLAST]; x++) { |
349 | 5ee18b9c | Michael Walle | D_EXEC(qemu_log("\nprocessing x=%d y=%d\n", x, y));
|
350 | 5ee18b9c | Michael Walle | |
351 | 5ee18b9c | Michael Walle | /* set current position */
|
352 | 5ee18b9c | Michael Walle | s->gp_regs[GPR_X] = x; |
353 | 5ee18b9c | Michael Walle | s->gp_regs[GPR_Y] = y; |
354 | 5ee18b9c | Michael Walle | |
355 | 5ee18b9c | Michael Walle | /* run microcode on this position */
|
356 | 5ee18b9c | Michael Walle | i = 0;
|
357 | 5ee18b9c | Michael Walle | while (pfpu_decode_insn(s)) {
|
358 | 5ee18b9c | Michael Walle | /* decode at most MICROCODE_WORDS instructions */
|
359 | 5ee18b9c | Michael Walle | if (i++ >= MICROCODE_WORDS) {
|
360 | 5ee18b9c | Michael Walle | error_report("milkymist_pfpu: too many instructions "
|
361 | 5ee18b9c | Michael Walle | "executed in microcode. No VECTOUT?\n");
|
362 | 5ee18b9c | Michael Walle | break;
|
363 | 5ee18b9c | Michael Walle | } |
364 | 5ee18b9c | Michael Walle | } |
365 | 5ee18b9c | Michael Walle | |
366 | 5ee18b9c | Michael Walle | /* reset pc for next run */
|
367 | 5ee18b9c | Michael Walle | s->regs[R_PC] = 0;
|
368 | 5ee18b9c | Michael Walle | } |
369 | 5ee18b9c | Michael Walle | } |
370 | 5ee18b9c | Michael Walle | |
371 | 5ee18b9c | Michael Walle | s->regs[R_VERTICES] = x * y; |
372 | 5ee18b9c | Michael Walle | |
373 | 5ee18b9c | Michael Walle | trace_milkymist_pfpu_pulse_irq(); |
374 | 5ee18b9c | Michael Walle | qemu_irq_pulse(s->irq); |
375 | 5ee18b9c | Michael Walle | } |
376 | 5ee18b9c | Michael Walle | |
377 | 5ee18b9c | Michael Walle | static inline int get_microcode_address(MilkymistPFPUState *s, uint32_t addr) |
378 | 5ee18b9c | Michael Walle | { |
379 | 5ee18b9c | Michael Walle | return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN; |
380 | 5ee18b9c | Michael Walle | } |
381 | 5ee18b9c | Michael Walle | |
382 | 5ee18b9c | Michael Walle | static uint32_t pfpu_read(void *opaque, target_phys_addr_t addr) |
383 | 5ee18b9c | Michael Walle | { |
384 | 5ee18b9c | Michael Walle | MilkymistPFPUState *s = opaque; |
385 | 5ee18b9c | Michael Walle | uint32_t r = 0;
|
386 | 5ee18b9c | Michael Walle | |
387 | 5ee18b9c | Michael Walle | addr >>= 2;
|
388 | 5ee18b9c | Michael Walle | switch (addr) {
|
389 | 5ee18b9c | Michael Walle | case R_CTL:
|
390 | 5ee18b9c | Michael Walle | case R_MESHBASE:
|
391 | 5ee18b9c | Michael Walle | case R_HMESHLAST:
|
392 | 5ee18b9c | Michael Walle | case R_VMESHLAST:
|
393 | 5ee18b9c | Michael Walle | case R_CODEPAGE:
|
394 | 5ee18b9c | Michael Walle | case R_VERTICES:
|
395 | 5ee18b9c | Michael Walle | case R_COLLISIONS:
|
396 | 5ee18b9c | Michael Walle | case R_STRAYWRITES:
|
397 | 5ee18b9c | Michael Walle | case R_LASTDMA:
|
398 | 5ee18b9c | Michael Walle | case R_PC:
|
399 | 5ee18b9c | Michael Walle | case R_DREGBASE:
|
400 | 5ee18b9c | Michael Walle | case R_CODEBASE:
|
401 | 5ee18b9c | Michael Walle | r = s->regs[addr]; |
402 | 5ee18b9c | Michael Walle | break;
|
403 | 5ee18b9c | Michael Walle | case GPR_BEGIN ... GPR_END:
|
404 | 5ee18b9c | Michael Walle | r = s->gp_regs[addr - GPR_BEGIN]; |
405 | 5ee18b9c | Michael Walle | break;
|
406 | 5ee18b9c | Michael Walle | case MICROCODE_BEGIN ... MICROCODE_END:
|
407 | 5ee18b9c | Michael Walle | r = s->microcode[get_microcode_address(s, addr)]; |
408 | 5ee18b9c | Michael Walle | break;
|
409 | 5ee18b9c | Michael Walle | |
410 | 5ee18b9c | Michael Walle | default:
|
411 | 5ee18b9c | Michael Walle | error_report("milkymist_pfpu: read access to unknown register 0x"
|
412 | 5ee18b9c | Michael Walle | TARGET_FMT_plx, addr << 2);
|
413 | 5ee18b9c | Michael Walle | break;
|
414 | 5ee18b9c | Michael Walle | } |
415 | 5ee18b9c | Michael Walle | |
416 | 5ee18b9c | Michael Walle | trace_milkymist_pfpu_memory_read(addr << 2, r);
|
417 | 5ee18b9c | Michael Walle | |
418 | 5ee18b9c | Michael Walle | return r;
|
419 | 5ee18b9c | Michael Walle | } |
420 | 5ee18b9c | Michael Walle | |
421 | 5ee18b9c | Michael Walle | static void |
422 | 5ee18b9c | Michael Walle | pfpu_write(void *opaque, target_phys_addr_t addr, uint32_t value)
|
423 | 5ee18b9c | Michael Walle | { |
424 | 5ee18b9c | Michael Walle | MilkymistPFPUState *s = opaque; |
425 | 5ee18b9c | Michael Walle | |
426 | 5ee18b9c | Michael Walle | trace_milkymist_pfpu_memory_write(addr, value); |
427 | 5ee18b9c | Michael Walle | |
428 | 5ee18b9c | Michael Walle | addr >>= 2;
|
429 | 5ee18b9c | Michael Walle | switch (addr) {
|
430 | 5ee18b9c | Michael Walle | case R_CTL:
|
431 | 5ee18b9c | Michael Walle | if (value & CTL_START_BUSY) {
|
432 | 5ee18b9c | Michael Walle | pfpu_start(s); |
433 | 5ee18b9c | Michael Walle | } |
434 | 5ee18b9c | Michael Walle | break;
|
435 | 5ee18b9c | Michael Walle | case R_MESHBASE:
|
436 | 5ee18b9c | Michael Walle | case R_HMESHLAST:
|
437 | 5ee18b9c | Michael Walle | case R_VMESHLAST:
|
438 | 5ee18b9c | Michael Walle | case R_CODEPAGE:
|
439 | 5ee18b9c | Michael Walle | case R_VERTICES:
|
440 | 5ee18b9c | Michael Walle | case R_COLLISIONS:
|
441 | 5ee18b9c | Michael Walle | case R_STRAYWRITES:
|
442 | 5ee18b9c | Michael Walle | case R_LASTDMA:
|
443 | 5ee18b9c | Michael Walle | case R_PC:
|
444 | 5ee18b9c | Michael Walle | case R_DREGBASE:
|
445 | 5ee18b9c | Michael Walle | case R_CODEBASE:
|
446 | 5ee18b9c | Michael Walle | s->regs[addr] = value; |
447 | 5ee18b9c | Michael Walle | break;
|
448 | 5ee18b9c | Michael Walle | case GPR_BEGIN ... GPR_END:
|
449 | 5ee18b9c | Michael Walle | s->gp_regs[addr - GPR_BEGIN] = value; |
450 | 5ee18b9c | Michael Walle | break;
|
451 | 5ee18b9c | Michael Walle | case MICROCODE_BEGIN ... MICROCODE_END:
|
452 | 5ee18b9c | Michael Walle | s->microcode[get_microcode_address(s, addr)] = value; |
453 | 5ee18b9c | Michael Walle | break;
|
454 | 5ee18b9c | Michael Walle | |
455 | 5ee18b9c | Michael Walle | default:
|
456 | 5ee18b9c | Michael Walle | error_report("milkymist_pfpu: write access to unknown register 0x"
|
457 | 5ee18b9c | Michael Walle | TARGET_FMT_plx, addr << 2);
|
458 | 5ee18b9c | Michael Walle | break;
|
459 | 5ee18b9c | Michael Walle | } |
460 | 5ee18b9c | Michael Walle | } |
461 | 5ee18b9c | Michael Walle | |
462 | 5ee18b9c | Michael Walle | static CPUReadMemoryFunc * const pfpu_read_fn[] = { |
463 | 5ee18b9c | Michael Walle | NULL,
|
464 | 5ee18b9c | Michael Walle | NULL,
|
465 | 5ee18b9c | Michael Walle | &pfpu_read, |
466 | 5ee18b9c | Michael Walle | }; |
467 | 5ee18b9c | Michael Walle | |
468 | 5ee18b9c | Michael Walle | static CPUWriteMemoryFunc * const pfpu_write_fn[] = { |
469 | 5ee18b9c | Michael Walle | NULL,
|
470 | 5ee18b9c | Michael Walle | NULL,
|
471 | 5ee18b9c | Michael Walle | &pfpu_write, |
472 | 5ee18b9c | Michael Walle | }; |
473 | 5ee18b9c | Michael Walle | |
474 | 5ee18b9c | Michael Walle | static void milkymist_pfpu_reset(DeviceState *d) |
475 | 5ee18b9c | Michael Walle | { |
476 | 5ee18b9c | Michael Walle | MilkymistPFPUState *s = container_of(d, MilkymistPFPUState, busdev.qdev); |
477 | 5ee18b9c | Michael Walle | int i;
|
478 | 5ee18b9c | Michael Walle | |
479 | 5ee18b9c | Michael Walle | for (i = 0; i < R_MAX; i++) { |
480 | 5ee18b9c | Michael Walle | s->regs[i] = 0;
|
481 | 5ee18b9c | Michael Walle | } |
482 | 5ee18b9c | Michael Walle | for (i = 0; i < 128; i++) { |
483 | 5ee18b9c | Michael Walle | s->gp_regs[i] = 0;
|
484 | 5ee18b9c | Michael Walle | } |
485 | 5ee18b9c | Michael Walle | for (i = 0; i < MICROCODE_WORDS; i++) { |
486 | 5ee18b9c | Michael Walle | s->microcode[i] = 0;
|
487 | 5ee18b9c | Michael Walle | } |
488 | 5ee18b9c | Michael Walle | s->output_queue_pos = 0;
|
489 | 5ee18b9c | Michael Walle | for (i = 0; i < MAX_LATENCY; i++) { |
490 | 5ee18b9c | Michael Walle | s->output_queue[i] = 0;
|
491 | 5ee18b9c | Michael Walle | } |
492 | 5ee18b9c | Michael Walle | } |
493 | 5ee18b9c | Michael Walle | |
494 | 5ee18b9c | Michael Walle | static int milkymist_pfpu_init(SysBusDevice *dev) |
495 | 5ee18b9c | Michael Walle | { |
496 | 5ee18b9c | Michael Walle | MilkymistPFPUState *s = FROM_SYSBUS(typeof(*s), dev); |
497 | 5ee18b9c | Michael Walle | int pfpu_regs;
|
498 | 5ee18b9c | Michael Walle | |
499 | 5ee18b9c | Michael Walle | sysbus_init_irq(dev, &s->irq); |
500 | 5ee18b9c | Michael Walle | |
501 | 5ee18b9c | Michael Walle | pfpu_regs = cpu_register_io_memory(pfpu_read_fn, pfpu_write_fn, s, |
502 | 5ee18b9c | Michael Walle | DEVICE_NATIVE_ENDIAN); |
503 | 5ee18b9c | Michael Walle | sysbus_init_mmio(dev, MICROCODE_END * 4, pfpu_regs);
|
504 | 5ee18b9c | Michael Walle | |
505 | 5ee18b9c | Michael Walle | return 0; |
506 | 5ee18b9c | Michael Walle | } |
507 | 5ee18b9c | Michael Walle | |
508 | 5ee18b9c | Michael Walle | static const VMStateDescription vmstate_milkymist_pfpu = { |
509 | 5ee18b9c | Michael Walle | .name = "milkymist-pfpu",
|
510 | 5ee18b9c | Michael Walle | .version_id = 1,
|
511 | 5ee18b9c | Michael Walle | .minimum_version_id = 1,
|
512 | 5ee18b9c | Michael Walle | .minimum_version_id_old = 1,
|
513 | 5ee18b9c | Michael Walle | .fields = (VMStateField[]) { |
514 | 5ee18b9c | Michael Walle | VMSTATE_UINT32_ARRAY(regs, MilkymistPFPUState, R_MAX), |
515 | 5ee18b9c | Michael Walle | VMSTATE_UINT32_ARRAY(gp_regs, MilkymistPFPUState, 128),
|
516 | 5ee18b9c | Michael Walle | VMSTATE_UINT32_ARRAY(microcode, MilkymistPFPUState, MICROCODE_WORDS), |
517 | 5ee18b9c | Michael Walle | VMSTATE_INT32(output_queue_pos, MilkymistPFPUState), |
518 | 5ee18b9c | Michael Walle | VMSTATE_UINT32_ARRAY(output_queue, MilkymistPFPUState, MAX_LATENCY), |
519 | 5ee18b9c | Michael Walle | VMSTATE_END_OF_LIST() |
520 | 5ee18b9c | Michael Walle | } |
521 | 5ee18b9c | Michael Walle | }; |
522 | 5ee18b9c | Michael Walle | |
523 | 5ee18b9c | Michael Walle | static SysBusDeviceInfo milkymist_pfpu_info = {
|
524 | 5ee18b9c | Michael Walle | .init = milkymist_pfpu_init, |
525 | 5ee18b9c | Michael Walle | .qdev.name = "milkymist-pfpu",
|
526 | 5ee18b9c | Michael Walle | .qdev.size = sizeof(MilkymistPFPUState),
|
527 | 5ee18b9c | Michael Walle | .qdev.vmsd = &vmstate_milkymist_pfpu, |
528 | 5ee18b9c | Michael Walle | .qdev.reset = milkymist_pfpu_reset, |
529 | 5ee18b9c | Michael Walle | }; |
530 | 5ee18b9c | Michael Walle | |
531 | 5ee18b9c | Michael Walle | static void milkymist_pfpu_register(void) |
532 | 5ee18b9c | Michael Walle | { |
533 | 5ee18b9c | Michael Walle | sysbus_register_withprop(&milkymist_pfpu_info); |
534 | 5ee18b9c | Michael Walle | } |
535 | 5ee18b9c | Michael Walle | |
536 | 5ee18b9c | Michael Walle | device_init(milkymist_pfpu_register) |