root / hw / ds1225y.c @ ad674e53
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1 | 30aa5c0d | aurel32 | /*
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2 | 30aa5c0d | aurel32 | * QEMU NVRAM emulation for DS1225Y chip
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3 | 02cb1585 | aurel32 | *
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4 | 02cb1585 | aurel32 | * Copyright (c) 2007-2008 Herv? Poussineau
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5 | 02cb1585 | aurel32 | *
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6 | 30aa5c0d | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 30aa5c0d | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 30aa5c0d | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 30aa5c0d | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 30aa5c0d | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 30aa5c0d | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 30aa5c0d | aurel32 | *
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13 | 30aa5c0d | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 30aa5c0d | aurel32 | * all copies or substantial portions of the Software.
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15 | 30aa5c0d | aurel32 | *
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16 | 30aa5c0d | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 30aa5c0d | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 30aa5c0d | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 30aa5c0d | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 30aa5c0d | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 30aa5c0d | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 30aa5c0d | aurel32 | * THE SOFTWARE.
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23 | 30aa5c0d | aurel32 | */
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24 | 30aa5c0d | aurel32 | |
25 | 30aa5c0d | aurel32 | #include "hw.h" |
26 | 30aa5c0d | aurel32 | #include "mips.h" |
27 | 30aa5c0d | aurel32 | #include "nvram.h" |
28 | 30aa5c0d | aurel32 | |
29 | 02cb1585 | aurel32 | //#define DEBUG_NVRAM
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30 | 30aa5c0d | aurel32 | |
31 | 02cb1585 | aurel32 | typedef struct ds1225y_t |
32 | 30aa5c0d | aurel32 | { |
33 | 02cb1585 | aurel32 | uint32_t chip_size; |
34 | 30aa5c0d | aurel32 | QEMUFile *file; |
35 | 02cb1585 | aurel32 | uint8_t *contents; |
36 | 02cb1585 | aurel32 | uint8_t protection; |
37 | c227f099 | Anthony Liguori | } ds1225y_t; |
38 | 30aa5c0d | aurel32 | |
39 | 30aa5c0d | aurel32 | |
40 | c227f099 | Anthony Liguori | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
41 | 30aa5c0d | aurel32 | { |
42 | c227f099 | Anthony Liguori | ds1225y_t *s = opaque; |
43 | 02cb1585 | aurel32 | uint32_t val; |
44 | 02cb1585 | aurel32 | |
45 | 8da3ff18 | pbrook | val = s->contents[addr]; |
46 | 02cb1585 | aurel32 | |
47 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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48 | 02cb1585 | aurel32 | printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr); |
49 | 02cb1585 | aurel32 | #endif
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50 | 02cb1585 | aurel32 | return val;
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51 | 02cb1585 | aurel32 | } |
52 | 30aa5c0d | aurel32 | |
53 | c227f099 | Anthony Liguori | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
54 | 02cb1585 | aurel32 | { |
55 | 02cb1585 | aurel32 | uint32_t v; |
56 | 02cb1585 | aurel32 | v = nvram_readb(opaque, addr); |
57 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 1) << 8; |
58 | 02cb1585 | aurel32 | return v;
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59 | 02cb1585 | aurel32 | } |
60 | 30aa5c0d | aurel32 | |
61 | c227f099 | Anthony Liguori | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
62 | 02cb1585 | aurel32 | { |
63 | 02cb1585 | aurel32 | uint32_t v; |
64 | 02cb1585 | aurel32 | v = nvram_readb(opaque, addr); |
65 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 1) << 8; |
66 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 2) << 16; |
67 | 02cb1585 | aurel32 | v |= nvram_readb(opaque, addr + 3) << 24; |
68 | 02cb1585 | aurel32 | return v;
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69 | 30aa5c0d | aurel32 | } |
70 | 30aa5c0d | aurel32 | |
71 | c227f099 | Anthony Liguori | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
72 | 30aa5c0d | aurel32 | { |
73 | c227f099 | Anthony Liguori | ds1225y_t *s = opaque; |
74 | 30aa5c0d | aurel32 | |
75 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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76 | 02cb1585 | aurel32 | printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr); |
77 | 02cb1585 | aurel32 | #endif
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78 | 02cb1585 | aurel32 | |
79 | 8da3ff18 | pbrook | s->contents[addr] = val & 0xff;
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80 | 02cb1585 | aurel32 | if (s->file) {
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81 | 8da3ff18 | pbrook | qemu_fseek(s->file, addr, SEEK_SET); |
82 | 02cb1585 | aurel32 | qemu_put_byte(s->file, (int)val);
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83 | 02cb1585 | aurel32 | qemu_fflush(s->file); |
84 | 30aa5c0d | aurel32 | } |
85 | 30aa5c0d | aurel32 | } |
86 | 30aa5c0d | aurel32 | |
87 | c227f099 | Anthony Liguori | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
88 | 02cb1585 | aurel32 | { |
89 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr, val & 0xff);
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90 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
91 | 02cb1585 | aurel32 | } |
92 | 02cb1585 | aurel32 | |
93 | c227f099 | Anthony Liguori | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
94 | 02cb1585 | aurel32 | { |
95 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr, val & 0xff);
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96 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
97 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
98 | 02cb1585 | aurel32 | nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
99 | 02cb1585 | aurel32 | } |
100 | 02cb1585 | aurel32 | |
101 | c227f099 | Anthony Liguori | static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
102 | 02cb1585 | aurel32 | { |
103 | c227f099 | Anthony Liguori | ds1225y_t *s = opaque; |
104 | 02cb1585 | aurel32 | |
105 | 02cb1585 | aurel32 | if (s->protection != 7) { |
106 | 02cb1585 | aurel32 | #ifdef DEBUG_NVRAM
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107 | 02cb1585 | aurel32 | printf("nvram: prevent write of 0x%x at " TARGET_FMT_lx "\n", val, addr); |
108 | 02cb1585 | aurel32 | #endif
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109 | 02cb1585 | aurel32 | return;
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110 | 02cb1585 | aurel32 | } |
111 | 02cb1585 | aurel32 | |
112 | 8da3ff18 | pbrook | nvram_writeb(opaque, addr, val); |
113 | 02cb1585 | aurel32 | } |
114 | 02cb1585 | aurel32 | |
115 | c227f099 | Anthony Liguori | static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
116 | 02cb1585 | aurel32 | { |
117 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr, val & 0xff);
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118 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); |
119 | 02cb1585 | aurel32 | } |
120 | 02cb1585 | aurel32 | |
121 | c227f099 | Anthony Liguori | static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val) |
122 | 02cb1585 | aurel32 | { |
123 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr, val & 0xff);
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124 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff); |
125 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 2, (val >> 16) & 0xff); |
126 | 02cb1585 | aurel32 | nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff); |
127 | 02cb1585 | aurel32 | } |
128 | 02cb1585 | aurel32 | |
129 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const nvram_read[] = { |
130 | 30aa5c0d | aurel32 | &nvram_readb, |
131 | 02cb1585 | aurel32 | &nvram_readw, |
132 | 02cb1585 | aurel32 | &nvram_readl, |
133 | 30aa5c0d | aurel32 | }; |
134 | 30aa5c0d | aurel32 | |
135 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const nvram_write[] = { |
136 | 30aa5c0d | aurel32 | &nvram_writeb, |
137 | 02cb1585 | aurel32 | &nvram_writew, |
138 | 02cb1585 | aurel32 | &nvram_writel, |
139 | 30aa5c0d | aurel32 | }; |
140 | 30aa5c0d | aurel32 | |
141 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const nvram_write_protected[] = { |
142 | 02cb1585 | aurel32 | &nvram_writeb_protected, |
143 | 02cb1585 | aurel32 | &nvram_writew_protected, |
144 | 02cb1585 | aurel32 | &nvram_writel_protected, |
145 | 30aa5c0d | aurel32 | }; |
146 | 30aa5c0d | aurel32 | |
147 | 30aa5c0d | aurel32 | /* Initialisation routine */
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148 | c227f099 | Anthony Liguori | void *ds1225y_init(target_phys_addr_t mem_base, const char *filename) |
149 | 30aa5c0d | aurel32 | { |
150 | c227f099 | Anthony Liguori | ds1225y_t *s; |
151 | 02cb1585 | aurel32 | int mem_indexRW, mem_indexRP;
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152 | 02cb1585 | aurel32 | QEMUFile *file; |
153 | 30aa5c0d | aurel32 | |
154 | c227f099 | Anthony Liguori | s = qemu_mallocz(sizeof(ds1225y_t));
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155 | 02cb1585 | aurel32 | s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */ |
156 | 02cb1585 | aurel32 | s->contents = qemu_mallocz(s->chip_size); |
157 | 02cb1585 | aurel32 | s->protection = 7;
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158 | 02cb1585 | aurel32 | |
159 | 02cb1585 | aurel32 | /* Read current file */
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160 | 02cb1585 | aurel32 | file = qemu_fopen(filename, "rb");
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161 | 02cb1585 | aurel32 | if (file) {
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162 | 02cb1585 | aurel32 | /* Read nvram contents */
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163 | 02cb1585 | aurel32 | qemu_get_buffer(file, s->contents, s->chip_size); |
164 | 02cb1585 | aurel32 | qemu_fclose(file); |
165 | 02cb1585 | aurel32 | } |
166 | 02cb1585 | aurel32 | s->file = qemu_fopen(filename, "wb");
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167 | 02cb1585 | aurel32 | if (s->file) {
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168 | 02cb1585 | aurel32 | /* Write back contents, as 'wb' mode cleaned the file */
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169 | 02cb1585 | aurel32 | qemu_put_buffer(s->file, s->contents, s->chip_size); |
170 | 02cb1585 | aurel32 | qemu_fflush(s->file); |
171 | 02cb1585 | aurel32 | } |
172 | 30aa5c0d | aurel32 | |
173 | 30aa5c0d | aurel32 | /* Read/write memory */
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174 | 1eed09cb | Avi Kivity | mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s); |
175 | 02cb1585 | aurel32 | cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW); |
176 | 02cb1585 | aurel32 | /* Read/write protected memory */
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177 | 1eed09cb | Avi Kivity | mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s); |
178 | 02cb1585 | aurel32 | cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP); |
179 | 30aa5c0d | aurel32 | return s;
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180 | 30aa5c0d | aurel32 | } |