Revision ad674e53
b/hw/mac_dbdma.c | ||
---|---|---|
184 | 184 |
static void dbdma_cmdptr_load(DBDMA_channel *ch) |
185 | 185 |
{ |
186 | 186 |
DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n", |
187 |
be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
|
|
188 |
cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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|
187 |
ch->regs[DBDMA_CMDPTR_LO]);
|
|
188 |
cpu_physical_memory_read(ch->regs[DBDMA_CMDPTR_LO],
|
|
189 | 189 |
(uint8_t*)&ch->current, sizeof(dbdma_cmd)); |
190 | 190 |
} |
191 | 191 |
|
192 | 192 |
static void dbdma_cmdptr_save(DBDMA_channel *ch) |
193 | 193 |
{ |
194 | 194 |
DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n", |
195 |
be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
|
|
195 |
ch->regs[DBDMA_CMDPTR_LO]);
|
|
196 | 196 |
DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n", |
197 | 197 |
le16_to_cpu(ch->current.xfer_status), |
198 | 198 |
le16_to_cpu(ch->current.res_count)); |
199 |
cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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|
199 |
cpu_physical_memory_write(ch->regs[DBDMA_CMDPTR_LO],
|
|
200 | 200 |
(uint8_t*)&ch->current, sizeof(dbdma_cmd)); |
201 | 201 |
} |
202 | 202 |
|
... | ... | |
204 | 204 |
{ |
205 | 205 |
DBDMA_DPRINTF("kill_channel\n"); |
206 | 206 |
|
207 |
ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
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|
208 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
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|
207 |
ch->regs[DBDMA_STATUS] |= DEAD;
|
|
208 |
ch->regs[DBDMA_STATUS] &= ~ACTIVE;
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|
209 | 209 |
|
210 | 210 |
qemu_irq_raise(ch->irq); |
211 | 211 |
} |
... | ... | |
230 | 230 |
return; |
231 | 231 |
} |
232 | 232 |
|
233 |
status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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|
233 |
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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|
234 | 234 |
|
235 |
sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
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|
236 |
sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
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|
235 |
sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f;
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|
236 |
sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
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|
237 | 237 |
|
238 | 238 |
cond = (status & sel_mask) == (sel_value & sel_mask); |
239 | 239 |
|
... | ... | |
268 | 268 |
return 1; |
269 | 269 |
} |
270 | 270 |
|
271 |
status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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|
271 |
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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272 | 272 |
|
273 |
sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
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|
274 |
sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
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|
273 |
sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f;
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|
274 |
sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
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|
275 | 275 |
|
276 | 276 |
cond = (status & sel_mask) == (sel_value & sel_mask); |
277 | 277 |
|
... | ... | |
292 | 292 |
{ |
293 | 293 |
uint32_t cp; |
294 | 294 |
|
295 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
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|
295 |
ch->regs[DBDMA_STATUS] &= ~BT;
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296 | 296 |
|
297 |
cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
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|
298 |
ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
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|
297 |
cp = ch->regs[DBDMA_CMDPTR_LO];
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|
298 |
ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
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|
299 | 299 |
dbdma_cmdptr_load(ch); |
300 | 300 |
} |
301 | 301 |
|
... | ... | |
304 | 304 |
dbdma_cmd *current = &ch->current; |
305 | 305 |
|
306 | 306 |
ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep; |
307 |
ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
|
|
307 |
ch->regs[DBDMA_STATUS] |= BT;
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|
308 | 308 |
dbdma_cmdptr_load(ch); |
309 | 309 |
} |
310 | 310 |
|
... | ... | |
331 | 331 |
return; |
332 | 332 |
} |
333 | 333 |
|
334 |
status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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|
334 |
status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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335 | 335 |
|
336 |
sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
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|
337 |
sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
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|
336 |
sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f;
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|
337 |
sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
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338 | 338 |
|
339 | 339 |
cond = (status & sel_mask) == (sel_value & sel_mask); |
340 | 340 |
|
... | ... | |
365 | 365 |
if (conditional_wait(ch)) |
366 | 366 |
goto wait; |
367 | 367 |
|
368 |
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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|
369 |
current->res_count = cpu_to_le16(be32_to_cpu(io->len));
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|
368 |
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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|
369 |
current->res_count = cpu_to_le16(io->len);
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|
370 | 370 |
dbdma_cmdptr_save(ch); |
371 | 371 |
if (io->is_last) |
372 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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|
372 |
ch->regs[DBDMA_STATUS] &= ~FLUSH;
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373 | 373 |
|
374 | 374 |
conditional_interrupt(ch); |
375 | 375 |
conditional_branch(ch); |
376 | 376 |
|
377 | 377 |
wait: |
378 | 378 |
ch->processing = 0; |
379 |
if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
|
|
380 |
(ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE)))
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|
379 |
if ((ch->regs[DBDMA_STATUS] & RUN) &&
|
|
380 |
(ch->regs[DBDMA_STATUS] & ACTIVE))
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|
381 | 381 |
channel_run(ch); |
382 | 382 |
} |
383 | 383 |
|
... | ... | |
456 | 456 |
if (conditional_wait(ch)) |
457 | 457 |
goto wait; |
458 | 458 |
|
459 |
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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|
459 |
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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460 | 460 |
dbdma_cmdptr_save(ch); |
461 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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|
461 |
ch->regs[DBDMA_STATUS] &= ~FLUSH;
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|
462 | 462 |
|
463 | 463 |
conditional_interrupt(ch); |
464 | 464 |
next(ch); |
... | ... | |
494 | 494 |
if (conditional_wait(ch)) |
495 | 495 |
goto wait; |
496 | 496 |
|
497 |
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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|
497 |
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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|
498 | 498 |
dbdma_cmdptr_save(ch); |
499 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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|
499 |
ch->regs[DBDMA_STATUS] &= ~FLUSH;
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|
500 | 500 |
|
501 | 501 |
conditional_interrupt(ch); |
502 | 502 |
next(ch); |
... | ... | |
512 | 512 |
if (conditional_wait(ch)) |
513 | 513 |
goto wait; |
514 | 514 |
|
515 |
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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|
515 |
current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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|
516 | 516 |
dbdma_cmdptr_save(ch); |
517 | 517 |
|
518 | 518 |
conditional_interrupt(ch); |
... | ... | |
524 | 524 |
|
525 | 525 |
static void stop(DBDMA_channel *ch) |
526 | 526 |
{ |
527 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH));
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|
527 |
ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH);
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|
528 | 528 |
|
529 | 529 |
/* the stop command does not increment command pointer */ |
530 | 530 |
} |
... | ... | |
541 | 541 |
|
542 | 542 |
/* clear WAKE flag at command fetch */ |
543 | 543 |
|
544 |
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
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|
544 |
ch->regs[DBDMA_STATUS] &= ~WAKE;
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|
545 | 545 |
|
546 | 546 |
cmd = le16_to_cpu(current->command) & COMMAND_MASK; |
547 | 547 |
|
... | ... | |
618 | 618 |
int channel; |
619 | 619 |
|
620 | 620 |
for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) { |
621 |
uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
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|
621 |
uint32_t status = ch->regs[DBDMA_STATUS];
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|
622 | 622 |
if (!ch->processing && (status & RUN) && (status & ACTIVE)) |
623 | 623 |
channel_run(ch); |
624 | 624 |
} |
... | ... | |
660 | 660 |
uint16_t mask, value; |
661 | 661 |
uint32_t status; |
662 | 662 |
|
663 |
mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
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|
664 |
value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
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|
663 |
mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff;
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|
664 |
value = ch->regs[DBDMA_CONTROL] & 0xffff;
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|
665 | 665 |
|
666 | 666 |
value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); |
667 | 667 |
|
668 |
status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
|
|
668 |
status = ch->regs[DBDMA_STATUS];
|
|
669 | 669 |
|
670 | 670 |
status = (value & mask) | (status & ~mask); |
671 | 671 |
|
... | ... | |
677 | 677 |
} |
678 | 678 |
if (status & PAUSE) |
679 | 679 |
status &= ~ACTIVE; |
680 |
if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
|
|
680 |
if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
|
|
681 | 681 |
/* RUN is cleared */ |
682 | 682 |
status &= ~(ACTIVE|DEAD); |
683 | 683 |
} |
684 | 684 |
|
685 | 685 |
DBDMA_DPRINTF(" status 0x%08x\n", status); |
686 | 686 |
|
687 |
ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
|
|
687 |
ch->regs[DBDMA_STATUS] = status;
|
|
688 | 688 |
|
689 | 689 |
if (status & ACTIVE) |
690 | 690 |
qemu_bh_schedule(dbdma_bh); |
... | ... | |
703 | 703 |
DBDMA_DPRINTF("channel 0x%x reg 0x%x\n", |
704 | 704 |
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); |
705 | 705 |
|
706 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
707 |
value = bswap32(value); |
|
708 |
#endif |
|
709 |
|
|
706 | 710 |
/* cmdptr cannot be modified if channel is RUN or ACTIVE */ |
707 | 711 |
|
708 | 712 |
if (reg == DBDMA_CMDPTR_LO && |
709 |
(ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
|
|
713 |
(ch->regs[DBDMA_STATUS] & (RUN | ACTIVE))) |
|
710 | 714 |
return; |
711 | 715 |
|
712 | 716 |
ch->regs[reg] = value; |
... | ... | |
717 | 721 |
break; |
718 | 722 |
case DBDMA_CMDPTR_LO: |
719 | 723 |
/* 16-byte aligned */ |
720 |
ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
|
|
724 |
ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
|
|
721 | 725 |
dbdma_cmdptr_load(ch); |
722 | 726 |
break; |
723 | 727 |
case DBDMA_STATUS: |
... | ... | |
782 | 786 |
break; |
783 | 787 |
} |
784 | 788 |
|
789 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
790 |
value = bswap32(value); |
|
791 |
#endif |
|
785 | 792 |
return value; |
786 | 793 |
} |
787 | 794 |
|
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