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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU SPARC iommu emulation
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3 | 420557e8 | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | /* debug iommu */
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27 | 420557e8 | bellard | //#define DEBUG_IOMMU
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28 | 420557e8 | bellard | |
29 | 66321a11 | bellard | #ifdef DEBUG_IOMMU
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30 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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31 | 66321a11 | bellard | do { printf("IOMMU: " fmt , ##args); } while (0) |
32 | 66321a11 | bellard | #else
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33 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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34 | 66321a11 | bellard | #endif
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35 | 420557e8 | bellard | |
36 | 4e3b1ea1 | bellard | #define IOMMU_NREGS (3*4096/4) |
37 | 4e3b1ea1 | bellard | #define IOMMU_CTRL (0x0000 >> 2) |
38 | 420557e8 | bellard | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
39 | 420557e8 | bellard | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
40 | 4e3b1ea1 | bellard | #define IOMMU_VERSION 0x04000000 |
41 | 420557e8 | bellard | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
42 | 420557e8 | bellard | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
43 | 420557e8 | bellard | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
44 | 420557e8 | bellard | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
45 | 420557e8 | bellard | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
46 | 420557e8 | bellard | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
47 | 420557e8 | bellard | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
48 | 420557e8 | bellard | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
49 | 420557e8 | bellard | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
50 | 420557e8 | bellard | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
51 | 4e3b1ea1 | bellard | #define IOMMU_CTRL_MASK 0x0000001d |
52 | 4e3b1ea1 | bellard | |
53 | 4e3b1ea1 | bellard | #define IOMMU_BASE (0x0004 >> 2) |
54 | 4e3b1ea1 | bellard | #define IOMMU_BASE_MASK 0x07fffc00 |
55 | 4e3b1ea1 | bellard | |
56 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH (0x0014 >> 2) |
57 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH_MASK 0xffffffff |
58 | 4e3b1ea1 | bellard | |
59 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH (0x0018 >> 2) |
60 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH_MASK 0xffffffff |
61 | 4e3b1ea1 | bellard | |
62 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
63 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
64 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
65 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
66 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ |
67 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
68 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
69 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
70 | 4e3b1ea1 | bellard | produced by this device as pure
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71 | 4e3b1ea1 | bellard | physical. */
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72 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_MASK 0x00010003 |
73 | 4e3b1ea1 | bellard | |
74 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
75 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN_MASK 0x001f0000 |
76 | 4e3b1ea1 | bellard | #define IOMMU_MID 0x00000008 |
77 | 420557e8 | bellard | |
78 | 420557e8 | bellard | /* The format of an iopte in the page tables */
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79 | 420557e8 | bellard | #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ |
80 | 420557e8 | bellard | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */ |
81 | 420557e8 | bellard | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
82 | 420557e8 | bellard | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
83 | 420557e8 | bellard | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
84 | 420557e8 | bellard | |
85 | 420557e8 | bellard | #define PAGE_SHIFT 12 |
86 | 420557e8 | bellard | #define PAGE_SIZE (1 << PAGE_SHIFT) |
87 | 420557e8 | bellard | #define PAGE_MASK (PAGE_SIZE - 1) |
88 | 420557e8 | bellard | |
89 | 420557e8 | bellard | typedef struct IOMMUState { |
90 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
91 | 66321a11 | bellard | uint32_t regs[IOMMU_NREGS]; |
92 | 5dcb6b91 | blueswir1 | target_phys_addr_t iostart; |
93 | 420557e8 | bellard | } IOMMUState; |
94 | 420557e8 | bellard | |
95 | 420557e8 | bellard | static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) |
96 | 420557e8 | bellard | { |
97 | 420557e8 | bellard | IOMMUState *s = opaque; |
98 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
99 | 420557e8 | bellard | |
100 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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101 | 420557e8 | bellard | switch (saddr) {
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102 | 420557e8 | bellard | default:
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103 | 66321a11 | bellard | DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
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104 | 420557e8 | bellard | return s->regs[saddr];
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105 | 420557e8 | bellard | break;
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106 | 420557e8 | bellard | } |
107 | 420557e8 | bellard | return 0; |
108 | 420557e8 | bellard | } |
109 | 420557e8 | bellard | |
110 | 420557e8 | bellard | static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
111 | 420557e8 | bellard | { |
112 | 420557e8 | bellard | IOMMUState *s = opaque; |
113 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
114 | 420557e8 | bellard | |
115 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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116 | 66321a11 | bellard | DPRINTF("write reg[%d] = %x\n", saddr, val);
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117 | 420557e8 | bellard | switch (saddr) {
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118 | 4e3b1ea1 | bellard | case IOMMU_CTRL:
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119 | 8d5f07fa | bellard | switch (val & IOMMU_CTRL_RNGE) {
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120 | 8d5f07fa | bellard | case IOMMU_RNGE_16MB:
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121 | 5dcb6b91 | blueswir1 | s->iostart = 0xffffffffff000000ULL;
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122 | 8d5f07fa | bellard | break;
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123 | 8d5f07fa | bellard | case IOMMU_RNGE_32MB:
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124 | 5dcb6b91 | blueswir1 | s->iostart = 0xfffffffffe000000ULL;
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125 | 8d5f07fa | bellard | break;
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126 | 8d5f07fa | bellard | case IOMMU_RNGE_64MB:
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127 | 5dcb6b91 | blueswir1 | s->iostart = 0xfffffffffc000000ULL;
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128 | 8d5f07fa | bellard | break;
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129 | 8d5f07fa | bellard | case IOMMU_RNGE_128MB:
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130 | 5dcb6b91 | blueswir1 | s->iostart = 0xfffffffff8000000ULL;
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131 | 8d5f07fa | bellard | break;
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132 | 8d5f07fa | bellard | case IOMMU_RNGE_256MB:
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133 | 5dcb6b91 | blueswir1 | s->iostart = 0xfffffffff0000000ULL;
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134 | 8d5f07fa | bellard | break;
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135 | 8d5f07fa | bellard | case IOMMU_RNGE_512MB:
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136 | 5dcb6b91 | blueswir1 | s->iostart = 0xffffffffe0000000ULL;
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137 | 8d5f07fa | bellard | break;
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138 | 8d5f07fa | bellard | case IOMMU_RNGE_1GB:
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139 | 5dcb6b91 | blueswir1 | s->iostart = 0xffffffffc0000000ULL;
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140 | 8d5f07fa | bellard | break;
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141 | 8d5f07fa | bellard | default:
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142 | 8d5f07fa | bellard | case IOMMU_RNGE_2GB:
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143 | 5dcb6b91 | blueswir1 | s->iostart = 0xffffffff80000000ULL;
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144 | 8d5f07fa | bellard | break;
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145 | 8d5f07fa | bellard | } |
146 | 5dcb6b91 | blueswir1 | DPRINTF("iostart = %llx\n", s->iostart);
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147 | 4e3b1ea1 | bellard | s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); |
148 | 4e3b1ea1 | bellard | break;
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149 | 4e3b1ea1 | bellard | case IOMMU_BASE:
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150 | 4e3b1ea1 | bellard | s->regs[saddr] = val & IOMMU_BASE_MASK; |
151 | 4e3b1ea1 | bellard | break;
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152 | 4e3b1ea1 | bellard | case IOMMU_TLBFLUSH:
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153 | 4e3b1ea1 | bellard | DPRINTF("tlb flush %x\n", val);
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154 | 4e3b1ea1 | bellard | s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
155 | 4e3b1ea1 | bellard | break;
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156 | 4e3b1ea1 | bellard | case IOMMU_PGFLUSH:
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157 | 4e3b1ea1 | bellard | DPRINTF("page flush %x\n", val);
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158 | 4e3b1ea1 | bellard | s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
159 | 4e3b1ea1 | bellard | break;
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160 | 4e3b1ea1 | bellard | case IOMMU_SBCFG0:
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161 | 4e3b1ea1 | bellard | case IOMMU_SBCFG1:
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162 | 4e3b1ea1 | bellard | case IOMMU_SBCFG2:
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163 | 4e3b1ea1 | bellard | case IOMMU_SBCFG3:
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164 | 4e3b1ea1 | bellard | s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
165 | 4e3b1ea1 | bellard | break;
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166 | 4e3b1ea1 | bellard | case IOMMU_ARBEN:
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167 | 4e3b1ea1 | bellard | // XXX implement SBus probing: fault when reading unmapped
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168 | 4e3b1ea1 | bellard | // addresses, fault cause and address stored to MMU/IOMMU
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169 | 4e3b1ea1 | bellard | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
170 | 4e3b1ea1 | bellard | break;
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171 | 420557e8 | bellard | default:
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172 | 420557e8 | bellard | s->regs[saddr] = val; |
173 | 420557e8 | bellard | break;
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174 | 420557e8 | bellard | } |
175 | 420557e8 | bellard | } |
176 | 420557e8 | bellard | |
177 | 420557e8 | bellard | static CPUReadMemoryFunc *iommu_mem_read[3] = { |
178 | 420557e8 | bellard | iommu_mem_readw, |
179 | 420557e8 | bellard | iommu_mem_readw, |
180 | 420557e8 | bellard | iommu_mem_readw, |
181 | 420557e8 | bellard | }; |
182 | 420557e8 | bellard | |
183 | 420557e8 | bellard | static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
184 | 420557e8 | bellard | iommu_mem_writew, |
185 | 420557e8 | bellard | iommu_mem_writew, |
186 | 420557e8 | bellard | iommu_mem_writew, |
187 | 420557e8 | bellard | }; |
188 | 420557e8 | bellard | |
189 | 5dcb6b91 | blueswir1 | static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
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190 | 420557e8 | bellard | { |
191 | a917d384 | pbrook | uint32_t iopte; |
192 | 420557e8 | bellard | |
193 | 66321a11 | bellard | iopte = s->regs[1] << 4; |
194 | 66321a11 | bellard | addr &= ~s->iostart; |
195 | 66321a11 | bellard | iopte += (addr >> (PAGE_SHIFT - 2)) & ~3; |
196 | a917d384 | pbrook | return ldl_phys(iopte);
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197 | a917d384 | pbrook | } |
198 | a917d384 | pbrook | |
199 | 5dcb6b91 | blueswir1 | static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
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200 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr, |
201 | 5dcb6b91 | blueswir1 | uint32_t pte) |
202 | a917d384 | pbrook | { |
203 | a917d384 | pbrook | uint32_t tmppte; |
204 | 5dcb6b91 | blueswir1 | target_phys_addr_t pa; |
205 | 5dcb6b91 | blueswir1 | |
206 | 5dcb6b91 | blueswir1 | tmppte = pte; |
207 | 5dcb6b91 | blueswir1 | pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
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208 | 5dcb6b91 | blueswir1 | DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
209 | 5dcb6b91 | blueswir1 | " (iopte = %x)\n", addr, pa, tmppte);
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210 | a917d384 | pbrook | |
211 | 66321a11 | bellard | return pa;
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212 | 420557e8 | bellard | } |
213 | 420557e8 | bellard | |
214 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
215 | 67e999be | bellard | uint8_t *buf, int len, int is_write) |
216 | a917d384 | pbrook | { |
217 | 5dcb6b91 | blueswir1 | int l;
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218 | 5dcb6b91 | blueswir1 | uint32_t flags; |
219 | 5dcb6b91 | blueswir1 | target_phys_addr_t page, phys_addr; |
220 | a917d384 | pbrook | |
221 | a917d384 | pbrook | while (len > 0) { |
222 | a917d384 | pbrook | page = addr & TARGET_PAGE_MASK; |
223 | a917d384 | pbrook | l = (page + TARGET_PAGE_SIZE) - addr; |
224 | a917d384 | pbrook | if (l > len)
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225 | a917d384 | pbrook | l = len; |
226 | a917d384 | pbrook | flags = iommu_page_get_flags(opaque, page); |
227 | a917d384 | pbrook | if (!(flags & IOPTE_VALID))
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228 | a917d384 | pbrook | return;
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229 | a917d384 | pbrook | phys_addr = iommu_translate_pa(opaque, addr, flags); |
230 | a917d384 | pbrook | if (is_write) {
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231 | a917d384 | pbrook | if (!(flags & IOPTE_WRITE))
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232 | a917d384 | pbrook | return;
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233 | a917d384 | pbrook | cpu_physical_memory_write(phys_addr, buf, len); |
234 | a917d384 | pbrook | } else {
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235 | a917d384 | pbrook | cpu_physical_memory_read(phys_addr, buf, len); |
236 | a917d384 | pbrook | } |
237 | a917d384 | pbrook | len -= l; |
238 | a917d384 | pbrook | buf += l; |
239 | a917d384 | pbrook | addr += l; |
240 | a917d384 | pbrook | } |
241 | a917d384 | pbrook | } |
242 | a917d384 | pbrook | |
243 | e80cfcfc | bellard | static void iommu_save(QEMUFile *f, void *opaque) |
244 | e80cfcfc | bellard | { |
245 | e80cfcfc | bellard | IOMMUState *s = opaque; |
246 | e80cfcfc | bellard | int i;
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247 | e80cfcfc | bellard | |
248 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
249 | e80cfcfc | bellard | qemu_put_be32s(f, &s->regs[i]); |
250 | 5dcb6b91 | blueswir1 | qemu_put_be64s(f, &s->iostart); |
251 | e80cfcfc | bellard | } |
252 | e80cfcfc | bellard | |
253 | e80cfcfc | bellard | static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
254 | e80cfcfc | bellard | { |
255 | e80cfcfc | bellard | IOMMUState *s = opaque; |
256 | e80cfcfc | bellard | int i;
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257 | e80cfcfc | bellard | |
258 | 5dcb6b91 | blueswir1 | if (version_id != 2) |
259 | e80cfcfc | bellard | return -EINVAL;
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260 | e80cfcfc | bellard | |
261 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
262 | e80cfcfc | bellard | qemu_put_be32s(f, &s->regs[i]); |
263 | 5dcb6b91 | blueswir1 | qemu_get_be64s(f, &s->iostart); |
264 | e80cfcfc | bellard | |
265 | e80cfcfc | bellard | return 0; |
266 | e80cfcfc | bellard | } |
267 | e80cfcfc | bellard | |
268 | e80cfcfc | bellard | static void iommu_reset(void *opaque) |
269 | e80cfcfc | bellard | { |
270 | e80cfcfc | bellard | IOMMUState *s = opaque; |
271 | e80cfcfc | bellard | |
272 | 66321a11 | bellard | memset(s->regs, 0, IOMMU_NREGS * 4); |
273 | e80cfcfc | bellard | s->iostart = 0;
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274 | 4e3b1ea1 | bellard | s->regs[0] = IOMMU_VERSION;
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275 | e80cfcfc | bellard | } |
276 | e80cfcfc | bellard | |
277 | 5dcb6b91 | blueswir1 | void *iommu_init(target_phys_addr_t addr)
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278 | 420557e8 | bellard | { |
279 | 420557e8 | bellard | IOMMUState *s; |
280 | 8d5f07fa | bellard | int iommu_io_memory;
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281 | 420557e8 | bellard | |
282 | 420557e8 | bellard | s = qemu_mallocz(sizeof(IOMMUState));
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283 | 420557e8 | bellard | if (!s)
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284 | e80cfcfc | bellard | return NULL; |
285 | 420557e8 | bellard | |
286 | 8d5f07fa | bellard | s->addr = addr; |
287 | 8d5f07fa | bellard | |
288 | 420557e8 | bellard | iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
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289 | 66321a11 | bellard | cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
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290 | 420557e8 | bellard | |
291 | 5dcb6b91 | blueswir1 | register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); |
292 | e80cfcfc | bellard | qemu_register_reset(iommu_reset, s); |
293 | e80cfcfc | bellard | return s;
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294 | 420557e8 | bellard | } |