Revision add78955 target-ppc/helper.c
| b/target-ppc/helper.c | ||
|---|---|---|
| 706 | 706 |
int h, int rw, int type) |
| 707 | 707 |
{
|
| 708 | 708 |
#if defined(TARGET_PPC64) |
| 709 |
if (env->mmu_model == POWERPC_MMU_64B)
|
|
| 709 |
if (env->mmu_model & POWERPC_MMU_64)
|
|
| 710 | 710 |
return find_pte64(ctx, h, rw, type); |
| 711 | 711 |
#endif |
| 712 | 712 |
|
| ... | ... | |
| 916 | 916 |
|
| 917 | 917 |
pr = msr_pr; |
| 918 | 918 |
#if defined(TARGET_PPC64) |
| 919 |
if (env->mmu_model == POWERPC_MMU_64B) {
|
|
| 919 |
if (env->mmu_model & POWERPC_MMU_64) {
|
|
| 920 | 920 |
#if defined (DEBUG_MMU) |
| 921 | 921 |
if (loglevel != 0) {
|
| 922 | 922 |
fprintf(logfile, "Check SLBs\n"); |
| ... | ... | |
| 973 | 973 |
sdr = env->sdr1; |
| 974 | 974 |
pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
| 975 | 975 |
#if defined(TARGET_PPC64) |
| 976 |
if (env->mmu_model == POWERPC_MMU_64B) {
|
|
| 976 |
if (env->mmu_model & POWERPC_MMU_64) {
|
|
| 977 | 977 |
htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
| 978 | 978 |
/* XXX: this is false for 1 TB segments */ |
| 979 | 979 |
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
| ... | ... | |
| 1002 | 1002 |
#endif |
| 1003 | 1003 |
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); |
| 1004 | 1004 |
#if defined(TARGET_PPC64) |
| 1005 |
if (env->mmu_model == POWERPC_MMU_64B) {
|
|
| 1005 |
if (env->mmu_model & POWERPC_MMU_64) {
|
|
| 1006 | 1006 |
/* Only 5 bits of the page index are used in the AVPN */ |
| 1007 | 1007 |
ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
| 1008 | 1008 |
} else |
| ... | ... | |
| 1362 | 1362 |
ctx->prot |= PAGE_WRITE; |
| 1363 | 1363 |
break; |
| 1364 | 1364 |
#if defined(TARGET_PPC64) |
| 1365 |
case POWERPC_MMU_620: |
|
| 1365 | 1366 |
case POWERPC_MMU_64B: |
| 1366 | 1367 |
/* Real address are 60 bits long */ |
| 1367 | 1368 |
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL; |
| ... | ... | |
| 1430 | 1431 |
case POWERPC_MMU_SOFT_6xx: |
| 1431 | 1432 |
case POWERPC_MMU_SOFT_74xx: |
| 1432 | 1433 |
#if defined(TARGET_PPC64) |
| 1434 |
case POWERPC_MMU_620: |
|
| 1433 | 1435 |
case POWERPC_MMU_64B: |
| 1434 | 1436 |
#endif |
| 1435 | 1437 |
/* Try to find a BAT */ |
| ... | ... | |
| 1538 | 1540 |
case POWERPC_MMU_32B: |
| 1539 | 1541 |
case POWERPC_MMU_601: |
| 1540 | 1542 |
#if defined(TARGET_PPC64) |
| 1543 |
case POWERPC_MMU_620: |
|
| 1541 | 1544 |
case POWERPC_MMU_64B: |
| 1542 | 1545 |
#endif |
| 1543 | 1546 |
env->exception_index = POWERPC_EXCP_ISI; |
| ... | ... | |
| 1583 | 1586 |
#if defined(TARGET_PPC64) |
| 1584 | 1587 |
case -5: |
| 1585 | 1588 |
/* No match in segment table */ |
| 1586 |
env->exception_index = POWERPC_EXCP_ISEG; |
|
| 1587 |
env->error_code = 0; |
|
| 1589 |
if (env->mmu_model == POWERPC_MMU_620) {
|
|
| 1590 |
env->exception_index = POWERPC_EXCP_ISI; |
|
| 1591 |
/* XXX: this might be incorrect */ |
|
| 1592 |
env->error_code = 0x40000000; |
|
| 1593 |
} else {
|
|
| 1594 |
env->exception_index = POWERPC_EXCP_ISEG; |
|
| 1595 |
env->error_code = 0; |
|
| 1596 |
} |
|
| 1588 | 1597 |
break; |
| 1589 | 1598 |
#endif |
| 1590 | 1599 |
} |
| ... | ... | |
| 1634 | 1643 |
case POWERPC_MMU_32B: |
| 1635 | 1644 |
case POWERPC_MMU_601: |
| 1636 | 1645 |
#if defined(TARGET_PPC64) |
| 1646 |
case POWERPC_MMU_620: |
|
| 1637 | 1647 |
case POWERPC_MMU_64B: |
| 1638 | 1648 |
#endif |
| 1639 | 1649 |
env->exception_index = POWERPC_EXCP_DSI; |
| ... | ... | |
| 1716 | 1726 |
#if defined(TARGET_PPC64) |
| 1717 | 1727 |
case -5: |
| 1718 | 1728 |
/* No match in segment table */ |
| 1719 |
env->exception_index = POWERPC_EXCP_DSEG; |
|
| 1720 |
env->error_code = 0; |
|
| 1721 |
env->spr[SPR_DAR] = address; |
|
| 1729 |
if (env->mmu_model == POWERPC_MMU_620) {
|
|
| 1730 |
env->exception_index = POWERPC_EXCP_DSI; |
|
| 1731 |
env->error_code = 0; |
|
| 1732 |
env->spr[SPR_DAR] = address; |
|
| 1733 |
/* XXX: this might be incorrect */ |
|
| 1734 |
if (rw == 1) |
|
| 1735 |
env->spr[SPR_DSISR] = 0x42000000; |
|
| 1736 |
else |
|
| 1737 |
env->spr[SPR_DSISR] = 0x40000000; |
|
| 1738 |
} else {
|
|
| 1739 |
env->exception_index = POWERPC_EXCP_DSEG; |
|
| 1740 |
env->error_code = 0; |
|
| 1741 |
env->spr[SPR_DAR] = address; |
|
| 1742 |
} |
|
| 1722 | 1743 |
break; |
| 1723 | 1744 |
#endif |
| 1724 | 1745 |
} |
| ... | ... | |
| 1955 | 1976 |
case POWERPC_MMU_32B: |
| 1956 | 1977 |
case POWERPC_MMU_601: |
| 1957 | 1978 |
#if defined(TARGET_PPC64) |
| 1979 |
case POWERPC_MMU_620: |
|
| 1958 | 1980 |
case POWERPC_MMU_64B: |
| 1959 | 1981 |
#endif /* defined(TARGET_PPC64) */ |
| 1960 | 1982 |
tlb_flush(env, 1); |
| ... | ... | |
| 2021 | 2043 |
tlb_flush_page(env, addr | (0xF << 28)); |
| 2022 | 2044 |
break; |
| 2023 | 2045 |
#if defined(TARGET_PPC64) |
| 2046 |
case POWERPC_MMU_620: |
|
| 2024 | 2047 |
case POWERPC_MMU_64B: |
| 2025 | 2048 |
/* tlbie invalidate TLBs for all segments */ |
| 2026 | 2049 |
/* XXX: given the fact that there are too many segments to invalidate, |
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