root / opc-i386.h @ ae48a073
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| 1 | 0ea00c9a | bellard | DEF(end, 0)
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|---|---|---|---|
| 2 | 0ea00c9a | bellard | DEF(movl_A0_EAX, 0)
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| 3 | 0ea00c9a | bellard | DEF(addl_A0_EAX, 0)
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| 4 | 0ea00c9a | bellard | DEF(addl_A0_EAX_s1, 0)
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| 5 | 0ea00c9a | bellard | DEF(addl_A0_EAX_s2, 0)
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| 6 | 0ea00c9a | bellard | DEF(addl_A0_EAX_s3, 0)
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| 7 | 0ea00c9a | bellard | DEF(movl_T0_EAX, 0)
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| 8 | 0ea00c9a | bellard | DEF(movl_T1_EAX, 0)
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| 9 | 0ea00c9a | bellard | DEF(movh_T0_EAX, 0)
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| 10 | 0ea00c9a | bellard | DEF(movh_T1_EAX, 0)
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| 11 | 0ea00c9a | bellard | DEF(movl_EAX_T0, 0)
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| 12 | 0ea00c9a | bellard | DEF(movl_EAX_T1, 0)
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| 13 | 0ea00c9a | bellard | DEF(movl_EAX_A0, 0)
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| 14 | 0ea00c9a | bellard | DEF(cmovw_EAX_T1_T0, 0)
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| 15 | 0ea00c9a | bellard | DEF(cmovl_EAX_T1_T0, 0)
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| 16 | 0ea00c9a | bellard | DEF(movw_EAX_T0, 0)
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| 17 | 0ea00c9a | bellard | DEF(movw_EAX_T1, 0)
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| 18 | 0ea00c9a | bellard | DEF(movw_EAX_A0, 0)
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| 19 | 0ea00c9a | bellard | DEF(movb_EAX_T0, 0)
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| 20 | 0ea00c9a | bellard | DEF(movh_EAX_T0, 0)
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| 21 | 0ea00c9a | bellard | DEF(movb_EAX_T1, 0)
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| 22 | 0ea00c9a | bellard | DEF(movh_EAX_T1, 0)
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| 23 | 0ea00c9a | bellard | DEF(movl_A0_ECX, 0)
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| 24 | 0ea00c9a | bellard | DEF(addl_A0_ECX, 0)
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| 25 | 0ea00c9a | bellard | DEF(addl_A0_ECX_s1, 0)
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| 26 | 0ea00c9a | bellard | DEF(addl_A0_ECX_s2, 0)
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| 27 | 0ea00c9a | bellard | DEF(addl_A0_ECX_s3, 0)
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| 28 | 0ea00c9a | bellard | DEF(movl_T0_ECX, 0)
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| 29 | 0ea00c9a | bellard | DEF(movl_T1_ECX, 0)
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| 30 | 0ea00c9a | bellard | DEF(movh_T0_ECX, 0)
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| 31 | 0ea00c9a | bellard | DEF(movh_T1_ECX, 0)
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| 32 | 0ea00c9a | bellard | DEF(movl_ECX_T0, 0)
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| 33 | 0ea00c9a | bellard | DEF(movl_ECX_T1, 0)
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| 34 | 0ea00c9a | bellard | DEF(movl_ECX_A0, 0)
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| 35 | 0ea00c9a | bellard | DEF(cmovw_ECX_T1_T0, 0)
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| 36 | 0ea00c9a | bellard | DEF(cmovl_ECX_T1_T0, 0)
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| 37 | 0ea00c9a | bellard | DEF(movw_ECX_T0, 0)
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| 38 | 0ea00c9a | bellard | DEF(movw_ECX_T1, 0)
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| 39 | 0ea00c9a | bellard | DEF(movw_ECX_A0, 0)
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| 40 | 0ea00c9a | bellard | DEF(movb_ECX_T0, 0)
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| 41 | 0ea00c9a | bellard | DEF(movh_ECX_T0, 0)
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| 42 | 0ea00c9a | bellard | DEF(movb_ECX_T1, 0)
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| 43 | 0ea00c9a | bellard | DEF(movh_ECX_T1, 0)
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| 44 | 0ea00c9a | bellard | DEF(movl_A0_EDX, 0)
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| 45 | 0ea00c9a | bellard | DEF(addl_A0_EDX, 0)
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| 46 | 0ea00c9a | bellard | DEF(addl_A0_EDX_s1, 0)
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| 47 | 0ea00c9a | bellard | DEF(addl_A0_EDX_s2, 0)
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| 48 | 0ea00c9a | bellard | DEF(addl_A0_EDX_s3, 0)
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| 49 | 0ea00c9a | bellard | DEF(movl_T0_EDX, 0)
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| 50 | 0ea00c9a | bellard | DEF(movl_T1_EDX, 0)
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| 51 | 0ea00c9a | bellard | DEF(movh_T0_EDX, 0)
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| 52 | 0ea00c9a | bellard | DEF(movh_T1_EDX, 0)
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| 53 | 0ea00c9a | bellard | DEF(movl_EDX_T0, 0)
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| 54 | 0ea00c9a | bellard | DEF(movl_EDX_T1, 0)
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| 55 | 0ea00c9a | bellard | DEF(movl_EDX_A0, 0)
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| 56 | 0ea00c9a | bellard | DEF(cmovw_EDX_T1_T0, 0)
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| 57 | 0ea00c9a | bellard | DEF(cmovl_EDX_T1_T0, 0)
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| 58 | 0ea00c9a | bellard | DEF(movw_EDX_T0, 0)
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| 59 | 0ea00c9a | bellard | DEF(movw_EDX_T1, 0)
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| 60 | 0ea00c9a | bellard | DEF(movw_EDX_A0, 0)
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| 61 | 0ea00c9a | bellard | DEF(movb_EDX_T0, 0)
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| 62 | 0ea00c9a | bellard | DEF(movh_EDX_T0, 0)
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| 63 | 0ea00c9a | bellard | DEF(movb_EDX_T1, 0)
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| 64 | 0ea00c9a | bellard | DEF(movh_EDX_T1, 0)
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| 65 | 0ea00c9a | bellard | DEF(movl_A0_EBX, 0)
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| 66 | 0ea00c9a | bellard | DEF(addl_A0_EBX, 0)
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| 67 | 0ea00c9a | bellard | DEF(addl_A0_EBX_s1, 0)
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| 68 | 0ea00c9a | bellard | DEF(addl_A0_EBX_s2, 0)
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| 69 | 0ea00c9a | bellard | DEF(addl_A0_EBX_s3, 0)
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| 70 | 0ea00c9a | bellard | DEF(movl_T0_EBX, 0)
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| 71 | 0ea00c9a | bellard | DEF(movl_T1_EBX, 0)
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| 72 | 0ea00c9a | bellard | DEF(movh_T0_EBX, 0)
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| 73 | 0ea00c9a | bellard | DEF(movh_T1_EBX, 0)
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| 74 | 0ea00c9a | bellard | DEF(movl_EBX_T0, 0)
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| 75 | 0ea00c9a | bellard | DEF(movl_EBX_T1, 0)
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| 76 | 0ea00c9a | bellard | DEF(movl_EBX_A0, 0)
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| 77 | 0ea00c9a | bellard | DEF(cmovw_EBX_T1_T0, 0)
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| 78 | 0ea00c9a | bellard | DEF(cmovl_EBX_T1_T0, 0)
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| 79 | 0ea00c9a | bellard | DEF(movw_EBX_T0, 0)
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| 80 | 0ea00c9a | bellard | DEF(movw_EBX_T1, 0)
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| 81 | 0ea00c9a | bellard | DEF(movw_EBX_A0, 0)
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| 82 | 0ea00c9a | bellard | DEF(movb_EBX_T0, 0)
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| 83 | 0ea00c9a | bellard | DEF(movh_EBX_T0, 0)
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| 84 | 0ea00c9a | bellard | DEF(movb_EBX_T1, 0)
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| 85 | 0ea00c9a | bellard | DEF(movh_EBX_T1, 0)
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| 86 | 0ea00c9a | bellard | DEF(movl_A0_ESP, 0)
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| 87 | 0ea00c9a | bellard | DEF(addl_A0_ESP, 0)
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| 88 | 0ea00c9a | bellard | DEF(addl_A0_ESP_s1, 0)
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| 89 | 0ea00c9a | bellard | DEF(addl_A0_ESP_s2, 0)
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| 90 | 0ea00c9a | bellard | DEF(addl_A0_ESP_s3, 0)
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| 91 | 0ea00c9a | bellard | DEF(movl_T0_ESP, 0)
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| 92 | 0ea00c9a | bellard | DEF(movl_T1_ESP, 0)
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| 93 | 0ea00c9a | bellard | DEF(movh_T0_ESP, 0)
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| 94 | 0ea00c9a | bellard | DEF(movh_T1_ESP, 0)
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| 95 | 0ea00c9a | bellard | DEF(movl_ESP_T0, 0)
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| 96 | 0ea00c9a | bellard | DEF(movl_ESP_T1, 0)
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| 97 | 0ea00c9a | bellard | DEF(movl_ESP_A0, 0)
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| 98 | 0ea00c9a | bellard | DEF(cmovw_ESP_T1_T0, 0)
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| 99 | 0ea00c9a | bellard | DEF(cmovl_ESP_T1_T0, 0)
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| 100 | 0ea00c9a | bellard | DEF(movw_ESP_T0, 0)
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| 101 | 0ea00c9a | bellard | DEF(movw_ESP_T1, 0)
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| 102 | 0ea00c9a | bellard | DEF(movw_ESP_A0, 0)
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| 103 | 0ea00c9a | bellard | DEF(movb_ESP_T0, 0)
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| 104 | 0ea00c9a | bellard | DEF(movh_ESP_T0, 0)
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| 105 | 0ea00c9a | bellard | DEF(movb_ESP_T1, 0)
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| 106 | 0ea00c9a | bellard | DEF(movh_ESP_T1, 0)
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| 107 | 0ea00c9a | bellard | DEF(movl_A0_EBP, 0)
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| 108 | 0ea00c9a | bellard | DEF(addl_A0_EBP, 0)
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| 109 | 0ea00c9a | bellard | DEF(addl_A0_EBP_s1, 0)
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| 110 | 0ea00c9a | bellard | DEF(addl_A0_EBP_s2, 0)
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| 111 | 0ea00c9a | bellard | DEF(addl_A0_EBP_s3, 0)
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| 112 | 0ea00c9a | bellard | DEF(movl_T0_EBP, 0)
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| 113 | 0ea00c9a | bellard | DEF(movl_T1_EBP, 0)
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| 114 | 0ea00c9a | bellard | DEF(movh_T0_EBP, 0)
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| 115 | 0ea00c9a | bellard | DEF(movh_T1_EBP, 0)
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| 116 | 0ea00c9a | bellard | DEF(movl_EBP_T0, 0)
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| 117 | 0ea00c9a | bellard | DEF(movl_EBP_T1, 0)
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| 118 | 0ea00c9a | bellard | DEF(movl_EBP_A0, 0)
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| 119 | 0ea00c9a | bellard | DEF(cmovw_EBP_T1_T0, 0)
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| 120 | 0ea00c9a | bellard | DEF(cmovl_EBP_T1_T0, 0)
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| 121 | 0ea00c9a | bellard | DEF(movw_EBP_T0, 0)
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| 122 | 0ea00c9a | bellard | DEF(movw_EBP_T1, 0)
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| 123 | 0ea00c9a | bellard | DEF(movw_EBP_A0, 0)
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| 124 | 0ea00c9a | bellard | DEF(movb_EBP_T0, 0)
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| 125 | 0ea00c9a | bellard | DEF(movh_EBP_T0, 0)
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| 126 | 0ea00c9a | bellard | DEF(movb_EBP_T1, 0)
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| 127 | 0ea00c9a | bellard | DEF(movh_EBP_T1, 0)
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| 128 | 0ea00c9a | bellard | DEF(movl_A0_ESI, 0)
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| 129 | 0ea00c9a | bellard | DEF(addl_A0_ESI, 0)
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| 130 | 0ea00c9a | bellard | DEF(addl_A0_ESI_s1, 0)
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| 131 | 0ea00c9a | bellard | DEF(addl_A0_ESI_s2, 0)
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| 132 | 0ea00c9a | bellard | DEF(addl_A0_ESI_s3, 0)
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| 133 | 0ea00c9a | bellard | DEF(movl_T0_ESI, 0)
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| 134 | 0ea00c9a | bellard | DEF(movl_T1_ESI, 0)
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| 135 | 0ea00c9a | bellard | DEF(movh_T0_ESI, 0)
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| 136 | 0ea00c9a | bellard | DEF(movh_T1_ESI, 0)
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| 137 | 0ea00c9a | bellard | DEF(movl_ESI_T0, 0)
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| 138 | 0ea00c9a | bellard | DEF(movl_ESI_T1, 0)
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| 139 | 0ea00c9a | bellard | DEF(movl_ESI_A0, 0)
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| 140 | 0ea00c9a | bellard | DEF(cmovw_ESI_T1_T0, 0)
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| 141 | 0ea00c9a | bellard | DEF(cmovl_ESI_T1_T0, 0)
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| 142 | 0ea00c9a | bellard | DEF(movw_ESI_T0, 0)
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| 143 | 0ea00c9a | bellard | DEF(movw_ESI_T1, 0)
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| 144 | 0ea00c9a | bellard | DEF(movw_ESI_A0, 0)
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| 145 | 0ea00c9a | bellard | DEF(movb_ESI_T0, 0)
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| 146 | 0ea00c9a | bellard | DEF(movh_ESI_T0, 0)
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| 147 | 0ea00c9a | bellard | DEF(movb_ESI_T1, 0)
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| 148 | 0ea00c9a | bellard | DEF(movh_ESI_T1, 0)
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| 149 | 0ea00c9a | bellard | DEF(movl_A0_EDI, 0)
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| 150 | 0ea00c9a | bellard | DEF(addl_A0_EDI, 0)
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| 151 | 0ea00c9a | bellard | DEF(addl_A0_EDI_s1, 0)
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| 152 | 0ea00c9a | bellard | DEF(addl_A0_EDI_s2, 0)
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| 153 | 0ea00c9a | bellard | DEF(addl_A0_EDI_s3, 0)
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| 154 | 0ea00c9a | bellard | DEF(movl_T0_EDI, 0)
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| 155 | 0ea00c9a | bellard | DEF(movl_T1_EDI, 0)
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| 156 | 0ea00c9a | bellard | DEF(movh_T0_EDI, 0)
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| 157 | 0ea00c9a | bellard | DEF(movh_T1_EDI, 0)
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| 158 | 0ea00c9a | bellard | DEF(movl_EDI_T0, 0)
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| 159 | 0ea00c9a | bellard | DEF(movl_EDI_T1, 0)
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| 160 | 0ea00c9a | bellard | DEF(movl_EDI_A0, 0)
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| 161 | 0ea00c9a | bellard | DEF(cmovw_EDI_T1_T0, 0)
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| 162 | 0ea00c9a | bellard | DEF(cmovl_EDI_T1_T0, 0)
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| 163 | 0ea00c9a | bellard | DEF(movw_EDI_T0, 0)
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| 164 | 0ea00c9a | bellard | DEF(movw_EDI_T1, 0)
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| 165 | 0ea00c9a | bellard | DEF(movw_EDI_A0, 0)
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| 166 | 0ea00c9a | bellard | DEF(movb_EDI_T0, 0)
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| 167 | 0ea00c9a | bellard | DEF(movh_EDI_T0, 0)
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| 168 | 0ea00c9a | bellard | DEF(movb_EDI_T1, 0)
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| 169 | 0ea00c9a | bellard | DEF(movh_EDI_T1, 0)
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| 170 | 0ea00c9a | bellard | DEF(addl_T0_T1_cc, 0)
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| 171 | 0ea00c9a | bellard | DEF(orl_T0_T1_cc, 0)
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| 172 | 0ea00c9a | bellard | DEF(andl_T0_T1_cc, 0)
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| 173 | 0ea00c9a | bellard | DEF(subl_T0_T1_cc, 0)
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| 174 | 0ea00c9a | bellard | DEF(xorl_T0_T1_cc, 0)
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| 175 | 0ea00c9a | bellard | DEF(cmpl_T0_T1_cc, 0)
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| 176 | 0ea00c9a | bellard | DEF(negl_T0_cc, 0)
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| 177 | 0ea00c9a | bellard | DEF(incl_T0_cc, 0)
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| 178 | 0ea00c9a | bellard | DEF(decl_T0_cc, 0)
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| 179 | 0ea00c9a | bellard | DEF(testl_T0_T1_cc, 0)
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| 180 | 0ea00c9a | bellard | DEF(addl_T0_T1, 0)
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| 181 | 0ea00c9a | bellard | DEF(orl_T0_T1, 0)
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| 182 | 0ea00c9a | bellard | DEF(andl_T0_T1, 0)
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| 183 | 0ea00c9a | bellard | DEF(subl_T0_T1, 0)
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| 184 | 0ea00c9a | bellard | DEF(xorl_T0_T1, 0)
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| 185 | 0ea00c9a | bellard | DEF(negl_T0, 0)
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| 186 | 0ea00c9a | bellard | DEF(incl_T0, 0)
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| 187 | 0ea00c9a | bellard | DEF(decl_T0, 0)
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| 188 | 0ea00c9a | bellard | DEF(notl_T0, 0)
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| 189 | 0ea00c9a | bellard | DEF(bswapl_T0, 0)
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| 190 | 0ea00c9a | bellard | DEF(mulb_AL_T0, 0)
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| 191 | 0ea00c9a | bellard | DEF(imulb_AL_T0, 0)
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| 192 | 0ea00c9a | bellard | DEF(mulw_AX_T0, 0)
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| 193 | 0ea00c9a | bellard | DEF(imulw_AX_T0, 0)
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| 194 | 0ea00c9a | bellard | DEF(mull_EAX_T0, 0)
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| 195 | 0ea00c9a | bellard | DEF(imull_EAX_T0, 0)
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| 196 | 0ea00c9a | bellard | DEF(imulw_T0_T1, 0)
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| 197 | 0ea00c9a | bellard | DEF(imull_T0_T1, 0)
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| 198 | 0ea00c9a | bellard | DEF(divb_AL_T0, 0)
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| 199 | 0ea00c9a | bellard | DEF(idivb_AL_T0, 0)
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| 200 | 0ea00c9a | bellard | DEF(divw_AX_T0, 0)
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| 201 | 0ea00c9a | bellard | DEF(idivw_AX_T0, 0)
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| 202 | 0ea00c9a | bellard | DEF(divl_EAX_T0, 0)
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| 203 | 0ea00c9a | bellard | DEF(idivl_EAX_T0, 0)
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| 204 | 0ea00c9a | bellard | DEF(movl_T0_im, 1)
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| 205 | 0ea00c9a | bellard | DEF(addl_T0_im, 1)
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| 206 | 0ea00c9a | bellard | DEF(andl_T0_ffff, 0)
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| 207 | 0ea00c9a | bellard | DEF(movl_T0_T1, 0)
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| 208 | 0ea00c9a | bellard | DEF(movl_T1_im, 1)
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| 209 | 0ea00c9a | bellard | DEF(addl_T1_im, 1)
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| 210 | 0ea00c9a | bellard | DEF(movl_T1_A0, 0)
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| 211 | 0ea00c9a | bellard | DEF(movl_A0_im, 1)
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| 212 | 0ea00c9a | bellard | DEF(addl_A0_im, 1)
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| 213 | 0ea00c9a | bellard | DEF(addl_A0_AL, 0)
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| 214 | 0ea00c9a | bellard | DEF(andl_A0_ffff, 0)
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| 215 | 0ea00c9a | bellard | DEF(ldub_T0_A0, 0)
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| 216 | 0ea00c9a | bellard | DEF(ldsb_T0_A0, 0)
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| 217 | 0ea00c9a | bellard | DEF(lduw_T0_A0, 0)
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| 218 | 0ea00c9a | bellard | DEF(ldsw_T0_A0, 0)
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| 219 | 0ea00c9a | bellard | DEF(ldl_T0_A0, 0)
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| 220 | 0ea00c9a | bellard | DEF(ldub_T1_A0, 0)
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| 221 | 0ea00c9a | bellard | DEF(ldsb_T1_A0, 0)
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| 222 | 0ea00c9a | bellard | DEF(lduw_T1_A0, 0)
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| 223 | 0ea00c9a | bellard | DEF(ldsw_T1_A0, 0)
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| 224 | 0ea00c9a | bellard | DEF(ldl_T1_A0, 0)
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| 225 | 0ea00c9a | bellard | DEF(stb_T0_A0, 0)
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| 226 | 0ea00c9a | bellard | DEF(stw_T0_A0, 0)
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| 227 | 0ea00c9a | bellard | DEF(stl_T0_A0, 0)
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| 228 | 0ea00c9a | bellard | DEF(add_bitw_A0_T1, 0)
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| 229 | 0ea00c9a | bellard | DEF(add_bitl_A0_T1, 0)
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| 230 | 0ea00c9a | bellard | DEF(jmp_T0, 0)
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| 231 | 0ea00c9a | bellard | DEF(jmp_im, 1)
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| 232 | 0ea00c9a | bellard | DEF(int_im, 1)
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| 233 | 0ea00c9a | bellard | DEF(int3, 1)
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| 234 | 0ea00c9a | bellard | DEF(into, 0)
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| 235 | f631ef9b | bellard | DEF(cli, 0)
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| 236 | f631ef9b | bellard | DEF(sti, 0)
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| 237 | f631ef9b | bellard | DEF(cli_vm, 0)
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| 238 | f631ef9b | bellard | DEF(sti_vm, 1)
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| 239 | 0ea00c9a | bellard | DEF(boundw, 0)
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| 240 | 0ea00c9a | bellard | DEF(boundl, 0)
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| 241 | 0ea00c9a | bellard | DEF(cmpxchg8b, 0)
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| 242 | 0ea00c9a | bellard | DEF(jb_subb, 2)
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| 243 | 0ea00c9a | bellard | DEF(jz_subb, 2)
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| 244 | 0ea00c9a | bellard | DEF(jbe_subb, 2)
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| 245 | 0ea00c9a | bellard | DEF(js_subb, 2)
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| 246 | 0ea00c9a | bellard | DEF(jl_subb, 2)
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| 247 | 0ea00c9a | bellard | DEF(jle_subb, 2)
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| 248 | 0ea00c9a | bellard | DEF(setb_T0_subb, 0)
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| 249 | 0ea00c9a | bellard | DEF(setz_T0_subb, 0)
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| 250 | 0ea00c9a | bellard | DEF(setbe_T0_subb, 0)
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| 251 | 0ea00c9a | bellard | DEF(sets_T0_subb, 0)
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| 252 | 0ea00c9a | bellard | DEF(setl_T0_subb, 0)
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| 253 | 0ea00c9a | bellard | DEF(setle_T0_subb, 0)
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| 254 | 0ea00c9a | bellard | DEF(rolb_T0_T1_cc, 0)
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| 255 | 0ea00c9a | bellard | DEF(rolb_T0_T1, 0)
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| 256 | 0ea00c9a | bellard | DEF(rorb_T0_T1_cc, 0)
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| 257 | 0ea00c9a | bellard | DEF(rorb_T0_T1, 0)
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| 258 | 0ea00c9a | bellard | DEF(rclb_T0_T1_cc, 0)
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| 259 | 0ea00c9a | bellard | DEF(rcrb_T0_T1_cc, 0)
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| 260 | 0ea00c9a | bellard | DEF(shlb_T0_T1_cc, 0)
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| 261 | 0ea00c9a | bellard | DEF(shlb_T0_T1, 0)
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| 262 | 0ea00c9a | bellard | DEF(shrb_T0_T1_cc, 0)
|
| 263 | 0ea00c9a | bellard | DEF(shrb_T0_T1, 0)
|
| 264 | 0ea00c9a | bellard | DEF(sarb_T0_T1_cc, 0)
|
| 265 | 0ea00c9a | bellard | DEF(sarb_T0_T1, 0)
|
| 266 | 0ea00c9a | bellard | DEF(adcb_T0_T1_cc, 0)
|
| 267 | 0ea00c9a | bellard | DEF(sbbb_T0_T1_cc, 0)
|
| 268 | 0ea00c9a | bellard | DEF(cmpxchgb_T0_T1_EAX_cc, 0)
|
| 269 | 0ea00c9a | bellard | DEF(movsb_fast, 0)
|
| 270 | 0ea00c9a | bellard | DEF(rep_movsb_fast, 0)
|
| 271 | 0ea00c9a | bellard | DEF(stosb_fast, 0)
|
| 272 | 0ea00c9a | bellard | DEF(rep_stosb_fast, 0)
|
| 273 | 0ea00c9a | bellard | DEF(lodsb_fast, 0)
|
| 274 | 0ea00c9a | bellard | DEF(rep_lodsb_fast, 0)
|
| 275 | 0ea00c9a | bellard | DEF(scasb_fast, 0)
|
| 276 | 0ea00c9a | bellard | DEF(repz_scasb_fast, 0)
|
| 277 | 0ea00c9a | bellard | DEF(repnz_scasb_fast, 0)
|
| 278 | 0ea00c9a | bellard | DEF(cmpsb_fast, 0)
|
| 279 | 0ea00c9a | bellard | DEF(repz_cmpsb_fast, 0)
|
| 280 | 0ea00c9a | bellard | DEF(repnz_cmpsb_fast, 0)
|
| 281 | 0ea00c9a | bellard | DEF(outsb_fast, 0)
|
| 282 | 0ea00c9a | bellard | DEF(rep_outsb_fast, 0)
|
| 283 | 0ea00c9a | bellard | DEF(insb_fast, 0)
|
| 284 | 0ea00c9a | bellard | DEF(rep_insb_fast, 0)
|
| 285 | 0ea00c9a | bellard | DEF(movsb_a32, 0)
|
| 286 | 0ea00c9a | bellard | DEF(rep_movsb_a32, 0)
|
| 287 | 0ea00c9a | bellard | DEF(stosb_a32, 0)
|
| 288 | 0ea00c9a | bellard | DEF(rep_stosb_a32, 0)
|
| 289 | 0ea00c9a | bellard | DEF(lodsb_a32, 0)
|
| 290 | 0ea00c9a | bellard | DEF(rep_lodsb_a32, 0)
|
| 291 | 0ea00c9a | bellard | DEF(scasb_a32, 0)
|
| 292 | 0ea00c9a | bellard | DEF(repz_scasb_a32, 0)
|
| 293 | 0ea00c9a | bellard | DEF(repnz_scasb_a32, 0)
|
| 294 | 0ea00c9a | bellard | DEF(cmpsb_a32, 0)
|
| 295 | 0ea00c9a | bellard | DEF(repz_cmpsb_a32, 0)
|
| 296 | 0ea00c9a | bellard | DEF(repnz_cmpsb_a32, 0)
|
| 297 | 0ea00c9a | bellard | DEF(outsb_a32, 0)
|
| 298 | 0ea00c9a | bellard | DEF(rep_outsb_a32, 0)
|
| 299 | 0ea00c9a | bellard | DEF(insb_a32, 0)
|
| 300 | 0ea00c9a | bellard | DEF(rep_insb_a32, 0)
|
| 301 | 0ea00c9a | bellard | DEF(movsb_a16, 0)
|
| 302 | 0ea00c9a | bellard | DEF(rep_movsb_a16, 0)
|
| 303 | 0ea00c9a | bellard | DEF(stosb_a16, 0)
|
| 304 | 0ea00c9a | bellard | DEF(rep_stosb_a16, 0)
|
| 305 | 0ea00c9a | bellard | DEF(lodsb_a16, 0)
|
| 306 | 0ea00c9a | bellard | DEF(rep_lodsb_a16, 0)
|
| 307 | 0ea00c9a | bellard | DEF(scasb_a16, 0)
|
| 308 | 0ea00c9a | bellard | DEF(repz_scasb_a16, 0)
|
| 309 | 0ea00c9a | bellard | DEF(repnz_scasb_a16, 0)
|
| 310 | 0ea00c9a | bellard | DEF(cmpsb_a16, 0)
|
| 311 | 0ea00c9a | bellard | DEF(repz_cmpsb_a16, 0)
|
| 312 | 0ea00c9a | bellard | DEF(repnz_cmpsb_a16, 0)
|
| 313 | 0ea00c9a | bellard | DEF(outsb_a16, 0)
|
| 314 | 0ea00c9a | bellard | DEF(rep_outsb_a16, 0)
|
| 315 | 0ea00c9a | bellard | DEF(insb_a16, 0)
|
| 316 | 0ea00c9a | bellard | DEF(rep_insb_a16, 0)
|
| 317 | 0ea00c9a | bellard | DEF(outb_T0_T1, 0)
|
| 318 | 0ea00c9a | bellard | DEF(inb_T0_T1, 0)
|
| 319 | 0ea00c9a | bellard | DEF(jb_subw, 2)
|
| 320 | 0ea00c9a | bellard | DEF(jz_subw, 2)
|
| 321 | 0ea00c9a | bellard | DEF(jbe_subw, 2)
|
| 322 | 0ea00c9a | bellard | DEF(js_subw, 2)
|
| 323 | 0ea00c9a | bellard | DEF(jl_subw, 2)
|
| 324 | 0ea00c9a | bellard | DEF(jle_subw, 2)
|
| 325 | 0ea00c9a | bellard | DEF(loopnzw, 2)
|
| 326 | 0ea00c9a | bellard | DEF(loopzw, 2)
|
| 327 | 0ea00c9a | bellard | DEF(loopw, 2)
|
| 328 | 0ea00c9a | bellard | DEF(jecxzw, 2)
|
| 329 | 0ea00c9a | bellard | DEF(setb_T0_subw, 0)
|
| 330 | 0ea00c9a | bellard | DEF(setz_T0_subw, 0)
|
| 331 | 0ea00c9a | bellard | DEF(setbe_T0_subw, 0)
|
| 332 | 0ea00c9a | bellard | DEF(sets_T0_subw, 0)
|
| 333 | 0ea00c9a | bellard | DEF(setl_T0_subw, 0)
|
| 334 | 0ea00c9a | bellard | DEF(setle_T0_subw, 0)
|
| 335 | 0ea00c9a | bellard | DEF(rolw_T0_T1_cc, 0)
|
| 336 | 0ea00c9a | bellard | DEF(rolw_T0_T1, 0)
|
| 337 | 0ea00c9a | bellard | DEF(rorw_T0_T1_cc, 0)
|
| 338 | 0ea00c9a | bellard | DEF(rorw_T0_T1, 0)
|
| 339 | 0ea00c9a | bellard | DEF(rclw_T0_T1_cc, 0)
|
| 340 | 0ea00c9a | bellard | DEF(rcrw_T0_T1_cc, 0)
|
| 341 | 0ea00c9a | bellard | DEF(shlw_T0_T1_cc, 0)
|
| 342 | 0ea00c9a | bellard | DEF(shlw_T0_T1, 0)
|
| 343 | 0ea00c9a | bellard | DEF(shrw_T0_T1_cc, 0)
|
| 344 | 0ea00c9a | bellard | DEF(shrw_T0_T1, 0)
|
| 345 | 0ea00c9a | bellard | DEF(sarw_T0_T1_cc, 0)
|
| 346 | 0ea00c9a | bellard | DEF(sarw_T0_T1, 0)
|
| 347 | 0ea00c9a | bellard | DEF(shldw_T0_T1_im_cc, 1)
|
| 348 | 0ea00c9a | bellard | DEF(shldw_T0_T1_ECX_cc, 0)
|
| 349 | 0ea00c9a | bellard | DEF(shrdw_T0_T1_im_cc, 1)
|
| 350 | 0ea00c9a | bellard | DEF(shrdw_T0_T1_ECX_cc, 0)
|
| 351 | 0ea00c9a | bellard | DEF(adcw_T0_T1_cc, 0)
|
| 352 | 0ea00c9a | bellard | DEF(sbbw_T0_T1_cc, 0)
|
| 353 | 0ea00c9a | bellard | DEF(cmpxchgw_T0_T1_EAX_cc, 0)
|
| 354 | 0ea00c9a | bellard | DEF(btw_T0_T1_cc, 0)
|
| 355 | 0ea00c9a | bellard | DEF(btsw_T0_T1_cc, 0)
|
| 356 | 0ea00c9a | bellard | DEF(btrw_T0_T1_cc, 0)
|
| 357 | 0ea00c9a | bellard | DEF(btcw_T0_T1_cc, 0)
|
| 358 | 0ea00c9a | bellard | DEF(bsfw_T0_cc, 0)
|
| 359 | 0ea00c9a | bellard | DEF(bsrw_T0_cc, 0)
|
| 360 | 0ea00c9a | bellard | DEF(movsw_fast, 0)
|
| 361 | 0ea00c9a | bellard | DEF(rep_movsw_fast, 0)
|
| 362 | 0ea00c9a | bellard | DEF(stosw_fast, 0)
|
| 363 | 0ea00c9a | bellard | DEF(rep_stosw_fast, 0)
|
| 364 | 0ea00c9a | bellard | DEF(lodsw_fast, 0)
|
| 365 | 0ea00c9a | bellard | DEF(rep_lodsw_fast, 0)
|
| 366 | 0ea00c9a | bellard | DEF(scasw_fast, 0)
|
| 367 | 0ea00c9a | bellard | DEF(repz_scasw_fast, 0)
|
| 368 | 0ea00c9a | bellard | DEF(repnz_scasw_fast, 0)
|
| 369 | 0ea00c9a | bellard | DEF(cmpsw_fast, 0)
|
| 370 | 0ea00c9a | bellard | DEF(repz_cmpsw_fast, 0)
|
| 371 | 0ea00c9a | bellard | DEF(repnz_cmpsw_fast, 0)
|
| 372 | 0ea00c9a | bellard | DEF(outsw_fast, 0)
|
| 373 | 0ea00c9a | bellard | DEF(rep_outsw_fast, 0)
|
| 374 | 0ea00c9a | bellard | DEF(insw_fast, 0)
|
| 375 | 0ea00c9a | bellard | DEF(rep_insw_fast, 0)
|
| 376 | 0ea00c9a | bellard | DEF(movsw_a32, 0)
|
| 377 | 0ea00c9a | bellard | DEF(rep_movsw_a32, 0)
|
| 378 | 0ea00c9a | bellard | DEF(stosw_a32, 0)
|
| 379 | 0ea00c9a | bellard | DEF(rep_stosw_a32, 0)
|
| 380 | 0ea00c9a | bellard | DEF(lodsw_a32, 0)
|
| 381 | 0ea00c9a | bellard | DEF(rep_lodsw_a32, 0)
|
| 382 | 0ea00c9a | bellard | DEF(scasw_a32, 0)
|
| 383 | 0ea00c9a | bellard | DEF(repz_scasw_a32, 0)
|
| 384 | 0ea00c9a | bellard | DEF(repnz_scasw_a32, 0)
|
| 385 | 0ea00c9a | bellard | DEF(cmpsw_a32, 0)
|
| 386 | 0ea00c9a | bellard | DEF(repz_cmpsw_a32, 0)
|
| 387 | 0ea00c9a | bellard | DEF(repnz_cmpsw_a32, 0)
|
| 388 | 0ea00c9a | bellard | DEF(outsw_a32, 0)
|
| 389 | 0ea00c9a | bellard | DEF(rep_outsw_a32, 0)
|
| 390 | 0ea00c9a | bellard | DEF(insw_a32, 0)
|
| 391 | 0ea00c9a | bellard | DEF(rep_insw_a32, 0)
|
| 392 | 0ea00c9a | bellard | DEF(movsw_a16, 0)
|
| 393 | 0ea00c9a | bellard | DEF(rep_movsw_a16, 0)
|
| 394 | 0ea00c9a | bellard | DEF(stosw_a16, 0)
|
| 395 | 0ea00c9a | bellard | DEF(rep_stosw_a16, 0)
|
| 396 | 0ea00c9a | bellard | DEF(lodsw_a16, 0)
|
| 397 | 0ea00c9a | bellard | DEF(rep_lodsw_a16, 0)
|
| 398 | 0ea00c9a | bellard | DEF(scasw_a16, 0)
|
| 399 | 0ea00c9a | bellard | DEF(repz_scasw_a16, 0)
|
| 400 | 0ea00c9a | bellard | DEF(repnz_scasw_a16, 0)
|
| 401 | 0ea00c9a | bellard | DEF(cmpsw_a16, 0)
|
| 402 | 0ea00c9a | bellard | DEF(repz_cmpsw_a16, 0)
|
| 403 | 0ea00c9a | bellard | DEF(repnz_cmpsw_a16, 0)
|
| 404 | 0ea00c9a | bellard | DEF(outsw_a16, 0)
|
| 405 | 0ea00c9a | bellard | DEF(rep_outsw_a16, 0)
|
| 406 | 0ea00c9a | bellard | DEF(insw_a16, 0)
|
| 407 | 0ea00c9a | bellard | DEF(rep_insw_a16, 0)
|
| 408 | 0ea00c9a | bellard | DEF(outw_T0_T1, 0)
|
| 409 | 0ea00c9a | bellard | DEF(inw_T0_T1, 0)
|
| 410 | 0ea00c9a | bellard | DEF(jb_subl, 2)
|
| 411 | 0ea00c9a | bellard | DEF(jz_subl, 2)
|
| 412 | 0ea00c9a | bellard | DEF(jbe_subl, 2)
|
| 413 | 0ea00c9a | bellard | DEF(js_subl, 2)
|
| 414 | 0ea00c9a | bellard | DEF(jl_subl, 2)
|
| 415 | 0ea00c9a | bellard | DEF(jle_subl, 2)
|
| 416 | 0ea00c9a | bellard | DEF(loopnzl, 2)
|
| 417 | 0ea00c9a | bellard | DEF(loopzl, 2)
|
| 418 | 0ea00c9a | bellard | DEF(loopl, 2)
|
| 419 | 0ea00c9a | bellard | DEF(jecxzl, 2)
|
| 420 | 0ea00c9a | bellard | DEF(setb_T0_subl, 0)
|
| 421 | 0ea00c9a | bellard | DEF(setz_T0_subl, 0)
|
| 422 | 0ea00c9a | bellard | DEF(setbe_T0_subl, 0)
|
| 423 | 0ea00c9a | bellard | DEF(sets_T0_subl, 0)
|
| 424 | 0ea00c9a | bellard | DEF(setl_T0_subl, 0)
|
| 425 | 0ea00c9a | bellard | DEF(setle_T0_subl, 0)
|
| 426 | 0ea00c9a | bellard | DEF(roll_T0_T1_cc, 0)
|
| 427 | 0ea00c9a | bellard | DEF(roll_T0_T1, 0)
|
| 428 | 0ea00c9a | bellard | DEF(rorl_T0_T1_cc, 0)
|
| 429 | 0ea00c9a | bellard | DEF(rorl_T0_T1, 0)
|
| 430 | 0ea00c9a | bellard | DEF(rcll_T0_T1_cc, 0)
|
| 431 | 0ea00c9a | bellard | DEF(rcrl_T0_T1_cc, 0)
|
| 432 | 0ea00c9a | bellard | DEF(shll_T0_T1_cc, 0)
|
| 433 | 0ea00c9a | bellard | DEF(shll_T0_T1, 0)
|
| 434 | 0ea00c9a | bellard | DEF(shrl_T0_T1_cc, 0)
|
| 435 | 0ea00c9a | bellard | DEF(shrl_T0_T1, 0)
|
| 436 | 0ea00c9a | bellard | DEF(sarl_T0_T1_cc, 0)
|
| 437 | 0ea00c9a | bellard | DEF(sarl_T0_T1, 0)
|
| 438 | 0ea00c9a | bellard | DEF(shldl_T0_T1_im_cc, 1)
|
| 439 | 0ea00c9a | bellard | DEF(shldl_T0_T1_ECX_cc, 0)
|
| 440 | 0ea00c9a | bellard | DEF(shrdl_T0_T1_im_cc, 1)
|
| 441 | 0ea00c9a | bellard | DEF(shrdl_T0_T1_ECX_cc, 0)
|
| 442 | 0ea00c9a | bellard | DEF(adcl_T0_T1_cc, 0)
|
| 443 | 0ea00c9a | bellard | DEF(sbbl_T0_T1_cc, 0)
|
| 444 | 0ea00c9a | bellard | DEF(cmpxchgl_T0_T1_EAX_cc, 0)
|
| 445 | 0ea00c9a | bellard | DEF(btl_T0_T1_cc, 0)
|
| 446 | 0ea00c9a | bellard | DEF(btsl_T0_T1_cc, 0)
|
| 447 | 0ea00c9a | bellard | DEF(btrl_T0_T1_cc, 0)
|
| 448 | 0ea00c9a | bellard | DEF(btcl_T0_T1_cc, 0)
|
| 449 | 0ea00c9a | bellard | DEF(bsfl_T0_cc, 0)
|
| 450 | 0ea00c9a | bellard | DEF(bsrl_T0_cc, 0)
|
| 451 | 0ea00c9a | bellard | DEF(movsl_fast, 0)
|
| 452 | 0ea00c9a | bellard | DEF(rep_movsl_fast, 0)
|
| 453 | 0ea00c9a | bellard | DEF(stosl_fast, 0)
|
| 454 | 0ea00c9a | bellard | DEF(rep_stosl_fast, 0)
|
| 455 | 0ea00c9a | bellard | DEF(lodsl_fast, 0)
|
| 456 | 0ea00c9a | bellard | DEF(rep_lodsl_fast, 0)
|
| 457 | 0ea00c9a | bellard | DEF(scasl_fast, 0)
|
| 458 | 0ea00c9a | bellard | DEF(repz_scasl_fast, 0)
|
| 459 | 0ea00c9a | bellard | DEF(repnz_scasl_fast, 0)
|
| 460 | 0ea00c9a | bellard | DEF(cmpsl_fast, 0)
|
| 461 | 0ea00c9a | bellard | DEF(repz_cmpsl_fast, 0)
|
| 462 | 0ea00c9a | bellard | DEF(repnz_cmpsl_fast, 0)
|
| 463 | 0ea00c9a | bellard | DEF(outsl_fast, 0)
|
| 464 | 0ea00c9a | bellard | DEF(rep_outsl_fast, 0)
|
| 465 | 0ea00c9a | bellard | DEF(insl_fast, 0)
|
| 466 | 0ea00c9a | bellard | DEF(rep_insl_fast, 0)
|
| 467 | 0ea00c9a | bellard | DEF(movsl_a32, 0)
|
| 468 | 0ea00c9a | bellard | DEF(rep_movsl_a32, 0)
|
| 469 | 0ea00c9a | bellard | DEF(stosl_a32, 0)
|
| 470 | 0ea00c9a | bellard | DEF(rep_stosl_a32, 0)
|
| 471 | 0ea00c9a | bellard | DEF(lodsl_a32, 0)
|
| 472 | 0ea00c9a | bellard | DEF(rep_lodsl_a32, 0)
|
| 473 | 0ea00c9a | bellard | DEF(scasl_a32, 0)
|
| 474 | 0ea00c9a | bellard | DEF(repz_scasl_a32, 0)
|
| 475 | 0ea00c9a | bellard | DEF(repnz_scasl_a32, 0)
|
| 476 | 0ea00c9a | bellard | DEF(cmpsl_a32, 0)
|
| 477 | 0ea00c9a | bellard | DEF(repz_cmpsl_a32, 0)
|
| 478 | 0ea00c9a | bellard | DEF(repnz_cmpsl_a32, 0)
|
| 479 | 0ea00c9a | bellard | DEF(outsl_a32, 0)
|
| 480 | 0ea00c9a | bellard | DEF(rep_outsl_a32, 0)
|
| 481 | 0ea00c9a | bellard | DEF(insl_a32, 0)
|
| 482 | 0ea00c9a | bellard | DEF(rep_insl_a32, 0)
|
| 483 | 0ea00c9a | bellard | DEF(movsl_a16, 0)
|
| 484 | 0ea00c9a | bellard | DEF(rep_movsl_a16, 0)
|
| 485 | 0ea00c9a | bellard | DEF(stosl_a16, 0)
|
| 486 | 0ea00c9a | bellard | DEF(rep_stosl_a16, 0)
|
| 487 | 0ea00c9a | bellard | DEF(lodsl_a16, 0)
|
| 488 | 0ea00c9a | bellard | DEF(rep_lodsl_a16, 0)
|
| 489 | 0ea00c9a | bellard | DEF(scasl_a16, 0)
|
| 490 | 0ea00c9a | bellard | DEF(repz_scasl_a16, 0)
|
| 491 | 0ea00c9a | bellard | DEF(repnz_scasl_a16, 0)
|
| 492 | 0ea00c9a | bellard | DEF(cmpsl_a16, 0)
|
| 493 | 0ea00c9a | bellard | DEF(repz_cmpsl_a16, 0)
|
| 494 | 0ea00c9a | bellard | DEF(repnz_cmpsl_a16, 0)
|
| 495 | 0ea00c9a | bellard | DEF(outsl_a16, 0)
|
| 496 | 0ea00c9a | bellard | DEF(rep_outsl_a16, 0)
|
| 497 | 0ea00c9a | bellard | DEF(insl_a16, 0)
|
| 498 | 0ea00c9a | bellard | DEF(rep_insl_a16, 0)
|
| 499 | 0ea00c9a | bellard | DEF(outl_T0_T1, 0)
|
| 500 | 0ea00c9a | bellard | DEF(inl_T0_T1, 0)
|
| 501 | 0ea00c9a | bellard | DEF(movsbl_T0_T0, 0)
|
| 502 | 0ea00c9a | bellard | DEF(movzbl_T0_T0, 0)
|
| 503 | 0ea00c9a | bellard | DEF(movswl_T0_T0, 0)
|
| 504 | 0ea00c9a | bellard | DEF(movzwl_T0_T0, 0)
|
| 505 | 0ea00c9a | bellard | DEF(movswl_EAX_AX, 0)
|
| 506 | 0ea00c9a | bellard | DEF(movsbw_AX_AL, 0)
|
| 507 | 0ea00c9a | bellard | DEF(movslq_EDX_EAX, 0)
|
| 508 | 0ea00c9a | bellard | DEF(movswl_DX_AX, 0)
|
| 509 | 0ea00c9a | bellard | DEF(pushl_T0, 0)
|
| 510 | 0ea00c9a | bellard | DEF(pushw_T0, 0)
|
| 511 | 0ea00c9a | bellard | DEF(pushl_ss32_T0, 0)
|
| 512 | 0ea00c9a | bellard | DEF(pushw_ss32_T0, 0)
|
| 513 | 0ea00c9a | bellard | DEF(pushl_ss16_T0, 0)
|
| 514 | 0ea00c9a | bellard | DEF(pushw_ss16_T0, 0)
|
| 515 | 0ea00c9a | bellard | DEF(popl_T0, 0)
|
| 516 | 0ea00c9a | bellard | DEF(popw_T0, 0)
|
| 517 | 0ea00c9a | bellard | DEF(popl_ss32_T0, 0)
|
| 518 | 0ea00c9a | bellard | DEF(popw_ss32_T0, 0)
|
| 519 | 0ea00c9a | bellard | DEF(popl_ss16_T0, 0)
|
| 520 | 0ea00c9a | bellard | DEF(popw_ss16_T0, 0)
|
| 521 | 0ea00c9a | bellard | DEF(addl_ESP_4, 0)
|
| 522 | 0ea00c9a | bellard | DEF(addl_ESP_2, 0)
|
| 523 | 0ea00c9a | bellard | DEF(addw_ESP_4, 0)
|
| 524 | 0ea00c9a | bellard | DEF(addw_ESP_2, 0)
|
| 525 | 0ea00c9a | bellard | DEF(addl_ESP_im, 1)
|
| 526 | 0ea00c9a | bellard | DEF(addw_ESP_im, 1)
|
| 527 | 0ea00c9a | bellard | DEF(rdtsc, 0)
|
| 528 | 0ea00c9a | bellard | DEF(cpuid, 0)
|
| 529 | 0ea00c9a | bellard | DEF(aam, 1)
|
| 530 | 0ea00c9a | bellard | DEF(aad, 1)
|
| 531 | 0ea00c9a | bellard | DEF(aaa, 0)
|
| 532 | 0ea00c9a | bellard | DEF(aas, 0)
|
| 533 | 0ea00c9a | bellard | DEF(daa, 0)
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| 534 | 0ea00c9a | bellard | DEF(das, 0)
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| 535 | 0ea00c9a | bellard | DEF(movl_seg_T0, 1)
|
| 536 | 0ea00c9a | bellard | DEF(movl_T0_seg, 1)
|
| 537 | 0ea00c9a | bellard | DEF(movl_A0_seg, 1)
|
| 538 | 0ea00c9a | bellard | DEF(addl_A0_seg, 1)
|
| 539 | 0ea00c9a | bellard | DEF(jo_cc, 2)
|
| 540 | 0ea00c9a | bellard | DEF(jb_cc, 2)
|
| 541 | 0ea00c9a | bellard | DEF(jz_cc, 2)
|
| 542 | 0ea00c9a | bellard | DEF(jbe_cc, 2)
|
| 543 | 0ea00c9a | bellard | DEF(js_cc, 2)
|
| 544 | 0ea00c9a | bellard | DEF(jp_cc, 2)
|
| 545 | 0ea00c9a | bellard | DEF(jl_cc, 2)
|
| 546 | 0ea00c9a | bellard | DEF(jle_cc, 2)
|
| 547 | 0ea00c9a | bellard | DEF(seto_T0_cc, 0)
|
| 548 | 0ea00c9a | bellard | DEF(setb_T0_cc, 0)
|
| 549 | 0ea00c9a | bellard | DEF(setz_T0_cc, 0)
|
| 550 | 0ea00c9a | bellard | DEF(setbe_T0_cc, 0)
|
| 551 | 0ea00c9a | bellard | DEF(sets_T0_cc, 0)
|
| 552 | 0ea00c9a | bellard | DEF(setp_T0_cc, 0)
|
| 553 | 0ea00c9a | bellard | DEF(setl_T0_cc, 0)
|
| 554 | 0ea00c9a | bellard | DEF(setle_T0_cc, 0)
|
| 555 | 0ea00c9a | bellard | DEF(xor_T0_1, 0)
|
| 556 | 0ea00c9a | bellard | DEF(set_cc_op, 1)
|
| 557 | 0ea00c9a | bellard | DEF(movl_eflags_T0, 0)
|
| 558 | f631ef9b | bellard | DEF(movw_eflags_T0, 0)
|
| 559 | f631ef9b | bellard | DEF(movw_eflags_T0_vm, 1)
|
| 560 | f631ef9b | bellard | DEF(movl_eflags_T0_vm, 1)
|
| 561 | 0ea00c9a | bellard | DEF(movb_eflags_T0, 0)
|
| 562 | 0ea00c9a | bellard | DEF(movl_T0_eflags, 0)
|
| 563 | f631ef9b | bellard | DEF(movl_T0_eflags_vm, 0)
|
| 564 | 0ea00c9a | bellard | DEF(cld, 0)
|
| 565 | 0ea00c9a | bellard | DEF(std, 0)
|
| 566 | 0ea00c9a | bellard | DEF(clc, 0)
|
| 567 | 0ea00c9a | bellard | DEF(stc, 0)
|
| 568 | 0ea00c9a | bellard | DEF(cmc, 0)
|
| 569 | 0ea00c9a | bellard | DEF(salc, 0)
|
| 570 | 0ea00c9a | bellard | DEF(flds_FT0_A0, 0)
|
| 571 | 0ea00c9a | bellard | DEF(fldl_FT0_A0, 0)
|
| 572 | 0ea00c9a | bellard | DEF(fild_FT0_A0, 0)
|
| 573 | 0ea00c9a | bellard | DEF(fildl_FT0_A0, 0)
|
| 574 | 0ea00c9a | bellard | DEF(fildll_FT0_A0, 0)
|
| 575 | 0ea00c9a | bellard | DEF(flds_ST0_A0, 0)
|
| 576 | 0ea00c9a | bellard | DEF(fldl_ST0_A0, 0)
|
| 577 | 0ea00c9a | bellard | DEF(fldt_ST0_A0, 0)
|
| 578 | 0ea00c9a | bellard | DEF(fild_ST0_A0, 0)
|
| 579 | 0ea00c9a | bellard | DEF(fildl_ST0_A0, 0)
|
| 580 | 0ea00c9a | bellard | DEF(fildll_ST0_A0, 0)
|
| 581 | 0ea00c9a | bellard | DEF(fsts_ST0_A0, 0)
|
| 582 | 0ea00c9a | bellard | DEF(fstl_ST0_A0, 0)
|
| 583 | 0ea00c9a | bellard | DEF(fstt_ST0_A0, 0)
|
| 584 | 0ea00c9a | bellard | DEF(fist_ST0_A0, 0)
|
| 585 | 0ea00c9a | bellard | DEF(fistl_ST0_A0, 0)
|
| 586 | 0ea00c9a | bellard | DEF(fistll_ST0_A0, 0)
|
| 587 | 0ea00c9a | bellard | DEF(fbld_ST0_A0, 0)
|
| 588 | 0ea00c9a | bellard | DEF(fbst_ST0_A0, 0)
|
| 589 | 0ea00c9a | bellard | DEF(fpush, 0)
|
| 590 | 0ea00c9a | bellard | DEF(fpop, 0)
|
| 591 | 0ea00c9a | bellard | DEF(fdecstp, 0)
|
| 592 | 0ea00c9a | bellard | DEF(fincstp, 0)
|
| 593 | 0ea00c9a | bellard | DEF(fmov_ST0_FT0, 0)
|
| 594 | 0ea00c9a | bellard | DEF(fmov_FT0_STN, 1)
|
| 595 | 0ea00c9a | bellard | DEF(fmov_ST0_STN, 1)
|
| 596 | 0ea00c9a | bellard | DEF(fmov_STN_ST0, 1)
|
| 597 | 0ea00c9a | bellard | DEF(fxchg_ST0_STN, 1)
|
| 598 | 0ea00c9a | bellard | DEF(fcom_ST0_FT0, 0)
|
| 599 | 0ea00c9a | bellard | DEF(fucom_ST0_FT0, 0)
|
| 600 | 0ea00c9a | bellard | DEF(fadd_ST0_FT0, 0)
|
| 601 | 0ea00c9a | bellard | DEF(fmul_ST0_FT0, 0)
|
| 602 | 0ea00c9a | bellard | DEF(fsub_ST0_FT0, 0)
|
| 603 | 0ea00c9a | bellard | DEF(fsubr_ST0_FT0, 0)
|
| 604 | 0ea00c9a | bellard | DEF(fdiv_ST0_FT0, 0)
|
| 605 | 0ea00c9a | bellard | DEF(fdivr_ST0_FT0, 0)
|
| 606 | 0ea00c9a | bellard | DEF(fadd_STN_ST0, 1)
|
| 607 | 0ea00c9a | bellard | DEF(fmul_STN_ST0, 1)
|
| 608 | 0ea00c9a | bellard | DEF(fsub_STN_ST0, 1)
|
| 609 | 0ea00c9a | bellard | DEF(fsubr_STN_ST0, 1)
|
| 610 | 0ea00c9a | bellard | DEF(fdiv_STN_ST0, 1)
|
| 611 | 0ea00c9a | bellard | DEF(fdivr_STN_ST0, 1)
|
| 612 | 0ea00c9a | bellard | DEF(fchs_ST0, 0)
|
| 613 | 0ea00c9a | bellard | DEF(fabs_ST0, 0)
|
| 614 | 0ea00c9a | bellard | DEF(fxam_ST0, 0)
|
| 615 | 0ea00c9a | bellard | DEF(fld1_ST0, 0)
|
| 616 | 0ea00c9a | bellard | DEF(fldl2t_ST0, 0)
|
| 617 | 0ea00c9a | bellard | DEF(fldl2e_ST0, 0)
|
| 618 | 0ea00c9a | bellard | DEF(fldpi_ST0, 0)
|
| 619 | 0ea00c9a | bellard | DEF(fldlg2_ST0, 0)
|
| 620 | 0ea00c9a | bellard | DEF(fldln2_ST0, 0)
|
| 621 | 0ea00c9a | bellard | DEF(fldz_ST0, 0)
|
| 622 | 0ea00c9a | bellard | DEF(fldz_FT0, 0)
|
| 623 | 0ea00c9a | bellard | DEF(f2xm1, 0)
|
| 624 | 0ea00c9a | bellard | DEF(fyl2x, 0)
|
| 625 | 0ea00c9a | bellard | DEF(fptan, 0)
|
| 626 | 0ea00c9a | bellard | DEF(fpatan, 0)
|
| 627 | 0ea00c9a | bellard | DEF(fxtract, 0)
|
| 628 | 0ea00c9a | bellard | DEF(fprem1, 0)
|
| 629 | 0ea00c9a | bellard | DEF(fprem, 0)
|
| 630 | 0ea00c9a | bellard | DEF(fyl2xp1, 0)
|
| 631 | 0ea00c9a | bellard | DEF(fsqrt, 0)
|
| 632 | 0ea00c9a | bellard | DEF(fsincos, 0)
|
| 633 | 0ea00c9a | bellard | DEF(frndint, 0)
|
| 634 | 0ea00c9a | bellard | DEF(fscale, 0)
|
| 635 | 0ea00c9a | bellard | DEF(fsin, 0)
|
| 636 | 0ea00c9a | bellard | DEF(fcos, 0)
|
| 637 | 0ea00c9a | bellard | DEF(fnstsw_A0, 0)
|
| 638 | 0ea00c9a | bellard | DEF(fnstsw_EAX, 0)
|
| 639 | 0ea00c9a | bellard | DEF(fnstcw_A0, 0)
|
| 640 | 0ea00c9a | bellard | DEF(fldcw_A0, 0)
|
| 641 | 0ea00c9a | bellard | DEF(fclex, 0)
|
| 642 | 0ea00c9a | bellard | DEF(fninit, 0)
|
| 643 | 0ea00c9a | bellard | DEF(lock, 0)
|
| 644 | 0ea00c9a | bellard | DEF(unlock, 0) |