root / hw / milkymist-hpdmc.c @ ae60fea9
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1 | e4dc6d2c | Michael Walle | /*
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2 | e4dc6d2c | Michael Walle | * QEMU model of the Milkymist High Performance Dynamic Memory Controller.
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3 | e4dc6d2c | Michael Walle | *
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4 | e4dc6d2c | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | e4dc6d2c | Michael Walle | *
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6 | e4dc6d2c | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | e4dc6d2c | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | e4dc6d2c | Michael Walle | * License as published by the Free Software Foundation; either
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9 | e4dc6d2c | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | e4dc6d2c | Michael Walle | *
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11 | e4dc6d2c | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | e4dc6d2c | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e4dc6d2c | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e4dc6d2c | Michael Walle | * Lesser General Public License for more details.
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15 | e4dc6d2c | Michael Walle | *
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16 | e4dc6d2c | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | e4dc6d2c | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | e4dc6d2c | Michael Walle | *
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19 | e4dc6d2c | Michael Walle | *
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20 | e4dc6d2c | Michael Walle | * Specification available at:
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21 | e4dc6d2c | Michael Walle | * http://www.milkymist.org/socdoc/hpdmc.pdf
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22 | e4dc6d2c | Michael Walle | */
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23 | e4dc6d2c | Michael Walle | |
24 | e4dc6d2c | Michael Walle | #include "hw.h" |
25 | e4dc6d2c | Michael Walle | #include "sysbus.h" |
26 | e4dc6d2c | Michael Walle | #include "trace.h" |
27 | e4dc6d2c | Michael Walle | #include "qemu-error.h" |
28 | e4dc6d2c | Michael Walle | |
29 | e4dc6d2c | Michael Walle | enum {
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30 | e4dc6d2c | Michael Walle | R_SYSTEM = 0,
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31 | e4dc6d2c | Michael Walle | R_BYPASS, |
32 | e4dc6d2c | Michael Walle | R_TIMING, |
33 | e4dc6d2c | Michael Walle | R_IODELAY, |
34 | e4dc6d2c | Michael Walle | R_MAX |
35 | e4dc6d2c | Michael Walle | }; |
36 | e4dc6d2c | Michael Walle | |
37 | e4dc6d2c | Michael Walle | enum {
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38 | e4dc6d2c | Michael Walle | IODELAY_DQSDELAY_RDY = (1<<5), |
39 | e4dc6d2c | Michael Walle | IODELAY_PLL1_LOCKED = (1<<6), |
40 | e4dc6d2c | Michael Walle | IODELAY_PLL2_LOCKED = (1<<7), |
41 | e4dc6d2c | Michael Walle | }; |
42 | e4dc6d2c | Michael Walle | |
43 | e4dc6d2c | Michael Walle | struct MilkymistHpdmcState {
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44 | e4dc6d2c | Michael Walle | SysBusDevice busdev; |
45 | e4dc6d2c | Michael Walle | |
46 | e4dc6d2c | Michael Walle | uint32_t regs[R_MAX]; |
47 | e4dc6d2c | Michael Walle | }; |
48 | e4dc6d2c | Michael Walle | typedef struct MilkymistHpdmcState MilkymistHpdmcState; |
49 | e4dc6d2c | Michael Walle | |
50 | e4dc6d2c | Michael Walle | static uint32_t hpdmc_read(void *opaque, target_phys_addr_t addr) |
51 | e4dc6d2c | Michael Walle | { |
52 | e4dc6d2c | Michael Walle | MilkymistHpdmcState *s = opaque; |
53 | e4dc6d2c | Michael Walle | uint32_t r = 0;
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54 | e4dc6d2c | Michael Walle | |
55 | e4dc6d2c | Michael Walle | addr >>= 2;
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56 | e4dc6d2c | Michael Walle | switch (addr) {
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57 | e4dc6d2c | Michael Walle | case R_SYSTEM:
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58 | e4dc6d2c | Michael Walle | case R_BYPASS:
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59 | e4dc6d2c | Michael Walle | case R_TIMING:
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60 | e4dc6d2c | Michael Walle | case R_IODELAY:
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61 | e4dc6d2c | Michael Walle | r = s->regs[addr]; |
62 | e4dc6d2c | Michael Walle | break;
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63 | e4dc6d2c | Michael Walle | |
64 | e4dc6d2c | Michael Walle | default:
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65 | e4dc6d2c | Michael Walle | error_report("milkymist_hpdmc: read access to unknown register 0x"
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66 | e4dc6d2c | Michael Walle | TARGET_FMT_plx, addr << 2);
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67 | e4dc6d2c | Michael Walle | break;
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68 | e4dc6d2c | Michael Walle | } |
69 | e4dc6d2c | Michael Walle | |
70 | e4dc6d2c | Michael Walle | trace_milkymist_hpdmc_memory_read(addr << 2, r);
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71 | e4dc6d2c | Michael Walle | |
72 | e4dc6d2c | Michael Walle | return r;
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73 | e4dc6d2c | Michael Walle | } |
74 | e4dc6d2c | Michael Walle | |
75 | e4dc6d2c | Michael Walle | static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
76 | e4dc6d2c | Michael Walle | { |
77 | e4dc6d2c | Michael Walle | MilkymistHpdmcState *s = opaque; |
78 | e4dc6d2c | Michael Walle | |
79 | e4dc6d2c | Michael Walle | trace_milkymist_hpdmc_memory_write(addr, value); |
80 | e4dc6d2c | Michael Walle | |
81 | e4dc6d2c | Michael Walle | addr >>= 2;
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82 | e4dc6d2c | Michael Walle | switch (addr) {
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83 | e4dc6d2c | Michael Walle | case R_SYSTEM:
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84 | e4dc6d2c | Michael Walle | case R_BYPASS:
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85 | e4dc6d2c | Michael Walle | case R_TIMING:
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86 | e4dc6d2c | Michael Walle | s->regs[addr] = value; |
87 | e4dc6d2c | Michael Walle | break;
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88 | e4dc6d2c | Michael Walle | case R_IODELAY:
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89 | e4dc6d2c | Michael Walle | /* ignore writes */
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90 | e4dc6d2c | Michael Walle | break;
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91 | e4dc6d2c | Michael Walle | |
92 | e4dc6d2c | Michael Walle | default:
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93 | e4dc6d2c | Michael Walle | error_report("milkymist_hpdmc: write access to unknown register 0x"
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94 | e4dc6d2c | Michael Walle | TARGET_FMT_plx, addr << 2);
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95 | e4dc6d2c | Michael Walle | break;
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96 | e4dc6d2c | Michael Walle | } |
97 | e4dc6d2c | Michael Walle | } |
98 | e4dc6d2c | Michael Walle | |
99 | e4dc6d2c | Michael Walle | static CPUReadMemoryFunc * const hpdmc_read_fn[] = { |
100 | e4dc6d2c | Michael Walle | NULL,
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101 | e4dc6d2c | Michael Walle | NULL,
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102 | e4dc6d2c | Michael Walle | &hpdmc_read, |
103 | e4dc6d2c | Michael Walle | }; |
104 | e4dc6d2c | Michael Walle | |
105 | e4dc6d2c | Michael Walle | static CPUWriteMemoryFunc * const hpdmc_write_fn[] = { |
106 | e4dc6d2c | Michael Walle | NULL,
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107 | e4dc6d2c | Michael Walle | NULL,
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108 | e4dc6d2c | Michael Walle | &hpdmc_write, |
109 | e4dc6d2c | Michael Walle | }; |
110 | e4dc6d2c | Michael Walle | |
111 | e4dc6d2c | Michael Walle | static void milkymist_hpdmc_reset(DeviceState *d) |
112 | e4dc6d2c | Michael Walle | { |
113 | e4dc6d2c | Michael Walle | MilkymistHpdmcState *s = container_of(d, MilkymistHpdmcState, busdev.qdev); |
114 | e4dc6d2c | Michael Walle | int i;
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115 | e4dc6d2c | Michael Walle | |
116 | e4dc6d2c | Michael Walle | for (i = 0; i < R_MAX; i++) { |
117 | e4dc6d2c | Michael Walle | s->regs[i] = 0;
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118 | e4dc6d2c | Michael Walle | } |
119 | e4dc6d2c | Michael Walle | |
120 | e4dc6d2c | Michael Walle | /* defaults */
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121 | e4dc6d2c | Michael Walle | s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED |
122 | e4dc6d2c | Michael Walle | | IODELAY_PLL2_LOCKED; |
123 | e4dc6d2c | Michael Walle | } |
124 | e4dc6d2c | Michael Walle | |
125 | e4dc6d2c | Michael Walle | static int milkymist_hpdmc_init(SysBusDevice *dev) |
126 | e4dc6d2c | Michael Walle | { |
127 | e4dc6d2c | Michael Walle | MilkymistHpdmcState *s = FROM_SYSBUS(typeof(*s), dev); |
128 | e4dc6d2c | Michael Walle | int hpdmc_regs;
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129 | e4dc6d2c | Michael Walle | |
130 | e4dc6d2c | Michael Walle | hpdmc_regs = cpu_register_io_memory(hpdmc_read_fn, hpdmc_write_fn, s, |
131 | e4dc6d2c | Michael Walle | DEVICE_NATIVE_ENDIAN); |
132 | e4dc6d2c | Michael Walle | sysbus_init_mmio(dev, R_MAX * 4, hpdmc_regs);
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133 | e4dc6d2c | Michael Walle | |
134 | e4dc6d2c | Michael Walle | return 0; |
135 | e4dc6d2c | Michael Walle | } |
136 | e4dc6d2c | Michael Walle | |
137 | e4dc6d2c | Michael Walle | static const VMStateDescription vmstate_milkymist_hpdmc = { |
138 | e4dc6d2c | Michael Walle | .name = "milkymist-hpdmc",
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139 | e4dc6d2c | Michael Walle | .version_id = 1,
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140 | e4dc6d2c | Michael Walle | .minimum_version_id = 1,
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141 | e4dc6d2c | Michael Walle | .minimum_version_id_old = 1,
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142 | e4dc6d2c | Michael Walle | .fields = (VMStateField[]) { |
143 | e4dc6d2c | Michael Walle | VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX), |
144 | e4dc6d2c | Michael Walle | VMSTATE_END_OF_LIST() |
145 | e4dc6d2c | Michael Walle | } |
146 | e4dc6d2c | Michael Walle | }; |
147 | e4dc6d2c | Michael Walle | |
148 | e4dc6d2c | Michael Walle | static SysBusDeviceInfo milkymist_hpdmc_info = {
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149 | e4dc6d2c | Michael Walle | .init = milkymist_hpdmc_init, |
150 | e4dc6d2c | Michael Walle | .qdev.name = "milkymist-hpdmc",
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151 | e4dc6d2c | Michael Walle | .qdev.size = sizeof(MilkymistHpdmcState),
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152 | e4dc6d2c | Michael Walle | .qdev.vmsd = &vmstate_milkymist_hpdmc, |
153 | e4dc6d2c | Michael Walle | .qdev.reset = milkymist_hpdmc_reset, |
154 | e4dc6d2c | Michael Walle | }; |
155 | e4dc6d2c | Michael Walle | |
156 | e4dc6d2c | Michael Walle | static void milkymist_hpdmc_register(void) |
157 | e4dc6d2c | Michael Walle | { |
158 | e4dc6d2c | Michael Walle | sysbus_register_withprop(&milkymist_hpdmc_info); |
159 | e4dc6d2c | Michael Walle | } |
160 | e4dc6d2c | Michael Walle | |
161 | e4dc6d2c | Michael Walle | device_init(milkymist_hpdmc_register) |