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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "apic_internal.h" |
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#include "apic.h" |
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#include "ioapic.h" |
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#include "msi.h" |
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#include "host-utils.h" |
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#include "trace.h" |
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#include "pc.h" |
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|
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#define MAX_APIC_WORDS 8 |
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/* Intel APIC constants: from include/asm/msidef.h */
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#define MSI_DATA_VECTOR_SHIFT 0 |
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#define MSI_DATA_VECTOR_MASK 0x000000ff |
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
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#define MSI_DATA_TRIGGER_SHIFT 15 |
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#define MSI_DATA_LEVEL_SHIFT 14 |
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#define MSI_ADDR_DEST_MODE_SHIFT 2 |
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#define MSI_ADDR_DEST_ID_SHIFT 12 |
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
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|
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#define SYNC_FROM_VAPIC 0x1 |
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#define SYNC_TO_VAPIC 0x2 |
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#define SYNC_ISR_IRR_TO_VAPIC 0x4 |
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|
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static APICCommonState *local_apics[MAX_APICS + 1]; |
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|
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
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static void apic_update_irq(APICCommonState *s); |
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
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uint8_t dest, uint8_t dest_mode); |
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|
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value) |
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{
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return 31 - clz32(value); |
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} |
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|
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value) |
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{
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return ctz32(value);
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} |
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|
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static inline void set_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] |= mask; |
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} |
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static inline void reset_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] &= ~mask; |
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} |
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static inline int get_bit(uint32_t *tab, int index) |
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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return !!(tab[i] & mask);
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} |
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|
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab) |
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{
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int i;
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for (i = 7; i >= 0; i--) { |
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if (tab[i] != 0) { |
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return i * 32 + fls_bit(tab[i]); |
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} |
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} |
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return -1; |
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} |
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|
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static void apic_sync_vapic(APICCommonState *s, int sync_type) |
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{
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VAPICState vapic_state; |
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size_t length; |
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off_t start; |
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int vector;
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|
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if (!s->vapic_paddr) {
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return;
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} |
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if (sync_type & SYNC_FROM_VAPIC) {
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cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state,
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sizeof(vapic_state), 0); |
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s->tpr = vapic_state.tpr; |
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} |
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if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
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start = offsetof(VAPICState, isr); |
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length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); |
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if (sync_type & SYNC_TO_VAPIC) {
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assert(qemu_cpu_is_self(s->cpu_env)); |
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vapic_state.tpr = s->tpr; |
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vapic_state.enabled = 1;
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start = 0;
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length = sizeof(VAPICState);
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} |
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vector = get_highest_priority_int(s->isr); |
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if (vector < 0) { |
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vector = 0;
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} |
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vapic_state.isr = vector & 0xf0;
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vapic_state.zero = 0;
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vector = get_highest_priority_int(s->irr); |
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if (vector < 0) { |
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vector = 0;
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} |
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vapic_state.irr = vector & 0xff;
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cpu_physical_memory_write_rom(s->vapic_paddr + start, |
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((void *)&vapic_state) + start, length);
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} |
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} |
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static void apic_vapic_base_update(APICCommonState *s) |
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{
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apic_sync_vapic(s, SYNC_TO_VAPIC); |
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} |
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static void apic_local_deliver(APICCommonState *s, int vector) |
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{
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uint32_t lvt = s->lvt[vector]; |
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int trigger_mode;
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trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_SMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
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break;
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|
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case APIC_DM_NMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
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break;
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|
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case APIC_DM_EXTINT:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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|
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE; |
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER)) |
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trigger_mode = APIC_TRIGGER_LEVEL; |
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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} |
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} |
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|
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void apic_deliver_pic_intr(DeviceState *d, int level) |
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0); |
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} |
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|
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static void apic_external_nmi(APICCommonState *s) |
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{
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apic_local_deliver(s, APIC_LVT_LINT1); |
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} |
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
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__mask = deliver_bitmask[__i];\ |
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\ |
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if (__mask & (1 << __j)) {\ |
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\ |
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}\ |
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}\ |
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}\ |
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}\ |
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}\ |
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} |
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|
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
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uint8_t delivery_mode, uint8_t vector_num, |
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uint8_t trigger_mode) |
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{
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APICCommonState *apic_iter; |
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|
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) { |
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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} |
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} |
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if (d >= 0) { |
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apic_iter = local_apics[d]; |
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode); |
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} |
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} |
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} |
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return;
|
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|
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case APIC_DM_FIXED:
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break;
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|
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case APIC_DM_SMI:
|
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
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return;
|
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|
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case APIC_DM_NMI:
|
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
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return;
|
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|
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case APIC_DM_INIT:
|
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
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return;
|
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|
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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|
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default:
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return;
|
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} |
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|
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
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} |
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|
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
|
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uint8_t vector_num, uint8_t trigger_mode) |
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{
|
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uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
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|
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
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trigger_mode); |
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|
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
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} |
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|
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static void apic_set_base(APICCommonState *s, uint64_t val) |
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{
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s->apicbase = (val & 0xfffff000) |
|
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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cpu_clear_apic_feature(s->cpu_env); |
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s->spurious_vec &= ~APIC_SV_ENABLE; |
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} |
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} |
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|
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static void apic_set_tpr(APICCommonState *s, uint8_t val) |
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{
|
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/* Updates from cr8 are ignored while the VAPIC is active */
|
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if (!s->vapic_paddr) {
|
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s->tpr = val << 4;
|
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apic_update_irq(s); |
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} |
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} |
| 317 |
|
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static uint8_t apic_get_tpr(APICCommonState *s)
|
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{
|
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apic_sync_vapic(s, SYNC_FROM_VAPIC); |
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return s->tpr >> 4; |
| 322 |
} |
| 323 |
|
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static int apic_get_ppr(APICCommonState *s) |
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{
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int tpr, isrv, ppr;
|
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|
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tpr = (s->tpr >> 4);
|
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isrv = get_highest_priority_int(s->isr); |
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if (isrv < 0) |
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isrv = 0;
|
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isrv >>= 4;
|
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if (tpr >= isrv)
|
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ppr = s->tpr; |
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else
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ppr = isrv << 4;
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return ppr;
|
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} |
| 339 |
|
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static int apic_get_arb_pri(APICCommonState *s) |
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{
|
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/* XXX: arbitration */
|
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return 0; |
| 344 |
} |
| 345 |
|
| 346 |
|
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/*
|
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* <0 - low prio interrupt,
|
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* 0 - no interrupt,
|
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* >0 - interrupt number
|
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*/
|
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static int apic_irq_pending(APICCommonState *s) |
| 353 |
{
|
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int irrv, ppr;
|
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irrv = get_highest_priority_int(s->irr); |
| 356 |
if (irrv < 0) { |
| 357 |
return 0; |
| 358 |
} |
| 359 |
ppr = apic_get_ppr(s); |
| 360 |
if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
| 361 |
return -1; |
| 362 |
} |
| 363 |
|
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return irrv;
|
| 365 |
} |
| 366 |
|
| 367 |
/* signal the CPU if an irq is pending */
|
| 368 |
static void apic_update_irq(APICCommonState *s) |
| 369 |
{
|
| 370 |
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
|
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return;
|
| 372 |
} |
| 373 |
if (apic_irq_pending(s) > 0) { |
| 374 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
| 375 |
} else if (apic_accept_pic_intr(&s->busdev.qdev) && |
| 376 |
pic_get_output(isa_pic)) {
|
| 377 |
apic_deliver_pic_intr(&s->busdev.qdev, 1);
|
| 378 |
} |
| 379 |
} |
| 380 |
|
| 381 |
void apic_poll_irq(DeviceState *d)
|
| 382 |
{
|
| 383 |
APICCommonState *s = APIC_COMMON(d); |
| 384 |
|
| 385 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 386 |
apic_update_irq(s); |
| 387 |
} |
| 388 |
|
| 389 |
static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
| 390 |
{
|
| 391 |
apic_report_irq_delivered(!get_bit(s->irr, vector_num)); |
| 392 |
|
| 393 |
set_bit(s->irr, vector_num); |
| 394 |
if (trigger_mode)
|
| 395 |
set_bit(s->tmr, vector_num); |
| 396 |
else
|
| 397 |
reset_bit(s->tmr, vector_num); |
| 398 |
if (s->vapic_paddr) {
|
| 399 |
apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); |
| 400 |
/*
|
| 401 |
* The vcpu thread needs to see the new IRR before we pull its current
|
| 402 |
* TPR value. That way, if we miss a lowering of the TRP, the guest
|
| 403 |
* has the chance to notice the new IRR and poll for IRQs on its own.
|
| 404 |
*/
|
| 405 |
smp_wmb(); |
| 406 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 407 |
} |
| 408 |
apic_update_irq(s); |
| 409 |
} |
| 410 |
|
| 411 |
static void apic_eoi(APICCommonState *s) |
| 412 |
{
|
| 413 |
int isrv;
|
| 414 |
isrv = get_highest_priority_int(s->isr); |
| 415 |
if (isrv < 0) |
| 416 |
return;
|
| 417 |
reset_bit(s->isr, isrv); |
| 418 |
if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
|
| 419 |
ioapic_eoi_broadcast(isrv); |
| 420 |
} |
| 421 |
apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
| 422 |
apic_update_irq(s); |
| 423 |
} |
| 424 |
|
| 425 |
static int apic_find_dest(uint8_t dest) |
| 426 |
{
|
| 427 |
APICCommonState *apic = local_apics[dest]; |
| 428 |
int i;
|
| 429 |
|
| 430 |
if (apic && apic->id == dest)
|
| 431 |
return dest; /* shortcut in case apic->id == apic->idx */ |
| 432 |
|
| 433 |
for (i = 0; i < MAX_APICS; i++) { |
| 434 |
apic = local_apics[i]; |
| 435 |
if (apic && apic->id == dest)
|
| 436 |
return i;
|
| 437 |
if (!apic)
|
| 438 |
break;
|
| 439 |
} |
| 440 |
|
| 441 |
return -1; |
| 442 |
} |
| 443 |
|
| 444 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
| 445 |
uint8_t dest, uint8_t dest_mode) |
| 446 |
{
|
| 447 |
APICCommonState *apic_iter; |
| 448 |
int i;
|
| 449 |
|
| 450 |
if (dest_mode == 0) { |
| 451 |
if (dest == 0xff) { |
| 452 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 453 |
} else {
|
| 454 |
int idx = apic_find_dest(dest);
|
| 455 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 456 |
if (idx >= 0) |
| 457 |
set_bit(deliver_bitmask, idx); |
| 458 |
} |
| 459 |
} else {
|
| 460 |
/* XXX: cluster mode */
|
| 461 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
| 462 |
for(i = 0; i < MAX_APICS; i++) { |
| 463 |
apic_iter = local_apics[i]; |
| 464 |
if (apic_iter) {
|
| 465 |
if (apic_iter->dest_mode == 0xf) { |
| 466 |
if (dest & apic_iter->log_dest)
|
| 467 |
set_bit(deliver_bitmask, i); |
| 468 |
} else if (apic_iter->dest_mode == 0x0) { |
| 469 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
| 470 |
(dest & apic_iter->log_dest & 0x0f)) {
|
| 471 |
set_bit(deliver_bitmask, i); |
| 472 |
} |
| 473 |
} |
| 474 |
} else {
|
| 475 |
break;
|
| 476 |
} |
| 477 |
} |
| 478 |
} |
| 479 |
} |
| 480 |
|
| 481 |
static void apic_startup(APICCommonState *s, int vector_num) |
| 482 |
{
|
| 483 |
s->sipi_vector = vector_num; |
| 484 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
| 485 |
} |
| 486 |
|
| 487 |
void apic_sipi(DeviceState *d)
|
| 488 |
{
|
| 489 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 490 |
|
| 491 |
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
| 492 |
|
| 493 |
if (!s->wait_for_sipi)
|
| 494 |
return;
|
| 495 |
cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
| 496 |
s->wait_for_sipi = 0;
|
| 497 |
} |
| 498 |
|
| 499 |
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
| 500 |
uint8_t delivery_mode, uint8_t vector_num, |
| 501 |
uint8_t trigger_mode) |
| 502 |
{
|
| 503 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 504 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
| 505 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
| 506 |
APICCommonState *apic_iter; |
| 507 |
|
| 508 |
switch (dest_shorthand) {
|
| 509 |
case 0: |
| 510 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
| 511 |
break;
|
| 512 |
case 1: |
| 513 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
| 514 |
set_bit(deliver_bitmask, s->idx); |
| 515 |
break;
|
| 516 |
case 2: |
| 517 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 518 |
break;
|
| 519 |
case 3: |
| 520 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
| 521 |
reset_bit(deliver_bitmask, s->idx); |
| 522 |
break;
|
| 523 |
} |
| 524 |
|
| 525 |
switch (delivery_mode) {
|
| 526 |
case APIC_DM_INIT:
|
| 527 |
{
|
| 528 |
int trig_mode = (s->icr[0] >> 15) & 1; |
| 529 |
int level = (s->icr[0] >> 14) & 1; |
| 530 |
if (level == 0 && trig_mode == 1) { |
| 531 |
foreach_apic(apic_iter, deliver_bitmask, |
| 532 |
apic_iter->arb_id = apic_iter->id ); |
| 533 |
return;
|
| 534 |
} |
| 535 |
} |
| 536 |
break;
|
| 537 |
|
| 538 |
case APIC_DM_SIPI:
|
| 539 |
foreach_apic(apic_iter, deliver_bitmask, |
| 540 |
apic_startup(apic_iter, vector_num) ); |
| 541 |
return;
|
| 542 |
} |
| 543 |
|
| 544 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
| 545 |
} |
| 546 |
|
| 547 |
int apic_get_interrupt(DeviceState *d)
|
| 548 |
{
|
| 549 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 550 |
int intno;
|
| 551 |
|
| 552 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
| 553 |
IRQs */
|
| 554 |
if (!s)
|
| 555 |
return -1; |
| 556 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
| 557 |
return -1; |
| 558 |
|
| 559 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 560 |
intno = apic_irq_pending(s); |
| 561 |
|
| 562 |
if (intno == 0) { |
| 563 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 564 |
return -1; |
| 565 |
} else if (intno < 0) { |
| 566 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 567 |
return s->spurious_vec & 0xff; |
| 568 |
} |
| 569 |
reset_bit(s->irr, intno); |
| 570 |
set_bit(s->isr, intno); |
| 571 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 572 |
apic_update_irq(s); |
| 573 |
return intno;
|
| 574 |
} |
| 575 |
|
| 576 |
int apic_accept_pic_intr(DeviceState *d)
|
| 577 |
{
|
| 578 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 579 |
uint32_t lvt0; |
| 580 |
|
| 581 |
if (!s)
|
| 582 |
return -1; |
| 583 |
|
| 584 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
| 585 |
|
| 586 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
| 587 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
| 588 |
return 1; |
| 589 |
|
| 590 |
return 0; |
| 591 |
} |
| 592 |
|
| 593 |
static uint32_t apic_get_current_count(APICCommonState *s)
|
| 594 |
{
|
| 595 |
int64_t d; |
| 596 |
uint32_t val; |
| 597 |
d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
| 598 |
s->count_shift; |
| 599 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
| 600 |
/* periodic */
|
| 601 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
| 602 |
} else {
|
| 603 |
if (d >= s->initial_count)
|
| 604 |
val = 0;
|
| 605 |
else
|
| 606 |
val = s->initial_count - d; |
| 607 |
} |
| 608 |
return val;
|
| 609 |
} |
| 610 |
|
| 611 |
static void apic_timer_update(APICCommonState *s, int64_t current_time) |
| 612 |
{
|
| 613 |
if (apic_next_timer(s, current_time)) {
|
| 614 |
qemu_mod_timer(s->timer, s->next_time); |
| 615 |
} else {
|
| 616 |
qemu_del_timer(s->timer); |
| 617 |
} |
| 618 |
} |
| 619 |
|
| 620 |
static void apic_timer(void *opaque) |
| 621 |
{
|
| 622 |
APICCommonState *s = opaque; |
| 623 |
|
| 624 |
apic_local_deliver(s, APIC_LVT_TIMER); |
| 625 |
apic_timer_update(s, s->next_time); |
| 626 |
} |
| 627 |
|
| 628 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
| 629 |
{
|
| 630 |
return 0; |
| 631 |
} |
| 632 |
|
| 633 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
| 634 |
{
|
| 635 |
return 0; |
| 636 |
} |
| 637 |
|
| 638 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 639 |
{
|
| 640 |
} |
| 641 |
|
| 642 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 643 |
{
|
| 644 |
} |
| 645 |
|
| 646 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
| 647 |
{
|
| 648 |
DeviceState *d; |
| 649 |
APICCommonState *s; |
| 650 |
uint32_t val; |
| 651 |
int index;
|
| 652 |
|
| 653 |
d = cpu_get_current_apic(); |
| 654 |
if (!d) {
|
| 655 |
return 0; |
| 656 |
} |
| 657 |
s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 658 |
|
| 659 |
index = (addr >> 4) & 0xff; |
| 660 |
switch(index) {
|
| 661 |
case 0x02: /* id */ |
| 662 |
val = s->id << 24;
|
| 663 |
break;
|
| 664 |
case 0x03: /* version */ |
| 665 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
| 666 |
break;
|
| 667 |
case 0x08: |
| 668 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 669 |
if (apic_report_tpr_access) {
|
| 670 |
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); |
| 671 |
} |
| 672 |
val = s->tpr; |
| 673 |
break;
|
| 674 |
case 0x09: |
| 675 |
val = apic_get_arb_pri(s); |
| 676 |
break;
|
| 677 |
case 0x0a: |
| 678 |
/* ppr */
|
| 679 |
val = apic_get_ppr(s); |
| 680 |
break;
|
| 681 |
case 0x0b: |
| 682 |
val = 0;
|
| 683 |
break;
|
| 684 |
case 0x0d: |
| 685 |
val = s->log_dest << 24;
|
| 686 |
break;
|
| 687 |
case 0x0e: |
| 688 |
val = s->dest_mode << 28;
|
| 689 |
break;
|
| 690 |
case 0x0f: |
| 691 |
val = s->spurious_vec; |
| 692 |
break;
|
| 693 |
case 0x10 ... 0x17: |
| 694 |
val = s->isr[index & 7];
|
| 695 |
break;
|
| 696 |
case 0x18 ... 0x1f: |
| 697 |
val = s->tmr[index & 7];
|
| 698 |
break;
|
| 699 |
case 0x20 ... 0x27: |
| 700 |
val = s->irr[index & 7];
|
| 701 |
break;
|
| 702 |
case 0x28: |
| 703 |
val = s->esr; |
| 704 |
break;
|
| 705 |
case 0x30: |
| 706 |
case 0x31: |
| 707 |
val = s->icr[index & 1];
|
| 708 |
break;
|
| 709 |
case 0x32 ... 0x37: |
| 710 |
val = s->lvt[index - 0x32];
|
| 711 |
break;
|
| 712 |
case 0x38: |
| 713 |
val = s->initial_count; |
| 714 |
break;
|
| 715 |
case 0x39: |
| 716 |
val = apic_get_current_count(s); |
| 717 |
break;
|
| 718 |
case 0x3e: |
| 719 |
val = s->divide_conf; |
| 720 |
break;
|
| 721 |
default:
|
| 722 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 723 |
val = 0;
|
| 724 |
break;
|
| 725 |
} |
| 726 |
trace_apic_mem_readl(addr, val); |
| 727 |
return val;
|
| 728 |
} |
| 729 |
|
| 730 |
static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
| 731 |
{
|
| 732 |
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
| 733 |
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
| 734 |
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
| 735 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
| 736 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
| 737 |
/* XXX: Ignore redirection hint. */
|
| 738 |
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
| 739 |
} |
| 740 |
|
| 741 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 742 |
{
|
| 743 |
DeviceState *d; |
| 744 |
APICCommonState *s; |
| 745 |
int index = (addr >> 4) & 0xff; |
| 746 |
if (addr > 0xfff || !index) { |
| 747 |
/* MSI and MMIO APIC are at the same memory location,
|
| 748 |
* but actually not on the global bus: MSI is on PCI bus
|
| 749 |
* APIC is connected directly to the CPU.
|
| 750 |
* Mapping them on the global bus happens to work because
|
| 751 |
* MSI registers are reserved in APIC MMIO and vice versa. */
|
| 752 |
apic_send_msi(addr, val); |
| 753 |
return;
|
| 754 |
} |
| 755 |
|
| 756 |
d = cpu_get_current_apic(); |
| 757 |
if (!d) {
|
| 758 |
return;
|
| 759 |
} |
| 760 |
s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
| 761 |
|
| 762 |
trace_apic_mem_writel(addr, val); |
| 763 |
|
| 764 |
switch(index) {
|
| 765 |
case 0x02: |
| 766 |
s->id = (val >> 24);
|
| 767 |
break;
|
| 768 |
case 0x03: |
| 769 |
break;
|
| 770 |
case 0x08: |
| 771 |
if (apic_report_tpr_access) {
|
| 772 |
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); |
| 773 |
} |
| 774 |
s->tpr = val; |
| 775 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
| 776 |
apic_update_irq(s); |
| 777 |
break;
|
| 778 |
case 0x09: |
| 779 |
case 0x0a: |
| 780 |
break;
|
| 781 |
case 0x0b: /* EOI */ |
| 782 |
apic_eoi(s); |
| 783 |
break;
|
| 784 |
case 0x0d: |
| 785 |
s->log_dest = val >> 24;
|
| 786 |
break;
|
| 787 |
case 0x0e: |
| 788 |
s->dest_mode = val >> 28;
|
| 789 |
break;
|
| 790 |
case 0x0f: |
| 791 |
s->spurious_vec = val & 0x1ff;
|
| 792 |
apic_update_irq(s); |
| 793 |
break;
|
| 794 |
case 0x10 ... 0x17: |
| 795 |
case 0x18 ... 0x1f: |
| 796 |
case 0x20 ... 0x27: |
| 797 |
case 0x28: |
| 798 |
break;
|
| 799 |
case 0x30: |
| 800 |
s->icr[0] = val;
|
| 801 |
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
| 802 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
| 803 |
(s->icr[0] >> 15) & 1); |
| 804 |
break;
|
| 805 |
case 0x31: |
| 806 |
s->icr[1] = val;
|
| 807 |
break;
|
| 808 |
case 0x32 ... 0x37: |
| 809 |
{
|
| 810 |
int n = index - 0x32; |
| 811 |
s->lvt[n] = val; |
| 812 |
if (n == APIC_LVT_TIMER)
|
| 813 |
apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
| 814 |
} |
| 815 |
break;
|
| 816 |
case 0x38: |
| 817 |
s->initial_count = val; |
| 818 |
s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
| 819 |
apic_timer_update(s, s->initial_count_load_time); |
| 820 |
break;
|
| 821 |
case 0x39: |
| 822 |
break;
|
| 823 |
case 0x3e: |
| 824 |
{
|
| 825 |
int v;
|
| 826 |
s->divide_conf = val & 0xb;
|
| 827 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
| 828 |
s->count_shift = (v + 1) & 7; |
| 829 |
} |
| 830 |
break;
|
| 831 |
default:
|
| 832 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
| 833 |
break;
|
| 834 |
} |
| 835 |
} |
| 836 |
|
| 837 |
static void apic_pre_save(APICCommonState *s) |
| 838 |
{
|
| 839 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
| 840 |
} |
| 841 |
|
| 842 |
static void apic_post_load(APICCommonState *s) |
| 843 |
{
|
| 844 |
if (s->timer_expiry != -1) { |
| 845 |
qemu_mod_timer(s->timer, s->timer_expiry); |
| 846 |
} else {
|
| 847 |
qemu_del_timer(s->timer); |
| 848 |
} |
| 849 |
} |
| 850 |
|
| 851 |
static const MemoryRegionOps apic_io_ops = { |
| 852 |
.old_mmio = {
|
| 853 |
.read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
|
| 854 |
.write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
|
| 855 |
}, |
| 856 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 857 |
}; |
| 858 |
|
| 859 |
static void apic_init(APICCommonState *s) |
| 860 |
{
|
| 861 |
memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi",
|
| 862 |
MSI_SPACE_SIZE); |
| 863 |
|
| 864 |
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
| 865 |
local_apics[s->idx] = s; |
| 866 |
|
| 867 |
msi_supported = true;
|
| 868 |
} |
| 869 |
|
| 870 |
static void apic_class_init(ObjectClass *klass, void *data) |
| 871 |
{
|
| 872 |
APICCommonClass *k = APIC_COMMON_CLASS(klass); |
| 873 |
|
| 874 |
k->init = apic_init; |
| 875 |
k->set_base = apic_set_base; |
| 876 |
k->set_tpr = apic_set_tpr; |
| 877 |
k->get_tpr = apic_get_tpr; |
| 878 |
k->vapic_base_update = apic_vapic_base_update; |
| 879 |
k->external_nmi = apic_external_nmi; |
| 880 |
k->pre_save = apic_pre_save; |
| 881 |
k->post_load = apic_post_load; |
| 882 |
} |
| 883 |
|
| 884 |
static TypeInfo apic_info = {
|
| 885 |
.name = "apic",
|
| 886 |
.instance_size = sizeof(APICCommonState),
|
| 887 |
.parent = TYPE_APIC_COMMON, |
| 888 |
.class_init = apic_class_init, |
| 889 |
}; |
| 890 |
|
| 891 |
static void apic_register_types(void) |
| 892 |
{
|
| 893 |
type_register_static(&apic_info); |
| 894 |
} |
| 895 |
|
| 896 |
type_init(apic_register_types) |